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mtd: remove use of __devexit_p
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of_device.h>
36 #include <linux/of_mtd.h>
37
38 #include <asm/mach/flash.h>
39 #include <linux/platform_data/mtd-mxc_nand.h>
40 #include <mach/hardware.h>
41
42 #define DRIVER_NAME "mxc_nand"
43
44 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
45 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
46 #define nfc_is_v3_2a() cpu_is_mx51()
47 #define nfc_is_v3_2b() cpu_is_mx53()
48
49 /* Addresses for NFC registers */
50 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
51 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
52 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
53 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
54 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
55 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
56 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
57 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
58 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
59 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
60 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
61 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
62 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
63 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
64 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
65 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
66 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
67 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
68 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
69 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
70 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
71 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
72
73 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
74 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
75 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
76 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
77 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
78 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
79 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
80 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
81 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
82 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
83
84 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
85
86 /*
87 * Operation modes for the NFC. Valid for v1, v2 and v3
88 * type controllers.
89 */
90 #define NFC_CMD (1 << 0)
91 #define NFC_ADDR (1 << 1)
92 #define NFC_INPUT (1 << 2)
93 #define NFC_OUTPUT (1 << 3)
94 #define NFC_ID (1 << 4)
95 #define NFC_STATUS (1 << 5)
96
97 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
98 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
99
100 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
101 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
102 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
103
104 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
105
106 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
107
108 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
109 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
110 #define NFC_V3_WRPROT_LOCK (1 << 1)
111 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
112 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
113
114 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
115
116 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
117 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
118 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
119 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
120 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
121 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
122 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
123 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
124 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
125 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
126 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
127 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
128 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
129 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
130
131 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
132 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
133 #define NFC_V3_CONFIG3_FW8 (1 << 3)
134 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
135 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
136 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
137 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
138
139 #define NFC_V3_IPC (host->regs_ip + 0x2C)
140 #define NFC_V3_IPC_CREQ (1 << 0)
141 #define NFC_V3_IPC_INT (1 << 31)
142
143 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
144
145 struct mxc_nand_host;
146
147 struct mxc_nand_devtype_data {
148 void (*preset)(struct mtd_info *);
149 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
150 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
151 void (*send_page)(struct mtd_info *, unsigned int);
152 void (*send_read_id)(struct mxc_nand_host *);
153 uint16_t (*get_dev_status)(struct mxc_nand_host *);
154 int (*check_int)(struct mxc_nand_host *);
155 void (*irq_control)(struct mxc_nand_host *, int);
156 u32 (*get_ecc_status)(struct mxc_nand_host *);
157 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
158 void (*select_chip)(struct mtd_info *mtd, int chip);
159 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
160 u_char *read_ecc, u_char *calc_ecc);
161
162 /*
163 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
164 * (CONFIG1:INT_MSK is set). To handle this the driver uses
165 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
166 */
167 int irqpending_quirk;
168 int needs_ip;
169
170 size_t regs_offset;
171 size_t spare0_offset;
172 size_t axi_offset;
173
174 int spare_len;
175 int eccbytes;
176 int eccsize;
177 int ppb_shift;
178 };
179
180 struct mxc_nand_host {
181 struct mtd_info mtd;
182 struct nand_chip nand;
183 struct device *dev;
184
185 void __iomem *spare0;
186 void __iomem *main_area0;
187
188 void __iomem *base;
189 void __iomem *regs;
190 void __iomem *regs_axi;
191 void __iomem *regs_ip;
192 int status_request;
193 struct clk *clk;
194 int clk_act;
195 int irq;
196 int eccsize;
197 int active_cs;
198
199 struct completion op_completion;
200
201 uint8_t *data_buf;
202 unsigned int buf_start;
203
204 const struct mxc_nand_devtype_data *devtype_data;
205 struct mxc_nand_platform_data pdata;
206 };
207
208 /* OOB placement block for use with hardware ecc generation */
209 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
210 .eccbytes = 5,
211 .eccpos = {6, 7, 8, 9, 10},
212 .oobfree = {{0, 5}, {12, 4}, }
213 };
214
215 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
216 .eccbytes = 20,
217 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
218 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
219 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
220 };
221
222 /* OOB description for 512 byte pages with 16 byte OOB */
223 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
224 .eccbytes = 1 * 9,
225 .eccpos = {
226 7, 8, 9, 10, 11, 12, 13, 14, 15
227 },
228 .oobfree = {
229 {.offset = 0, .length = 5}
230 }
231 };
232
233 /* OOB description for 2048 byte pages with 64 byte OOB */
234 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
235 .eccbytes = 4 * 9,
236 .eccpos = {
237 7, 8, 9, 10, 11, 12, 13, 14, 15,
238 23, 24, 25, 26, 27, 28, 29, 30, 31,
239 39, 40, 41, 42, 43, 44, 45, 46, 47,
240 55, 56, 57, 58, 59, 60, 61, 62, 63
241 },
242 .oobfree = {
243 {.offset = 2, .length = 4},
244 {.offset = 16, .length = 7},
245 {.offset = 32, .length = 7},
246 {.offset = 48, .length = 7}
247 }
248 };
249
250 /* OOB description for 4096 byte pages with 128 byte OOB */
251 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
252 .eccbytes = 8 * 9,
253 .eccpos = {
254 7, 8, 9, 10, 11, 12, 13, 14, 15,
255 23, 24, 25, 26, 27, 28, 29, 30, 31,
256 39, 40, 41, 42, 43, 44, 45, 46, 47,
257 55, 56, 57, 58, 59, 60, 61, 62, 63,
258 71, 72, 73, 74, 75, 76, 77, 78, 79,
259 87, 88, 89, 90, 91, 92, 93, 94, 95,
260 103, 104, 105, 106, 107, 108, 109, 110, 111,
261 119, 120, 121, 122, 123, 124, 125, 126, 127,
262 },
263 .oobfree = {
264 {.offset = 2, .length = 4},
265 {.offset = 16, .length = 7},
266 {.offset = 32, .length = 7},
267 {.offset = 48, .length = 7},
268 {.offset = 64, .length = 7},
269 {.offset = 80, .length = 7},
270 {.offset = 96, .length = 7},
271 {.offset = 112, .length = 7},
272 }
273 };
274
275 static const char *part_probes[] = { "RedBoot", "cmdlinepart", "ofpart", NULL };
276
277 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
278 {
279 int i;
280 u32 *t = trg;
281 const __iomem u32 *s = src;
282
283 for (i = 0; i < (size >> 2); i++)
284 *t++ = __raw_readl(s++);
285 }
286
287 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
288 {
289 int i;
290 u32 __iomem *t = trg;
291 const u32 *s = src;
292
293 for (i = 0; i < (size >> 2); i++)
294 __raw_writel(*s++, t++);
295 }
296
297 static int check_int_v3(struct mxc_nand_host *host)
298 {
299 uint32_t tmp;
300
301 tmp = readl(NFC_V3_IPC);
302 if (!(tmp & NFC_V3_IPC_INT))
303 return 0;
304
305 tmp &= ~NFC_V3_IPC_INT;
306 writel(tmp, NFC_V3_IPC);
307
308 return 1;
309 }
310
311 static int check_int_v1_v2(struct mxc_nand_host *host)
312 {
313 uint32_t tmp;
314
315 tmp = readw(NFC_V1_V2_CONFIG2);
316 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
317 return 0;
318
319 if (!host->devtype_data->irqpending_quirk)
320 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
321
322 return 1;
323 }
324
325 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
326 {
327 uint16_t tmp;
328
329 tmp = readw(NFC_V1_V2_CONFIG1);
330
331 if (activate)
332 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
333 else
334 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
335
336 writew(tmp, NFC_V1_V2_CONFIG1);
337 }
338
339 static void irq_control_v3(struct mxc_nand_host *host, int activate)
340 {
341 uint32_t tmp;
342
343 tmp = readl(NFC_V3_CONFIG2);
344
345 if (activate)
346 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
347 else
348 tmp |= NFC_V3_CONFIG2_INT_MSK;
349
350 writel(tmp, NFC_V3_CONFIG2);
351 }
352
353 static void irq_control(struct mxc_nand_host *host, int activate)
354 {
355 if (host->devtype_data->irqpending_quirk) {
356 if (activate)
357 enable_irq(host->irq);
358 else
359 disable_irq_nosync(host->irq);
360 } else {
361 host->devtype_data->irq_control(host, activate);
362 }
363 }
364
365 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
366 {
367 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
368 }
369
370 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
371 {
372 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
373 }
374
375 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
376 {
377 return readl(NFC_V3_ECC_STATUS_RESULT);
378 }
379
380 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
381 {
382 struct mxc_nand_host *host = dev_id;
383
384 if (!host->devtype_data->check_int(host))
385 return IRQ_NONE;
386
387 irq_control(host, 0);
388
389 complete(&host->op_completion);
390
391 return IRQ_HANDLED;
392 }
393
394 /* This function polls the NANDFC to wait for the basic operation to
395 * complete by checking the INT bit of config2 register.
396 */
397 static void wait_op_done(struct mxc_nand_host *host, int useirq)
398 {
399 int max_retries = 8000;
400
401 if (useirq) {
402 if (!host->devtype_data->check_int(host)) {
403 INIT_COMPLETION(host->op_completion);
404 irq_control(host, 1);
405 wait_for_completion(&host->op_completion);
406 }
407 } else {
408 while (max_retries-- > 0) {
409 if (host->devtype_data->check_int(host))
410 break;
411
412 udelay(1);
413 }
414 if (max_retries < 0)
415 pr_debug("%s: INT not set\n", __func__);
416 }
417 }
418
419 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
420 {
421 /* fill command */
422 writel(cmd, NFC_V3_FLASH_CMD);
423
424 /* send out command */
425 writel(NFC_CMD, NFC_V3_LAUNCH);
426
427 /* Wait for operation to complete */
428 wait_op_done(host, useirq);
429 }
430
431 /* This function issues the specified command to the NAND device and
432 * waits for completion. */
433 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
434 {
435 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
436
437 writew(cmd, NFC_V1_V2_FLASH_CMD);
438 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
439
440 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
441 int max_retries = 100;
442 /* Reset completion is indicated by NFC_CONFIG2 */
443 /* being set to 0 */
444 while (max_retries-- > 0) {
445 if (readw(NFC_V1_V2_CONFIG2) == 0) {
446 break;
447 }
448 udelay(1);
449 }
450 if (max_retries < 0)
451 pr_debug("%s: RESET failed\n", __func__);
452 } else {
453 /* Wait for operation to complete */
454 wait_op_done(host, useirq);
455 }
456 }
457
458 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
459 {
460 /* fill address */
461 writel(addr, NFC_V3_FLASH_ADDR0);
462
463 /* send out address */
464 writel(NFC_ADDR, NFC_V3_LAUNCH);
465
466 wait_op_done(host, 0);
467 }
468
469 /* This function sends an address (or partial address) to the
470 * NAND device. The address is used to select the source/destination for
471 * a NAND command. */
472 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
473 {
474 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
475
476 writew(addr, NFC_V1_V2_FLASH_ADDR);
477 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
478
479 /* Wait for operation to complete */
480 wait_op_done(host, islast);
481 }
482
483 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
484 {
485 struct nand_chip *nand_chip = mtd->priv;
486 struct mxc_nand_host *host = nand_chip->priv;
487 uint32_t tmp;
488
489 tmp = readl(NFC_V3_CONFIG1);
490 tmp &= ~(7 << 4);
491 writel(tmp, NFC_V3_CONFIG1);
492
493 /* transfer data from NFC ram to nand */
494 writel(ops, NFC_V3_LAUNCH);
495
496 wait_op_done(host, false);
497 }
498
499 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
500 {
501 struct nand_chip *nand_chip = mtd->priv;
502 struct mxc_nand_host *host = nand_chip->priv;
503
504 /* NANDFC buffer 0 is used for page read/write */
505 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
506
507 writew(ops, NFC_V1_V2_CONFIG2);
508
509 /* Wait for operation to complete */
510 wait_op_done(host, true);
511 }
512
513 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
514 {
515 struct nand_chip *nand_chip = mtd->priv;
516 struct mxc_nand_host *host = nand_chip->priv;
517 int bufs, i;
518
519 if (mtd->writesize > 512)
520 bufs = 4;
521 else
522 bufs = 1;
523
524 for (i = 0; i < bufs; i++) {
525
526 /* NANDFC buffer 0 is used for page read/write */
527 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
528
529 writew(ops, NFC_V1_V2_CONFIG2);
530
531 /* Wait for operation to complete */
532 wait_op_done(host, true);
533 }
534 }
535
536 static void send_read_id_v3(struct mxc_nand_host *host)
537 {
538 /* Read ID into main buffer */
539 writel(NFC_ID, NFC_V3_LAUNCH);
540
541 wait_op_done(host, true);
542
543 memcpy32_fromio(host->data_buf, host->main_area0, 16);
544 }
545
546 /* Request the NANDFC to perform a read of the NAND device ID. */
547 static void send_read_id_v1_v2(struct mxc_nand_host *host)
548 {
549 struct nand_chip *this = &host->nand;
550
551 /* NANDFC buffer 0 is used for device ID output */
552 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
553
554 writew(NFC_ID, NFC_V1_V2_CONFIG2);
555
556 /* Wait for operation to complete */
557 wait_op_done(host, true);
558
559 memcpy32_fromio(host->data_buf, host->main_area0, 16);
560
561 if (this->options & NAND_BUSWIDTH_16) {
562 /* compress the ID info */
563 host->data_buf[1] = host->data_buf[2];
564 host->data_buf[2] = host->data_buf[4];
565 host->data_buf[3] = host->data_buf[6];
566 host->data_buf[4] = host->data_buf[8];
567 host->data_buf[5] = host->data_buf[10];
568 }
569 }
570
571 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
572 {
573 writew(NFC_STATUS, NFC_V3_LAUNCH);
574 wait_op_done(host, true);
575
576 return readl(NFC_V3_CONFIG1) >> 16;
577 }
578
579 /* This function requests the NANDFC to perform a read of the
580 * NAND device status and returns the current status. */
581 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
582 {
583 void __iomem *main_buf = host->main_area0;
584 uint32_t store;
585 uint16_t ret;
586
587 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
588
589 /*
590 * The device status is stored in main_area0. To
591 * prevent corruption of the buffer save the value
592 * and restore it afterwards.
593 */
594 store = readl(main_buf);
595
596 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
597 wait_op_done(host, true);
598
599 ret = readw(main_buf);
600
601 writel(store, main_buf);
602
603 return ret;
604 }
605
606 /* This functions is used by upper layer to checks if device is ready */
607 static int mxc_nand_dev_ready(struct mtd_info *mtd)
608 {
609 /*
610 * NFC handles R/B internally. Therefore, this function
611 * always returns status as ready.
612 */
613 return 1;
614 }
615
616 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
617 {
618 /*
619 * If HW ECC is enabled, we turn it on during init. There is
620 * no need to enable again here.
621 */
622 }
623
624 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
625 u_char *read_ecc, u_char *calc_ecc)
626 {
627 struct nand_chip *nand_chip = mtd->priv;
628 struct mxc_nand_host *host = nand_chip->priv;
629
630 /*
631 * 1-Bit errors are automatically corrected in HW. No need for
632 * additional correction. 2-Bit errors cannot be corrected by
633 * HW ECC, so we need to return failure
634 */
635 uint16_t ecc_status = get_ecc_status_v1(host);
636
637 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
638 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
639 return -1;
640 }
641
642 return 0;
643 }
644
645 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
646 u_char *read_ecc, u_char *calc_ecc)
647 {
648 struct nand_chip *nand_chip = mtd->priv;
649 struct mxc_nand_host *host = nand_chip->priv;
650 u32 ecc_stat, err;
651 int no_subpages = 1;
652 int ret = 0;
653 u8 ecc_bit_mask, err_limit;
654
655 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
656 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
657
658 no_subpages = mtd->writesize >> 9;
659
660 ecc_stat = host->devtype_data->get_ecc_status(host);
661
662 do {
663 err = ecc_stat & ecc_bit_mask;
664 if (err > err_limit) {
665 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
666 return -1;
667 } else {
668 ret += err;
669 }
670 ecc_stat >>= 4;
671 } while (--no_subpages);
672
673 mtd->ecc_stats.corrected += ret;
674 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
675
676 return ret;
677 }
678
679 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
680 u_char *ecc_code)
681 {
682 return 0;
683 }
684
685 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
686 {
687 struct nand_chip *nand_chip = mtd->priv;
688 struct mxc_nand_host *host = nand_chip->priv;
689 uint8_t ret;
690
691 /* Check for status request */
692 if (host->status_request)
693 return host->devtype_data->get_dev_status(host) & 0xFF;
694
695 ret = *(uint8_t *)(host->data_buf + host->buf_start);
696 host->buf_start++;
697
698 return ret;
699 }
700
701 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
702 {
703 struct nand_chip *nand_chip = mtd->priv;
704 struct mxc_nand_host *host = nand_chip->priv;
705 uint16_t ret;
706
707 ret = *(uint16_t *)(host->data_buf + host->buf_start);
708 host->buf_start += 2;
709
710 return ret;
711 }
712
713 /* Write data of length len to buffer buf. The data to be
714 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
715 * Operation by the NFC, the data is written to NAND Flash */
716 static void mxc_nand_write_buf(struct mtd_info *mtd,
717 const u_char *buf, int len)
718 {
719 struct nand_chip *nand_chip = mtd->priv;
720 struct mxc_nand_host *host = nand_chip->priv;
721 u16 col = host->buf_start;
722 int n = mtd->oobsize + mtd->writesize - col;
723
724 n = min(n, len);
725
726 memcpy(host->data_buf + col, buf, n);
727
728 host->buf_start += n;
729 }
730
731 /* Read the data buffer from the NAND Flash. To read the data from NAND
732 * Flash first the data output cycle is initiated by the NFC, which copies
733 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
734 */
735 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
736 {
737 struct nand_chip *nand_chip = mtd->priv;
738 struct mxc_nand_host *host = nand_chip->priv;
739 u16 col = host->buf_start;
740 int n = mtd->oobsize + mtd->writesize - col;
741
742 n = min(n, len);
743
744 memcpy(buf, host->data_buf + col, n);
745
746 host->buf_start += n;
747 }
748
749 /* This function is used by upper layer for select and
750 * deselect of the NAND chip */
751 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
752 {
753 struct nand_chip *nand_chip = mtd->priv;
754 struct mxc_nand_host *host = nand_chip->priv;
755
756 if (chip == -1) {
757 /* Disable the NFC clock */
758 if (host->clk_act) {
759 clk_disable_unprepare(host->clk);
760 host->clk_act = 0;
761 }
762 return;
763 }
764
765 if (!host->clk_act) {
766 /* Enable the NFC clock */
767 clk_prepare_enable(host->clk);
768 host->clk_act = 1;
769 }
770 }
771
772 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
773 {
774 struct nand_chip *nand_chip = mtd->priv;
775 struct mxc_nand_host *host = nand_chip->priv;
776
777 if (chip == -1) {
778 /* Disable the NFC clock */
779 if (host->clk_act) {
780 clk_disable_unprepare(host->clk);
781 host->clk_act = 0;
782 }
783 return;
784 }
785
786 if (!host->clk_act) {
787 /* Enable the NFC clock */
788 clk_prepare_enable(host->clk);
789 host->clk_act = 1;
790 }
791
792 host->active_cs = chip;
793 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
794 }
795
796 /*
797 * Function to transfer data to/from spare area.
798 */
799 static void copy_spare(struct mtd_info *mtd, bool bfrom)
800 {
801 struct nand_chip *this = mtd->priv;
802 struct mxc_nand_host *host = this->priv;
803 u16 i, j;
804 u16 n = mtd->writesize >> 9;
805 u8 *d = host->data_buf + mtd->writesize;
806 u8 __iomem *s = host->spare0;
807 u16 t = host->devtype_data->spare_len;
808
809 j = (mtd->oobsize / n >> 1) << 1;
810
811 if (bfrom) {
812 for (i = 0; i < n - 1; i++)
813 memcpy32_fromio(d + i * j, s + i * t, j);
814
815 /* the last section */
816 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
817 } else {
818 for (i = 0; i < n - 1; i++)
819 memcpy32_toio(&s[i * t], &d[i * j], j);
820
821 /* the last section */
822 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
823 }
824 }
825
826 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
827 {
828 struct nand_chip *nand_chip = mtd->priv;
829 struct mxc_nand_host *host = nand_chip->priv;
830
831 /* Write out column address, if necessary */
832 if (column != -1) {
833 /*
834 * MXC NANDFC can only perform full page+spare or
835 * spare-only read/write. When the upper layers
836 * perform a read/write buf operation, the saved column
837 * address is used to index into the full page.
838 */
839 host->devtype_data->send_addr(host, 0, page_addr == -1);
840 if (mtd->writesize > 512)
841 /* another col addr cycle for 2k page */
842 host->devtype_data->send_addr(host, 0, false);
843 }
844
845 /* Write out page address, if necessary */
846 if (page_addr != -1) {
847 /* paddr_0 - p_addr_7 */
848 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
849
850 if (mtd->writesize > 512) {
851 if (mtd->size >= 0x10000000) {
852 /* paddr_8 - paddr_15 */
853 host->devtype_data->send_addr(host,
854 (page_addr >> 8) & 0xff,
855 false);
856 host->devtype_data->send_addr(host,
857 (page_addr >> 16) & 0xff,
858 true);
859 } else
860 /* paddr_8 - paddr_15 */
861 host->devtype_data->send_addr(host,
862 (page_addr >> 8) & 0xff, true);
863 } else {
864 /* One more address cycle for higher density devices */
865 if (mtd->size >= 0x4000000) {
866 /* paddr_8 - paddr_15 */
867 host->devtype_data->send_addr(host,
868 (page_addr >> 8) & 0xff,
869 false);
870 host->devtype_data->send_addr(host,
871 (page_addr >> 16) & 0xff,
872 true);
873 } else
874 /* paddr_8 - paddr_15 */
875 host->devtype_data->send_addr(host,
876 (page_addr >> 8) & 0xff, true);
877 }
878 }
879 }
880
881 /*
882 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
883 * on how much oob the nand chip has. For 8bit ecc we need at least
884 * 26 bytes of oob data per 512 byte block.
885 */
886 static int get_eccsize(struct mtd_info *mtd)
887 {
888 int oobbytes_per_512 = 0;
889
890 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
891
892 if (oobbytes_per_512 < 26)
893 return 4;
894 else
895 return 8;
896 }
897
898 static void preset_v1(struct mtd_info *mtd)
899 {
900 struct nand_chip *nand_chip = mtd->priv;
901 struct mxc_nand_host *host = nand_chip->priv;
902 uint16_t config1 = 0;
903
904 if (nand_chip->ecc.mode == NAND_ECC_HW)
905 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
906
907 if (!host->devtype_data->irqpending_quirk)
908 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
909
910 host->eccsize = 1;
911
912 writew(config1, NFC_V1_V2_CONFIG1);
913 /* preset operation */
914
915 /* Unlock the internal RAM Buffer */
916 writew(0x2, NFC_V1_V2_CONFIG);
917
918 /* Blocks to be unlocked */
919 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
920 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
921
922 /* Unlock Block Command for given address range */
923 writew(0x4, NFC_V1_V2_WRPROT);
924 }
925
926 static void preset_v2(struct mtd_info *mtd)
927 {
928 struct nand_chip *nand_chip = mtd->priv;
929 struct mxc_nand_host *host = nand_chip->priv;
930 uint16_t config1 = 0;
931
932 if (nand_chip->ecc.mode == NAND_ECC_HW)
933 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
934
935 config1 |= NFC_V2_CONFIG1_FP_INT;
936
937 if (!host->devtype_data->irqpending_quirk)
938 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
939
940 if (mtd->writesize) {
941 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
942
943 host->eccsize = get_eccsize(mtd);
944 if (host->eccsize == 4)
945 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
946
947 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
948 } else {
949 host->eccsize = 1;
950 }
951
952 writew(config1, NFC_V1_V2_CONFIG1);
953 /* preset operation */
954
955 /* Unlock the internal RAM Buffer */
956 writew(0x2, NFC_V1_V2_CONFIG);
957
958 /* Blocks to be unlocked */
959 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
960 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
961 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
962 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
963 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
964 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
965 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
966 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
967
968 /* Unlock Block Command for given address range */
969 writew(0x4, NFC_V1_V2_WRPROT);
970 }
971
972 static void preset_v3(struct mtd_info *mtd)
973 {
974 struct nand_chip *chip = mtd->priv;
975 struct mxc_nand_host *host = chip->priv;
976 uint32_t config2, config3;
977 int i, addr_phases;
978
979 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
980 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
981
982 /* Unlock the internal RAM Buffer */
983 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
984 NFC_V3_WRPROT);
985
986 /* Blocks to be unlocked */
987 for (i = 0; i < NAND_MAX_CHIPS; i++)
988 writel(0x0 | (0xffff << 16),
989 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
990
991 writel(0, NFC_V3_IPC);
992
993 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
994 NFC_V3_CONFIG2_2CMD_PHASES |
995 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
996 NFC_V3_CONFIG2_ST_CMD(0x70) |
997 NFC_V3_CONFIG2_INT_MSK |
998 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
999
1000 if (chip->ecc.mode == NAND_ECC_HW)
1001 config2 |= NFC_V3_CONFIG2_ECC_EN;
1002
1003 addr_phases = fls(chip->pagemask) >> 3;
1004
1005 if (mtd->writesize == 2048) {
1006 config2 |= NFC_V3_CONFIG2_PS_2048;
1007 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1008 } else if (mtd->writesize == 4096) {
1009 config2 |= NFC_V3_CONFIG2_PS_4096;
1010 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1011 } else {
1012 config2 |= NFC_V3_CONFIG2_PS_512;
1013 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1014 }
1015
1016 if (mtd->writesize) {
1017 config2 |= NFC_V3_CONFIG2_PPB(
1018 ffs(mtd->erasesize / mtd->writesize) - 6,
1019 host->devtype_data->ppb_shift);
1020 host->eccsize = get_eccsize(mtd);
1021 if (host->eccsize == 8)
1022 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1023 }
1024
1025 writel(config2, NFC_V3_CONFIG2);
1026
1027 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1028 NFC_V3_CONFIG3_NO_SDMA |
1029 NFC_V3_CONFIG3_RBB_MODE |
1030 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1031 NFC_V3_CONFIG3_ADD_OP(0);
1032
1033 if (!(chip->options & NAND_BUSWIDTH_16))
1034 config3 |= NFC_V3_CONFIG3_FW8;
1035
1036 writel(config3, NFC_V3_CONFIG3);
1037
1038 writel(0, NFC_V3_DELAY_LINE);
1039 }
1040
1041 /* Used by the upper layer to write command to NAND Flash for
1042 * different operations to be carried out on NAND Flash */
1043 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1044 int column, int page_addr)
1045 {
1046 struct nand_chip *nand_chip = mtd->priv;
1047 struct mxc_nand_host *host = nand_chip->priv;
1048
1049 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1050 command, column, page_addr);
1051
1052 /* Reset command state information */
1053 host->status_request = false;
1054
1055 /* Command pre-processing step */
1056 switch (command) {
1057 case NAND_CMD_RESET:
1058 host->devtype_data->preset(mtd);
1059 host->devtype_data->send_cmd(host, command, false);
1060 break;
1061
1062 case NAND_CMD_STATUS:
1063 host->buf_start = 0;
1064 host->status_request = true;
1065
1066 host->devtype_data->send_cmd(host, command, true);
1067 mxc_do_addr_cycle(mtd, column, page_addr);
1068 break;
1069
1070 case NAND_CMD_READ0:
1071 case NAND_CMD_READOOB:
1072 if (command == NAND_CMD_READ0)
1073 host->buf_start = column;
1074 else
1075 host->buf_start = column + mtd->writesize;
1076
1077 command = NAND_CMD_READ0; /* only READ0 is valid */
1078
1079 host->devtype_data->send_cmd(host, command, false);
1080 mxc_do_addr_cycle(mtd, column, page_addr);
1081
1082 if (mtd->writesize > 512)
1083 host->devtype_data->send_cmd(host,
1084 NAND_CMD_READSTART, true);
1085
1086 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1087
1088 memcpy32_fromio(host->data_buf, host->main_area0,
1089 mtd->writesize);
1090 copy_spare(mtd, true);
1091 break;
1092
1093 case NAND_CMD_SEQIN:
1094 if (column >= mtd->writesize)
1095 /* call ourself to read a page */
1096 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1097
1098 host->buf_start = column;
1099
1100 host->devtype_data->send_cmd(host, command, false);
1101 mxc_do_addr_cycle(mtd, column, page_addr);
1102 break;
1103
1104 case NAND_CMD_PAGEPROG:
1105 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1106 copy_spare(mtd, false);
1107 host->devtype_data->send_page(mtd, NFC_INPUT);
1108 host->devtype_data->send_cmd(host, command, true);
1109 mxc_do_addr_cycle(mtd, column, page_addr);
1110 break;
1111
1112 case NAND_CMD_READID:
1113 host->devtype_data->send_cmd(host, command, true);
1114 mxc_do_addr_cycle(mtd, column, page_addr);
1115 host->devtype_data->send_read_id(host);
1116 host->buf_start = column;
1117 break;
1118
1119 case NAND_CMD_ERASE1:
1120 case NAND_CMD_ERASE2:
1121 host->devtype_data->send_cmd(host, command, false);
1122 mxc_do_addr_cycle(mtd, column, page_addr);
1123
1124 break;
1125 }
1126 }
1127
1128 /*
1129 * The generic flash bbt decriptors overlap with our ecc
1130 * hardware, so define some i.MX specific ones.
1131 */
1132 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1133 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1134
1135 static struct nand_bbt_descr bbt_main_descr = {
1136 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1137 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1138 .offs = 0,
1139 .len = 4,
1140 .veroffs = 4,
1141 .maxblocks = 4,
1142 .pattern = bbt_pattern,
1143 };
1144
1145 static struct nand_bbt_descr bbt_mirror_descr = {
1146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1147 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1148 .offs = 0,
1149 .len = 4,
1150 .veroffs = 4,
1151 .maxblocks = 4,
1152 .pattern = mirror_pattern,
1153 };
1154
1155 /* v1 + irqpending_quirk: i.MX21 */
1156 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1157 .preset = preset_v1,
1158 .send_cmd = send_cmd_v1_v2,
1159 .send_addr = send_addr_v1_v2,
1160 .send_page = send_page_v1,
1161 .send_read_id = send_read_id_v1_v2,
1162 .get_dev_status = get_dev_status_v1_v2,
1163 .check_int = check_int_v1_v2,
1164 .irq_control = irq_control_v1_v2,
1165 .get_ecc_status = get_ecc_status_v1,
1166 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1167 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1168 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1169 .select_chip = mxc_nand_select_chip_v1_v3,
1170 .correct_data = mxc_nand_correct_data_v1,
1171 .irqpending_quirk = 1,
1172 .needs_ip = 0,
1173 .regs_offset = 0xe00,
1174 .spare0_offset = 0x800,
1175 .spare_len = 16,
1176 .eccbytes = 3,
1177 .eccsize = 1,
1178 };
1179
1180 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1181 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1182 .preset = preset_v1,
1183 .send_cmd = send_cmd_v1_v2,
1184 .send_addr = send_addr_v1_v2,
1185 .send_page = send_page_v1,
1186 .send_read_id = send_read_id_v1_v2,
1187 .get_dev_status = get_dev_status_v1_v2,
1188 .check_int = check_int_v1_v2,
1189 .irq_control = irq_control_v1_v2,
1190 .get_ecc_status = get_ecc_status_v1,
1191 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1192 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1193 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1194 .select_chip = mxc_nand_select_chip_v1_v3,
1195 .correct_data = mxc_nand_correct_data_v1,
1196 .irqpending_quirk = 0,
1197 .needs_ip = 0,
1198 .regs_offset = 0xe00,
1199 .spare0_offset = 0x800,
1200 .axi_offset = 0,
1201 .spare_len = 16,
1202 .eccbytes = 3,
1203 .eccsize = 1,
1204 };
1205
1206 /* v21: i.MX25, i.MX35 */
1207 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1208 .preset = preset_v2,
1209 .send_cmd = send_cmd_v1_v2,
1210 .send_addr = send_addr_v1_v2,
1211 .send_page = send_page_v2,
1212 .send_read_id = send_read_id_v1_v2,
1213 .get_dev_status = get_dev_status_v1_v2,
1214 .check_int = check_int_v1_v2,
1215 .irq_control = irq_control_v1_v2,
1216 .get_ecc_status = get_ecc_status_v2,
1217 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1218 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1219 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1220 .select_chip = mxc_nand_select_chip_v2,
1221 .correct_data = mxc_nand_correct_data_v2_v3,
1222 .irqpending_quirk = 0,
1223 .needs_ip = 0,
1224 .regs_offset = 0x1e00,
1225 .spare0_offset = 0x1000,
1226 .axi_offset = 0,
1227 .spare_len = 64,
1228 .eccbytes = 9,
1229 .eccsize = 0,
1230 };
1231
1232 /* v3.2a: i.MX51 */
1233 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1234 .preset = preset_v3,
1235 .send_cmd = send_cmd_v3,
1236 .send_addr = send_addr_v3,
1237 .send_page = send_page_v3,
1238 .send_read_id = send_read_id_v3,
1239 .get_dev_status = get_dev_status_v3,
1240 .check_int = check_int_v3,
1241 .irq_control = irq_control_v3,
1242 .get_ecc_status = get_ecc_status_v3,
1243 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1244 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1245 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1246 .select_chip = mxc_nand_select_chip_v1_v3,
1247 .correct_data = mxc_nand_correct_data_v2_v3,
1248 .irqpending_quirk = 0,
1249 .needs_ip = 1,
1250 .regs_offset = 0,
1251 .spare0_offset = 0x1000,
1252 .axi_offset = 0x1e00,
1253 .spare_len = 64,
1254 .eccbytes = 0,
1255 .eccsize = 0,
1256 .ppb_shift = 7,
1257 };
1258
1259 /* v3.2b: i.MX53 */
1260 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1261 .preset = preset_v3,
1262 .send_cmd = send_cmd_v3,
1263 .send_addr = send_addr_v3,
1264 .send_page = send_page_v3,
1265 .send_read_id = send_read_id_v3,
1266 .get_dev_status = get_dev_status_v3,
1267 .check_int = check_int_v3,
1268 .irq_control = irq_control_v3,
1269 .get_ecc_status = get_ecc_status_v3,
1270 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1271 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1272 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1273 .select_chip = mxc_nand_select_chip_v1_v3,
1274 .correct_data = mxc_nand_correct_data_v2_v3,
1275 .irqpending_quirk = 0,
1276 .needs_ip = 1,
1277 .regs_offset = 0,
1278 .spare0_offset = 0x1000,
1279 .axi_offset = 0x1e00,
1280 .spare_len = 64,
1281 .eccbytes = 0,
1282 .eccsize = 0,
1283 .ppb_shift = 8,
1284 };
1285
1286 #ifdef CONFIG_OF_MTD
1287 static const struct of_device_id mxcnd_dt_ids[] = {
1288 {
1289 .compatible = "fsl,imx21-nand",
1290 .data = &imx21_nand_devtype_data,
1291 }, {
1292 .compatible = "fsl,imx27-nand",
1293 .data = &imx27_nand_devtype_data,
1294 }, {
1295 .compatible = "fsl,imx25-nand",
1296 .data = &imx25_nand_devtype_data,
1297 }, {
1298 .compatible = "fsl,imx51-nand",
1299 .data = &imx51_nand_devtype_data,
1300 }, {
1301 .compatible = "fsl,imx53-nand",
1302 .data = &imx53_nand_devtype_data,
1303 },
1304 { /* sentinel */ }
1305 };
1306
1307 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1308 {
1309 struct device_node *np = host->dev->of_node;
1310 struct mxc_nand_platform_data *pdata = &host->pdata;
1311 const struct of_device_id *of_id =
1312 of_match_device(mxcnd_dt_ids, host->dev);
1313 int buswidth;
1314
1315 if (!np)
1316 return 1;
1317
1318 if (of_get_nand_ecc_mode(np) >= 0)
1319 pdata->hw_ecc = 1;
1320
1321 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1322
1323 buswidth = of_get_nand_bus_width(np);
1324 if (buswidth < 0)
1325 return buswidth;
1326
1327 pdata->width = buswidth / 8;
1328
1329 host->devtype_data = of_id->data;
1330
1331 return 0;
1332 }
1333 #else
1334 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1335 {
1336 return 1;
1337 }
1338 #endif
1339
1340 static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
1341 {
1342 struct mxc_nand_platform_data *pdata = host->dev->platform_data;
1343
1344 if (!pdata)
1345 return -ENODEV;
1346
1347 host->pdata = *pdata;
1348
1349 if (nfc_is_v1()) {
1350 if (cpu_is_mx21())
1351 host->devtype_data = &imx21_nand_devtype_data;
1352 else
1353 host->devtype_data = &imx27_nand_devtype_data;
1354 } else if (nfc_is_v21()) {
1355 host->devtype_data = &imx25_nand_devtype_data;
1356 } else if (nfc_is_v3_2a()) {
1357 host->devtype_data = &imx51_nand_devtype_data;
1358 } else if (nfc_is_v3_2b()) {
1359 host->devtype_data = &imx53_nand_devtype_data;
1360 } else
1361 BUG();
1362
1363 return 0;
1364 }
1365
1366 static int __devinit mxcnd_probe(struct platform_device *pdev)
1367 {
1368 struct nand_chip *this;
1369 struct mtd_info *mtd;
1370 struct mxc_nand_host *host;
1371 struct resource *res;
1372 int err = 0;
1373
1374 /* Allocate memory for MTD device structure and private data */
1375 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
1376 NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
1377 if (!host)
1378 return -ENOMEM;
1379
1380 host->data_buf = (uint8_t *)(host + 1);
1381
1382 host->dev = &pdev->dev;
1383 /* structures must be linked */
1384 this = &host->nand;
1385 mtd = &host->mtd;
1386 mtd->priv = this;
1387 mtd->owner = THIS_MODULE;
1388 mtd->dev.parent = &pdev->dev;
1389 mtd->name = DRIVER_NAME;
1390
1391 /* 50 us command delay time */
1392 this->chip_delay = 5;
1393
1394 this->priv = host;
1395 this->dev_ready = mxc_nand_dev_ready;
1396 this->cmdfunc = mxc_nand_command;
1397 this->read_byte = mxc_nand_read_byte;
1398 this->read_word = mxc_nand_read_word;
1399 this->write_buf = mxc_nand_write_buf;
1400 this->read_buf = mxc_nand_read_buf;
1401
1402 host->clk = devm_clk_get(&pdev->dev, NULL);
1403 if (IS_ERR(host->clk))
1404 return PTR_ERR(host->clk);
1405
1406 err = mxcnd_probe_dt(host);
1407 if (err > 0)
1408 err = mxcnd_probe_pdata(host);
1409 if (err < 0)
1410 return err;
1411
1412 if (host->devtype_data->needs_ip) {
1413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1414 if (!res)
1415 return -ENODEV;
1416 host->regs_ip = devm_request_and_ioremap(&pdev->dev, res);
1417 if (!host->regs_ip)
1418 return -ENOMEM;
1419
1420 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1421 } else {
1422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1423 }
1424
1425 if (!res)
1426 return -ENODEV;
1427
1428 host->base = devm_request_and_ioremap(&pdev->dev, res);
1429 if (!host->base)
1430 return -ENOMEM;
1431
1432 host->main_area0 = host->base;
1433
1434 if (host->devtype_data->regs_offset)
1435 host->regs = host->base + host->devtype_data->regs_offset;
1436 host->spare0 = host->base + host->devtype_data->spare0_offset;
1437 if (host->devtype_data->axi_offset)
1438 host->regs_axi = host->base + host->devtype_data->axi_offset;
1439
1440 this->ecc.bytes = host->devtype_data->eccbytes;
1441 host->eccsize = host->devtype_data->eccsize;
1442
1443 this->select_chip = host->devtype_data->select_chip;
1444 this->ecc.size = 512;
1445 this->ecc.layout = host->devtype_data->ecclayout_512;
1446
1447 if (host->pdata.hw_ecc) {
1448 this->ecc.calculate = mxc_nand_calculate_ecc;
1449 this->ecc.hwctl = mxc_nand_enable_hwecc;
1450 this->ecc.correct = host->devtype_data->correct_data;
1451 this->ecc.mode = NAND_ECC_HW;
1452 } else {
1453 this->ecc.mode = NAND_ECC_SOFT;
1454 }
1455
1456 /* NAND bus width determines access functions used by upper layer */
1457 if (host->pdata.width == 2)
1458 this->options |= NAND_BUSWIDTH_16;
1459
1460 if (host->pdata.flash_bbt) {
1461 this->bbt_td = &bbt_main_descr;
1462 this->bbt_md = &bbt_mirror_descr;
1463 /* update flash based bbt */
1464 this->bbt_options |= NAND_BBT_USE_FLASH;
1465 }
1466
1467 init_completion(&host->op_completion);
1468
1469 host->irq = platform_get_irq(pdev, 0);
1470
1471 /*
1472 * Use host->devtype_data->irq_control() here instead of irq_control()
1473 * because we must not disable_irq_nosync without having requested the
1474 * irq.
1475 */
1476 host->devtype_data->irq_control(host, 0);
1477
1478 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1479 IRQF_DISABLED, DRIVER_NAME, host);
1480 if (err)
1481 return err;
1482
1483 clk_prepare_enable(host->clk);
1484 host->clk_act = 1;
1485
1486 /*
1487 * Now that we "own" the interrupt make sure the interrupt mask bit is
1488 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1489 * on this machine.
1490 */
1491 if (host->devtype_data->irqpending_quirk) {
1492 disable_irq_nosync(host->irq);
1493 host->devtype_data->irq_control(host, 1);
1494 }
1495
1496 /* first scan to find the device and get the page size */
1497 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1498 err = -ENXIO;
1499 goto escan;
1500 }
1501
1502 /* Call preset again, with correct writesize this time */
1503 host->devtype_data->preset(mtd);
1504
1505 if (mtd->writesize == 2048)
1506 this->ecc.layout = host->devtype_data->ecclayout_2k;
1507 else if (mtd->writesize == 4096)
1508 this->ecc.layout = host->devtype_data->ecclayout_4k;
1509
1510 if (this->ecc.mode == NAND_ECC_HW) {
1511 if (nfc_is_v1())
1512 this->ecc.strength = 1;
1513 else
1514 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1515 }
1516
1517 /* second phase scan */
1518 if (nand_scan_tail(mtd)) {
1519 err = -ENXIO;
1520 goto escan;
1521 }
1522
1523 /* Register the partitions */
1524 mtd_device_parse_register(mtd, part_probes,
1525 &(struct mtd_part_parser_data){
1526 .of_node = pdev->dev.of_node,
1527 },
1528 host->pdata.parts,
1529 host->pdata.nr_parts);
1530
1531 platform_set_drvdata(pdev, host);
1532
1533 return 0;
1534
1535 escan:
1536 clk_disable_unprepare(host->clk);
1537
1538 return err;
1539 }
1540
1541 static int __devexit mxcnd_remove(struct platform_device *pdev)
1542 {
1543 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1544
1545 platform_set_drvdata(pdev, NULL);
1546
1547 nand_release(&host->mtd);
1548
1549 return 0;
1550 }
1551
1552 static struct platform_driver mxcnd_driver = {
1553 .driver = {
1554 .name = DRIVER_NAME,
1555 .owner = THIS_MODULE,
1556 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1557 },
1558 .probe = mxcnd_probe,
1559 .remove = mxcnd_remove,
1560 };
1561 module_platform_driver(mxcnd_driver);
1562
1563 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1564 MODULE_DESCRIPTION("MXC NAND MTD driver");
1565 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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