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[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
38
39 #include <asm/mach/flash.h>
40 #include <linux/platform_data/mtd-mxc_nand.h>
41
42 #define DRIVER_NAME "mxc_nand"
43
44 /* Addresses for NFC registers */
45 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
54 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
56 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
64 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
68 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
69 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
74 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
75 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78
79 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81 /*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85 #define NFC_CMD (1 << 0)
86 #define NFC_ADDR (1 << 1)
87 #define NFC_INPUT (1 << 2)
88 #define NFC_OUTPUT (1 << 3)
89 #define NFC_ID (1 << 4)
90 #define NFC_STATUS (1 << 5)
91
92 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
97 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105 #define NFC_V3_WRPROT_LOCK (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8 (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134 #define NFC_V3_IPC (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ (1 << 0)
136 #define NFC_V3_IPC_INT (1 << 31)
137
138 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139
140 struct mxc_nand_host;
141
142 struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
151 u32 (*get_ecc_status)(struct mxc_nand_host *);
152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
153 void (*select_chip)(struct mtd_info *mtd, int chip);
154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
172 int ppb_shift;
173 };
174
175 struct mxc_nand_host {
176 struct mtd_info mtd;
177 struct nand_chip nand;
178 struct device *dev;
179
180 void __iomem *spare0;
181 void __iomem *main_area0;
182
183 void __iomem *base;
184 void __iomem *regs;
185 void __iomem *regs_axi;
186 void __iomem *regs_ip;
187 int status_request;
188 struct clk *clk;
189 int clk_act;
190 int irq;
191 int eccsize;
192 int active_cs;
193
194 struct completion op_completion;
195
196 uint8_t *data_buf;
197 unsigned int buf_start;
198
199 const struct mxc_nand_devtype_data *devtype_data;
200 struct mxc_nand_platform_data pdata;
201 };
202
203 /* OOB placement block for use with hardware ecc generation */
204 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
205 .eccbytes = 5,
206 .eccpos = {6, 7, 8, 9, 10},
207 .oobfree = {{0, 5}, {12, 4}, }
208 };
209
210 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
211 .eccbytes = 20,
212 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
215 };
216
217 /* OOB description for 512 byte pages with 16 byte OOB */
218 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219 .eccbytes = 1 * 9,
220 .eccpos = {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
222 },
223 .oobfree = {
224 {.offset = 0, .length = 5}
225 }
226 };
227
228 /* OOB description for 2048 byte pages with 64 byte OOB */
229 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230 .eccbytes = 4 * 9,
231 .eccpos = {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
236 },
237 .oobfree = {
238 {.offset = 2, .length = 4},
239 {.offset = 16, .length = 7},
240 {.offset = 32, .length = 7},
241 {.offset = 48, .length = 7}
242 }
243 };
244
245 /* OOB description for 4096 byte pages with 128 byte OOB */
246 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247 .eccbytes = 8 * 9,
248 .eccpos = {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
257 },
258 .oobfree = {
259 {.offset = 2, .length = 4},
260 {.offset = 16, .length = 7},
261 {.offset = 32, .length = 7},
262 {.offset = 48, .length = 7},
263 {.offset = 64, .length = 7},
264 {.offset = 80, .length = 7},
265 {.offset = 96, .length = 7},
266 {.offset = 112, .length = 7},
267 }
268 };
269
270 static const char * const part_probes[] = {
271 "cmdlinepart", "RedBoot", "ofpart", NULL };
272
273 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
274 {
275 int i;
276 u32 *t = trg;
277 const __iomem u32 *s = src;
278
279 for (i = 0; i < (size >> 2); i++)
280 *t++ = __raw_readl(s++);
281 }
282
283 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
284 {
285 /* __iowrite32_copy use 32bit size values so divide by 4 */
286 __iowrite32_copy(trg, src, size / 4);
287 }
288
289 static int check_int_v3(struct mxc_nand_host *host)
290 {
291 uint32_t tmp;
292
293 tmp = readl(NFC_V3_IPC);
294 if (!(tmp & NFC_V3_IPC_INT))
295 return 0;
296
297 tmp &= ~NFC_V3_IPC_INT;
298 writel(tmp, NFC_V3_IPC);
299
300 return 1;
301 }
302
303 static int check_int_v1_v2(struct mxc_nand_host *host)
304 {
305 uint32_t tmp;
306
307 tmp = readw(NFC_V1_V2_CONFIG2);
308 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
309 return 0;
310
311 if (!host->devtype_data->irqpending_quirk)
312 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
313
314 return 1;
315 }
316
317 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
318 {
319 uint16_t tmp;
320
321 tmp = readw(NFC_V1_V2_CONFIG1);
322
323 if (activate)
324 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
325 else
326 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
327
328 writew(tmp, NFC_V1_V2_CONFIG1);
329 }
330
331 static void irq_control_v3(struct mxc_nand_host *host, int activate)
332 {
333 uint32_t tmp;
334
335 tmp = readl(NFC_V3_CONFIG2);
336
337 if (activate)
338 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
339 else
340 tmp |= NFC_V3_CONFIG2_INT_MSK;
341
342 writel(tmp, NFC_V3_CONFIG2);
343 }
344
345 static void irq_control(struct mxc_nand_host *host, int activate)
346 {
347 if (host->devtype_data->irqpending_quirk) {
348 if (activate)
349 enable_irq(host->irq);
350 else
351 disable_irq_nosync(host->irq);
352 } else {
353 host->devtype_data->irq_control(host, activate);
354 }
355 }
356
357 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
358 {
359 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
360 }
361
362 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
363 {
364 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
365 }
366
367 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
368 {
369 return readl(NFC_V3_ECC_STATUS_RESULT);
370 }
371
372 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
373 {
374 struct mxc_nand_host *host = dev_id;
375
376 if (!host->devtype_data->check_int(host))
377 return IRQ_NONE;
378
379 irq_control(host, 0);
380
381 complete(&host->op_completion);
382
383 return IRQ_HANDLED;
384 }
385
386 /* This function polls the NANDFC to wait for the basic operation to
387 * complete by checking the INT bit of config2 register.
388 */
389 static int wait_op_done(struct mxc_nand_host *host, int useirq)
390 {
391 int ret = 0;
392
393 /*
394 * If operation is already complete, don't bother to setup an irq or a
395 * loop.
396 */
397 if (host->devtype_data->check_int(host))
398 return 0;
399
400 if (useirq) {
401 unsigned long timeout;
402
403 reinit_completion(&host->op_completion);
404
405 irq_control(host, 1);
406
407 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
408 if (!timeout && !host->devtype_data->check_int(host)) {
409 dev_dbg(host->dev, "timeout waiting for irq\n");
410 ret = -ETIMEDOUT;
411 }
412 } else {
413 int max_retries = 8000;
414 int done;
415
416 do {
417 udelay(1);
418
419 done = host->devtype_data->check_int(host);
420 if (done)
421 break;
422
423 } while (--max_retries);
424
425 if (!done) {
426 dev_dbg(host->dev, "timeout polling for completion\n");
427 ret = -ETIMEDOUT;
428 }
429 }
430
431 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
432
433 return ret;
434 }
435
436 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
437 {
438 /* fill command */
439 writel(cmd, NFC_V3_FLASH_CMD);
440
441 /* send out command */
442 writel(NFC_CMD, NFC_V3_LAUNCH);
443
444 /* Wait for operation to complete */
445 wait_op_done(host, useirq);
446 }
447
448 /* This function issues the specified command to the NAND device and
449 * waits for completion. */
450 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
451 {
452 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
453
454 writew(cmd, NFC_V1_V2_FLASH_CMD);
455 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
456
457 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
458 int max_retries = 100;
459 /* Reset completion is indicated by NFC_CONFIG2 */
460 /* being set to 0 */
461 while (max_retries-- > 0) {
462 if (readw(NFC_V1_V2_CONFIG2) == 0) {
463 break;
464 }
465 udelay(1);
466 }
467 if (max_retries < 0)
468 pr_debug("%s: RESET failed\n", __func__);
469 } else {
470 /* Wait for operation to complete */
471 wait_op_done(host, useirq);
472 }
473 }
474
475 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
476 {
477 /* fill address */
478 writel(addr, NFC_V3_FLASH_ADDR0);
479
480 /* send out address */
481 writel(NFC_ADDR, NFC_V3_LAUNCH);
482
483 wait_op_done(host, 0);
484 }
485
486 /* This function sends an address (or partial address) to the
487 * NAND device. The address is used to select the source/destination for
488 * a NAND command. */
489 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
490 {
491 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
492
493 writew(addr, NFC_V1_V2_FLASH_ADDR);
494 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
495
496 /* Wait for operation to complete */
497 wait_op_done(host, islast);
498 }
499
500 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
501 {
502 struct nand_chip *nand_chip = mtd->priv;
503 struct mxc_nand_host *host = nand_chip->priv;
504 uint32_t tmp;
505
506 tmp = readl(NFC_V3_CONFIG1);
507 tmp &= ~(7 << 4);
508 writel(tmp, NFC_V3_CONFIG1);
509
510 /* transfer data from NFC ram to nand */
511 writel(ops, NFC_V3_LAUNCH);
512
513 wait_op_done(host, false);
514 }
515
516 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
517 {
518 struct nand_chip *nand_chip = mtd->priv;
519 struct mxc_nand_host *host = nand_chip->priv;
520
521 /* NANDFC buffer 0 is used for page read/write */
522 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
523
524 writew(ops, NFC_V1_V2_CONFIG2);
525
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
528 }
529
530 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
531 {
532 struct nand_chip *nand_chip = mtd->priv;
533 struct mxc_nand_host *host = nand_chip->priv;
534 int bufs, i;
535
536 if (mtd->writesize > 512)
537 bufs = 4;
538 else
539 bufs = 1;
540
541 for (i = 0; i < bufs; i++) {
542
543 /* NANDFC buffer 0 is used for page read/write */
544 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
545
546 writew(ops, NFC_V1_V2_CONFIG2);
547
548 /* Wait for operation to complete */
549 wait_op_done(host, true);
550 }
551 }
552
553 static void send_read_id_v3(struct mxc_nand_host *host)
554 {
555 /* Read ID into main buffer */
556 writel(NFC_ID, NFC_V3_LAUNCH);
557
558 wait_op_done(host, true);
559
560 memcpy32_fromio(host->data_buf, host->main_area0, 16);
561 }
562
563 /* Request the NANDFC to perform a read of the NAND device ID. */
564 static void send_read_id_v1_v2(struct mxc_nand_host *host)
565 {
566 /* NANDFC buffer 0 is used for device ID output */
567 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
568
569 writew(NFC_ID, NFC_V1_V2_CONFIG2);
570
571 /* Wait for operation to complete */
572 wait_op_done(host, true);
573
574 memcpy32_fromio(host->data_buf, host->main_area0, 16);
575 }
576
577 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
578 {
579 writew(NFC_STATUS, NFC_V3_LAUNCH);
580 wait_op_done(host, true);
581
582 return readl(NFC_V3_CONFIG1) >> 16;
583 }
584
585 /* This function requests the NANDFC to perform a read of the
586 * NAND device status and returns the current status. */
587 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
588 {
589 void __iomem *main_buf = host->main_area0;
590 uint32_t store;
591 uint16_t ret;
592
593 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
594
595 /*
596 * The device status is stored in main_area0. To
597 * prevent corruption of the buffer save the value
598 * and restore it afterwards.
599 */
600 store = readl(main_buf);
601
602 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
603 wait_op_done(host, true);
604
605 ret = readw(main_buf);
606
607 writel(store, main_buf);
608
609 return ret;
610 }
611
612 /* This functions is used by upper layer to checks if device is ready */
613 static int mxc_nand_dev_ready(struct mtd_info *mtd)
614 {
615 /*
616 * NFC handles R/B internally. Therefore, this function
617 * always returns status as ready.
618 */
619 return 1;
620 }
621
622 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
623 {
624 /*
625 * If HW ECC is enabled, we turn it on during init. There is
626 * no need to enable again here.
627 */
628 }
629
630 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
631 u_char *read_ecc, u_char *calc_ecc)
632 {
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
635
636 /*
637 * 1-Bit errors are automatically corrected in HW. No need for
638 * additional correction. 2-Bit errors cannot be corrected by
639 * HW ECC, so we need to return failure
640 */
641 uint16_t ecc_status = get_ecc_status_v1(host);
642
643 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
644 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
645 return -1;
646 }
647
648 return 0;
649 }
650
651 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
653 {
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u32 ecc_stat, err;
657 int no_subpages = 1;
658 int ret = 0;
659 u8 ecc_bit_mask, err_limit;
660
661 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
662 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
663
664 no_subpages = mtd->writesize >> 9;
665
666 ecc_stat = host->devtype_data->get_ecc_status(host);
667
668 do {
669 err = ecc_stat & ecc_bit_mask;
670 if (err > err_limit) {
671 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
672 return -1;
673 } else {
674 ret += err;
675 }
676 ecc_stat >>= 4;
677 } while (--no_subpages);
678
679 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
680
681 return ret;
682 }
683
684 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
685 u_char *ecc_code)
686 {
687 return 0;
688 }
689
690 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
691 {
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
694 uint8_t ret;
695
696 /* Check for status request */
697 if (host->status_request)
698 return host->devtype_data->get_dev_status(host) & 0xFF;
699
700 if (nand_chip->options & NAND_BUSWIDTH_16) {
701 /* only take the lower byte of each word */
702 ret = *(uint16_t *)(host->data_buf + host->buf_start);
703
704 host->buf_start += 2;
705 } else {
706 ret = *(uint8_t *)(host->data_buf + host->buf_start);
707 host->buf_start++;
708 }
709
710 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
711 return ret;
712 }
713
714 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
715 {
716 struct nand_chip *nand_chip = mtd->priv;
717 struct mxc_nand_host *host = nand_chip->priv;
718 uint16_t ret;
719
720 ret = *(uint16_t *)(host->data_buf + host->buf_start);
721 host->buf_start += 2;
722
723 return ret;
724 }
725
726 /* Write data of length len to buffer buf. The data to be
727 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
728 * Operation by the NFC, the data is written to NAND Flash */
729 static void mxc_nand_write_buf(struct mtd_info *mtd,
730 const u_char *buf, int len)
731 {
732 struct nand_chip *nand_chip = mtd->priv;
733 struct mxc_nand_host *host = nand_chip->priv;
734 u16 col = host->buf_start;
735 int n = mtd->oobsize + mtd->writesize - col;
736
737 n = min(n, len);
738
739 memcpy(host->data_buf + col, buf, n);
740
741 host->buf_start += n;
742 }
743
744 /* Read the data buffer from the NAND Flash. To read the data from NAND
745 * Flash first the data output cycle is initiated by the NFC, which copies
746 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
747 */
748 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
749 {
750 struct nand_chip *nand_chip = mtd->priv;
751 struct mxc_nand_host *host = nand_chip->priv;
752 u16 col = host->buf_start;
753 int n = mtd->oobsize + mtd->writesize - col;
754
755 n = min(n, len);
756
757 memcpy(buf, host->data_buf + col, n);
758
759 host->buf_start += n;
760 }
761
762 /* This function is used by upper layer for select and
763 * deselect of the NAND chip */
764 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
765 {
766 struct nand_chip *nand_chip = mtd->priv;
767 struct mxc_nand_host *host = nand_chip->priv;
768
769 if (chip == -1) {
770 /* Disable the NFC clock */
771 if (host->clk_act) {
772 clk_disable_unprepare(host->clk);
773 host->clk_act = 0;
774 }
775 return;
776 }
777
778 if (!host->clk_act) {
779 /* Enable the NFC clock */
780 clk_prepare_enable(host->clk);
781 host->clk_act = 1;
782 }
783 }
784
785 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
786 {
787 struct nand_chip *nand_chip = mtd->priv;
788 struct mxc_nand_host *host = nand_chip->priv;
789
790 if (chip == -1) {
791 /* Disable the NFC clock */
792 if (host->clk_act) {
793 clk_disable_unprepare(host->clk);
794 host->clk_act = 0;
795 }
796 return;
797 }
798
799 if (!host->clk_act) {
800 /* Enable the NFC clock */
801 clk_prepare_enable(host->clk);
802 host->clk_act = 1;
803 }
804
805 host->active_cs = chip;
806 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
807 }
808
809 /*
810 * Function to transfer data to/from spare area.
811 */
812 static void copy_spare(struct mtd_info *mtd, bool bfrom)
813 {
814 struct nand_chip *this = mtd->priv;
815 struct mxc_nand_host *host = this->priv;
816 u16 i, j;
817 u16 n = mtd->writesize >> 9;
818 u8 *d = host->data_buf + mtd->writesize;
819 u8 __iomem *s = host->spare0;
820 u16 t = host->devtype_data->spare_len;
821
822 j = (mtd->oobsize / n >> 1) << 1;
823
824 if (bfrom) {
825 for (i = 0; i < n - 1; i++)
826 memcpy32_fromio(d + i * j, s + i * t, j);
827
828 /* the last section */
829 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
830 } else {
831 for (i = 0; i < n - 1; i++)
832 memcpy32_toio(&s[i * t], &d[i * j], j);
833
834 /* the last section */
835 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
836 }
837 }
838
839 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
840 {
841 struct nand_chip *nand_chip = mtd->priv;
842 struct mxc_nand_host *host = nand_chip->priv;
843
844 /* Write out column address, if necessary */
845 if (column != -1) {
846 /*
847 * MXC NANDFC can only perform full page+spare or
848 * spare-only read/write. When the upper layers
849 * perform a read/write buf operation, the saved column
850 * address is used to index into the full page.
851 */
852 host->devtype_data->send_addr(host, 0, page_addr == -1);
853 if (mtd->writesize > 512)
854 /* another col addr cycle for 2k page */
855 host->devtype_data->send_addr(host, 0, false);
856 }
857
858 /* Write out page address, if necessary */
859 if (page_addr != -1) {
860 /* paddr_0 - p_addr_7 */
861 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
862
863 if (mtd->writesize > 512) {
864 if (mtd->size >= 0x10000000) {
865 /* paddr_8 - paddr_15 */
866 host->devtype_data->send_addr(host,
867 (page_addr >> 8) & 0xff,
868 false);
869 host->devtype_data->send_addr(host,
870 (page_addr >> 16) & 0xff,
871 true);
872 } else
873 /* paddr_8 - paddr_15 */
874 host->devtype_data->send_addr(host,
875 (page_addr >> 8) & 0xff, true);
876 } else {
877 /* One more address cycle for higher density devices */
878 if (mtd->size >= 0x4000000) {
879 /* paddr_8 - paddr_15 */
880 host->devtype_data->send_addr(host,
881 (page_addr >> 8) & 0xff,
882 false);
883 host->devtype_data->send_addr(host,
884 (page_addr >> 16) & 0xff,
885 true);
886 } else
887 /* paddr_8 - paddr_15 */
888 host->devtype_data->send_addr(host,
889 (page_addr >> 8) & 0xff, true);
890 }
891 }
892 }
893
894 /*
895 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
896 * on how much oob the nand chip has. For 8bit ecc we need at least
897 * 26 bytes of oob data per 512 byte block.
898 */
899 static int get_eccsize(struct mtd_info *mtd)
900 {
901 int oobbytes_per_512 = 0;
902
903 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
904
905 if (oobbytes_per_512 < 26)
906 return 4;
907 else
908 return 8;
909 }
910
911 static void preset_v1(struct mtd_info *mtd)
912 {
913 struct nand_chip *nand_chip = mtd->priv;
914 struct mxc_nand_host *host = nand_chip->priv;
915 uint16_t config1 = 0;
916
917 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
918 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
919
920 if (!host->devtype_data->irqpending_quirk)
921 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
922
923 host->eccsize = 1;
924
925 writew(config1, NFC_V1_V2_CONFIG1);
926 /* preset operation */
927
928 /* Unlock the internal RAM Buffer */
929 writew(0x2, NFC_V1_V2_CONFIG);
930
931 /* Blocks to be unlocked */
932 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
933 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
934
935 /* Unlock Block Command for given address range */
936 writew(0x4, NFC_V1_V2_WRPROT);
937 }
938
939 static void preset_v2(struct mtd_info *mtd)
940 {
941 struct nand_chip *nand_chip = mtd->priv;
942 struct mxc_nand_host *host = nand_chip->priv;
943 uint16_t config1 = 0;
944
945 config1 |= NFC_V2_CONFIG1_FP_INT;
946
947 if (!host->devtype_data->irqpending_quirk)
948 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
949
950 if (mtd->writesize) {
951 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
952
953 if (nand_chip->ecc.mode == NAND_ECC_HW)
954 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
955
956 host->eccsize = get_eccsize(mtd);
957 if (host->eccsize == 4)
958 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
959
960 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
961 } else {
962 host->eccsize = 1;
963 }
964
965 writew(config1, NFC_V1_V2_CONFIG1);
966 /* preset operation */
967
968 /* Unlock the internal RAM Buffer */
969 writew(0x2, NFC_V1_V2_CONFIG);
970
971 /* Blocks to be unlocked */
972 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
973 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
974 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
975 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
976 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
977 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
978 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
979 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
980
981 /* Unlock Block Command for given address range */
982 writew(0x4, NFC_V1_V2_WRPROT);
983 }
984
985 static void preset_v3(struct mtd_info *mtd)
986 {
987 struct nand_chip *chip = mtd->priv;
988 struct mxc_nand_host *host = chip->priv;
989 uint32_t config2, config3;
990 int i, addr_phases;
991
992 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
993 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
994
995 /* Unlock the internal RAM Buffer */
996 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
997 NFC_V3_WRPROT);
998
999 /* Blocks to be unlocked */
1000 for (i = 0; i < NAND_MAX_CHIPS; i++)
1001 writel(0x0 | (0xffff << 16),
1002 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1003
1004 writel(0, NFC_V3_IPC);
1005
1006 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1007 NFC_V3_CONFIG2_2CMD_PHASES |
1008 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1009 NFC_V3_CONFIG2_ST_CMD(0x70) |
1010 NFC_V3_CONFIG2_INT_MSK |
1011 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1012
1013 addr_phases = fls(chip->pagemask) >> 3;
1014
1015 if (mtd->writesize == 2048) {
1016 config2 |= NFC_V3_CONFIG2_PS_2048;
1017 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1018 } else if (mtd->writesize == 4096) {
1019 config2 |= NFC_V3_CONFIG2_PS_4096;
1020 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1021 } else {
1022 config2 |= NFC_V3_CONFIG2_PS_512;
1023 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1024 }
1025
1026 if (mtd->writesize) {
1027 if (chip->ecc.mode == NAND_ECC_HW)
1028 config2 |= NFC_V3_CONFIG2_ECC_EN;
1029
1030 config2 |= NFC_V3_CONFIG2_PPB(
1031 ffs(mtd->erasesize / mtd->writesize) - 6,
1032 host->devtype_data->ppb_shift);
1033 host->eccsize = get_eccsize(mtd);
1034 if (host->eccsize == 8)
1035 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1036 }
1037
1038 writel(config2, NFC_V3_CONFIG2);
1039
1040 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1041 NFC_V3_CONFIG3_NO_SDMA |
1042 NFC_V3_CONFIG3_RBB_MODE |
1043 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1044 NFC_V3_CONFIG3_ADD_OP(0);
1045
1046 if (!(chip->options & NAND_BUSWIDTH_16))
1047 config3 |= NFC_V3_CONFIG3_FW8;
1048
1049 writel(config3, NFC_V3_CONFIG3);
1050
1051 writel(0, NFC_V3_DELAY_LINE);
1052 }
1053
1054 /* Used by the upper layer to write command to NAND Flash for
1055 * different operations to be carried out on NAND Flash */
1056 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1057 int column, int page_addr)
1058 {
1059 struct nand_chip *nand_chip = mtd->priv;
1060 struct mxc_nand_host *host = nand_chip->priv;
1061
1062 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1063 command, column, page_addr);
1064
1065 /* Reset command state information */
1066 host->status_request = false;
1067
1068 /* Command pre-processing step */
1069 switch (command) {
1070 case NAND_CMD_RESET:
1071 host->devtype_data->preset(mtd);
1072 host->devtype_data->send_cmd(host, command, false);
1073 break;
1074
1075 case NAND_CMD_STATUS:
1076 host->buf_start = 0;
1077 host->status_request = true;
1078
1079 host->devtype_data->send_cmd(host, command, true);
1080 mxc_do_addr_cycle(mtd, column, page_addr);
1081 break;
1082
1083 case NAND_CMD_READ0:
1084 case NAND_CMD_READOOB:
1085 if (command == NAND_CMD_READ0)
1086 host->buf_start = column;
1087 else
1088 host->buf_start = column + mtd->writesize;
1089
1090 command = NAND_CMD_READ0; /* only READ0 is valid */
1091
1092 host->devtype_data->send_cmd(host, command, false);
1093 mxc_do_addr_cycle(mtd, column, page_addr);
1094
1095 if (mtd->writesize > 512)
1096 host->devtype_data->send_cmd(host,
1097 NAND_CMD_READSTART, true);
1098
1099 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1100
1101 memcpy32_fromio(host->data_buf, host->main_area0,
1102 mtd->writesize);
1103 copy_spare(mtd, true);
1104 break;
1105
1106 case NAND_CMD_SEQIN:
1107 if (column >= mtd->writesize)
1108 /* call ourself to read a page */
1109 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1110
1111 host->buf_start = column;
1112
1113 host->devtype_data->send_cmd(host, command, false);
1114 mxc_do_addr_cycle(mtd, column, page_addr);
1115 break;
1116
1117 case NAND_CMD_PAGEPROG:
1118 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1119 copy_spare(mtd, false);
1120 host->devtype_data->send_page(mtd, NFC_INPUT);
1121 host->devtype_data->send_cmd(host, command, true);
1122 mxc_do_addr_cycle(mtd, column, page_addr);
1123 break;
1124
1125 case NAND_CMD_READID:
1126 host->devtype_data->send_cmd(host, command, true);
1127 mxc_do_addr_cycle(mtd, column, page_addr);
1128 host->devtype_data->send_read_id(host);
1129 host->buf_start = column;
1130 break;
1131
1132 case NAND_CMD_ERASE1:
1133 case NAND_CMD_ERASE2:
1134 host->devtype_data->send_cmd(host, command, false);
1135 mxc_do_addr_cycle(mtd, column, page_addr);
1136
1137 break;
1138 }
1139 }
1140
1141 /*
1142 * The generic flash bbt decriptors overlap with our ecc
1143 * hardware, so define some i.MX specific ones.
1144 */
1145 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1146 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1147
1148 static struct nand_bbt_descr bbt_main_descr = {
1149 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1150 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1151 .offs = 0,
1152 .len = 4,
1153 .veroffs = 4,
1154 .maxblocks = 4,
1155 .pattern = bbt_pattern,
1156 };
1157
1158 static struct nand_bbt_descr bbt_mirror_descr = {
1159 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1160 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1161 .offs = 0,
1162 .len = 4,
1163 .veroffs = 4,
1164 .maxblocks = 4,
1165 .pattern = mirror_pattern,
1166 };
1167
1168 /* v1 + irqpending_quirk: i.MX21 */
1169 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1170 .preset = preset_v1,
1171 .send_cmd = send_cmd_v1_v2,
1172 .send_addr = send_addr_v1_v2,
1173 .send_page = send_page_v1,
1174 .send_read_id = send_read_id_v1_v2,
1175 .get_dev_status = get_dev_status_v1_v2,
1176 .check_int = check_int_v1_v2,
1177 .irq_control = irq_control_v1_v2,
1178 .get_ecc_status = get_ecc_status_v1,
1179 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1180 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1181 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1182 .select_chip = mxc_nand_select_chip_v1_v3,
1183 .correct_data = mxc_nand_correct_data_v1,
1184 .irqpending_quirk = 1,
1185 .needs_ip = 0,
1186 .regs_offset = 0xe00,
1187 .spare0_offset = 0x800,
1188 .spare_len = 16,
1189 .eccbytes = 3,
1190 .eccsize = 1,
1191 };
1192
1193 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1194 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1195 .preset = preset_v1,
1196 .send_cmd = send_cmd_v1_v2,
1197 .send_addr = send_addr_v1_v2,
1198 .send_page = send_page_v1,
1199 .send_read_id = send_read_id_v1_v2,
1200 .get_dev_status = get_dev_status_v1_v2,
1201 .check_int = check_int_v1_v2,
1202 .irq_control = irq_control_v1_v2,
1203 .get_ecc_status = get_ecc_status_v1,
1204 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1205 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1206 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1207 .select_chip = mxc_nand_select_chip_v1_v3,
1208 .correct_data = mxc_nand_correct_data_v1,
1209 .irqpending_quirk = 0,
1210 .needs_ip = 0,
1211 .regs_offset = 0xe00,
1212 .spare0_offset = 0x800,
1213 .axi_offset = 0,
1214 .spare_len = 16,
1215 .eccbytes = 3,
1216 .eccsize = 1,
1217 };
1218
1219 /* v21: i.MX25, i.MX35 */
1220 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1221 .preset = preset_v2,
1222 .send_cmd = send_cmd_v1_v2,
1223 .send_addr = send_addr_v1_v2,
1224 .send_page = send_page_v2,
1225 .send_read_id = send_read_id_v1_v2,
1226 .get_dev_status = get_dev_status_v1_v2,
1227 .check_int = check_int_v1_v2,
1228 .irq_control = irq_control_v1_v2,
1229 .get_ecc_status = get_ecc_status_v2,
1230 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1231 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1232 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1233 .select_chip = mxc_nand_select_chip_v2,
1234 .correct_data = mxc_nand_correct_data_v2_v3,
1235 .irqpending_quirk = 0,
1236 .needs_ip = 0,
1237 .regs_offset = 0x1e00,
1238 .spare0_offset = 0x1000,
1239 .axi_offset = 0,
1240 .spare_len = 64,
1241 .eccbytes = 9,
1242 .eccsize = 0,
1243 };
1244
1245 /* v3.2a: i.MX51 */
1246 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1247 .preset = preset_v3,
1248 .send_cmd = send_cmd_v3,
1249 .send_addr = send_addr_v3,
1250 .send_page = send_page_v3,
1251 .send_read_id = send_read_id_v3,
1252 .get_dev_status = get_dev_status_v3,
1253 .check_int = check_int_v3,
1254 .irq_control = irq_control_v3,
1255 .get_ecc_status = get_ecc_status_v3,
1256 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1257 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1258 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1259 .select_chip = mxc_nand_select_chip_v1_v3,
1260 .correct_data = mxc_nand_correct_data_v2_v3,
1261 .irqpending_quirk = 0,
1262 .needs_ip = 1,
1263 .regs_offset = 0,
1264 .spare0_offset = 0x1000,
1265 .axi_offset = 0x1e00,
1266 .spare_len = 64,
1267 .eccbytes = 0,
1268 .eccsize = 0,
1269 .ppb_shift = 7,
1270 };
1271
1272 /* v3.2b: i.MX53 */
1273 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1274 .preset = preset_v3,
1275 .send_cmd = send_cmd_v3,
1276 .send_addr = send_addr_v3,
1277 .send_page = send_page_v3,
1278 .send_read_id = send_read_id_v3,
1279 .get_dev_status = get_dev_status_v3,
1280 .check_int = check_int_v3,
1281 .irq_control = irq_control_v3,
1282 .get_ecc_status = get_ecc_status_v3,
1283 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1284 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1285 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1286 .select_chip = mxc_nand_select_chip_v1_v3,
1287 .correct_data = mxc_nand_correct_data_v2_v3,
1288 .irqpending_quirk = 0,
1289 .needs_ip = 1,
1290 .regs_offset = 0,
1291 .spare0_offset = 0x1000,
1292 .axi_offset = 0x1e00,
1293 .spare_len = 64,
1294 .eccbytes = 0,
1295 .eccsize = 0,
1296 .ppb_shift = 8,
1297 };
1298
1299 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1300 {
1301 return host->devtype_data == &imx21_nand_devtype_data;
1302 }
1303
1304 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1305 {
1306 return host->devtype_data == &imx27_nand_devtype_data;
1307 }
1308
1309 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1310 {
1311 return host->devtype_data == &imx25_nand_devtype_data;
1312 }
1313
1314 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1315 {
1316 return host->devtype_data == &imx51_nand_devtype_data;
1317 }
1318
1319 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1320 {
1321 return host->devtype_data == &imx53_nand_devtype_data;
1322 }
1323
1324 static struct platform_device_id mxcnd_devtype[] = {
1325 {
1326 .name = "imx21-nand",
1327 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1328 }, {
1329 .name = "imx27-nand",
1330 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1331 }, {
1332 .name = "imx25-nand",
1333 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1334 }, {
1335 .name = "imx51-nand",
1336 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1337 }, {
1338 .name = "imx53-nand",
1339 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1340 }, {
1341 /* sentinel */
1342 }
1343 };
1344 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1345
1346 #ifdef CONFIG_OF_MTD
1347 static const struct of_device_id mxcnd_dt_ids[] = {
1348 {
1349 .compatible = "fsl,imx21-nand",
1350 .data = &imx21_nand_devtype_data,
1351 }, {
1352 .compatible = "fsl,imx27-nand",
1353 .data = &imx27_nand_devtype_data,
1354 }, {
1355 .compatible = "fsl,imx25-nand",
1356 .data = &imx25_nand_devtype_data,
1357 }, {
1358 .compatible = "fsl,imx51-nand",
1359 .data = &imx51_nand_devtype_data,
1360 }, {
1361 .compatible = "fsl,imx53-nand",
1362 .data = &imx53_nand_devtype_data,
1363 },
1364 { /* sentinel */ }
1365 };
1366
1367 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1368 {
1369 struct device_node *np = host->dev->of_node;
1370 struct mxc_nand_platform_data *pdata = &host->pdata;
1371 const struct of_device_id *of_id =
1372 of_match_device(mxcnd_dt_ids, host->dev);
1373 int buswidth;
1374
1375 if (!np)
1376 return 1;
1377
1378 if (of_get_nand_ecc_mode(np) >= 0)
1379 pdata->hw_ecc = 1;
1380
1381 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1382
1383 buswidth = of_get_nand_bus_width(np);
1384 if (buswidth < 0)
1385 return buswidth;
1386
1387 pdata->width = buswidth / 8;
1388
1389 host->devtype_data = of_id->data;
1390
1391 return 0;
1392 }
1393 #else
1394 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1395 {
1396 return 1;
1397 }
1398 #endif
1399
1400 static int mxcnd_probe(struct platform_device *pdev)
1401 {
1402 struct nand_chip *this;
1403 struct mtd_info *mtd;
1404 struct mxc_nand_host *host;
1405 struct resource *res;
1406 int err = 0;
1407
1408 /* Allocate memory for MTD device structure and private data */
1409 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1410 GFP_KERNEL);
1411 if (!host)
1412 return -ENOMEM;
1413
1414 /* allocate a temporary buffer for the nand_scan_ident() */
1415 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1416 if (!host->data_buf)
1417 return -ENOMEM;
1418
1419 host->dev = &pdev->dev;
1420 /* structures must be linked */
1421 this = &host->nand;
1422 mtd = &host->mtd;
1423 mtd->priv = this;
1424 mtd->owner = THIS_MODULE;
1425 mtd->dev.parent = &pdev->dev;
1426 mtd->name = DRIVER_NAME;
1427
1428 /* 50 us command delay time */
1429 this->chip_delay = 5;
1430
1431 this->priv = host;
1432 this->dev_ready = mxc_nand_dev_ready;
1433 this->cmdfunc = mxc_nand_command;
1434 this->read_byte = mxc_nand_read_byte;
1435 this->read_word = mxc_nand_read_word;
1436 this->write_buf = mxc_nand_write_buf;
1437 this->read_buf = mxc_nand_read_buf;
1438
1439 host->clk = devm_clk_get(&pdev->dev, NULL);
1440 if (IS_ERR(host->clk))
1441 return PTR_ERR(host->clk);
1442
1443 err = mxcnd_probe_dt(host);
1444 if (err > 0) {
1445 struct mxc_nand_platform_data *pdata =
1446 dev_get_platdata(&pdev->dev);
1447 if (pdata) {
1448 host->pdata = *pdata;
1449 host->devtype_data = (struct mxc_nand_devtype_data *)
1450 pdev->id_entry->driver_data;
1451 } else {
1452 err = -ENODEV;
1453 }
1454 }
1455 if (err < 0)
1456 return err;
1457
1458 if (host->devtype_data->needs_ip) {
1459 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1460 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1461 if (IS_ERR(host->regs_ip))
1462 return PTR_ERR(host->regs_ip);
1463
1464 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1465 } else {
1466 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1467 }
1468
1469 host->base = devm_ioremap_resource(&pdev->dev, res);
1470 if (IS_ERR(host->base))
1471 return PTR_ERR(host->base);
1472
1473 host->main_area0 = host->base;
1474
1475 if (host->devtype_data->regs_offset)
1476 host->regs = host->base + host->devtype_data->regs_offset;
1477 host->spare0 = host->base + host->devtype_data->spare0_offset;
1478 if (host->devtype_data->axi_offset)
1479 host->regs_axi = host->base + host->devtype_data->axi_offset;
1480
1481 this->ecc.bytes = host->devtype_data->eccbytes;
1482 host->eccsize = host->devtype_data->eccsize;
1483
1484 this->select_chip = host->devtype_data->select_chip;
1485 this->ecc.size = 512;
1486 this->ecc.layout = host->devtype_data->ecclayout_512;
1487
1488 if (host->pdata.hw_ecc) {
1489 this->ecc.calculate = mxc_nand_calculate_ecc;
1490 this->ecc.hwctl = mxc_nand_enable_hwecc;
1491 this->ecc.correct = host->devtype_data->correct_data;
1492 this->ecc.mode = NAND_ECC_HW;
1493 } else {
1494 this->ecc.mode = NAND_ECC_SOFT;
1495 }
1496
1497 /* NAND bus width determines access functions used by upper layer */
1498 if (host->pdata.width == 2)
1499 this->options |= NAND_BUSWIDTH_16;
1500
1501 if (host->pdata.flash_bbt) {
1502 this->bbt_td = &bbt_main_descr;
1503 this->bbt_md = &bbt_mirror_descr;
1504 /* update flash based bbt */
1505 this->bbt_options |= NAND_BBT_USE_FLASH;
1506 }
1507
1508 init_completion(&host->op_completion);
1509
1510 host->irq = platform_get_irq(pdev, 0);
1511 if (host->irq < 0)
1512 return host->irq;
1513
1514 /*
1515 * Use host->devtype_data->irq_control() here instead of irq_control()
1516 * because we must not disable_irq_nosync without having requested the
1517 * irq.
1518 */
1519 host->devtype_data->irq_control(host, 0);
1520
1521 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1522 0, DRIVER_NAME, host);
1523 if (err)
1524 return err;
1525
1526 err = clk_prepare_enable(host->clk);
1527 if (err)
1528 return err;
1529 host->clk_act = 1;
1530
1531 /*
1532 * Now that we "own" the interrupt make sure the interrupt mask bit is
1533 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1534 * on this machine.
1535 */
1536 if (host->devtype_data->irqpending_quirk) {
1537 disable_irq_nosync(host->irq);
1538 host->devtype_data->irq_control(host, 1);
1539 }
1540
1541 /* first scan to find the device and get the page size */
1542 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1543 err = -ENXIO;
1544 goto escan;
1545 }
1546
1547 /* allocate the right size buffer now */
1548 devm_kfree(&pdev->dev, (void *)host->data_buf);
1549 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1550 GFP_KERNEL);
1551 if (!host->data_buf) {
1552 err = -ENOMEM;
1553 goto escan;
1554 }
1555
1556 /* Call preset again, with correct writesize this time */
1557 host->devtype_data->preset(mtd);
1558
1559 if (mtd->writesize == 2048)
1560 this->ecc.layout = host->devtype_data->ecclayout_2k;
1561 else if (mtd->writesize == 4096)
1562 this->ecc.layout = host->devtype_data->ecclayout_4k;
1563
1564 if (this->ecc.mode == NAND_ECC_HW) {
1565 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1566 this->ecc.strength = 1;
1567 else
1568 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1569 }
1570
1571 /* second phase scan */
1572 if (nand_scan_tail(mtd)) {
1573 err = -ENXIO;
1574 goto escan;
1575 }
1576
1577 /* Register the partitions */
1578 mtd_device_parse_register(mtd, part_probes,
1579 &(struct mtd_part_parser_data){
1580 .of_node = pdev->dev.of_node,
1581 },
1582 host->pdata.parts,
1583 host->pdata.nr_parts);
1584
1585 platform_set_drvdata(pdev, host);
1586
1587 return 0;
1588
1589 escan:
1590 if (host->clk_act)
1591 clk_disable_unprepare(host->clk);
1592
1593 return err;
1594 }
1595
1596 static int mxcnd_remove(struct platform_device *pdev)
1597 {
1598 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1599
1600 nand_release(&host->mtd);
1601 if (host->clk_act)
1602 clk_disable_unprepare(host->clk);
1603
1604 return 0;
1605 }
1606
1607 static struct platform_driver mxcnd_driver = {
1608 .driver = {
1609 .name = DRIVER_NAME,
1610 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1611 },
1612 .id_table = mxcnd_devtype,
1613 .probe = mxcnd_probe,
1614 .remove = mxcnd_remove,
1615 };
1616 module_platform_driver(mxcnd_driver);
1617
1618 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1619 MODULE_DESCRIPTION("MXC NAND MTD driver");
1620 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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