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mxc_nand: merge send_read_page and send_prog_page
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36
37 #define DRIVER_NAME "mxc_nand"
38
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
54
55 /* Addresses for NFC RAM BUFFER Main area 0 */
56 #define MAIN_AREA0 0x000
57 #define MAIN_AREA1 0x200
58 #define MAIN_AREA2 0x400
59 #define MAIN_AREA3 0x600
60
61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
62 #define SPARE_AREA0 0x800
63 #define SPARE_AREA1 0x810
64 #define SPARE_AREA2 0x820
65 #define SPARE_AREA3 0x830
66
67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
69 #define NFC_CMD 0x1
70
71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
73 #define NFC_ADDR 0x2
74
75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
77 #define NFC_INPUT 0x4
78
79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81 #define NFC_OUTPUT 0x8
82
83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
85 #define NFC_ID 0x10
86
87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89 #define NFC_STATUS 0x20
90
91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
92 * Status operation */
93 #define NFC_INT 0x8000
94
95 #define NFC_SP_EN (1 << 2)
96 #define NFC_ECC_EN (1 << 3)
97 #define NFC_INT_MSK (1 << 4)
98 #define NFC_BIG (1 << 5)
99 #define NFC_RST (1 << 6)
100 #define NFC_CE (1 << 7)
101 #define NFC_ONE_CYCLE (1 << 8)
102
103 struct mxc_nand_host {
104 struct mtd_info mtd;
105 struct nand_chip nand;
106 struct mtd_partition *parts;
107 struct device *dev;
108
109 void __iomem *regs;
110 int spare_only;
111 int status_request;
112 int pagesize_2k;
113 uint16_t col_addr;
114 struct clk *clk;
115 int clk_act;
116 int irq;
117
118 wait_queue_head_t irq_waitq;
119 };
120
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
123 /* Macros to get byte and bit positions of ECC */
124 #define COLPOS(x) ((x) >> 3)
125 #define BITPOS(x) ((x) & 0xf)
126
127 /* Define single bit Error positions in Main & Spare area */
128 #define MAIN_SINGLEBIT_ERROR 0x4
129 #define SPARE_SINGLEBIT_ERROR 0x1
130
131 /* OOB placement block for use with hardware ecc generation */
132 static struct nand_ecclayout nand_hw_eccoob_smallpage = {
133 .eccbytes = 5,
134 .eccpos = {6, 7, 8, 9, 10},
135 .oobfree = {{0, 5}, {12, 4}, }
136 };
137
138 static struct nand_ecclayout nand_hw_eccoob_largepage = {
139 .eccbytes = 20,
140 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
141 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
142 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
143 };
144
145 #ifdef CONFIG_MTD_PARTITIONS
146 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
147 #endif
148
149 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
150 {
151 struct mxc_nand_host *host = dev_id;
152
153 uint16_t tmp;
154
155 tmp = readw(host->regs + NFC_CONFIG1);
156 tmp |= NFC_INT_MSK; /* Disable interrupt */
157 writew(tmp, host->regs + NFC_CONFIG1);
158
159 wake_up(&host->irq_waitq);
160
161 return IRQ_HANDLED;
162 }
163
164 /* This function polls the NANDFC to wait for the basic operation to
165 * complete by checking the INT bit of config2 register.
166 */
167 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
168 uint16_t param, int useirq)
169 {
170 uint32_t tmp;
171
172 if (useirq) {
173 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
174
175 tmp = readw(host->regs + NFC_CONFIG1);
176 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
177 writew(tmp, host->regs + NFC_CONFIG1);
178
179 wait_event(host->irq_waitq,
180 readw(host->regs + NFC_CONFIG2) & NFC_INT);
181
182 tmp = readw(host->regs + NFC_CONFIG2);
183 tmp &= ~NFC_INT;
184 writew(tmp, host->regs + NFC_CONFIG2);
185 }
186 } else {
187 while (max_retries-- > 0) {
188 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
189 tmp = readw(host->regs + NFC_CONFIG2);
190 tmp &= ~NFC_INT;
191 writew(tmp, host->regs + NFC_CONFIG2);
192 break;
193 }
194 udelay(1);
195 }
196 if (max_retries < 0)
197 DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
198 __func__, param);
199 }
200 }
201
202 /* This function issues the specified command to the NAND device and
203 * waits for completion. */
204 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
205 {
206 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
207
208 writew(cmd, host->regs + NFC_FLASH_CMD);
209 writew(NFC_CMD, host->regs + NFC_CONFIG2);
210
211 /* Wait for operation to complete */
212 wait_op_done(host, TROP_US_DELAY, cmd, useirq);
213 }
214
215 /* This function sends an address (or partial address) to the
216 * NAND device. The address is used to select the source/destination for
217 * a NAND command. */
218 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
219 {
220 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
221
222 writew(addr, host->regs + NFC_FLASH_ADDR);
223 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
224
225 /* Wait for operation to complete */
226 wait_op_done(host, TROP_US_DELAY, addr, islast);
227 }
228
229 static void send_page(struct mxc_nand_host *host, uint8_t buf_id,
230 int spare_only, unsigned int ops)
231 {
232 DEBUG(MTD_DEBUG_LEVEL3, "send_page (%d)\n", spare_only);
233
234 /* NANDFC buffer 0 is used for page read/write */
235 writew(buf_id, host->regs + NFC_BUF_ADDR);
236
237 /* Configure spare or page+spare access */
238 if (!host->pagesize_2k) {
239 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
240 if (spare_only)
241 config1 |= NFC_SP_EN;
242 else
243 config1 &= ~(NFC_SP_EN);
244 writew(config1, host->regs + NFC_CONFIG1);
245 }
246
247 writew(ops, host->regs + NFC_CONFIG2);
248
249 /* Wait for operation to complete */
250 wait_op_done(host, TROP_US_DELAY, spare_only, true);
251 }
252
253 /* Request the NANDFC to perform a read of the NAND device ID. */
254 static void send_read_id(struct mxc_nand_host *host)
255 {
256 struct nand_chip *this = &host->nand;
257 uint16_t tmp;
258
259 /* NANDFC buffer 0 is used for device ID output */
260 writew(0x0, host->regs + NFC_BUF_ADDR);
261
262 /* Read ID into main buffer */
263 tmp = readw(host->regs + NFC_CONFIG1);
264 tmp &= ~NFC_SP_EN;
265 writew(tmp, host->regs + NFC_CONFIG1);
266
267 writew(NFC_ID, host->regs + NFC_CONFIG2);
268
269 /* Wait for operation to complete */
270 wait_op_done(host, TROP_US_DELAY, 0, true);
271
272 if (this->options & NAND_BUSWIDTH_16) {
273 void __iomem *main_buf = host->regs + MAIN_AREA0;
274 /* compress the ID info */
275 writeb(readb(main_buf + 2), main_buf + 1);
276 writeb(readb(main_buf + 4), main_buf + 2);
277 writeb(readb(main_buf + 6), main_buf + 3);
278 writeb(readb(main_buf + 8), main_buf + 4);
279 writeb(readb(main_buf + 10), main_buf + 5);
280 }
281 }
282
283 /* This function requests the NANDFC to perform a read of the
284 * NAND device status and returns the current status. */
285 static uint16_t get_dev_status(struct mxc_nand_host *host)
286 {
287 void __iomem *main_buf = host->regs + MAIN_AREA1;
288 uint32_t store;
289 uint16_t ret, tmp;
290 /* Issue status request to NAND device */
291
292 /* store the main area1 first word, later do recovery */
293 store = readl(main_buf);
294 /* NANDFC buffer 1 is used for device status to prevent
295 * corruption of read/write buffer on status requests. */
296 writew(1, host->regs + NFC_BUF_ADDR);
297
298 /* Read status into main buffer */
299 tmp = readw(host->regs + NFC_CONFIG1);
300 tmp &= ~NFC_SP_EN;
301 writew(tmp, host->regs + NFC_CONFIG1);
302
303 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
304
305 /* Wait for operation to complete */
306 wait_op_done(host, TROP_US_DELAY, 0, true);
307
308 /* Status is placed in first word of main buffer */
309 /* get status, then recovery area 1 data */
310 ret = readw(main_buf);
311 writel(store, main_buf);
312
313 return ret;
314 }
315
316 /* This functions is used by upper layer to checks if device is ready */
317 static int mxc_nand_dev_ready(struct mtd_info *mtd)
318 {
319 /*
320 * NFC handles R/B internally. Therefore, this function
321 * always returns status as ready.
322 */
323 return 1;
324 }
325
326 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
327 {
328 /*
329 * If HW ECC is enabled, we turn it on during init. There is
330 * no need to enable again here.
331 */
332 }
333
334 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
335 u_char *read_ecc, u_char *calc_ecc)
336 {
337 struct nand_chip *nand_chip = mtd->priv;
338 struct mxc_nand_host *host = nand_chip->priv;
339
340 /*
341 * 1-Bit errors are automatically corrected in HW. No need for
342 * additional correction. 2-Bit errors cannot be corrected by
343 * HW ECC, so we need to return failure
344 */
345 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
346
347 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
348 DEBUG(MTD_DEBUG_LEVEL0,
349 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
350 return -1;
351 }
352
353 return 0;
354 }
355
356 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
357 u_char *ecc_code)
358 {
359 return 0;
360 }
361
362 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
363 {
364 struct nand_chip *nand_chip = mtd->priv;
365 struct mxc_nand_host *host = nand_chip->priv;
366 uint8_t ret = 0;
367 uint16_t col, rd_word;
368 uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
369 uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
370
371 /* Check for status request */
372 if (host->status_request)
373 return get_dev_status(host) & 0xFF;
374
375 /* Get column for 16-bit access */
376 col = host->col_addr >> 1;
377
378 /* If we are accessing the spare region */
379 if (host->spare_only)
380 rd_word = readw(&spare_buf[col]);
381 else
382 rd_word = readw(&main_buf[col]);
383
384 /* Pick upper/lower byte of word from RAM buffer */
385 if (host->col_addr & 0x1)
386 ret = (rd_word >> 8) & 0xFF;
387 else
388 ret = rd_word & 0xFF;
389
390 /* Update saved column address */
391 host->col_addr++;
392
393 return ret;
394 }
395
396 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
397 {
398 struct nand_chip *nand_chip = mtd->priv;
399 struct mxc_nand_host *host = nand_chip->priv;
400 uint16_t col, rd_word, ret;
401 uint16_t __iomem *p;
402
403 DEBUG(MTD_DEBUG_LEVEL3,
404 "mxc_nand_read_word(col = %d)\n", host->col_addr);
405
406 col = host->col_addr;
407 /* Adjust saved column address */
408 if (col < mtd->writesize && host->spare_only)
409 col += mtd->writesize;
410
411 if (col < mtd->writesize)
412 p = (host->regs + MAIN_AREA0) + (col >> 1);
413 else
414 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
415
416 if (col & 1) {
417 rd_word = readw(p);
418 ret = (rd_word >> 8) & 0xff;
419 rd_word = readw(&p[1]);
420 ret |= (rd_word << 8) & 0xff00;
421
422 } else
423 ret = readw(p);
424
425 /* Update saved column address */
426 host->col_addr = col + 2;
427
428 return ret;
429 }
430
431 /* Write data of length len to buffer buf. The data to be
432 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
433 * Operation by the NFC, the data is written to NAND Flash */
434 static void mxc_nand_write_buf(struct mtd_info *mtd,
435 const u_char *buf, int len)
436 {
437 struct nand_chip *nand_chip = mtd->priv;
438 struct mxc_nand_host *host = nand_chip->priv;
439 int n, col, i = 0;
440
441 DEBUG(MTD_DEBUG_LEVEL3,
442 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
443 len);
444
445 col = host->col_addr;
446
447 /* Adjust saved column address */
448 if (col < mtd->writesize && host->spare_only)
449 col += mtd->writesize;
450
451 n = mtd->writesize + mtd->oobsize - col;
452 n = min(len, n);
453
454 DEBUG(MTD_DEBUG_LEVEL3,
455 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
456
457 while (n) {
458 void __iomem *p;
459
460 if (col < mtd->writesize)
461 p = host->regs + MAIN_AREA0 + (col & ~3);
462 else
463 p = host->regs + SPARE_AREA0 -
464 mtd->writesize + (col & ~3);
465
466 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
467 __LINE__, p);
468
469 if (((col | (int)&buf[i]) & 3) || n < 16) {
470 uint32_t data = 0;
471
472 if (col & 3 || n < 4)
473 data = readl(p);
474
475 switch (col & 3) {
476 case 0:
477 if (n) {
478 data = (data & 0xffffff00) |
479 (buf[i++] << 0);
480 n--;
481 col++;
482 }
483 case 1:
484 if (n) {
485 data = (data & 0xffff00ff) |
486 (buf[i++] << 8);
487 n--;
488 col++;
489 }
490 case 2:
491 if (n) {
492 data = (data & 0xff00ffff) |
493 (buf[i++] << 16);
494 n--;
495 col++;
496 }
497 case 3:
498 if (n) {
499 data = (data & 0x00ffffff) |
500 (buf[i++] << 24);
501 n--;
502 col++;
503 }
504 }
505
506 writel(data, p);
507 } else {
508 int m = mtd->writesize - col;
509
510 if (col >= mtd->writesize)
511 m += mtd->oobsize;
512
513 m = min(n, m) & ~3;
514
515 DEBUG(MTD_DEBUG_LEVEL3,
516 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
517 __func__, __LINE__, n, m, i, col);
518
519 memcpy(p, &buf[i], m);
520 col += m;
521 i += m;
522 n -= m;
523 }
524 }
525 /* Update saved column address */
526 host->col_addr = col;
527 }
528
529 /* Read the data buffer from the NAND Flash. To read the data from NAND
530 * Flash first the data output cycle is initiated by the NFC, which copies
531 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
532 */
533 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
534 {
535 struct nand_chip *nand_chip = mtd->priv;
536 struct mxc_nand_host *host = nand_chip->priv;
537 int n, col, i = 0;
538
539 DEBUG(MTD_DEBUG_LEVEL3,
540 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
541
542 col = host->col_addr;
543
544 /* Adjust saved column address */
545 if (col < mtd->writesize && host->spare_only)
546 col += mtd->writesize;
547
548 n = mtd->writesize + mtd->oobsize - col;
549 n = min(len, n);
550
551 while (n) {
552 void __iomem *p;
553
554 if (col < mtd->writesize)
555 p = host->regs + MAIN_AREA0 + (col & ~3);
556 else
557 p = host->regs + SPARE_AREA0 -
558 mtd->writesize + (col & ~3);
559
560 if (((col | (int)&buf[i]) & 3) || n < 16) {
561 uint32_t data;
562
563 data = readl(p);
564 switch (col & 3) {
565 case 0:
566 if (n) {
567 buf[i++] = (uint8_t) (data);
568 n--;
569 col++;
570 }
571 case 1:
572 if (n) {
573 buf[i++] = (uint8_t) (data >> 8);
574 n--;
575 col++;
576 }
577 case 2:
578 if (n) {
579 buf[i++] = (uint8_t) (data >> 16);
580 n--;
581 col++;
582 }
583 case 3:
584 if (n) {
585 buf[i++] = (uint8_t) (data >> 24);
586 n--;
587 col++;
588 }
589 }
590 } else {
591 int m = mtd->writesize - col;
592
593 if (col >= mtd->writesize)
594 m += mtd->oobsize;
595
596 m = min(n, m) & ~3;
597 memcpy(&buf[i], p, m);
598 col += m;
599 i += m;
600 n -= m;
601 }
602 }
603 /* Update saved column address */
604 host->col_addr = col;
605
606 }
607
608 /* Used by the upper layer to verify the data in NAND Flash
609 * with the data in the buf. */
610 static int mxc_nand_verify_buf(struct mtd_info *mtd,
611 const u_char *buf, int len)
612 {
613 return -EFAULT;
614 }
615
616 /* This function is used by upper layer for select and
617 * deselect of the NAND chip */
618 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
619 {
620 struct nand_chip *nand_chip = mtd->priv;
621 struct mxc_nand_host *host = nand_chip->priv;
622
623 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
624 if (chip > 0) {
625 DEBUG(MTD_DEBUG_LEVEL0,
626 "ERROR: Illegal chip select (chip = %d)\n", chip);
627 return;
628 }
629
630 if (chip == -1) {
631 writew(readw(host->regs + NFC_CONFIG1) & ~NFC_CE,
632 host->regs + NFC_CONFIG1);
633 return;
634 }
635
636 writew(readw(host->regs + NFC_CONFIG1) | NFC_CE,
637 host->regs + NFC_CONFIG1);
638 #endif
639
640 switch (chip) {
641 case -1:
642 /* Disable the NFC clock */
643 if (host->clk_act) {
644 clk_disable(host->clk);
645 host->clk_act = 0;
646 }
647 break;
648 case 0:
649 /* Enable the NFC clock */
650 if (!host->clk_act) {
651 clk_enable(host->clk);
652 host->clk_act = 1;
653 }
654 break;
655
656 default:
657 break;
658 }
659 }
660
661 /* Used by the upper layer to write command to NAND Flash for
662 * different operations to be carried out on NAND Flash */
663 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
664 int column, int page_addr)
665 {
666 struct nand_chip *nand_chip = mtd->priv;
667 struct mxc_nand_host *host = nand_chip->priv;
668 int useirq = true;
669
670 DEBUG(MTD_DEBUG_LEVEL3,
671 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
672 command, column, page_addr);
673
674 /* Reset command state information */
675 host->status_request = false;
676
677 /* Command pre-processing step */
678 switch (command) {
679
680 case NAND_CMD_STATUS:
681 host->col_addr = 0;
682 host->status_request = true;
683 break;
684
685 case NAND_CMD_READ0:
686 host->col_addr = column;
687 host->spare_only = false;
688 useirq = false;
689 break;
690
691 case NAND_CMD_READOOB:
692 host->col_addr = column;
693 host->spare_only = true;
694 useirq = false;
695 if (host->pagesize_2k)
696 command = NAND_CMD_READ0; /* only READ0 is valid */
697 break;
698
699 case NAND_CMD_SEQIN:
700 if (column >= mtd->writesize) {
701 /*
702 * FIXME: before send SEQIN command for write OOB,
703 * We must read one page out.
704 * For K9F1GXX has no READ1 command to set current HW
705 * pointer to spare area, we must write the whole page
706 * including OOB together.
707 */
708 if (host->pagesize_2k)
709 /* call ourself to read a page */
710 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
711 page_addr);
712
713 host->col_addr = column - mtd->writesize;
714 host->spare_only = true;
715
716 /* Set program pointer to spare region */
717 if (!host->pagesize_2k)
718 send_cmd(host, NAND_CMD_READOOB, false);
719 } else {
720 host->spare_only = false;
721 host->col_addr = column;
722
723 /* Set program pointer to page start */
724 if (!host->pagesize_2k)
725 send_cmd(host, NAND_CMD_READ0, false);
726 }
727 useirq = false;
728 break;
729
730 case NAND_CMD_PAGEPROG:
731 send_page(host, 0, host->spare_only, NFC_INPUT);
732
733 if (host->pagesize_2k) {
734 /* data in 4 areas datas */
735 send_page(host, 1, host->spare_only, NFC_INPUT);
736 send_page(host, 2, host->spare_only, NFC_INPUT);
737 send_page(host, 3, host->spare_only, NFC_INPUT);
738 }
739
740 break;
741
742 case NAND_CMD_ERASE1:
743 useirq = false;
744 break;
745 }
746
747 /* Write out the command to the device. */
748 send_cmd(host, command, useirq);
749
750 /* Write out column address, if necessary */
751 if (column != -1) {
752 /*
753 * MXC NANDFC can only perform full page+spare or
754 * spare-only read/write. When the upper layers
755 * layers perform a read/write buf operation,
756 * we will used the saved column adress to index into
757 * the full page.
758 */
759 send_addr(host, 0, page_addr == -1);
760 if (host->pagesize_2k)
761 /* another col addr cycle for 2k page */
762 send_addr(host, 0, false);
763 }
764
765 /* Write out page address, if necessary */
766 if (page_addr != -1) {
767 /* paddr_0 - p_addr_7 */
768 send_addr(host, (page_addr & 0xff), false);
769
770 if (host->pagesize_2k) {
771 if (mtd->size >= 0x10000000) {
772 /* paddr_8 - paddr_15 */
773 send_addr(host, (page_addr >> 8) & 0xff, false);
774 send_addr(host, (page_addr >> 16) & 0xff, true);
775 } else
776 /* paddr_8 - paddr_15 */
777 send_addr(host, (page_addr >> 8) & 0xff, true);
778 } else {
779 /* One more address cycle for higher density devices */
780 if (mtd->size >= 0x4000000) {
781 /* paddr_8 - paddr_15 */
782 send_addr(host, (page_addr >> 8) & 0xff, false);
783 send_addr(host, (page_addr >> 16) & 0xff, true);
784 } else
785 /* paddr_8 - paddr_15 */
786 send_addr(host, (page_addr >> 8) & 0xff, true);
787 }
788 }
789
790 /* Command post-processing step */
791 switch (command) {
792
793 case NAND_CMD_RESET:
794 break;
795
796 case NAND_CMD_READOOB:
797 case NAND_CMD_READ0:
798 if (host->pagesize_2k) {
799 /* send read confirm command */
800 send_cmd(host, NAND_CMD_READSTART, true);
801 /* read for each AREA */
802 send_page(host, 0, host->spare_only, NFC_OUTPUT);
803 send_page(host, 1, host->spare_only, NFC_OUTPUT);
804 send_page(host, 2, host->spare_only, NFC_OUTPUT);
805 send_page(host, 3, host->spare_only, NFC_OUTPUT);
806 } else
807 send_page(host, 0, host->spare_only, NFC_OUTPUT);
808 break;
809
810 case NAND_CMD_READID:
811 host->col_addr = 0;
812 send_read_id(host);
813 break;
814
815 case NAND_CMD_PAGEPROG:
816 break;
817
818 case NAND_CMD_STATUS:
819 break;
820
821 case NAND_CMD_ERASE2:
822 break;
823 }
824 }
825
826 static int __init mxcnd_probe(struct platform_device *pdev)
827 {
828 struct nand_chip *this;
829 struct mtd_info *mtd;
830 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
831 struct mxc_nand_host *host;
832 struct resource *res;
833 uint16_t tmp;
834 int err = 0, nr_parts = 0;
835
836 /* Allocate memory for MTD device structure and private data */
837 host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL);
838 if (!host)
839 return -ENOMEM;
840
841 host->dev = &pdev->dev;
842 /* structures must be linked */
843 this = &host->nand;
844 mtd = &host->mtd;
845 mtd->priv = this;
846 mtd->owner = THIS_MODULE;
847 mtd->dev.parent = &pdev->dev;
848 mtd->name = "mxc_nand";
849
850 /* 50 us command delay time */
851 this->chip_delay = 5;
852
853 this->priv = host;
854 this->dev_ready = mxc_nand_dev_ready;
855 this->cmdfunc = mxc_nand_command;
856 this->select_chip = mxc_nand_select_chip;
857 this->read_byte = mxc_nand_read_byte;
858 this->read_word = mxc_nand_read_word;
859 this->write_buf = mxc_nand_write_buf;
860 this->read_buf = mxc_nand_read_buf;
861 this->verify_buf = mxc_nand_verify_buf;
862
863 host->clk = clk_get(&pdev->dev, "nfc");
864 if (IS_ERR(host->clk)) {
865 err = PTR_ERR(host->clk);
866 goto eclk;
867 }
868
869 clk_enable(host->clk);
870 host->clk_act = 1;
871
872 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
873 if (!res) {
874 err = -ENODEV;
875 goto eres;
876 }
877
878 host->regs = ioremap(res->start, res->end - res->start + 1);
879 if (!host->regs) {
880 err = -ENOMEM;
881 goto eres;
882 }
883
884 tmp = readw(host->regs + NFC_CONFIG1);
885 tmp |= NFC_INT_MSK;
886 writew(tmp, host->regs + NFC_CONFIG1);
887
888 init_waitqueue_head(&host->irq_waitq);
889
890 host->irq = platform_get_irq(pdev, 0);
891
892 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
893 if (err)
894 goto eirq;
895
896 /* Reset NAND */
897 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
898
899 /* preset operation */
900 /* Unlock the internal RAM Buffer */
901 writew(0x2, host->regs + NFC_CONFIG);
902
903 /* Blocks to be unlocked */
904 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
905 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
906
907 /* Unlock Block Command for given address range */
908 writew(0x4, host->regs + NFC_WRPROT);
909
910 this->ecc.size = 512;
911 this->ecc.bytes = 3;
912 this->ecc.layout = &nand_hw_eccoob_smallpage;
913
914 if (pdata->hw_ecc) {
915 this->ecc.calculate = mxc_nand_calculate_ecc;
916 this->ecc.hwctl = mxc_nand_enable_hwecc;
917 this->ecc.correct = mxc_nand_correct_data;
918 this->ecc.mode = NAND_ECC_HW;
919 tmp = readw(host->regs + NFC_CONFIG1);
920 tmp |= NFC_ECC_EN;
921 writew(tmp, host->regs + NFC_CONFIG1);
922 } else {
923 this->ecc.mode = NAND_ECC_SOFT;
924 tmp = readw(host->regs + NFC_CONFIG1);
925 tmp &= ~NFC_ECC_EN;
926 writew(tmp, host->regs + NFC_CONFIG1);
927 }
928
929 /* NAND bus width determines access funtions used by upper layer */
930 if (pdata->width == 2)
931 this->options |= NAND_BUSWIDTH_16;
932
933 /* first scan to find the device and get the page size */
934 if (nand_scan_ident(mtd, 1)) {
935 err = -ENXIO;
936 goto escan;
937 }
938
939 if (mtd->writesize == 2048) {
940 host->pagesize_2k = 1;
941 this->ecc.layout = &nand_hw_eccoob_largepage;
942 }
943
944 /* second phase scan */
945 if (nand_scan_tail(mtd)) {
946 err = -ENXIO;
947 goto escan;
948 }
949
950 /* Register the partitions */
951 #ifdef CONFIG_MTD_PARTITIONS
952 nr_parts =
953 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
954 if (nr_parts > 0)
955 add_mtd_partitions(mtd, host->parts, nr_parts);
956 else
957 #endif
958 {
959 pr_info("Registering %s as whole device\n", mtd->name);
960 add_mtd_device(mtd);
961 }
962
963 platform_set_drvdata(pdev, host);
964
965 return 0;
966
967 escan:
968 free_irq(host->irq, host);
969 eirq:
970 iounmap(host->regs);
971 eres:
972 clk_put(host->clk);
973 eclk:
974 kfree(host);
975
976 return err;
977 }
978
979 static int __exit mxcnd_remove(struct platform_device *pdev)
980 {
981 struct mxc_nand_host *host = platform_get_drvdata(pdev);
982
983 clk_put(host->clk);
984
985 platform_set_drvdata(pdev, NULL);
986
987 nand_release(&host->mtd);
988 free_irq(host->irq, host);
989 iounmap(host->regs);
990 kfree(host);
991
992 return 0;
993 }
994
995 #ifdef CONFIG_PM
996 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
997 {
998 struct mtd_info *mtd = platform_get_drvdata(pdev);
999 struct nand_chip *nand_chip = mtd->priv;
1000 struct mxc_nand_host *host = nand_chip->priv;
1001 int ret = 0;
1002
1003 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
1004 if (mtd) {
1005 ret = mtd->suspend(mtd);
1006 /* Disable the NFC clock */
1007 clk_disable(host->clk);
1008 }
1009
1010 return ret;
1011 }
1012
1013 static int mxcnd_resume(struct platform_device *pdev)
1014 {
1015 struct mtd_info *mtd = platform_get_drvdata(pdev);
1016 struct nand_chip *nand_chip = mtd->priv;
1017 struct mxc_nand_host *host = nand_chip->priv;
1018 int ret = 0;
1019
1020 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
1021
1022 if (mtd) {
1023 /* Enable the NFC clock */
1024 clk_enable(host->clk);
1025 mtd->resume(mtd);
1026 }
1027
1028 return ret;
1029 }
1030
1031 #else
1032 # define mxcnd_suspend NULL
1033 # define mxcnd_resume NULL
1034 #endif /* CONFIG_PM */
1035
1036 static struct platform_driver mxcnd_driver = {
1037 .driver = {
1038 .name = DRIVER_NAME,
1039 },
1040 .remove = __exit_p(mxcnd_remove),
1041 .suspend = mxcnd_suspend,
1042 .resume = mxcnd_resume,
1043 };
1044
1045 static int __init mxc_nd_init(void)
1046 {
1047 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1048 }
1049
1050 static void __exit mxc_nd_cleanup(void)
1051 {
1052 /* Unregister the device structure */
1053 platform_driver_unregister(&mxcnd_driver);
1054 }
1055
1056 module_init(mxc_nd_init);
1057 module_exit(mxc_nd_cleanup);
1058
1059 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1060 MODULE_DESCRIPTION("MXC NAND MTD driver");
1061 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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