2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
37 #define DRIVER_NAME "mxc_nand"
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
55 /* Addresses for NFC RAM BUFFER Main area 0 */
56 #define MAIN_AREA0 0x000
57 #define MAIN_AREA1 0x200
58 #define MAIN_AREA2 0x400
59 #define MAIN_AREA3 0x600
61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
62 #define SPARE_AREA0 0x800
63 #define SPARE_AREA1 0x810
64 #define SPARE_AREA2 0x820
65 #define SPARE_AREA3 0x830
67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81 #define NFC_OUTPUT 0x8
83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89 #define NFC_STATUS 0x20
91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
93 #define NFC_INT 0x8000
95 #define NFC_SP_EN (1 << 2)
96 #define NFC_ECC_EN (1 << 3)
97 #define NFC_INT_MSK (1 << 4)
98 #define NFC_BIG (1 << 5)
99 #define NFC_RST (1 << 6)
100 #define NFC_CE (1 << 7)
101 #define NFC_ONE_CYCLE (1 << 8)
103 struct mxc_nand_host
{
105 struct nand_chip nand
;
106 struct mtd_partition
*parts
;
118 wait_queue_head_t irq_waitq
;
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
123 /* Macros to get byte and bit positions of ECC */
124 #define COLPOS(x) ((x) >> 3)
125 #define BITPOS(x) ((x) & 0xf)
127 /* Define single bit Error positions in Main & Spare area */
128 #define MAIN_SINGLEBIT_ERROR 0x4
129 #define SPARE_SINGLEBIT_ERROR 0x1
131 /* OOB placement block for use with hardware ecc generation */
132 static struct nand_ecclayout nand_hw_eccoob_smallpage
= {
134 .eccpos
= {6, 7, 8, 9, 10},
135 .oobfree
= {{0, 5}, {12, 4}, }
138 static struct nand_ecclayout nand_hw_eccoob_largepage
= {
140 .eccpos
= {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
141 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
142 .oobfree
= {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
145 #ifdef CONFIG_MTD_PARTITIONS
146 static const char *part_probes
[] = { "RedBoot", "cmdlinepart", NULL
};
149 static irqreturn_t
mxc_nfc_irq(int irq
, void *dev_id
)
151 struct mxc_nand_host
*host
= dev_id
;
155 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
156 tmp
|= NFC_INT_MSK
; /* Disable interrupt */
157 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
159 wake_up(&host
->irq_waitq
);
164 /* This function polls the NANDFC to wait for the basic operation to
165 * complete by checking the INT bit of config2 register.
167 static void wait_op_done(struct mxc_nand_host
*host
, int max_retries
,
173 if ((readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
) == 0) {
175 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
176 tmp
&= ~NFC_INT_MSK
; /* Enable interrupt */
177 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
179 wait_event(host
->irq_waitq
,
180 readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
);
182 tmp
= readw(host
->regs
+ NFC_CONFIG2
);
184 writew(tmp
, host
->regs
+ NFC_CONFIG2
);
187 while (max_retries
-- > 0) {
188 if (readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
) {
189 tmp
= readw(host
->regs
+ NFC_CONFIG2
);
191 writew(tmp
, host
->regs
+ NFC_CONFIG2
);
197 DEBUG(MTD_DEBUG_LEVEL0
, "%s: INT not set\n",
202 /* This function issues the specified command to the NAND device and
203 * waits for completion. */
204 static void send_cmd(struct mxc_nand_host
*host
, uint16_t cmd
, int useirq
)
206 DEBUG(MTD_DEBUG_LEVEL3
, "send_cmd(host, 0x%x, %d)\n", cmd
, useirq
);
208 writew(cmd
, host
->regs
+ NFC_FLASH_CMD
);
209 writew(NFC_CMD
, host
->regs
+ NFC_CONFIG2
);
211 /* Wait for operation to complete */
212 wait_op_done(host
, TROP_US_DELAY
, useirq
);
215 /* This function sends an address (or partial address) to the
216 * NAND device. The address is used to select the source/destination for
218 static void send_addr(struct mxc_nand_host
*host
, uint16_t addr
, int islast
)
220 DEBUG(MTD_DEBUG_LEVEL3
, "send_addr(host, 0x%x %d)\n", addr
, islast
);
222 writew(addr
, host
->regs
+ NFC_FLASH_ADDR
);
223 writew(NFC_ADDR
, host
->regs
+ NFC_CONFIG2
);
225 /* Wait for operation to complete */
226 wait_op_done(host
, TROP_US_DELAY
, islast
);
229 static void send_page(struct mxc_nand_host
*host
, uint8_t buf_id
,
230 int spare_only
, unsigned int ops
)
232 DEBUG(MTD_DEBUG_LEVEL3
, "send_page (%d)\n", spare_only
);
234 /* NANDFC buffer 0 is used for page read/write */
235 writew(buf_id
, host
->regs
+ NFC_BUF_ADDR
);
237 /* Configure spare or page+spare access */
238 if (!host
->pagesize_2k
) {
239 uint16_t config1
= readw(host
->regs
+ NFC_CONFIG1
);
241 config1
|= NFC_SP_EN
;
243 config1
&= ~(NFC_SP_EN
);
244 writew(config1
, host
->regs
+ NFC_CONFIG1
);
247 writew(ops
, host
->regs
+ NFC_CONFIG2
);
249 /* Wait for operation to complete */
250 wait_op_done(host
, TROP_US_DELAY
, true);
253 /* Request the NANDFC to perform a read of the NAND device ID. */
254 static void send_read_id(struct mxc_nand_host
*host
)
256 struct nand_chip
*this = &host
->nand
;
259 /* NANDFC buffer 0 is used for device ID output */
260 writew(0x0, host
->regs
+ NFC_BUF_ADDR
);
262 /* Read ID into main buffer */
263 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
265 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
267 writew(NFC_ID
, host
->regs
+ NFC_CONFIG2
);
269 /* Wait for operation to complete */
270 wait_op_done(host
, TROP_US_DELAY
, true);
272 if (this->options
& NAND_BUSWIDTH_16
) {
273 void __iomem
*main_buf
= host
->regs
+ MAIN_AREA0
;
274 /* compress the ID info */
275 writeb(readb(main_buf
+ 2), main_buf
+ 1);
276 writeb(readb(main_buf
+ 4), main_buf
+ 2);
277 writeb(readb(main_buf
+ 6), main_buf
+ 3);
278 writeb(readb(main_buf
+ 8), main_buf
+ 4);
279 writeb(readb(main_buf
+ 10), main_buf
+ 5);
283 /* This function requests the NANDFC to perform a read of the
284 * NAND device status and returns the current status. */
285 static uint16_t get_dev_status(struct mxc_nand_host
*host
)
287 void __iomem
*main_buf
= host
->regs
+ MAIN_AREA1
;
290 /* Issue status request to NAND device */
292 /* store the main area1 first word, later do recovery */
293 store
= readl(main_buf
);
294 /* NANDFC buffer 1 is used for device status to prevent
295 * corruption of read/write buffer on status requests. */
296 writew(1, host
->regs
+ NFC_BUF_ADDR
);
298 /* Read status into main buffer */
299 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
301 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
303 writew(NFC_STATUS
, host
->regs
+ NFC_CONFIG2
);
305 /* Wait for operation to complete */
306 wait_op_done(host
, TROP_US_DELAY
, true);
308 /* Status is placed in first word of main buffer */
309 /* get status, then recovery area 1 data */
310 ret
= readw(main_buf
);
311 writel(store
, main_buf
);
316 /* This functions is used by upper layer to checks if device is ready */
317 static int mxc_nand_dev_ready(struct mtd_info
*mtd
)
320 * NFC handles R/B internally. Therefore, this function
321 * always returns status as ready.
326 static void mxc_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
329 * If HW ECC is enabled, we turn it on during init. There is
330 * no need to enable again here.
334 static int mxc_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
335 u_char
*read_ecc
, u_char
*calc_ecc
)
337 struct nand_chip
*nand_chip
= mtd
->priv
;
338 struct mxc_nand_host
*host
= nand_chip
->priv
;
341 * 1-Bit errors are automatically corrected in HW. No need for
342 * additional correction. 2-Bit errors cannot be corrected by
343 * HW ECC, so we need to return failure
345 uint16_t ecc_status
= readw(host
->regs
+ NFC_ECC_STATUS_RESULT
);
347 if (((ecc_status
& 0x3) == 2) || ((ecc_status
>> 2) == 2)) {
348 DEBUG(MTD_DEBUG_LEVEL0
,
349 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
356 static int mxc_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
362 static u_char
mxc_nand_read_byte(struct mtd_info
*mtd
)
364 struct nand_chip
*nand_chip
= mtd
->priv
;
365 struct mxc_nand_host
*host
= nand_chip
->priv
;
367 uint16_t col
, rd_word
;
368 uint16_t __iomem
*main_buf
= host
->regs
+ MAIN_AREA0
;
369 uint16_t __iomem
*spare_buf
= host
->regs
+ SPARE_AREA0
;
371 /* Check for status request */
372 if (host
->status_request
)
373 return get_dev_status(host
) & 0xFF;
375 /* Get column for 16-bit access */
376 col
= host
->col_addr
>> 1;
378 /* If we are accessing the spare region */
379 if (host
->spare_only
)
380 rd_word
= readw(&spare_buf
[col
]);
382 rd_word
= readw(&main_buf
[col
]);
384 /* Pick upper/lower byte of word from RAM buffer */
385 if (host
->col_addr
& 0x1)
386 ret
= (rd_word
>> 8) & 0xFF;
388 ret
= rd_word
& 0xFF;
390 /* Update saved column address */
396 static uint16_t mxc_nand_read_word(struct mtd_info
*mtd
)
398 struct nand_chip
*nand_chip
= mtd
->priv
;
399 struct mxc_nand_host
*host
= nand_chip
->priv
;
400 uint16_t col
, rd_word
, ret
;
403 DEBUG(MTD_DEBUG_LEVEL3
,
404 "mxc_nand_read_word(col = %d)\n", host
->col_addr
);
406 col
= host
->col_addr
;
407 /* Adjust saved column address */
408 if (col
< mtd
->writesize
&& host
->spare_only
)
409 col
+= mtd
->writesize
;
411 if (col
< mtd
->writesize
)
412 p
= (host
->regs
+ MAIN_AREA0
) + (col
>> 1);
414 p
= (host
->regs
+ SPARE_AREA0
) + ((col
- mtd
->writesize
) >> 1);
418 ret
= (rd_word
>> 8) & 0xff;
419 rd_word
= readw(&p
[1]);
420 ret
|= (rd_word
<< 8) & 0xff00;
425 /* Update saved column address */
426 host
->col_addr
= col
+ 2;
431 /* Write data of length len to buffer buf. The data to be
432 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
433 * Operation by the NFC, the data is written to NAND Flash */
434 static void mxc_nand_write_buf(struct mtd_info
*mtd
,
435 const u_char
*buf
, int len
)
437 struct nand_chip
*nand_chip
= mtd
->priv
;
438 struct mxc_nand_host
*host
= nand_chip
->priv
;
441 DEBUG(MTD_DEBUG_LEVEL3
,
442 "mxc_nand_write_buf(col = %d, len = %d)\n", host
->col_addr
,
445 col
= host
->col_addr
;
447 /* Adjust saved column address */
448 if (col
< mtd
->writesize
&& host
->spare_only
)
449 col
+= mtd
->writesize
;
451 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
454 DEBUG(MTD_DEBUG_LEVEL3
,
455 "%s:%d: col = %d, n = %d\n", __func__
, __LINE__
, col
, n
);
460 if (col
< mtd
->writesize
)
461 p
= host
->regs
+ MAIN_AREA0
+ (col
& ~3);
463 p
= host
->regs
+ SPARE_AREA0
-
464 mtd
->writesize
+ (col
& ~3);
466 DEBUG(MTD_DEBUG_LEVEL3
, "%s:%d: p = %p\n", __func__
,
469 if (((col
| (int)&buf
[i
]) & 3) || n
< 16) {
472 if (col
& 3 || n
< 4)
478 data
= (data
& 0xffffff00) |
485 data
= (data
& 0xffff00ff) |
492 data
= (data
& 0xff00ffff) |
499 data
= (data
& 0x00ffffff) |
508 int m
= mtd
->writesize
- col
;
510 if (col
>= mtd
->writesize
)
515 DEBUG(MTD_DEBUG_LEVEL3
,
516 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
517 __func__
, __LINE__
, n
, m
, i
, col
);
519 memcpy(p
, &buf
[i
], m
);
525 /* Update saved column address */
526 host
->col_addr
= col
;
529 /* Read the data buffer from the NAND Flash. To read the data from NAND
530 * Flash first the data output cycle is initiated by the NFC, which copies
531 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
533 static void mxc_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
535 struct nand_chip
*nand_chip
= mtd
->priv
;
536 struct mxc_nand_host
*host
= nand_chip
->priv
;
539 DEBUG(MTD_DEBUG_LEVEL3
,
540 "mxc_nand_read_buf(col = %d, len = %d)\n", host
->col_addr
, len
);
542 col
= host
->col_addr
;
544 /* Adjust saved column address */
545 if (col
< mtd
->writesize
&& host
->spare_only
)
546 col
+= mtd
->writesize
;
548 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
554 if (col
< mtd
->writesize
)
555 p
= host
->regs
+ MAIN_AREA0
+ (col
& ~3);
557 p
= host
->regs
+ SPARE_AREA0
-
558 mtd
->writesize
+ (col
& ~3);
560 if (((col
| (int)&buf
[i
]) & 3) || n
< 16) {
567 buf
[i
++] = (uint8_t) (data
);
573 buf
[i
++] = (uint8_t) (data
>> 8);
579 buf
[i
++] = (uint8_t) (data
>> 16);
585 buf
[i
++] = (uint8_t) (data
>> 24);
591 int m
= mtd
->writesize
- col
;
593 if (col
>= mtd
->writesize
)
597 memcpy(&buf
[i
], p
, m
);
603 /* Update saved column address */
604 host
->col_addr
= col
;
608 /* Used by the upper layer to verify the data in NAND Flash
609 * with the data in the buf. */
610 static int mxc_nand_verify_buf(struct mtd_info
*mtd
,
611 const u_char
*buf
, int len
)
616 /* This function is used by upper layer for select and
617 * deselect of the NAND chip */
618 static void mxc_nand_select_chip(struct mtd_info
*mtd
, int chip
)
620 struct nand_chip
*nand_chip
= mtd
->priv
;
621 struct mxc_nand_host
*host
= nand_chip
->priv
;
623 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
625 DEBUG(MTD_DEBUG_LEVEL0
,
626 "ERROR: Illegal chip select (chip = %d)\n", chip
);
631 writew(readw(host
->regs
+ NFC_CONFIG1
) & ~NFC_CE
,
632 host
->regs
+ NFC_CONFIG1
);
636 writew(readw(host
->regs
+ NFC_CONFIG1
) | NFC_CE
,
637 host
->regs
+ NFC_CONFIG1
);
642 /* Disable the NFC clock */
644 clk_disable(host
->clk
);
649 /* Enable the NFC clock */
650 if (!host
->clk_act
) {
651 clk_enable(host
->clk
);
661 static void mxc_do_addr_cycle(struct mtd_info
*mtd
, int column
, int page_addr
)
663 struct nand_chip
*nand_chip
= mtd
->priv
;
664 struct mxc_nand_host
*host
= nand_chip
->priv
;
666 /* Write out column address, if necessary */
669 * MXC NANDFC can only perform full page+spare or
670 * spare-only read/write. When the upper layers
671 * layers perform a read/write buf operation,
672 * we will used the saved column adress to index into
675 send_addr(host
, 0, page_addr
== -1);
676 if (host
->pagesize_2k
)
677 /* another col addr cycle for 2k page */
678 send_addr(host
, 0, false);
681 /* Write out page address, if necessary */
682 if (page_addr
!= -1) {
683 /* paddr_0 - p_addr_7 */
684 send_addr(host
, (page_addr
& 0xff), false);
686 if (host
->pagesize_2k
) {
687 if (mtd
->size
>= 0x10000000) {
688 /* paddr_8 - paddr_15 */
689 send_addr(host
, (page_addr
>> 8) & 0xff, false);
690 send_addr(host
, (page_addr
>> 16) & 0xff, true);
692 /* paddr_8 - paddr_15 */
693 send_addr(host
, (page_addr
>> 8) & 0xff, true);
695 /* One more address cycle for higher density devices */
696 if (mtd
->size
>= 0x4000000) {
697 /* paddr_8 - paddr_15 */
698 send_addr(host
, (page_addr
>> 8) & 0xff, false);
699 send_addr(host
, (page_addr
>> 16) & 0xff, true);
701 /* paddr_8 - paddr_15 */
702 send_addr(host
, (page_addr
>> 8) & 0xff, true);
707 /* Used by the upper layer to write command to NAND Flash for
708 * different operations to be carried out on NAND Flash */
709 static void mxc_nand_command(struct mtd_info
*mtd
, unsigned command
,
710 int column
, int page_addr
)
712 struct nand_chip
*nand_chip
= mtd
->priv
;
713 struct mxc_nand_host
*host
= nand_chip
->priv
;
716 DEBUG(MTD_DEBUG_LEVEL3
,
717 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
718 command
, column
, page_addr
);
720 /* Reset command state information */
721 host
->status_request
= false;
723 /* Command pre-processing step */
726 case NAND_CMD_STATUS
:
728 host
->status_request
= true;
732 host
->col_addr
= column
;
733 host
->spare_only
= false;
737 case NAND_CMD_READOOB
:
738 host
->col_addr
= column
;
739 host
->spare_only
= true;
741 if (host
->pagesize_2k
)
742 command
= NAND_CMD_READ0
; /* only READ0 is valid */
746 if (column
>= mtd
->writesize
) {
748 * FIXME: before send SEQIN command for write OOB,
749 * We must read one page out.
750 * For K9F1GXX has no READ1 command to set current HW
751 * pointer to spare area, we must write the whole page
752 * including OOB together.
754 if (host
->pagesize_2k
)
755 /* call ourself to read a page */
756 mxc_nand_command(mtd
, NAND_CMD_READ0
, 0,
759 host
->col_addr
= column
- mtd
->writesize
;
760 host
->spare_only
= true;
762 /* Set program pointer to spare region */
763 if (!host
->pagesize_2k
)
764 send_cmd(host
, NAND_CMD_READOOB
, false);
766 host
->spare_only
= false;
767 host
->col_addr
= column
;
769 /* Set program pointer to page start */
770 if (!host
->pagesize_2k
)
771 send_cmd(host
, NAND_CMD_READ0
, false);
776 case NAND_CMD_PAGEPROG
:
777 send_page(host
, 0, host
->spare_only
, NFC_INPUT
);
779 if (host
->pagesize_2k
) {
780 /* data in 4 areas datas */
781 send_page(host
, 1, host
->spare_only
, NFC_INPUT
);
782 send_page(host
, 2, host
->spare_only
, NFC_INPUT
);
783 send_page(host
, 3, host
->spare_only
, NFC_INPUT
);
788 case NAND_CMD_ERASE1
:
793 /* Write out the command to the device. */
794 send_cmd(host
, command
, useirq
);
795 mxc_do_addr_cycle(mtd
, column
, page_addr
);
797 /* Command post-processing step */
803 case NAND_CMD_READOOB
:
805 if (host
->pagesize_2k
) {
806 /* send read confirm command */
807 send_cmd(host
, NAND_CMD_READSTART
, true);
808 /* read for each AREA */
809 send_page(host
, 0, host
->spare_only
, NFC_OUTPUT
);
810 send_page(host
, 1, host
->spare_only
, NFC_OUTPUT
);
811 send_page(host
, 2, host
->spare_only
, NFC_OUTPUT
);
812 send_page(host
, 3, host
->spare_only
, NFC_OUTPUT
);
814 send_page(host
, 0, host
->spare_only
, NFC_OUTPUT
);
817 case NAND_CMD_READID
:
822 case NAND_CMD_PAGEPROG
:
825 case NAND_CMD_STATUS
:
828 case NAND_CMD_ERASE2
:
833 static int __init
mxcnd_probe(struct platform_device
*pdev
)
835 struct nand_chip
*this;
836 struct mtd_info
*mtd
;
837 struct mxc_nand_platform_data
*pdata
= pdev
->dev
.platform_data
;
838 struct mxc_nand_host
*host
;
839 struct resource
*res
;
841 int err
= 0, nr_parts
= 0;
843 /* Allocate memory for MTD device structure and private data */
844 host
= kzalloc(sizeof(struct mxc_nand_host
), GFP_KERNEL
);
848 host
->dev
= &pdev
->dev
;
849 /* structures must be linked */
853 mtd
->owner
= THIS_MODULE
;
854 mtd
->dev
.parent
= &pdev
->dev
;
855 mtd
->name
= "mxc_nand";
857 /* 50 us command delay time */
858 this->chip_delay
= 5;
861 this->dev_ready
= mxc_nand_dev_ready
;
862 this->cmdfunc
= mxc_nand_command
;
863 this->select_chip
= mxc_nand_select_chip
;
864 this->read_byte
= mxc_nand_read_byte
;
865 this->read_word
= mxc_nand_read_word
;
866 this->write_buf
= mxc_nand_write_buf
;
867 this->read_buf
= mxc_nand_read_buf
;
868 this->verify_buf
= mxc_nand_verify_buf
;
870 host
->clk
= clk_get(&pdev
->dev
, "nfc");
871 if (IS_ERR(host
->clk
)) {
872 err
= PTR_ERR(host
->clk
);
876 clk_enable(host
->clk
);
879 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
885 host
->regs
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
891 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
893 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
895 init_waitqueue_head(&host
->irq_waitq
);
897 host
->irq
= platform_get_irq(pdev
, 0);
899 err
= request_irq(host
->irq
, mxc_nfc_irq
, 0, "mxc_nd", host
);
904 this->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
906 /* preset operation */
907 /* Unlock the internal RAM Buffer */
908 writew(0x2, host
->regs
+ NFC_CONFIG
);
910 /* Blocks to be unlocked */
911 writew(0x0, host
->regs
+ NFC_UNLOCKSTART_BLKADDR
);
912 writew(0x4000, host
->regs
+ NFC_UNLOCKEND_BLKADDR
);
914 /* Unlock Block Command for given address range */
915 writew(0x4, host
->regs
+ NFC_WRPROT
);
917 this->ecc
.size
= 512;
919 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
922 this->ecc
.calculate
= mxc_nand_calculate_ecc
;
923 this->ecc
.hwctl
= mxc_nand_enable_hwecc
;
924 this->ecc
.correct
= mxc_nand_correct_data
;
925 this->ecc
.mode
= NAND_ECC_HW
;
926 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
928 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
930 this->ecc
.mode
= NAND_ECC_SOFT
;
931 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
933 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
936 /* NAND bus width determines access funtions used by upper layer */
937 if (pdata
->width
== 2)
938 this->options
|= NAND_BUSWIDTH_16
;
940 /* first scan to find the device and get the page size */
941 if (nand_scan_ident(mtd
, 1)) {
946 if (mtd
->writesize
== 2048) {
947 host
->pagesize_2k
= 1;
948 this->ecc
.layout
= &nand_hw_eccoob_largepage
;
951 /* second phase scan */
952 if (nand_scan_tail(mtd
)) {
957 /* Register the partitions */
958 #ifdef CONFIG_MTD_PARTITIONS
960 parse_mtd_partitions(mtd
, part_probes
, &host
->parts
, 0);
962 add_mtd_partitions(mtd
, host
->parts
, nr_parts
);
966 pr_info("Registering %s as whole device\n", mtd
->name
);
970 platform_set_drvdata(pdev
, host
);
975 free_irq(host
->irq
, host
);
986 static int __exit
mxcnd_remove(struct platform_device
*pdev
)
988 struct mxc_nand_host
*host
= platform_get_drvdata(pdev
);
992 platform_set_drvdata(pdev
, NULL
);
994 nand_release(&host
->mtd
);
995 free_irq(host
->irq
, host
);
1003 static int mxcnd_suspend(struct platform_device
*pdev
, pm_message_t state
)
1005 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1006 struct nand_chip
*nand_chip
= mtd
->priv
;
1007 struct mxc_nand_host
*host
= nand_chip
->priv
;
1010 DEBUG(MTD_DEBUG_LEVEL0
, "MXC_ND : NAND suspend\n");
1012 ret
= mtd
->suspend(mtd
);
1013 /* Disable the NFC clock */
1014 clk_disable(host
->clk
);
1020 static int mxcnd_resume(struct platform_device
*pdev
)
1022 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1023 struct nand_chip
*nand_chip
= mtd
->priv
;
1024 struct mxc_nand_host
*host
= nand_chip
->priv
;
1027 DEBUG(MTD_DEBUG_LEVEL0
, "MXC_ND : NAND resume\n");
1030 /* Enable the NFC clock */
1031 clk_enable(host
->clk
);
1039 # define mxcnd_suspend NULL
1040 # define mxcnd_resume NULL
1041 #endif /* CONFIG_PM */
1043 static struct platform_driver mxcnd_driver
= {
1045 .name
= DRIVER_NAME
,
1047 .remove
= __exit_p(mxcnd_remove
),
1048 .suspend
= mxcnd_suspend
,
1049 .resume
= mxcnd_resume
,
1052 static int __init
mxc_nd_init(void)
1054 return platform_driver_probe(&mxcnd_driver
, mxcnd_probe
);
1057 static void __exit
mxc_nd_cleanup(void)
1059 /* Unregister the device structure */
1060 platform_driver_unregister(&mxcnd_driver
);
1063 module_init(mxc_nd_init
);
1064 module_exit(mxc_nd_cleanup
);
1066 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1067 MODULE_DESCRIPTION("MXC NAND MTD driver");
1068 MODULE_LICENSE("GPL");