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mxc_nand: disable sp_en bit only once
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
37
38 #define DRIVER_NAME "mxc_nand"
39
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
42
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0xE00
45 #define NFC_BUF_ADDR 0xE04
46 #define NFC_FLASH_ADDR 0xE06
47 #define NFC_FLASH_CMD 0xE08
48 #define NFC_CONFIG 0xE0A
49 #define NFC_ECC_STATUS_RESULT 0xE0C
50 #define NFC_RSLTMAIN_AREA 0xE0E
51 #define NFC_RSLTSPARE_AREA 0xE10
52 #define NFC_WRPROT 0xE12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0xe22
57 #define NFC_NF_WRPRST 0xE18
58 #define NFC_CONFIG1 0xE1A
59 #define NFC_CONFIG2 0xE1C
60
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
63 #define NFC_CMD 0x1
64
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
67 #define NFC_ADDR 0x2
68
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
71 #define NFC_INPUT 0x4
72
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
76
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
79 #define NFC_ID 0x10
80
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
84
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
86 * Status operation */
87 #define NFC_INT 0x8000
88
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
96
97 struct mxc_nand_host {
98 struct mtd_info mtd;
99 struct nand_chip nand;
100 struct mtd_partition *parts;
101 struct device *dev;
102
103 void *spare0;
104 void *main_area0;
105 void *main_area1;
106
107 void __iomem *base;
108 void __iomem *regs;
109 int status_request;
110 struct clk *clk;
111 int clk_act;
112 int irq;
113
114 wait_queue_head_t irq_waitq;
115
116 uint8_t *data_buf;
117 unsigned int buf_start;
118 int spare_len;
119 };
120
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
123
124 /* OOB placement block for use with hardware ecc generation */
125 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
126 .eccbytes = 5,
127 .eccpos = {6, 7, 8, 9, 10},
128 .oobfree = {{0, 5}, {12, 4}, }
129 };
130
131 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
132 .eccbytes = 20,
133 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
134 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
135 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
136 };
137
138 /* OOB description for 512 byte pages with 16 byte OOB */
139 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
140 .eccbytes = 1 * 9,
141 .eccpos = {
142 7, 8, 9, 10, 11, 12, 13, 14, 15
143 },
144 .oobfree = {
145 {.offset = 0, .length = 5}
146 }
147 };
148
149 /* OOB description for 2048 byte pages with 64 byte OOB */
150 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
151 .eccbytes = 4 * 9,
152 .eccpos = {
153 7, 8, 9, 10, 11, 12, 13, 14, 15,
154 23, 24, 25, 26, 27, 28, 29, 30, 31,
155 39, 40, 41, 42, 43, 44, 45, 46, 47,
156 55, 56, 57, 58, 59, 60, 61, 62, 63
157 },
158 .oobfree = {
159 {.offset = 2, .length = 4},
160 {.offset = 16, .length = 7},
161 {.offset = 32, .length = 7},
162 {.offset = 48, .length = 7}
163 }
164 };
165
166 #ifdef CONFIG_MTD_PARTITIONS
167 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
168 #endif
169
170 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
171 {
172 struct mxc_nand_host *host = dev_id;
173
174 uint16_t tmp;
175
176 tmp = readw(host->regs + NFC_CONFIG1);
177 tmp |= NFC_INT_MSK; /* Disable interrupt */
178 writew(tmp, host->regs + NFC_CONFIG1);
179
180 wake_up(&host->irq_waitq);
181
182 return IRQ_HANDLED;
183 }
184
185 /* This function polls the NANDFC to wait for the basic operation to
186 * complete by checking the INT bit of config2 register.
187 */
188 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
189 int useirq)
190 {
191 uint32_t tmp;
192
193 if (useirq) {
194 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
195
196 tmp = readw(host->regs + NFC_CONFIG1);
197 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
198 writew(tmp, host->regs + NFC_CONFIG1);
199
200 wait_event(host->irq_waitq,
201 readw(host->regs + NFC_CONFIG2) & NFC_INT);
202
203 tmp = readw(host->regs + NFC_CONFIG2);
204 tmp &= ~NFC_INT;
205 writew(tmp, host->regs + NFC_CONFIG2);
206 }
207 } else {
208 while (max_retries-- > 0) {
209 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
210 tmp = readw(host->regs + NFC_CONFIG2);
211 tmp &= ~NFC_INT;
212 writew(tmp, host->regs + NFC_CONFIG2);
213 break;
214 }
215 udelay(1);
216 }
217 if (max_retries < 0)
218 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
219 __func__);
220 }
221 }
222
223 /* This function issues the specified command to the NAND device and
224 * waits for completion. */
225 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
226 {
227 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
228
229 writew(cmd, host->regs + NFC_FLASH_CMD);
230 writew(NFC_CMD, host->regs + NFC_CONFIG2);
231
232 /* Wait for operation to complete */
233 wait_op_done(host, TROP_US_DELAY, useirq);
234 }
235
236 /* This function sends an address (or partial address) to the
237 * NAND device. The address is used to select the source/destination for
238 * a NAND command. */
239 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
240 {
241 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
242
243 writew(addr, host->regs + NFC_FLASH_ADDR);
244 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
245
246 /* Wait for operation to complete */
247 wait_op_done(host, TROP_US_DELAY, islast);
248 }
249
250 static void send_page(struct mtd_info *mtd, unsigned int ops)
251 {
252 struct nand_chip *nand_chip = mtd->priv;
253 struct mxc_nand_host *host = nand_chip->priv;
254 int bufs, i;
255
256 if (nfc_is_v1() && mtd->writesize > 512)
257 bufs = 4;
258 else
259 bufs = 1;
260
261 for (i = 0; i < bufs; i++) {
262
263 /* NANDFC buffer 0 is used for page read/write */
264 writew(i, host->regs + NFC_BUF_ADDR);
265
266 writew(ops, host->regs + NFC_CONFIG2);
267
268 /* Wait for operation to complete */
269 wait_op_done(host, TROP_US_DELAY, true);
270 }
271 }
272
273 /* Request the NANDFC to perform a read of the NAND device ID. */
274 static void send_read_id(struct mxc_nand_host *host)
275 {
276 struct nand_chip *this = &host->nand;
277
278 /* NANDFC buffer 0 is used for device ID output */
279 writew(0x0, host->regs + NFC_BUF_ADDR);
280
281 writew(NFC_ID, host->regs + NFC_CONFIG2);
282
283 /* Wait for operation to complete */
284 wait_op_done(host, TROP_US_DELAY, true);
285
286 if (this->options & NAND_BUSWIDTH_16) {
287 void __iomem *main_buf = host->main_area0;
288 /* compress the ID info */
289 writeb(readb(main_buf + 2), main_buf + 1);
290 writeb(readb(main_buf + 4), main_buf + 2);
291 writeb(readb(main_buf + 6), main_buf + 3);
292 writeb(readb(main_buf + 8), main_buf + 4);
293 writeb(readb(main_buf + 10), main_buf + 5);
294 }
295 memcpy(host->data_buf, host->main_area0, 16);
296 }
297
298 /* This function requests the NANDFC to perform a read of the
299 * NAND device status and returns the current status. */
300 static uint16_t get_dev_status(struct mxc_nand_host *host)
301 {
302 void __iomem *main_buf = host->main_area1;
303 uint32_t store;
304 uint16_t ret;
305 /* Issue status request to NAND device */
306
307 /* store the main area1 first word, later do recovery */
308 store = readl(main_buf);
309 /* NANDFC buffer 1 is used for device status to prevent
310 * corruption of read/write buffer on status requests. */
311 writew(1, host->regs + NFC_BUF_ADDR);
312
313 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
314
315 /* Wait for operation to complete */
316 wait_op_done(host, TROP_US_DELAY, true);
317
318 /* Status is placed in first word of main buffer */
319 /* get status, then recovery area 1 data */
320 ret = readw(main_buf);
321 writel(store, main_buf);
322
323 return ret;
324 }
325
326 /* This functions is used by upper layer to checks if device is ready */
327 static int mxc_nand_dev_ready(struct mtd_info *mtd)
328 {
329 /*
330 * NFC handles R/B internally. Therefore, this function
331 * always returns status as ready.
332 */
333 return 1;
334 }
335
336 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
337 {
338 /*
339 * If HW ECC is enabled, we turn it on during init. There is
340 * no need to enable again here.
341 */
342 }
343
344 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
345 u_char *read_ecc, u_char *calc_ecc)
346 {
347 struct nand_chip *nand_chip = mtd->priv;
348 struct mxc_nand_host *host = nand_chip->priv;
349
350 /*
351 * 1-Bit errors are automatically corrected in HW. No need for
352 * additional correction. 2-Bit errors cannot be corrected by
353 * HW ECC, so we need to return failure
354 */
355 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
356
357 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
358 DEBUG(MTD_DEBUG_LEVEL0,
359 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
360 return -1;
361 }
362
363 return 0;
364 }
365
366 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
367 u_char *ecc_code)
368 {
369 return 0;
370 }
371
372 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
373 {
374 struct nand_chip *nand_chip = mtd->priv;
375 struct mxc_nand_host *host = nand_chip->priv;
376 uint8_t ret;
377
378 /* Check for status request */
379 if (host->status_request)
380 return get_dev_status(host) & 0xFF;
381
382 ret = *(uint8_t *)(host->data_buf + host->buf_start);
383 host->buf_start++;
384
385 return ret;
386 }
387
388 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
389 {
390 struct nand_chip *nand_chip = mtd->priv;
391 struct mxc_nand_host *host = nand_chip->priv;
392 uint16_t ret;
393
394 ret = *(uint16_t *)(host->data_buf + host->buf_start);
395 host->buf_start += 2;
396
397 return ret;
398 }
399
400 /* Write data of length len to buffer buf. The data to be
401 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
402 * Operation by the NFC, the data is written to NAND Flash */
403 static void mxc_nand_write_buf(struct mtd_info *mtd,
404 const u_char *buf, int len)
405 {
406 struct nand_chip *nand_chip = mtd->priv;
407 struct mxc_nand_host *host = nand_chip->priv;
408 u16 col = host->buf_start;
409 int n = mtd->oobsize + mtd->writesize - col;
410
411 n = min(n, len);
412
413 memcpy(host->data_buf + col, buf, n);
414
415 host->buf_start += n;
416 }
417
418 /* Read the data buffer from the NAND Flash. To read the data from NAND
419 * Flash first the data output cycle is initiated by the NFC, which copies
420 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
421 */
422 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
423 {
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
426 u16 col = host->buf_start;
427 int n = mtd->oobsize + mtd->writesize - col;
428
429 n = min(n, len);
430
431 memcpy(buf, host->data_buf + col, len);
432
433 host->buf_start += len;
434 }
435
436 /* Used by the upper layer to verify the data in NAND Flash
437 * with the data in the buf. */
438 static int mxc_nand_verify_buf(struct mtd_info *mtd,
439 const u_char *buf, int len)
440 {
441 return -EFAULT;
442 }
443
444 /* This function is used by upper layer for select and
445 * deselect of the NAND chip */
446 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
447 {
448 struct nand_chip *nand_chip = mtd->priv;
449 struct mxc_nand_host *host = nand_chip->priv;
450
451 switch (chip) {
452 case -1:
453 /* Disable the NFC clock */
454 if (host->clk_act) {
455 clk_disable(host->clk);
456 host->clk_act = 0;
457 }
458 break;
459 case 0:
460 /* Enable the NFC clock */
461 if (!host->clk_act) {
462 clk_enable(host->clk);
463 host->clk_act = 1;
464 }
465 break;
466
467 default:
468 break;
469 }
470 }
471
472 /*
473 * Function to transfer data to/from spare area.
474 */
475 static void copy_spare(struct mtd_info *mtd, bool bfrom)
476 {
477 struct nand_chip *this = mtd->priv;
478 struct mxc_nand_host *host = this->priv;
479 u16 i, j;
480 u16 n = mtd->writesize >> 9;
481 u8 *d = host->data_buf + mtd->writesize;
482 u8 *s = host->spare0;
483 u16 t = host->spare_len;
484
485 j = (mtd->oobsize / n >> 1) << 1;
486
487 if (bfrom) {
488 for (i = 0; i < n - 1; i++)
489 memcpy(d + i * j, s + i * t, j);
490
491 /* the last section */
492 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
493 } else {
494 for (i = 0; i < n - 1; i++)
495 memcpy(&s[i * t], &d[i * j], j);
496
497 /* the last section */
498 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
499 }
500 }
501
502 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
503 {
504 struct nand_chip *nand_chip = mtd->priv;
505 struct mxc_nand_host *host = nand_chip->priv;
506
507 /* Write out column address, if necessary */
508 if (column != -1) {
509 /*
510 * MXC NANDFC can only perform full page+spare or
511 * spare-only read/write. When the upper layers
512 * layers perform a read/write buf operation,
513 * we will used the saved column adress to index into
514 * the full page.
515 */
516 send_addr(host, 0, page_addr == -1);
517 if (mtd->writesize > 512)
518 /* another col addr cycle for 2k page */
519 send_addr(host, 0, false);
520 }
521
522 /* Write out page address, if necessary */
523 if (page_addr != -1) {
524 /* paddr_0 - p_addr_7 */
525 send_addr(host, (page_addr & 0xff), false);
526
527 if (mtd->writesize > 512) {
528 if (mtd->size >= 0x10000000) {
529 /* paddr_8 - paddr_15 */
530 send_addr(host, (page_addr >> 8) & 0xff, false);
531 send_addr(host, (page_addr >> 16) & 0xff, true);
532 } else
533 /* paddr_8 - paddr_15 */
534 send_addr(host, (page_addr >> 8) & 0xff, true);
535 } else {
536 /* One more address cycle for higher density devices */
537 if (mtd->size >= 0x4000000) {
538 /* paddr_8 - paddr_15 */
539 send_addr(host, (page_addr >> 8) & 0xff, false);
540 send_addr(host, (page_addr >> 16) & 0xff, true);
541 } else
542 /* paddr_8 - paddr_15 */
543 send_addr(host, (page_addr >> 8) & 0xff, true);
544 }
545 }
546 }
547
548 /* Used by the upper layer to write command to NAND Flash for
549 * different operations to be carried out on NAND Flash */
550 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
551 int column, int page_addr)
552 {
553 struct nand_chip *nand_chip = mtd->priv;
554 struct mxc_nand_host *host = nand_chip->priv;
555
556 DEBUG(MTD_DEBUG_LEVEL3,
557 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
558 command, column, page_addr);
559
560 /* Reset command state information */
561 host->status_request = false;
562
563 /* Command pre-processing step */
564 switch (command) {
565
566 case NAND_CMD_STATUS:
567 host->buf_start = 0;
568 host->status_request = true;
569
570 send_cmd(host, command, true);
571 mxc_do_addr_cycle(mtd, column, page_addr);
572 break;
573
574 case NAND_CMD_READ0:
575 case NAND_CMD_READOOB:
576 if (command == NAND_CMD_READ0)
577 host->buf_start = column;
578 else
579 host->buf_start = column + mtd->writesize;
580
581 if (mtd->writesize > 512)
582 command = NAND_CMD_READ0; /* only READ0 is valid */
583
584 send_cmd(host, command, false);
585 mxc_do_addr_cycle(mtd, column, page_addr);
586
587 if (mtd->writesize > 512)
588 send_cmd(host, NAND_CMD_READSTART, true);
589
590 send_page(mtd, NFC_OUTPUT);
591
592 memcpy(host->data_buf, host->main_area0, mtd->writesize);
593 copy_spare(mtd, true);
594 break;
595
596 case NAND_CMD_SEQIN:
597 if (column >= mtd->writesize) {
598 /*
599 * FIXME: before send SEQIN command for write OOB,
600 * We must read one page out.
601 * For K9F1GXX has no READ1 command to set current HW
602 * pointer to spare area, we must write the whole page
603 * including OOB together.
604 */
605 if (mtd->writesize > 512)
606 /* call ourself to read a page */
607 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
608 page_addr);
609
610 host->buf_start = column;
611
612 /* Set program pointer to spare region */
613 if (mtd->writesize == 512)
614 send_cmd(host, NAND_CMD_READOOB, false);
615 } else {
616 host->buf_start = column;
617
618 /* Set program pointer to page start */
619 if (mtd->writesize == 512)
620 send_cmd(host, NAND_CMD_READ0, false);
621 }
622
623 send_cmd(host, command, false);
624 mxc_do_addr_cycle(mtd, column, page_addr);
625 break;
626
627 case NAND_CMD_PAGEPROG:
628 memcpy(host->main_area0, host->data_buf, mtd->writesize);
629 copy_spare(mtd, false);
630 send_page(mtd, NFC_INPUT);
631 send_cmd(host, command, true);
632 mxc_do_addr_cycle(mtd, column, page_addr);
633 break;
634
635 case NAND_CMD_READID:
636 send_cmd(host, command, true);
637 mxc_do_addr_cycle(mtd, column, page_addr);
638 send_read_id(host);
639 host->buf_start = column;
640 break;
641
642 case NAND_CMD_ERASE1:
643 case NAND_CMD_ERASE2:
644 send_cmd(host, command, false);
645 mxc_do_addr_cycle(mtd, column, page_addr);
646
647 break;
648 }
649 }
650
651 static int __init mxcnd_probe(struct platform_device *pdev)
652 {
653 struct nand_chip *this;
654 struct mtd_info *mtd;
655 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
656 struct mxc_nand_host *host;
657 struct resource *res;
658 uint16_t tmp;
659 int err = 0, nr_parts = 0;
660 struct nand_ecclayout *oob_smallpage, *oob_largepage;
661
662 /* Allocate memory for MTD device structure and private data */
663 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
664 NAND_MAX_OOBSIZE, GFP_KERNEL);
665 if (!host)
666 return -ENOMEM;
667
668 host->data_buf = (uint8_t *)(host + 1);
669
670 host->dev = &pdev->dev;
671 /* structures must be linked */
672 this = &host->nand;
673 mtd = &host->mtd;
674 mtd->priv = this;
675 mtd->owner = THIS_MODULE;
676 mtd->dev.parent = &pdev->dev;
677 mtd->name = "mxc_nand";
678
679 /* 50 us command delay time */
680 this->chip_delay = 5;
681
682 this->priv = host;
683 this->dev_ready = mxc_nand_dev_ready;
684 this->cmdfunc = mxc_nand_command;
685 this->select_chip = mxc_nand_select_chip;
686 this->read_byte = mxc_nand_read_byte;
687 this->read_word = mxc_nand_read_word;
688 this->write_buf = mxc_nand_write_buf;
689 this->read_buf = mxc_nand_read_buf;
690 this->verify_buf = mxc_nand_verify_buf;
691
692 host->clk = clk_get(&pdev->dev, "nfc");
693 if (IS_ERR(host->clk)) {
694 err = PTR_ERR(host->clk);
695 goto eclk;
696 }
697
698 clk_enable(host->clk);
699 host->clk_act = 1;
700
701 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
702 if (!res) {
703 err = -ENODEV;
704 goto eres;
705 }
706
707 host->base = ioremap(res->start, resource_size(res));
708 if (!host->base) {
709 err = -ENOMEM;
710 goto eres;
711 }
712
713 host->main_area0 = host->base;
714 host->main_area1 = host->base + 0x200;
715
716 if (nfc_is_v21()) {
717 host->regs = host->base + 0x1000;
718 host->spare0 = host->base + 0x1000;
719 host->spare_len = 64;
720 oob_smallpage = &nandv2_hw_eccoob_smallpage;
721 oob_largepage = &nandv2_hw_eccoob_largepage;
722 } else if (nfc_is_v1()) {
723 host->regs = host->base;
724 host->spare0 = host->base + 0x800;
725 host->spare_len = 16;
726 oob_smallpage = &nandv1_hw_eccoob_smallpage;
727 oob_largepage = &nandv1_hw_eccoob_largepage;
728 } else
729 BUG();
730
731 /* disable interrupt and spare enable */
732 tmp = readw(host->regs + NFC_CONFIG1);
733 tmp |= NFC_INT_MSK;
734 tmp &= ~NFC_SP_EN;
735 writew(tmp, host->regs + NFC_CONFIG1);
736
737 init_waitqueue_head(&host->irq_waitq);
738
739 host->irq = platform_get_irq(pdev, 0);
740
741 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
742 if (err)
743 goto eirq;
744
745 /* Reset NAND */
746 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
747
748 /* preset operation */
749 /* Unlock the internal RAM Buffer */
750 writew(0x2, host->regs + NFC_CONFIG);
751
752 /* Blocks to be unlocked */
753 if (nfc_is_v21()) {
754 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
755 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
756 this->ecc.bytes = 9;
757 } else if (nfc_is_v1()) {
758 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
759 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
760 this->ecc.bytes = 3;
761 } else
762 BUG();
763
764 /* Unlock Block Command for given address range */
765 writew(0x4, host->regs + NFC_WRPROT);
766
767 this->ecc.size = 512;
768 this->ecc.layout = oob_smallpage;
769
770 if (pdata->hw_ecc) {
771 this->ecc.calculate = mxc_nand_calculate_ecc;
772 this->ecc.hwctl = mxc_nand_enable_hwecc;
773 this->ecc.correct = mxc_nand_correct_data;
774 this->ecc.mode = NAND_ECC_HW;
775 tmp = readw(host->regs + NFC_CONFIG1);
776 tmp |= NFC_ECC_EN;
777 writew(tmp, host->regs + NFC_CONFIG1);
778 } else {
779 this->ecc.mode = NAND_ECC_SOFT;
780 tmp = readw(host->regs + NFC_CONFIG1);
781 tmp &= ~NFC_ECC_EN;
782 writew(tmp, host->regs + NFC_CONFIG1);
783 }
784
785 /* NAND bus width determines access funtions used by upper layer */
786 if (pdata->width == 2)
787 this->options |= NAND_BUSWIDTH_16;
788
789 /* first scan to find the device and get the page size */
790 if (nand_scan_ident(mtd, 1)) {
791 err = -ENXIO;
792 goto escan;
793 }
794
795 if (mtd->writesize == 2048)
796 this->ecc.layout = oob_largepage;
797
798 /* second phase scan */
799 if (nand_scan_tail(mtd)) {
800 err = -ENXIO;
801 goto escan;
802 }
803
804 /* Register the partitions */
805 #ifdef CONFIG_MTD_PARTITIONS
806 nr_parts =
807 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
808 if (nr_parts > 0)
809 add_mtd_partitions(mtd, host->parts, nr_parts);
810 else
811 #endif
812 {
813 pr_info("Registering %s as whole device\n", mtd->name);
814 add_mtd_device(mtd);
815 }
816
817 platform_set_drvdata(pdev, host);
818
819 return 0;
820
821 escan:
822 free_irq(host->irq, host);
823 eirq:
824 iounmap(host->base);
825 eres:
826 clk_put(host->clk);
827 eclk:
828 kfree(host);
829
830 return err;
831 }
832
833 static int __exit mxcnd_remove(struct platform_device *pdev)
834 {
835 struct mxc_nand_host *host = platform_get_drvdata(pdev);
836
837 clk_put(host->clk);
838
839 platform_set_drvdata(pdev, NULL);
840
841 nand_release(&host->mtd);
842 free_irq(host->irq, host);
843 iounmap(host->base);
844 kfree(host);
845
846 return 0;
847 }
848
849 #ifdef CONFIG_PM
850 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
851 {
852 struct mtd_info *mtd = platform_get_drvdata(pdev);
853 struct nand_chip *nand_chip = mtd->priv;
854 struct mxc_nand_host *host = nand_chip->priv;
855 int ret = 0;
856
857 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
858 if (mtd) {
859 ret = mtd->suspend(mtd);
860 /* Disable the NFC clock */
861 clk_disable(host->clk);
862 }
863
864 return ret;
865 }
866
867 static int mxcnd_resume(struct platform_device *pdev)
868 {
869 struct mtd_info *mtd = platform_get_drvdata(pdev);
870 struct nand_chip *nand_chip = mtd->priv;
871 struct mxc_nand_host *host = nand_chip->priv;
872 int ret = 0;
873
874 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
875
876 if (mtd) {
877 /* Enable the NFC clock */
878 clk_enable(host->clk);
879 mtd->resume(mtd);
880 }
881
882 return ret;
883 }
884
885 #else
886 # define mxcnd_suspend NULL
887 # define mxcnd_resume NULL
888 #endif /* CONFIG_PM */
889
890 static struct platform_driver mxcnd_driver = {
891 .driver = {
892 .name = DRIVER_NAME,
893 },
894 .remove = __exit_p(mxcnd_remove),
895 .suspend = mxcnd_suspend,
896 .resume = mxcnd_resume,
897 };
898
899 static int __init mxc_nd_init(void)
900 {
901 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
902 }
903
904 static void __exit mxc_nd_cleanup(void)
905 {
906 /* Unregister the device structure */
907 platform_driver_unregister(&mxcnd_driver);
908 }
909
910 module_init(mxc_nd_init);
911 module_exit(mxc_nd_cleanup);
912
913 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
914 MODULE_DESCRIPTION("MXC NAND MTD driver");
915 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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