projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mtd: nand: teach write_page and write_page_raw return an error code
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <linux/io.h>
50 #include <linux/mtd/partitions.h>
51
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61 };
62
63 static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69 };
70
71 static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80 };
81
82 static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94 };
95
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102 /*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106 DEFINE_LED_TRIGGER(nand_led_trigger);
107
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110 {
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
123 ret = -EINVAL;
124 }
125
126 return ret;
127 }
128
129 /**
130 * nand_release_device - [GENERIC] release chip
131 * @mtd: MTD device structure
132 *
133 * Deselect, release chip lock and wake up anyone waiting on the device.
134 */
135 static void nand_release_device(struct mtd_info *mtd)
136 {
137 struct nand_chip *chip = mtd->priv;
138
139 /* De-select the NAND device */
140 chip->select_chip(mtd, -1);
141
142 /* Release the controller and the chip */
143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
148 }
149
150 /**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
152 * @mtd: MTD device structure
153 *
154 * Default read function for 8bit buswidth
155 */
156 static uint8_t nand_read_byte(struct mtd_info *mtd)
157 {
158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
160 }
161
162 /**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
165 * @mtd: MTD device structure
166 *
167 * Default read function for 16bit buswidth with endianness conversion.
168 *
169 */
170 static uint8_t nand_read_byte16(struct mtd_info *mtd)
171 {
172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
174 }
175
176 /**
177 * nand_read_word - [DEFAULT] read one word from the chip
178 * @mtd: MTD device structure
179 *
180 * Default read function for 16bit buswidth without endianness conversion.
181 */
182 static u16 nand_read_word(struct mtd_info *mtd)
183 {
184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
186 }
187
188 /**
189 * nand_select_chip - [DEFAULT] control CE line
190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
192 *
193 * Default select function for 1 chip devices.
194 */
195 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
196 {
197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
200 case -1:
201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
202 break;
203 case 0:
204 break;
205
206 default:
207 BUG();
208 }
209 }
210
211 /**
212 * nand_write_buf - [DEFAULT] write buffer to chip
213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
216 *
217 * Default write function for 8bit buswidth.
218 */
219 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
220 {
221 int i;
222 struct nand_chip *chip = mtd->priv;
223
224 for (i = 0; i < len; i++)
225 writeb(buf[i], chip->IO_ADDR_W);
226 }
227
228 /**
229 * nand_read_buf - [DEFAULT] read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
233 *
234 * Default read function for 8bit buswidth.
235 */
236 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
237 {
238 int i;
239 struct nand_chip *chip = mtd->priv;
240
241 for (i = 0; i < len; i++)
242 buf[i] = readb(chip->IO_ADDR_R);
243 }
244
245 /**
246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
250 *
251 * Default verify function for 8bit buswidth.
252 */
253 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
254 {
255 int i;
256 struct nand_chip *chip = mtd->priv;
257
258 for (i = 0; i < len; i++)
259 if (buf[i] != readb(chip->IO_ADDR_R))
260 return -EFAULT;
261 return 0;
262 }
263
264 /**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
269 *
270 * Default write function for 16bit buswidth.
271 */
272 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
273 {
274 int i;
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
277 len >>= 1;
278
279 for (i = 0; i < len; i++)
280 writew(p[i], chip->IO_ADDR_W);
281
282 }
283
284 /**
285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
289 *
290 * Default read function for 16bit buswidth.
291 */
292 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
293 {
294 int i;
295 struct nand_chip *chip = mtd->priv;
296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
299 for (i = 0; i < len; i++)
300 p[i] = readw(chip->IO_ADDR_R);
301 }
302
303 /**
304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
308 *
309 * Default verify function for 16bit buswidth.
310 */
311 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
312 {
313 int i;
314 struct nand_chip *chip = mtd->priv;
315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
318 for (i = 0; i < len; i++)
319 if (p[i] != readw(chip->IO_ADDR_R))
320 return -EFAULT;
321
322 return 0;
323 }
324
325 /**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
330 *
331 * Check, if the block is bad.
332 */
333 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334 {
335 int page, chipnr, res = 0, i = 0;
336 struct nand_chip *chip = mtd->priv;
337 u16 bad;
338
339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
340 ofs += mtd->erasesize - mtd->writesize;
341
342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
344 if (getchip) {
345 chipnr = (int)(ofs >> chip->chip_shift);
346
347 nand_get_device(chip, mtd, FL_READING);
348
349 /* Select the NAND device */
350 chip->select_chip(mtd, chipnr);
351 }
352
353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
370 else
371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
376
377 if (getchip)
378 nand_release_device(mtd);
379
380 return res;
381 }
382
383 /**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
387 *
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
397 */
398 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399 {
400 struct nand_chip *chip = mtd->priv;
401 uint8_t buf[2] = { 0, 0 };
402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
404
405 if (write_oob) {
406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
416 /* Get block number */
417 block = (int)(ofs >> chip->bbt_erase_shift);
418 /* Mark block bad in memory-based BBT */
419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
421
422 /* Write bad block marker to OOB */
423 if (write_oob) {
424 struct mtd_oob_ops ops;
425 loff_t wr_ofs = ofs;
426
427 nand_get_device(chip, mtd, FL_WRITING);
428
429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
438 ops.mode = MTD_OPS_PLACE_OOB;
439
440 /* Write to first/last page(s) if necessary */
441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
443 do {
444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
447
448 i++;
449 wr_ofs += mtd->writesize;
450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
451
452 nand_release_device(mtd);
453 }
454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
462 if (!ret)
463 mtd->ecc_stats.badblocks++;
464
465 return ret;
466 }
467
468 /**
469 * nand_check_wp - [GENERIC] check if the chip is write protected
470 * @mtd: MTD device structure
471 *
472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
474 */
475 static int nand_check_wp(struct mtd_info *mtd)
476 {
477 struct nand_chip *chip = mtd->priv;
478
479 /* Broken xD cards report WP despite being writable */
480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
483 /* Check the WP bit */
484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
486 }
487
488 /**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
498 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
500 {
501 struct nand_chip *chip = mtd->priv;
502
503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
505
506 /* Return info from the table */
507 return nand_isbad_bbt(mtd, ofs, allowbbt);
508 }
509
510 /**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
512 * @mtd: MTD device structure
513 * @timeo: Timeout
514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519 {
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530 }
531
532 /* Wait for the ready pin, after a command. The timeout is caught later. */
533 void nand_wait_ready(struct mtd_info *mtd)
534 {
535 struct nand_chip *chip = mtd->priv;
536 unsigned long timeo = jiffies + 2;
537
538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
542 led_trigger_event(nand_led_trigger, LED_FULL);
543 /* Wait until command is processed or timeout occurs */
544 do {
545 if (chip->dev_ready(mtd))
546 break;
547 touch_softlockup_watchdog();
548 } while (time_before(jiffies, timeo));
549 led_trigger_event(nand_led_trigger, LED_OFF);
550 }
551 EXPORT_SYMBOL_GPL(nand_wait_ready);
552
553 /**
554 * nand_command - [DEFAULT] Send command to NAND device
555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
559 *
560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
562 */
563 static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
565 {
566 register struct nand_chip *chip = mtd->priv;
567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
568
569 /* Write out the command to the device */
570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
573 if (column >= mtd->writesize) {
574 /* OOB area */
575 column -= mtd->writesize;
576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
584 chip->cmd_ctrl(mtd, readcmd, ctrl);
585 ctrl &= ~NAND_CTRL_CHANGE;
586 }
587 chip->cmd_ctrl(mtd, command, ctrl);
588
589 /* Address cycle, when necessary */
590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
594 if (chip->options & NAND_BUSWIDTH_16)
595 column >>= 1;
596 chip->cmd_ctrl(mtd, column, ctrl);
597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
600 chip->cmd_ctrl(mtd, page_addr, ctrl);
601 ctrl &= ~NAND_CTRL_CHANGE;
602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
603 /* One more address cycle for devices > 32MiB */
604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
606 }
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
608
609 /*
610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
612 */
613 switch (command) {
614
615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
623 if (chip->dev_ready)
624 break;
625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
632 return;
633
634 /* This applies to read commands */
635 default:
636 /*
637 * If we don't have access to the busy pin, we apply the given
638 * command delay
639 */
640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
642 return;
643 }
644 }
645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
649 ndelay(100);
650
651 nand_wait_ready(mtd);
652 }
653
654 /**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
660 *
661 * Send command to NAND device. This is the version for the new large page
662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
664 */
665 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
667 {
668 register struct nand_chip *chip = mtd->priv;
669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
672 column += mtd->writesize;
673 command = NAND_CMD_READ0;
674 }
675
676 /* Command latch cycle */
677 chip->cmd_ctrl(mtd, command & 0xff,
678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
679
680 if (column != -1 || page_addr != -1) {
681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
686 if (chip->options & NAND_BUSWIDTH_16)
687 column >>= 1;
688 chip->cmd_ctrl(mtd, column, ctrl);
689 ctrl &= ~NAND_CTRL_CHANGE;
690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
691 }
692 if (page_addr != -1) {
693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
695 NAND_NCE | NAND_ALE);
696 /* One more address cycle for devices > 128MiB */
697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
699 NAND_NCE | NAND_ALE);
700 }
701 }
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
703
704 /*
705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
707 */
708 switch (command) {
709
710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
715 case NAND_CMD_RNDIN:
716 case NAND_CMD_STATUS:
717 case NAND_CMD_DEPLETE1:
718 return;
719
720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
725 /* Read error status commands require only a short delay */
726 udelay(chip->chip_delay);
727 return;
728
729 case NAND_CMD_RESET:
730 if (chip->dev_ready)
731 break;
732 udelay(chip->chip_delay);
733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
739 return;
740
741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
749 case NAND_CMD_READ0:
750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
754
755 /* This applies to read commands */
756 default:
757 /*
758 * If we don't have access to the busy pin, we apply the given
759 * command delay.
760 */
761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
763 return;
764 }
765 }
766
767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
771 ndelay(100);
772
773 nand_wait_ready(mtd);
774 }
775
776 /**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
781 *
782 * Used when in panic, no locks are taken.
783 */
784 static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786 {
787 /* Hardware controller shared among independent devices */
788 chip->controller->active = chip;
789 chip->state = new_state;
790 }
791
792 /**
793 * nand_get_device - [GENERIC] Get chip for selected access
794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
797 *
798 * Get the device and lock it for exclusive access
799 */
800 static int
801 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
802 {
803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
805 DECLARE_WAITQUEUE(wait, current);
806 retry:
807 spin_lock(lock);
808
809 /* Hardware controller shared among independent devices */
810 if (!chip->controller->active)
811 chip->controller->active = chip;
812
813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
815 spin_unlock(lock);
816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
823 }
824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
830 goto retry;
831 }
832
833 /**
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
842 */
843 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845 {
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
856 }
857 }
858
859 /**
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
863 *
864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
867 */
868 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
869 {
870
871 unsigned long timeo = jiffies;
872 int status, state = chip->state;
873
874 if (state == FL_ERASING)
875 timeo += (HZ * 400) / 1000;
876 else
877 timeo += (HZ * 20) / 1000;
878
879 led_trigger_event(nand_led_trigger, LED_FULL);
880
881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
885 ndelay(100);
886
887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
889 else
890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
891
892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
904 }
905 }
906 led_trigger_event(nand_led_trigger, LED_OFF);
907
908 status = (int)chip->read_byte(mtd);
909 return status;
910 }
911
912 /**
913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
921 *
922 * Returs unlock status.
923 */
924 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926 {
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
944 pr_debug("%s: error status = 0x%08x\n",
945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950 }
951
952 /**
953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
957 *
958 * Returns unlock status.
959 */
960 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961 {
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
985 pr_debug("%s: device is write protected!\n",
986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993 out:
994 nand_release_device(mtd);
995
996 return ret;
997 }
998 EXPORT_SYMBOL(nand_unlock);
999
1000 /**
1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
1005 *
1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
1010 *
1011 * Returns lock status.
1012 */
1013 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014 {
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
1034 pr_debug("%s: device is write protected!\n",
1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
1049 pr_debug("%s: error status = 0x%08x\n",
1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057 out:
1058 nand_release_device(mtd);
1059
1060 return ret;
1061 }
1062 EXPORT_SYMBOL(nand_lock);
1063
1064 /**
1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @oob_required: caller requires OOB data read to chip->oob_poi
1070 * @page: page number to read
1071 *
1072 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1073 */
1074 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1075 uint8_t *buf, int oob_required, int page)
1076 {
1077 chip->read_buf(mtd, buf, mtd->writesize);
1078 if (oob_required)
1079 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1080 return 0;
1081 }
1082
1083 /**
1084 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1085 * @mtd: mtd info structure
1086 * @chip: nand chip info structure
1087 * @buf: buffer to store read data
1088 * @oob_required: caller requires OOB data read to chip->oob_poi
1089 * @page: page number to read
1090 *
1091 * We need a special oob layout and handling even when OOB isn't used.
1092 */
1093 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1094 struct nand_chip *chip, uint8_t *buf,
1095 int oob_required, int page)
1096 {
1097 int eccsize = chip->ecc.size;
1098 int eccbytes = chip->ecc.bytes;
1099 uint8_t *oob = chip->oob_poi;
1100 int steps, size;
1101
1102 for (steps = chip->ecc.steps; steps > 0; steps--) {
1103 chip->read_buf(mtd, buf, eccsize);
1104 buf += eccsize;
1105
1106 if (chip->ecc.prepad) {
1107 chip->read_buf(mtd, oob, chip->ecc.prepad);
1108 oob += chip->ecc.prepad;
1109 }
1110
1111 chip->read_buf(mtd, oob, eccbytes);
1112 oob += eccbytes;
1113
1114 if (chip->ecc.postpad) {
1115 chip->read_buf(mtd, oob, chip->ecc.postpad);
1116 oob += chip->ecc.postpad;
1117 }
1118 }
1119
1120 size = mtd->oobsize - (oob - chip->oob_poi);
1121 if (size)
1122 chip->read_buf(mtd, oob, size);
1123
1124 return 0;
1125 }
1126
1127 /**
1128 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1129 * @mtd: mtd info structure
1130 * @chip: nand chip info structure
1131 * @buf: buffer to store read data
1132 * @oob_required: caller requires OOB data read to chip->oob_poi
1133 * @page: page number to read
1134 */
1135 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1136 uint8_t *buf, int oob_required, int page)
1137 {
1138 int i, eccsize = chip->ecc.size;
1139 int eccbytes = chip->ecc.bytes;
1140 int eccsteps = chip->ecc.steps;
1141 uint8_t *p = buf;
1142 uint8_t *ecc_calc = chip->buffers->ecccalc;
1143 uint8_t *ecc_code = chip->buffers->ecccode;
1144 uint32_t *eccpos = chip->ecc.layout->eccpos;
1145 unsigned int max_bitflips = 0;
1146
1147 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1148
1149 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1150 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1151
1152 for (i = 0; i < chip->ecc.total; i++)
1153 ecc_code[i] = chip->oob_poi[eccpos[i]];
1154
1155 eccsteps = chip->ecc.steps;
1156 p = buf;
1157
1158 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1159 int stat;
1160
1161 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1162 if (stat < 0) {
1163 mtd->ecc_stats.failed++;
1164 } else {
1165 mtd->ecc_stats.corrected += stat;
1166 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1167 }
1168 }
1169 return max_bitflips;
1170 }
1171
1172 /**
1173 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1174 * @mtd: mtd info structure
1175 * @chip: nand chip info structure
1176 * @data_offs: offset of requested data within the page
1177 * @readlen: data length
1178 * @bufpoi: buffer to store read data
1179 */
1180 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1181 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1182 {
1183 int start_step, end_step, num_steps;
1184 uint32_t *eccpos = chip->ecc.layout->eccpos;
1185 uint8_t *p;
1186 int data_col_addr, i, gaps = 0;
1187 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1188 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1189 int index = 0;
1190 unsigned int max_bitflips = 0;
1191
1192 /* Column address within the page aligned to ECC size (256bytes) */
1193 start_step = data_offs / chip->ecc.size;
1194 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1195 num_steps = end_step - start_step + 1;
1196
1197 /* Data size aligned to ECC ecc.size */
1198 datafrag_len = num_steps * chip->ecc.size;
1199 eccfrag_len = num_steps * chip->ecc.bytes;
1200
1201 data_col_addr = start_step * chip->ecc.size;
1202 /* If we read not a page aligned data */
1203 if (data_col_addr != 0)
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1205
1206 p = bufpoi + data_col_addr;
1207 chip->read_buf(mtd, p, datafrag_len);
1208
1209 /* Calculate ECC */
1210 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1211 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1212
1213 /*
1214 * The performance is faster if we position offsets according to
1215 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1216 */
1217 for (i = 0; i < eccfrag_len - 1; i++) {
1218 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1219 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1220 gaps = 1;
1221 break;
1222 }
1223 }
1224 if (gaps) {
1225 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1226 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1227 } else {
1228 /*
1229 * Send the command to read the particular ECC bytes take care
1230 * about buswidth alignment in read_buf.
1231 */
1232 index = start_step * chip->ecc.bytes;
1233
1234 aligned_pos = eccpos[index] & ~(busw - 1);
1235 aligned_len = eccfrag_len;
1236 if (eccpos[index] & (busw - 1))
1237 aligned_len++;
1238 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1239 aligned_len++;
1240
1241 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1242 mtd->writesize + aligned_pos, -1);
1243 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1244 }
1245
1246 for (i = 0; i < eccfrag_len; i++)
1247 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1248
1249 p = bufpoi + data_col_addr;
1250 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1251 int stat;
1252
1253 stat = chip->ecc.correct(mtd, p,
1254 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1255 if (stat < 0) {
1256 mtd->ecc_stats.failed++;
1257 } else {
1258 mtd->ecc_stats.corrected += stat;
1259 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1260 }
1261 }
1262 return max_bitflips;
1263 }
1264
1265 /**
1266 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1267 * @mtd: mtd info structure
1268 * @chip: nand chip info structure
1269 * @buf: buffer to store read data
1270 * @oob_required: caller requires OOB data read to chip->oob_poi
1271 * @page: page number to read
1272 *
1273 * Not for syndrome calculating ECC controllers which need a special oob layout.
1274 */
1275 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1276 uint8_t *buf, int oob_required, int page)
1277 {
1278 int i, eccsize = chip->ecc.size;
1279 int eccbytes = chip->ecc.bytes;
1280 int eccsteps = chip->ecc.steps;
1281 uint8_t *p = buf;
1282 uint8_t *ecc_calc = chip->buffers->ecccalc;
1283 uint8_t *ecc_code = chip->buffers->ecccode;
1284 uint32_t *eccpos = chip->ecc.layout->eccpos;
1285 unsigned int max_bitflips = 0;
1286
1287 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1291 }
1292 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1293
1294 for (i = 0; i < chip->ecc.total; i++)
1295 ecc_code[i] = chip->oob_poi[eccpos[i]];
1296
1297 eccsteps = chip->ecc.steps;
1298 p = buf;
1299
1300 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1301 int stat;
1302
1303 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1304 if (stat < 0) {
1305 mtd->ecc_stats.failed++;
1306 } else {
1307 mtd->ecc_stats.corrected += stat;
1308 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1309 }
1310 }
1311 return max_bitflips;
1312 }
1313
1314 /**
1315 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @buf: buffer to store read data
1319 * @oob_required: caller requires OOB data read to chip->oob_poi
1320 * @page: page number to read
1321 *
1322 * Hardware ECC for large page chips, require OOB to be read first. For this
1323 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1324 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1325 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1326 * the data area, by overwriting the NAND manufacturer bad block markings.
1327 */
1328 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1329 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1330 {
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
1335 uint8_t *ecc_code = chip->buffers->ecccode;
1336 uint32_t *eccpos = chip->ecc.layout->eccpos;
1337 uint8_t *ecc_calc = chip->buffers->ecccalc;
1338 unsigned int max_bitflips = 0;
1339
1340 /* Read the OOB area first */
1341 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1342 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1343 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1344
1345 for (i = 0; i < chip->ecc.total; i++)
1346 ecc_code[i] = chip->oob_poi[eccpos[i]];
1347
1348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1349 int stat;
1350
1351 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352 chip->read_buf(mtd, p, eccsize);
1353 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1354
1355 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1356 if (stat < 0) {
1357 mtd->ecc_stats.failed++;
1358 } else {
1359 mtd->ecc_stats.corrected += stat;
1360 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1361 }
1362 }
1363 return max_bitflips;
1364 }
1365
1366 /**
1367 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @buf: buffer to store read data
1371 * @oob_required: caller requires OOB data read to chip->oob_poi
1372 * @page: page number to read
1373 *
1374 * The hw generator calculates the error syndrome automatically. Therefore we
1375 * need a special oob layout and handling.
1376 */
1377 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1378 uint8_t *buf, int oob_required, int page)
1379 {
1380 int i, eccsize = chip->ecc.size;
1381 int eccbytes = chip->ecc.bytes;
1382 int eccsteps = chip->ecc.steps;
1383 uint8_t *p = buf;
1384 uint8_t *oob = chip->oob_poi;
1385 unsigned int max_bitflips = 0;
1386
1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1388 int stat;
1389
1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1392
1393 if (chip->ecc.prepad) {
1394 chip->read_buf(mtd, oob, chip->ecc.prepad);
1395 oob += chip->ecc.prepad;
1396 }
1397
1398 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1399 chip->read_buf(mtd, oob, eccbytes);
1400 stat = chip->ecc.correct(mtd, p, oob, NULL);
1401
1402 if (stat < 0) {
1403 mtd->ecc_stats.failed++;
1404 } else {
1405 mtd->ecc_stats.corrected += stat;
1406 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1407 }
1408
1409 oob += eccbytes;
1410
1411 if (chip->ecc.postpad) {
1412 chip->read_buf(mtd, oob, chip->ecc.postpad);
1413 oob += chip->ecc.postpad;
1414 }
1415 }
1416
1417 /* Calculate remaining oob bytes */
1418 i = mtd->oobsize - (oob - chip->oob_poi);
1419 if (i)
1420 chip->read_buf(mtd, oob, i);
1421
1422 return max_bitflips;
1423 }
1424
1425 /**
1426 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1427 * @chip: nand chip structure
1428 * @oob: oob destination address
1429 * @ops: oob ops structure
1430 * @len: size of oob to transfer
1431 */
1432 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1433 struct mtd_oob_ops *ops, size_t len)
1434 {
1435 switch (ops->mode) {
1436
1437 case MTD_OPS_PLACE_OOB:
1438 case MTD_OPS_RAW:
1439 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1440 return oob + len;
1441
1442 case MTD_OPS_AUTO_OOB: {
1443 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1444 uint32_t boffs = 0, roffs = ops->ooboffs;
1445 size_t bytes = 0;
1446
1447 for (; free->length && len; free++, len -= bytes) {
1448 /* Read request not from offset 0? */
1449 if (unlikely(roffs)) {
1450 if (roffs >= free->length) {
1451 roffs -= free->length;
1452 continue;
1453 }
1454 boffs = free->offset + roffs;
1455 bytes = min_t(size_t, len,
1456 (free->length - roffs));
1457 roffs = 0;
1458 } else {
1459 bytes = min_t(size_t, len, free->length);
1460 boffs = free->offset;
1461 }
1462 memcpy(oob, chip->oob_poi + boffs, bytes);
1463 oob += bytes;
1464 }
1465 return oob;
1466 }
1467 default:
1468 BUG();
1469 }
1470 return NULL;
1471 }
1472
1473 /**
1474 * nand_do_read_ops - [INTERN] Read data with ECC
1475 * @mtd: MTD device structure
1476 * @from: offset to read from
1477 * @ops: oob ops structure
1478 *
1479 * Internal function. Called with chip held.
1480 */
1481 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1482 struct mtd_oob_ops *ops)
1483 {
1484 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1485 struct nand_chip *chip = mtd->priv;
1486 struct mtd_ecc_stats stats;
1487 int ret = 0;
1488 uint32_t readlen = ops->len;
1489 uint32_t oobreadlen = ops->ooblen;
1490 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1491 mtd->oobavail : mtd->oobsize;
1492
1493 uint8_t *bufpoi, *oob, *buf;
1494 unsigned int max_bitflips = 0;
1495
1496 stats = mtd->ecc_stats;
1497
1498 chipnr = (int)(from >> chip->chip_shift);
1499 chip->select_chip(mtd, chipnr);
1500
1501 realpage = (int)(from >> chip->page_shift);
1502 page = realpage & chip->pagemask;
1503
1504 col = (int)(from & (mtd->writesize - 1));
1505
1506 buf = ops->datbuf;
1507 oob = ops->oobbuf;
1508 oob_required = oob ? 1 : 0;
1509
1510 while (1) {
1511 bytes = min(mtd->writesize - col, readlen);
1512 aligned = (bytes == mtd->writesize);
1513
1514 /* Is the current page in the buffer? */
1515 if (realpage != chip->pagebuf || oob) {
1516 bufpoi = aligned ? buf : chip->buffers->databuf;
1517
1518 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1519
1520 /*
1521 * Now read the page into the buffer. Absent an error,
1522 * the read methods return max bitflips per ecc step.
1523 */
1524 if (unlikely(ops->mode == MTD_OPS_RAW))
1525 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1526 oob_required,
1527 page);
1528 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1529 ret = chip->ecc.read_subpage(mtd, chip,
1530 col, bytes, bufpoi);
1531 else
1532 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1533 oob_required, page);
1534 if (ret < 0) {
1535 if (!aligned)
1536 /* Invalidate page cache */
1537 chip->pagebuf = -1;
1538 break;
1539 }
1540
1541 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1542
1543 /* Transfer not aligned data */
1544 if (!aligned) {
1545 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1546 !(mtd->ecc_stats.failed - stats.failed) &&
1547 (ops->mode != MTD_OPS_RAW)) {
1548 chip->pagebuf = realpage;
1549 chip->pagebuf_bitflips = ret;
1550 } else {
1551 /* Invalidate page cache */
1552 chip->pagebuf = -1;
1553 }
1554 memcpy(buf, chip->buffers->databuf + col, bytes);
1555 }
1556
1557 buf += bytes;
1558
1559 if (unlikely(oob)) {
1560 int toread = min(oobreadlen, max_oobsize);
1561
1562 if (toread) {
1563 oob = nand_transfer_oob(chip,
1564 oob, ops, toread);
1565 oobreadlen -= toread;
1566 }
1567 }
1568 } else {
1569 memcpy(buf, chip->buffers->databuf + col, bytes);
1570 buf += bytes;
1571 max_bitflips = max_t(unsigned int, max_bitflips,
1572 chip->pagebuf_bitflips);
1573 }
1574
1575 readlen -= bytes;
1576
1577 if (!readlen)
1578 break;
1579
1580 /* For subsequent reads align to page boundary */
1581 col = 0;
1582 /* Increment page address */
1583 realpage++;
1584
1585 page = realpage & chip->pagemask;
1586 /* Check, if we cross a chip boundary */
1587 if (!page) {
1588 chipnr++;
1589 chip->select_chip(mtd, -1);
1590 chip->select_chip(mtd, chipnr);
1591 }
1592 }
1593
1594 ops->retlen = ops->len - (size_t) readlen;
1595 if (oob)
1596 ops->oobretlen = ops->ooblen - oobreadlen;
1597
1598 if (ret < 0)
1599 return ret;
1600
1601 if (mtd->ecc_stats.failed - stats.failed)
1602 return -EBADMSG;
1603
1604 return max_bitflips;
1605 }
1606
1607 /**
1608 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1609 * @mtd: MTD device structure
1610 * @from: offset to read from
1611 * @len: number of bytes to read
1612 * @retlen: pointer to variable to store the number of read bytes
1613 * @buf: the databuffer to put data
1614 *
1615 * Get hold of the chip and call nand_do_read.
1616 */
1617 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1618 size_t *retlen, uint8_t *buf)
1619 {
1620 struct nand_chip *chip = mtd->priv;
1621 struct mtd_oob_ops ops;
1622 int ret;
1623
1624 nand_get_device(chip, mtd, FL_READING);
1625 ops.len = len;
1626 ops.datbuf = buf;
1627 ops.oobbuf = NULL;
1628 ops.mode = 0;
1629 ret = nand_do_read_ops(mtd, from, &ops);
1630 *retlen = ops.retlen;
1631 nand_release_device(mtd);
1632 return ret;
1633 }
1634
1635 /**
1636 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1637 * @mtd: mtd info structure
1638 * @chip: nand chip info structure
1639 * @page: page number to read
1640 */
1641 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1642 int page)
1643 {
1644 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1645 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1646 return 0;
1647 }
1648
1649 /**
1650 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1651 * with syndromes
1652 * @mtd: mtd info structure
1653 * @chip: nand chip info structure
1654 * @page: page number to read
1655 */
1656 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1657 int page)
1658 {
1659 uint8_t *buf = chip->oob_poi;
1660 int length = mtd->oobsize;
1661 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1662 int eccsize = chip->ecc.size;
1663 uint8_t *bufpoi = buf;
1664 int i, toread, sndrnd = 0, pos;
1665
1666 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1667 for (i = 0; i < chip->ecc.steps; i++) {
1668 if (sndrnd) {
1669 pos = eccsize + i * (eccsize + chunk);
1670 if (mtd->writesize > 512)
1671 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1672 else
1673 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1674 } else
1675 sndrnd = 1;
1676 toread = min_t(int, length, chunk);
1677 chip->read_buf(mtd, bufpoi, toread);
1678 bufpoi += toread;
1679 length -= toread;
1680 }
1681 if (length > 0)
1682 chip->read_buf(mtd, bufpoi, length);
1683
1684 return 0;
1685 }
1686
1687 /**
1688 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1689 * @mtd: mtd info structure
1690 * @chip: nand chip info structure
1691 * @page: page number to write
1692 */
1693 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1694 int page)
1695 {
1696 int status = 0;
1697 const uint8_t *buf = chip->oob_poi;
1698 int length = mtd->oobsize;
1699
1700 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1701 chip->write_buf(mtd, buf, length);
1702 /* Send command to program the OOB data */
1703 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1704
1705 status = chip->waitfunc(mtd, chip);
1706
1707 return status & NAND_STATUS_FAIL ? -EIO : 0;
1708 }
1709
1710 /**
1711 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1712 * with syndrome - only for large page flash
1713 * @mtd: mtd info structure
1714 * @chip: nand chip info structure
1715 * @page: page number to write
1716 */
1717 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1718 struct nand_chip *chip, int page)
1719 {
1720 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1721 int eccsize = chip->ecc.size, length = mtd->oobsize;
1722 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1723 const uint8_t *bufpoi = chip->oob_poi;
1724
1725 /*
1726 * data-ecc-data-ecc ... ecc-oob
1727 * or
1728 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1729 */
1730 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1731 pos = steps * (eccsize + chunk);
1732 steps = 0;
1733 } else
1734 pos = eccsize;
1735
1736 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1737 for (i = 0; i < steps; i++) {
1738 if (sndcmd) {
1739 if (mtd->writesize <= 512) {
1740 uint32_t fill = 0xFFFFFFFF;
1741
1742 len = eccsize;
1743 while (len > 0) {
1744 int num = min_t(int, len, 4);
1745 chip->write_buf(mtd, (uint8_t *)&fill,
1746 num);
1747 len -= num;
1748 }
1749 } else {
1750 pos = eccsize + i * (eccsize + chunk);
1751 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1752 }
1753 } else
1754 sndcmd = 1;
1755 len = min_t(int, length, chunk);
1756 chip->write_buf(mtd, bufpoi, len);
1757 bufpoi += len;
1758 length -= len;
1759 }
1760 if (length > 0)
1761 chip->write_buf(mtd, bufpoi, length);
1762
1763 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1764 status = chip->waitfunc(mtd, chip);
1765
1766 return status & NAND_STATUS_FAIL ? -EIO : 0;
1767 }
1768
1769 /**
1770 * nand_do_read_oob - [INTERN] NAND read out-of-band
1771 * @mtd: MTD device structure
1772 * @from: offset to read from
1773 * @ops: oob operations description structure
1774 *
1775 * NAND read out-of-band data from the spare area.
1776 */
1777 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1778 struct mtd_oob_ops *ops)
1779 {
1780 int page, realpage, chipnr;
1781 struct nand_chip *chip = mtd->priv;
1782 struct mtd_ecc_stats stats;
1783 int readlen = ops->ooblen;
1784 int len;
1785 uint8_t *buf = ops->oobbuf;
1786 int ret = 0;
1787
1788 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1789 __func__, (unsigned long long)from, readlen);
1790
1791 stats = mtd->ecc_stats;
1792
1793 if (ops->mode == MTD_OPS_AUTO_OOB)
1794 len = chip->ecc.layout->oobavail;
1795 else
1796 len = mtd->oobsize;
1797
1798 if (unlikely(ops->ooboffs >= len)) {
1799 pr_debug("%s: attempt to start read outside oob\n",
1800 __func__);
1801 return -EINVAL;
1802 }
1803
1804 /* Do not allow reads past end of device */
1805 if (unlikely(from >= mtd->size ||
1806 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1807 (from >> chip->page_shift)) * len)) {
1808 pr_debug("%s: attempt to read beyond end of device\n",
1809 __func__);
1810 return -EINVAL;
1811 }
1812
1813 chipnr = (int)(from >> chip->chip_shift);
1814 chip->select_chip(mtd, chipnr);
1815
1816 /* Shift to get page */
1817 realpage = (int)(from >> chip->page_shift);
1818 page = realpage & chip->pagemask;
1819
1820 while (1) {
1821 if (ops->mode == MTD_OPS_RAW)
1822 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1823 else
1824 ret = chip->ecc.read_oob(mtd, chip, page);
1825
1826 if (ret < 0)
1827 break;
1828
1829 len = min(len, readlen);
1830 buf = nand_transfer_oob(chip, buf, ops, len);
1831
1832 readlen -= len;
1833 if (!readlen)
1834 break;
1835
1836 /* Increment page address */
1837 realpage++;
1838
1839 page = realpage & chip->pagemask;
1840 /* Check, if we cross a chip boundary */
1841 if (!page) {
1842 chipnr++;
1843 chip->select_chip(mtd, -1);
1844 chip->select_chip(mtd, chipnr);
1845 }
1846 }
1847
1848 ops->oobretlen = ops->ooblen - readlen;
1849
1850 if (ret < 0)
1851 return ret;
1852
1853 if (mtd->ecc_stats.failed - stats.failed)
1854 return -EBADMSG;
1855
1856 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1857 }
1858
1859 /**
1860 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1861 * @mtd: MTD device structure
1862 * @from: offset to read from
1863 * @ops: oob operation description structure
1864 *
1865 * NAND read data and/or out-of-band data.
1866 */
1867 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1868 struct mtd_oob_ops *ops)
1869 {
1870 struct nand_chip *chip = mtd->priv;
1871 int ret = -ENOTSUPP;
1872
1873 ops->retlen = 0;
1874
1875 /* Do not allow reads past end of device */
1876 if (ops->datbuf && (from + ops->len) > mtd->size) {
1877 pr_debug("%s: attempt to read beyond end of device\n",
1878 __func__);
1879 return -EINVAL;
1880 }
1881
1882 nand_get_device(chip, mtd, FL_READING);
1883
1884 switch (ops->mode) {
1885 case MTD_OPS_PLACE_OOB:
1886 case MTD_OPS_AUTO_OOB:
1887 case MTD_OPS_RAW:
1888 break;
1889
1890 default:
1891 goto out;
1892 }
1893
1894 if (!ops->datbuf)
1895 ret = nand_do_read_oob(mtd, from, ops);
1896 else
1897 ret = nand_do_read_ops(mtd, from, ops);
1898
1899 out:
1900 nand_release_device(mtd);
1901 return ret;
1902 }
1903
1904
1905 /**
1906 * nand_write_page_raw - [INTERN] raw page write function
1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @buf: data buffer
1910 * @oob_required: must write chip->oob_poi to OOB
1911 *
1912 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1913 */
1914 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1915 const uint8_t *buf, int oob_required)
1916 {
1917 chip->write_buf(mtd, buf, mtd->writesize);
1918 if (oob_required)
1919 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1920
1921 return 0;
1922 }
1923
1924 /**
1925 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1926 * @mtd: mtd info structure
1927 * @chip: nand chip info structure
1928 * @buf: data buffer
1929 * @oob_required: must write chip->oob_poi to OOB
1930 *
1931 * We need a special oob layout and handling even when ECC isn't checked.
1932 */
1933 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1934 struct nand_chip *chip,
1935 const uint8_t *buf, int oob_required)
1936 {
1937 int eccsize = chip->ecc.size;
1938 int eccbytes = chip->ecc.bytes;
1939 uint8_t *oob = chip->oob_poi;
1940 int steps, size;
1941
1942 for (steps = chip->ecc.steps; steps > 0; steps--) {
1943 chip->write_buf(mtd, buf, eccsize);
1944 buf += eccsize;
1945
1946 if (chip->ecc.prepad) {
1947 chip->write_buf(mtd, oob, chip->ecc.prepad);
1948 oob += chip->ecc.prepad;
1949 }
1950
1951 chip->read_buf(mtd, oob, eccbytes);
1952 oob += eccbytes;
1953
1954 if (chip->ecc.postpad) {
1955 chip->write_buf(mtd, oob, chip->ecc.postpad);
1956 oob += chip->ecc.postpad;
1957 }
1958 }
1959
1960 size = mtd->oobsize - (oob - chip->oob_poi);
1961 if (size)
1962 chip->write_buf(mtd, oob, size);
1963
1964 return 0;
1965 }
1966 /**
1967 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1968 * @mtd: mtd info structure
1969 * @chip: nand chip info structure
1970 * @buf: data buffer
1971 * @oob_required: must write chip->oob_poi to OOB
1972 */
1973 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1974 const uint8_t *buf, int oob_required)
1975 {
1976 int i, eccsize = chip->ecc.size;
1977 int eccbytes = chip->ecc.bytes;
1978 int eccsteps = chip->ecc.steps;
1979 uint8_t *ecc_calc = chip->buffers->ecccalc;
1980 const uint8_t *p = buf;
1981 uint32_t *eccpos = chip->ecc.layout->eccpos;
1982
1983 /* Software ECC calculation */
1984 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1985 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1986
1987 for (i = 0; i < chip->ecc.total; i++)
1988 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1989
1990 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1991 }
1992
1993 /**
1994 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1995 * @mtd: mtd info structure
1996 * @chip: nand chip info structure
1997 * @buf: data buffer
1998 * @oob_required: must write chip->oob_poi to OOB
1999 */
2000 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2001 const uint8_t *buf, int oob_required)
2002 {
2003 int i, eccsize = chip->ecc.size;
2004 int eccbytes = chip->ecc.bytes;
2005 int eccsteps = chip->ecc.steps;
2006 uint8_t *ecc_calc = chip->buffers->ecccalc;
2007 const uint8_t *p = buf;
2008 uint32_t *eccpos = chip->ecc.layout->eccpos;
2009
2010 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2011 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2012 chip->write_buf(mtd, p, eccsize);
2013 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2014 }
2015
2016 for (i = 0; i < chip->ecc.total; i++)
2017 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2018
2019 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2020
2021 return 0;
2022 }
2023
2024 /**
2025 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2026 * @mtd: mtd info structure
2027 * @chip: nand chip info structure
2028 * @buf: data buffer
2029 * @oob_required: must write chip->oob_poi to OOB
2030 *
2031 * The hw generator calculates the error syndrome automatically. Therefore we
2032 * need a special oob layout and handling.
2033 */
2034 static int nand_write_page_syndrome(struct mtd_info *mtd,
2035 struct nand_chip *chip,
2036 const uint8_t *buf, int oob_required)
2037 {
2038 int i, eccsize = chip->ecc.size;
2039 int eccbytes = chip->ecc.bytes;
2040 int eccsteps = chip->ecc.steps;
2041 const uint8_t *p = buf;
2042 uint8_t *oob = chip->oob_poi;
2043
2044 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2045
2046 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2047 chip->write_buf(mtd, p, eccsize);
2048
2049 if (chip->ecc.prepad) {
2050 chip->write_buf(mtd, oob, chip->ecc.prepad);
2051 oob += chip->ecc.prepad;
2052 }
2053
2054 chip->ecc.calculate(mtd, p, oob);
2055 chip->write_buf(mtd, oob, eccbytes);
2056 oob += eccbytes;
2057
2058 if (chip->ecc.postpad) {
2059 chip->write_buf(mtd, oob, chip->ecc.postpad);
2060 oob += chip->ecc.postpad;
2061 }
2062 }
2063
2064 /* Calculate remaining oob bytes */
2065 i = mtd->oobsize - (oob - chip->oob_poi);
2066 if (i)
2067 chip->write_buf(mtd, oob, i);
2068
2069 return 0;
2070 }
2071
2072 /**
2073 * nand_write_page - [REPLACEABLE] write one page
2074 * @mtd: MTD device structure
2075 * @chip: NAND chip descriptor
2076 * @buf: the data to write
2077 * @oob_required: must write chip->oob_poi to OOB
2078 * @page: page number to write
2079 * @cached: cached programming
2080 * @raw: use _raw version of write_page
2081 */
2082 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2083 const uint8_t *buf, int oob_required, int page,
2084 int cached, int raw)
2085 {
2086 int status;
2087
2088 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2089
2090 if (unlikely(raw))
2091 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
2092 else
2093 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2094
2095 if (status < 0)
2096 return status;
2097
2098 /*
2099 * Cached progamming disabled for now. Not sure if it's worth the
2100 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2101 */
2102 cached = 0;
2103
2104 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2105
2106 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2107 status = chip->waitfunc(mtd, chip);
2108 /*
2109 * See if operation failed and additional status checks are
2110 * available.
2111 */
2112 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2113 status = chip->errstat(mtd, chip, FL_WRITING, status,
2114 page);
2115
2116 if (status & NAND_STATUS_FAIL)
2117 return -EIO;
2118 } else {
2119 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2120 status = chip->waitfunc(mtd, chip);
2121 }
2122
2123 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2124 /* Send command to read back the data */
2125 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2126
2127 if (chip->verify_buf(mtd, buf, mtd->writesize))
2128 return -EIO;
2129
2130 /* Make sure the next page prog is preceded by a status read */
2131 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2132 #endif
2133 return 0;
2134 }
2135
2136 /**
2137 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2138 * @mtd: MTD device structure
2139 * @oob: oob data buffer
2140 * @len: oob data write length
2141 * @ops: oob ops structure
2142 */
2143 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2144 struct mtd_oob_ops *ops)
2145 {
2146 struct nand_chip *chip = mtd->priv;
2147
2148 /*
2149 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2150 * data from a previous OOB read.
2151 */
2152 memset(chip->oob_poi, 0xff, mtd->oobsize);
2153
2154 switch (ops->mode) {
2155
2156 case MTD_OPS_PLACE_OOB:
2157 case MTD_OPS_RAW:
2158 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2159 return oob + len;
2160
2161 case MTD_OPS_AUTO_OOB: {
2162 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2163 uint32_t boffs = 0, woffs = ops->ooboffs;
2164 size_t bytes = 0;
2165
2166 for (; free->length && len; free++, len -= bytes) {
2167 /* Write request not from offset 0? */
2168 if (unlikely(woffs)) {
2169 if (woffs >= free->length) {
2170 woffs -= free->length;
2171 continue;
2172 }
2173 boffs = free->offset + woffs;
2174 bytes = min_t(size_t, len,
2175 (free->length - woffs));
2176 woffs = 0;
2177 } else {
2178 bytes = min_t(size_t, len, free->length);
2179 boffs = free->offset;
2180 }
2181 memcpy(chip->oob_poi + boffs, oob, bytes);
2182 oob += bytes;
2183 }
2184 return oob;
2185 }
2186 default:
2187 BUG();
2188 }
2189 return NULL;
2190 }
2191
2192 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2193
2194 /**
2195 * nand_do_write_ops - [INTERN] NAND write with ECC
2196 * @mtd: MTD device structure
2197 * @to: offset to write to
2198 * @ops: oob operations description structure
2199 *
2200 * NAND write with ECC.
2201 */
2202 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2203 struct mtd_oob_ops *ops)
2204 {
2205 int chipnr, realpage, page, blockmask, column;
2206 struct nand_chip *chip = mtd->priv;
2207 uint32_t writelen = ops->len;
2208
2209 uint32_t oobwritelen = ops->ooblen;
2210 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2211 mtd->oobavail : mtd->oobsize;
2212
2213 uint8_t *oob = ops->oobbuf;
2214 uint8_t *buf = ops->datbuf;
2215 int ret, subpage;
2216 int oob_required = oob ? 1 : 0;
2217
2218 ops->retlen = 0;
2219 if (!writelen)
2220 return 0;
2221
2222 /* Reject writes, which are not page aligned */
2223 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2224 pr_notice("%s: attempt to write non page aligned data\n",
2225 __func__);
2226 return -EINVAL;
2227 }
2228
2229 column = to & (mtd->writesize - 1);
2230 subpage = column || (writelen & (mtd->writesize - 1));
2231
2232 if (subpage && oob)
2233 return -EINVAL;
2234
2235 chipnr = (int)(to >> chip->chip_shift);
2236 chip->select_chip(mtd, chipnr);
2237
2238 /* Check, if it is write protected */
2239 if (nand_check_wp(mtd))
2240 return -EIO;
2241
2242 realpage = (int)(to >> chip->page_shift);
2243 page = realpage & chip->pagemask;
2244 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2245
2246 /* Invalidate the page cache, when we write to the cached page */
2247 if (to <= (chip->pagebuf << chip->page_shift) &&
2248 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2249 chip->pagebuf = -1;
2250
2251 /* Don't allow multipage oob writes with offset */
2252 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2253 return -EINVAL;
2254
2255 while (1) {
2256 int bytes = mtd->writesize;
2257 int cached = writelen > bytes && page != blockmask;
2258 uint8_t *wbuf = buf;
2259
2260 /* Partial page write? */
2261 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2262 cached = 0;
2263 bytes = min_t(int, bytes - column, (int) writelen);
2264 chip->pagebuf = -1;
2265 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2266 memcpy(&chip->buffers->databuf[column], buf, bytes);
2267 wbuf = chip->buffers->databuf;
2268 }
2269
2270 if (unlikely(oob)) {
2271 size_t len = min(oobwritelen, oobmaxlen);
2272 oob = nand_fill_oob(mtd, oob, len, ops);
2273 oobwritelen -= len;
2274 } else {
2275 /* We still need to erase leftover OOB data */
2276 memset(chip->oob_poi, 0xff, mtd->oobsize);
2277 }
2278
2279 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2280 cached, (ops->mode == MTD_OPS_RAW));
2281 if (ret)
2282 break;
2283
2284 writelen -= bytes;
2285 if (!writelen)
2286 break;
2287
2288 column = 0;
2289 buf += bytes;
2290 realpage++;
2291
2292 page = realpage & chip->pagemask;
2293 /* Check, if we cross a chip boundary */
2294 if (!page) {
2295 chipnr++;
2296 chip->select_chip(mtd, -1);
2297 chip->select_chip(mtd, chipnr);
2298 }
2299 }
2300
2301 ops->retlen = ops->len - writelen;
2302 if (unlikely(oob))
2303 ops->oobretlen = ops->ooblen;
2304 return ret;
2305 }
2306
2307 /**
2308 * panic_nand_write - [MTD Interface] NAND write with ECC
2309 * @mtd: MTD device structure
2310 * @to: offset to write to
2311 * @len: number of bytes to write
2312 * @retlen: pointer to variable to store the number of written bytes
2313 * @buf: the data to write
2314 *
2315 * NAND write with ECC. Used when performing writes in interrupt context, this
2316 * may for example be called by mtdoops when writing an oops while in panic.
2317 */
2318 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2319 size_t *retlen, const uint8_t *buf)
2320 {
2321 struct nand_chip *chip = mtd->priv;
2322 struct mtd_oob_ops ops;
2323 int ret;
2324
2325 /* Wait for the device to get ready */
2326 panic_nand_wait(mtd, chip, 400);
2327
2328 /* Grab the device */
2329 panic_nand_get_device(chip, mtd, FL_WRITING);
2330
2331 ops.len = len;
2332 ops.datbuf = (uint8_t *)buf;
2333 ops.oobbuf = NULL;
2334 ops.mode = 0;
2335
2336 ret = nand_do_write_ops(mtd, to, &ops);
2337
2338 *retlen = ops.retlen;
2339 return ret;
2340 }
2341
2342 /**
2343 * nand_write - [MTD Interface] NAND write with ECC
2344 * @mtd: MTD device structure
2345 * @to: offset to write to
2346 * @len: number of bytes to write
2347 * @retlen: pointer to variable to store the number of written bytes
2348 * @buf: the data to write
2349 *
2350 * NAND write with ECC.
2351 */
2352 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2353 size_t *retlen, const uint8_t *buf)
2354 {
2355 struct nand_chip *chip = mtd->priv;
2356 struct mtd_oob_ops ops;
2357 int ret;
2358
2359 nand_get_device(chip, mtd, FL_WRITING);
2360 ops.len = len;
2361 ops.datbuf = (uint8_t *)buf;
2362 ops.oobbuf = NULL;
2363 ops.mode = 0;
2364 ret = nand_do_write_ops(mtd, to, &ops);
2365 *retlen = ops.retlen;
2366 nand_release_device(mtd);
2367 return ret;
2368 }
2369
2370 /**
2371 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2372 * @mtd: MTD device structure
2373 * @to: offset to write to
2374 * @ops: oob operation description structure
2375 *
2376 * NAND write out-of-band.
2377 */
2378 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2379 struct mtd_oob_ops *ops)
2380 {
2381 int chipnr, page, status, len;
2382 struct nand_chip *chip = mtd->priv;
2383
2384 pr_debug("%s: to = 0x%08x, len = %i\n",
2385 __func__, (unsigned int)to, (int)ops->ooblen);
2386
2387 if (ops->mode == MTD_OPS_AUTO_OOB)
2388 len = chip->ecc.layout->oobavail;
2389 else
2390 len = mtd->oobsize;
2391
2392 /* Do not allow write past end of page */
2393 if ((ops->ooboffs + ops->ooblen) > len) {
2394 pr_debug("%s: attempt to write past end of page\n",
2395 __func__);
2396 return -EINVAL;
2397 }
2398
2399 if (unlikely(ops->ooboffs >= len)) {
2400 pr_debug("%s: attempt to start write outside oob\n",
2401 __func__);
2402 return -EINVAL;
2403 }
2404
2405 /* Do not allow write past end of device */
2406 if (unlikely(to >= mtd->size ||
2407 ops->ooboffs + ops->ooblen >
2408 ((mtd->size >> chip->page_shift) -
2409 (to >> chip->page_shift)) * len)) {
2410 pr_debug("%s: attempt to write beyond end of device\n",
2411 __func__);
2412 return -EINVAL;
2413 }
2414
2415 chipnr = (int)(to >> chip->chip_shift);
2416 chip->select_chip(mtd, chipnr);
2417
2418 /* Shift to get page */
2419 page = (int)(to >> chip->page_shift);
2420
2421 /*
2422 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2423 * of my DiskOnChip 2000 test units) will clear the whole data page too
2424 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2425 * it in the doc2000 driver in August 1999. dwmw2.
2426 */
2427 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2428
2429 /* Check, if it is write protected */
2430 if (nand_check_wp(mtd))
2431 return -EROFS;
2432
2433 /* Invalidate the page cache, if we write to the cached page */
2434 if (page == chip->pagebuf)
2435 chip->pagebuf = -1;
2436
2437 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2438
2439 if (ops->mode == MTD_OPS_RAW)
2440 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2441 else
2442 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2443
2444 if (status)
2445 return status;
2446
2447 ops->oobretlen = ops->ooblen;
2448
2449 return 0;
2450 }
2451
2452 /**
2453 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2454 * @mtd: MTD device structure
2455 * @to: offset to write to
2456 * @ops: oob operation description structure
2457 */
2458 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2459 struct mtd_oob_ops *ops)
2460 {
2461 struct nand_chip *chip = mtd->priv;
2462 int ret = -ENOTSUPP;
2463
2464 ops->retlen = 0;
2465
2466 /* Do not allow writes past end of device */
2467 if (ops->datbuf && (to + ops->len) > mtd->size) {
2468 pr_debug("%s: attempt to write beyond end of device\n",
2469 __func__);
2470 return -EINVAL;
2471 }
2472
2473 nand_get_device(chip, mtd, FL_WRITING);
2474
2475 switch (ops->mode) {
2476 case MTD_OPS_PLACE_OOB:
2477 case MTD_OPS_AUTO_OOB:
2478 case MTD_OPS_RAW:
2479 break;
2480
2481 default:
2482 goto out;
2483 }
2484
2485 if (!ops->datbuf)
2486 ret = nand_do_write_oob(mtd, to, ops);
2487 else
2488 ret = nand_do_write_ops(mtd, to, ops);
2489
2490 out:
2491 nand_release_device(mtd);
2492 return ret;
2493 }
2494
2495 /**
2496 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2497 * @mtd: MTD device structure
2498 * @page: the page address of the block which will be erased
2499 *
2500 * Standard erase command for NAND chips.
2501 */
2502 static void single_erase_cmd(struct mtd_info *mtd, int page)
2503 {
2504 struct nand_chip *chip = mtd->priv;
2505 /* Send commands to erase a block */
2506 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2507 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2508 }
2509
2510 /**
2511 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2512 * @mtd: MTD device structure
2513 * @page: the page address of the block which will be erased
2514 *
2515 * AND multi block erase command function. Erase 4 consecutive blocks.
2516 */
2517 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2518 {
2519 struct nand_chip *chip = mtd->priv;
2520 /* Send commands to erase a block */
2521 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2522 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2523 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2524 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2525 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2526 }
2527
2528 /**
2529 * nand_erase - [MTD Interface] erase block(s)
2530 * @mtd: MTD device structure
2531 * @instr: erase instruction
2532 *
2533 * Erase one ore more blocks.
2534 */
2535 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2536 {
2537 return nand_erase_nand(mtd, instr, 0);
2538 }
2539
2540 #define BBT_PAGE_MASK 0xffffff3f
2541 /**
2542 * nand_erase_nand - [INTERN] erase block(s)
2543 * @mtd: MTD device structure
2544 * @instr: erase instruction
2545 * @allowbbt: allow erasing the bbt area
2546 *
2547 * Erase one ore more blocks.
2548 */
2549 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2550 int allowbbt)
2551 {
2552 int page, status, pages_per_block, ret, chipnr;
2553 struct nand_chip *chip = mtd->priv;
2554 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2555 unsigned int bbt_masked_page = 0xffffffff;
2556 loff_t len;
2557
2558 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2559 __func__, (unsigned long long)instr->addr,
2560 (unsigned long long)instr->len);
2561
2562 if (check_offs_len(mtd, instr->addr, instr->len))
2563 return -EINVAL;
2564
2565 /* Grab the lock and see if the device is available */
2566 nand_get_device(chip, mtd, FL_ERASING);
2567
2568 /* Shift to get first page */
2569 page = (int)(instr->addr >> chip->page_shift);
2570 chipnr = (int)(instr->addr >> chip->chip_shift);
2571
2572 /* Calculate pages in each block */
2573 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2574
2575 /* Select the NAND device */
2576 chip->select_chip(mtd, chipnr);
2577
2578 /* Check, if it is write protected */
2579 if (nand_check_wp(mtd)) {
2580 pr_debug("%s: device is write protected!\n",
2581 __func__);
2582 instr->state = MTD_ERASE_FAILED;
2583 goto erase_exit;
2584 }
2585
2586 /*
2587 * If BBT requires refresh, set the BBT page mask to see if the BBT
2588 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2589 * can not be matched. This is also done when the bbt is actually
2590 * erased to avoid recursive updates.
2591 */
2592 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2593 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2594
2595 /* Loop through the pages */
2596 len = instr->len;
2597
2598 instr->state = MTD_ERASING;
2599
2600 while (len) {
2601 /* Check if we have a bad block, we do not erase bad blocks! */
2602 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2603 chip->page_shift, 0, allowbbt)) {
2604 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2605 __func__, page);
2606 instr->state = MTD_ERASE_FAILED;
2607 goto erase_exit;
2608 }
2609
2610 /*
2611 * Invalidate the page cache, if we erase the block which
2612 * contains the current cached page.
2613 */
2614 if (page <= chip->pagebuf && chip->pagebuf <
2615 (page + pages_per_block))
2616 chip->pagebuf = -1;
2617
2618 chip->erase_cmd(mtd, page & chip->pagemask);
2619
2620 status = chip->waitfunc(mtd, chip);
2621
2622 /*
2623 * See if operation failed and additional status checks are
2624 * available
2625 */
2626 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2627 status = chip->errstat(mtd, chip, FL_ERASING,
2628 status, page);
2629
2630 /* See if block erase succeeded */
2631 if (status & NAND_STATUS_FAIL) {
2632 pr_debug("%s: failed erase, page 0x%08x\n",
2633 __func__, page);
2634 instr->state = MTD_ERASE_FAILED;
2635 instr->fail_addr =
2636 ((loff_t)page << chip->page_shift);
2637 goto erase_exit;
2638 }
2639
2640 /*
2641 * If BBT requires refresh, set the BBT rewrite flag to the
2642 * page being erased.
2643 */
2644 if (bbt_masked_page != 0xffffffff &&
2645 (page & BBT_PAGE_MASK) == bbt_masked_page)
2646 rewrite_bbt[chipnr] =
2647 ((loff_t)page << chip->page_shift);
2648
2649 /* Increment page address and decrement length */
2650 len -= (1 << chip->phys_erase_shift);
2651 page += pages_per_block;
2652
2653 /* Check, if we cross a chip boundary */
2654 if (len && !(page & chip->pagemask)) {
2655 chipnr++;
2656 chip->select_chip(mtd, -1);
2657 chip->select_chip(mtd, chipnr);
2658
2659 /*
2660 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2661 * page mask to see if this BBT should be rewritten.
2662 */
2663 if (bbt_masked_page != 0xffffffff &&
2664 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2665 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2666 BBT_PAGE_MASK;
2667 }
2668 }
2669 instr->state = MTD_ERASE_DONE;
2670
2671 erase_exit:
2672
2673 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2674
2675 /* Deselect and wake up anyone waiting on the device */
2676 nand_release_device(mtd);
2677
2678 /* Do call back function */
2679 if (!ret)
2680 mtd_erase_callback(instr);
2681
2682 /*
2683 * If BBT requires refresh and erase was successful, rewrite any
2684 * selected bad block tables.
2685 */
2686 if (bbt_masked_page == 0xffffffff || ret)
2687 return ret;
2688
2689 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2690 if (!rewrite_bbt[chipnr])
2691 continue;
2692 /* Update the BBT for chip */
2693 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2694 __func__, chipnr, rewrite_bbt[chipnr],
2695 chip->bbt_td->pages[chipnr]);
2696 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2697 }
2698
2699 /* Return more or less happy */
2700 return ret;
2701 }
2702
2703 /**
2704 * nand_sync - [MTD Interface] sync
2705 * @mtd: MTD device structure
2706 *
2707 * Sync is actually a wait for chip ready function.
2708 */
2709 static void nand_sync(struct mtd_info *mtd)
2710 {
2711 struct nand_chip *chip = mtd->priv;
2712
2713 pr_debug("%s: called\n", __func__);
2714
2715 /* Grab the lock and see if the device is available */
2716 nand_get_device(chip, mtd, FL_SYNCING);
2717 /* Release it and go back */
2718 nand_release_device(mtd);
2719 }
2720
2721 /**
2722 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2723 * @mtd: MTD device structure
2724 * @offs: offset relative to mtd start
2725 */
2726 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2727 {
2728 return nand_block_checkbad(mtd, offs, 1, 0);
2729 }
2730
2731 /**
2732 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2733 * @mtd: MTD device structure
2734 * @ofs: offset relative to mtd start
2735 */
2736 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2737 {
2738 struct nand_chip *chip = mtd->priv;
2739 int ret;
2740
2741 ret = nand_block_isbad(mtd, ofs);
2742 if (ret) {
2743 /* If it was bad already, return success and do nothing */
2744 if (ret > 0)
2745 return 0;
2746 return ret;
2747 }
2748
2749 return chip->block_markbad(mtd, ofs);
2750 }
2751
2752 /**
2753 * nand_suspend - [MTD Interface] Suspend the NAND flash
2754 * @mtd: MTD device structure
2755 */
2756 static int nand_suspend(struct mtd_info *mtd)
2757 {
2758 struct nand_chip *chip = mtd->priv;
2759
2760 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2761 }
2762
2763 /**
2764 * nand_resume - [MTD Interface] Resume the NAND flash
2765 * @mtd: MTD device structure
2766 */
2767 static void nand_resume(struct mtd_info *mtd)
2768 {
2769 struct nand_chip *chip = mtd->priv;
2770
2771 if (chip->state == FL_PM_SUSPENDED)
2772 nand_release_device(mtd);
2773 else
2774 pr_err("%s called for a chip which is not in suspended state\n",
2775 __func__);
2776 }
2777
2778 /* Set default functions */
2779 static void nand_set_defaults(struct nand_chip *chip, int busw)
2780 {
2781 /* check for proper chip_delay setup, set 20us if not */
2782 if (!chip->chip_delay)
2783 chip->chip_delay = 20;
2784
2785 /* check, if a user supplied command function given */
2786 if (chip->cmdfunc == NULL)
2787 chip->cmdfunc = nand_command;
2788
2789 /* check, if a user supplied wait function given */
2790 if (chip->waitfunc == NULL)
2791 chip->waitfunc = nand_wait;
2792
2793 if (!chip->select_chip)
2794 chip->select_chip = nand_select_chip;
2795 if (!chip->read_byte)
2796 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2797 if (!chip->read_word)
2798 chip->read_word = nand_read_word;
2799 if (!chip->block_bad)
2800 chip->block_bad = nand_block_bad;
2801 if (!chip->block_markbad)
2802 chip->block_markbad = nand_default_block_markbad;
2803 if (!chip->write_buf)
2804 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2805 if (!chip->read_buf)
2806 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2807 if (!chip->verify_buf)
2808 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2809 if (!chip->scan_bbt)
2810 chip->scan_bbt = nand_default_bbt;
2811
2812 if (!chip->controller) {
2813 chip->controller = &chip->hwcontrol;
2814 spin_lock_init(&chip->controller->lock);
2815 init_waitqueue_head(&chip->controller->wq);
2816 }
2817
2818 }
2819
2820 /* Sanitize ONFI strings so we can safely print them */
2821 static void sanitize_string(uint8_t *s, size_t len)
2822 {
2823 ssize_t i;
2824
2825 /* Null terminate */
2826 s[len - 1] = 0;
2827
2828 /* Remove non printable chars */
2829 for (i = 0; i < len - 1; i++) {
2830 if (s[i] < ' ' || s[i] > 127)
2831 s[i] = '?';
2832 }
2833
2834 /* Remove trailing spaces */
2835 strim(s);
2836 }
2837
2838 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2839 {
2840 int i;
2841 while (len--) {
2842 crc ^= *p++ << 8;
2843 for (i = 0; i < 8; i++)
2844 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2845 }
2846
2847 return crc;
2848 }
2849
2850 /*
2851 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2852 */
2853 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2854 int *busw)
2855 {
2856 struct nand_onfi_params *p = &chip->onfi_params;
2857 int i;
2858 int val;
2859
2860 /* Try ONFI for unknown chip or LP */
2861 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2862 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2863 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2864 return 0;
2865
2866 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2867 for (i = 0; i < 3; i++) {
2868 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2869 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2870 le16_to_cpu(p->crc)) {
2871 pr_info("ONFI param page %d valid\n", i);
2872 break;
2873 }
2874 }
2875
2876 if (i == 3)
2877 return 0;
2878
2879 /* Check version */
2880 val = le16_to_cpu(p->revision);
2881 if (val & (1 << 5))
2882 chip->onfi_version = 23;
2883 else if (val & (1 << 4))
2884 chip->onfi_version = 22;
2885 else if (val & (1 << 3))
2886 chip->onfi_version = 21;
2887 else if (val & (1 << 2))
2888 chip->onfi_version = 20;
2889 else if (val & (1 << 1))
2890 chip->onfi_version = 10;
2891 else
2892 chip->onfi_version = 0;
2893
2894 if (!chip->onfi_version) {
2895 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2896 return 0;
2897 }
2898
2899 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2900 sanitize_string(p->model, sizeof(p->model));
2901 if (!mtd->name)
2902 mtd->name = p->model;
2903 mtd->writesize = le32_to_cpu(p->byte_per_page);
2904 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2905 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2906 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2907 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2908 *busw = 0;
2909 if (le16_to_cpu(p->features) & 1)
2910 *busw = NAND_BUSWIDTH_16;
2911
2912 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2913
2914 pr_info("ONFI flash detected\n");
2915 return 1;
2916 }
2917
2918 /*
2919 * Get the flash and manufacturer id and lookup if the type is supported.
2920 */
2921 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2922 struct nand_chip *chip,
2923 int busw,
2924 int *maf_id, int *dev_id,
2925 struct nand_flash_dev *type)
2926 {
2927 int i, maf_idx;
2928 u8 id_data[8];
2929 int ret;
2930
2931 /* Select the device */
2932 chip->select_chip(mtd, 0);
2933
2934 /*
2935 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2936 * after power-up.
2937 */
2938 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2939
2940 /* Send the command for reading device ID */
2941 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2942
2943 /* Read manufacturer and device IDs */
2944 *maf_id = chip->read_byte(mtd);
2945 *dev_id = chip->read_byte(mtd);
2946
2947 /*
2948 * Try again to make sure, as some systems the bus-hold or other
2949 * interface concerns can cause random data which looks like a
2950 * possibly credible NAND flash to appear. If the two results do
2951 * not match, ignore the device completely.
2952 */
2953
2954 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2955
2956 for (i = 0; i < 2; i++)
2957 id_data[i] = chip->read_byte(mtd);
2958
2959 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2960 pr_info("%s: second ID read did not match "
2961 "%02x,%02x against %02x,%02x\n", __func__,
2962 *maf_id, *dev_id, id_data[0], id_data[1]);
2963 return ERR_PTR(-ENODEV);
2964 }
2965
2966 if (!type)
2967 type = nand_flash_ids;
2968
2969 for (; type->name != NULL; type++)
2970 if (*dev_id == type->id)
2971 break;
2972
2973 chip->onfi_version = 0;
2974 if (!type->name || !type->pagesize) {
2975 /* Check is chip is ONFI compliant */
2976 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2977 if (ret)
2978 goto ident_done;
2979 }
2980
2981 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2982
2983 /* Read entire ID string */
2984
2985 for (i = 0; i < 8; i++)
2986 id_data[i] = chip->read_byte(mtd);
2987
2988 if (!type->name)
2989 return ERR_PTR(-ENODEV);
2990
2991 if (!mtd->name)
2992 mtd->name = type->name;
2993
2994 chip->chipsize = (uint64_t)type->chipsize << 20;
2995
2996 if (!type->pagesize && chip->init_size) {
2997 /* Set the pagesize, oobsize, erasesize by the driver */
2998 busw = chip->init_size(mtd, chip, id_data);
2999 } else if (!type->pagesize) {
3000 int extid;
3001 /* The 3rd id byte holds MLC / multichip data */
3002 chip->cellinfo = id_data[2];
3003 /* The 4th id byte is the important one */
3004 extid = id_data[3];
3005
3006 /*
3007 * Field definitions are in the following datasheets:
3008 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3009 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
3010 *
3011 * Check for wraparound + Samsung ID + nonzero 6th byte
3012 * to decide what to do.
3013 */
3014 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3015 id_data[0] == NAND_MFR_SAMSUNG &&
3016 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3017 id_data[5] != 0x00) {
3018 /* Calc pagesize */
3019 mtd->writesize = 2048 << (extid & 0x03);
3020 extid >>= 2;
3021 /* Calc oobsize */
3022 switch (extid & 0x03) {
3023 case 1:
3024 mtd->oobsize = 128;
3025 break;
3026 case 2:
3027 mtd->oobsize = 218;
3028 break;
3029 case 3:
3030 mtd->oobsize = 400;
3031 break;
3032 default:
3033 mtd->oobsize = 436;
3034 break;
3035 }
3036 extid >>= 2;
3037 /* Calc blocksize */
3038 mtd->erasesize = (128 * 1024) <<
3039 (((extid >> 1) & 0x04) | (extid & 0x03));
3040 busw = 0;
3041 } else {
3042 /* Calc pagesize */
3043 mtd->writesize = 1024 << (extid & 0x03);
3044 extid >>= 2;
3045 /* Calc oobsize */
3046 mtd->oobsize = (8 << (extid & 0x01)) *
3047 (mtd->writesize >> 9);
3048 extid >>= 2;
3049 /* Calc blocksize. Blocksize is multiples of 64KiB */
3050 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3051 extid >>= 2;
3052 /* Get buswidth information */
3053 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3054 }
3055 } else {
3056 /*
3057 * Old devices have chip data hardcoded in the device id table.
3058 */
3059 mtd->erasesize = type->erasesize;
3060 mtd->writesize = type->pagesize;
3061 mtd->oobsize = mtd->writesize / 32;
3062 busw = type->options & NAND_BUSWIDTH_16;
3063
3064 /*
3065 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3066 * some Spansion chips have erasesize that conflicts with size
3067 * listed in nand_ids table.
3068 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3069 */
3070 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3071 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3072 id_data[7] == 0x00 && mtd->writesize == 512) {
3073 mtd->erasesize = 128 * 1024;
3074 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3075 }
3076 }
3077 /* Get chip options, preserve non chip based options */
3078 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3079 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3080
3081 /*
3082 * Check if chip is not a Samsung device. Do not clear the
3083 * options for chips which do not have an extended id.
3084 */
3085 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3086 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3087 ident_done:
3088
3089 /* Try to identify manufacturer */
3090 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3091 if (nand_manuf_ids[maf_idx].id == *maf_id)
3092 break;
3093 }
3094
3095 /*
3096 * Check, if buswidth is correct. Hardware drivers should set
3097 * chip correct!
3098 */
3099 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3100 pr_info("NAND device: Manufacturer ID:"
3101 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3102 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3103 pr_warn("NAND bus width %d instead %d bit\n",
3104 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3105 busw ? 16 : 8);
3106 return ERR_PTR(-EINVAL);
3107 }
3108
3109 /* Calculate the address shift from the page size */
3110 chip->page_shift = ffs(mtd->writesize) - 1;
3111 /* Convert chipsize to number of pages per chip -1 */
3112 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3113
3114 chip->bbt_erase_shift = chip->phys_erase_shift =
3115 ffs(mtd->erasesize) - 1;
3116 if (chip->chipsize & 0xffffffff)
3117 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3118 else {
3119 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3120 chip->chip_shift += 32 - 1;
3121 }
3122
3123 chip->badblockbits = 8;
3124
3125 /* Set the bad block position */
3126 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3127 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3128 else
3129 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3130
3131 /*
3132 * Bad block marker is stored in the last page of each block
3133 * on Samsung and Hynix MLC devices; stored in first two pages
3134 * of each block on Micron devices with 2KiB pages and on
3135 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3136 * All others scan only the first page.
3137 */
3138 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139 (*maf_id == NAND_MFR_SAMSUNG ||
3140 *maf_id == NAND_MFR_HYNIX))
3141 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3142 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3143 (*maf_id == NAND_MFR_SAMSUNG ||
3144 *maf_id == NAND_MFR_HYNIX ||
3145 *maf_id == NAND_MFR_TOSHIBA ||
3146 *maf_id == NAND_MFR_AMD ||
3147 *maf_id == NAND_MFR_MACRONIX)) ||
3148 (mtd->writesize == 2048 &&
3149 *maf_id == NAND_MFR_MICRON))
3150 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3151
3152 /* Check for AND chips with 4 page planes */
3153 if (chip->options & NAND_4PAGE_ARRAY)
3154 chip->erase_cmd = multi_erase_cmd;
3155 else
3156 chip->erase_cmd = single_erase_cmd;
3157
3158 /* Do not replace user supplied command function! */
3159 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3160 chip->cmdfunc = nand_command_lp;
3161
3162 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3163 " page size: %d, OOB size: %d\n",
3164 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3165 chip->onfi_version ? chip->onfi_params.model : type->name,
3166 mtd->writesize, mtd->oobsize);
3167
3168 return type;
3169 }
3170
3171 /**
3172 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3173 * @mtd: MTD device structure
3174 * @maxchips: number of chips to scan for
3175 * @table: alternative NAND ID table
3176 *
3177 * This is the first phase of the normal nand_scan() function. It reads the
3178 * flash ID and sets up MTD fields accordingly.
3179 *
3180 * The mtd->owner field must be set to the module of the caller.
3181 */
3182 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3183 struct nand_flash_dev *table)
3184 {
3185 int i, busw, nand_maf_id, nand_dev_id;
3186 struct nand_chip *chip = mtd->priv;
3187 struct nand_flash_dev *type;
3188
3189 /* Get buswidth to select the correct functions */
3190 busw = chip->options & NAND_BUSWIDTH_16;
3191 /* Set the default functions */
3192 nand_set_defaults(chip, busw);
3193
3194 /* Read the flash type */
3195 type = nand_get_flash_type(mtd, chip, busw,
3196 &nand_maf_id, &nand_dev_id, table);
3197
3198 if (IS_ERR(type)) {
3199 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3200 pr_warn("No NAND device found\n");
3201 chip->select_chip(mtd, -1);
3202 return PTR_ERR(type);
3203 }
3204
3205 /* Check for a chip array */
3206 for (i = 1; i < maxchips; i++) {
3207 chip->select_chip(mtd, i);
3208 /* See comment in nand_get_flash_type for reset */
3209 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3210 /* Send the command for reading device ID */
3211 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3212 /* Read manufacturer and device IDs */
3213 if (nand_maf_id != chip->read_byte(mtd) ||
3214 nand_dev_id != chip->read_byte(mtd))
3215 break;
3216 }
3217 if (i > 1)
3218 pr_info("%d NAND chips detected\n", i);
3219
3220 /* Store the number of chips and calc total size for mtd */
3221 chip->numchips = i;
3222 mtd->size = i * chip->chipsize;
3223
3224 return 0;
3225 }
3226 EXPORT_SYMBOL(nand_scan_ident);
3227
3228
3229 /**
3230 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3231 * @mtd: MTD device structure
3232 *
3233 * This is the second phase of the normal nand_scan() function. It fills out
3234 * all the uninitialized function pointers with the defaults and scans for a
3235 * bad block table if appropriate.
3236 */
3237 int nand_scan_tail(struct mtd_info *mtd)
3238 {
3239 int i;
3240 struct nand_chip *chip = mtd->priv;
3241
3242 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3243 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3244 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3245
3246 if (!(chip->options & NAND_OWN_BUFFERS))
3247 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3248 if (!chip->buffers)
3249 return -ENOMEM;
3250
3251 /* Set the internal oob buffer location, just after the page data */
3252 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3253
3254 /*
3255 * If no default placement scheme is given, select an appropriate one.
3256 */
3257 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3258 switch (mtd->oobsize) {
3259 case 8:
3260 chip->ecc.layout = &nand_oob_8;
3261 break;
3262 case 16:
3263 chip->ecc.layout = &nand_oob_16;
3264 break;
3265 case 64:
3266 chip->ecc.layout = &nand_oob_64;
3267 break;
3268 case 128:
3269 chip->ecc.layout = &nand_oob_128;
3270 break;
3271 default:
3272 pr_warn("No oob scheme defined for oobsize %d\n",
3273 mtd->oobsize);
3274 BUG();
3275 }
3276 }
3277
3278 if (!chip->write_page)
3279 chip->write_page = nand_write_page;
3280
3281 /*
3282 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3283 * selected and we have 256 byte pagesize fallback to software ECC
3284 */
3285
3286 switch (chip->ecc.mode) {
3287 case NAND_ECC_HW_OOB_FIRST:
3288 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3289 if (!chip->ecc.calculate || !chip->ecc.correct ||
3290 !chip->ecc.hwctl) {
3291 pr_warn("No ECC functions supplied; "
3292 "hardware ECC not possible\n");
3293 BUG();
3294 }
3295 if (!chip->ecc.read_page)
3296 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3297
3298 case NAND_ECC_HW:
3299 /* Use standard hwecc read page function? */
3300 if (!chip->ecc.read_page)
3301 chip->ecc.read_page = nand_read_page_hwecc;
3302 if (!chip->ecc.write_page)
3303 chip->ecc.write_page = nand_write_page_hwecc;
3304 if (!chip->ecc.read_page_raw)
3305 chip->ecc.read_page_raw = nand_read_page_raw;
3306 if (!chip->ecc.write_page_raw)
3307 chip->ecc.write_page_raw = nand_write_page_raw;
3308 if (!chip->ecc.read_oob)
3309 chip->ecc.read_oob = nand_read_oob_std;
3310 if (!chip->ecc.write_oob)
3311 chip->ecc.write_oob = nand_write_oob_std;
3312
3313 case NAND_ECC_HW_SYNDROME:
3314 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3315 !chip->ecc.hwctl) &&
3316 (!chip->ecc.read_page ||
3317 chip->ecc.read_page == nand_read_page_hwecc ||
3318 !chip->ecc.write_page ||
3319 chip->ecc.write_page == nand_write_page_hwecc)) {
3320 pr_warn("No ECC functions supplied; "
3321 "hardware ECC not possible\n");
3322 BUG();
3323 }
3324 /* Use standard syndrome read/write page function? */
3325 if (!chip->ecc.read_page)
3326 chip->ecc.read_page = nand_read_page_syndrome;
3327 if (!chip->ecc.write_page)
3328 chip->ecc.write_page = nand_write_page_syndrome;
3329 if (!chip->ecc.read_page_raw)
3330 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3331 if (!chip->ecc.write_page_raw)
3332 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3333 if (!chip->ecc.read_oob)
3334 chip->ecc.read_oob = nand_read_oob_syndrome;
3335 if (!chip->ecc.write_oob)
3336 chip->ecc.write_oob = nand_write_oob_syndrome;
3337
3338 if (mtd->writesize >= chip->ecc.size) {
3339 if (!chip->ecc.strength) {
3340 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3341 BUG();
3342 }
3343 break;
3344 }
3345 pr_warn("%d byte HW ECC not possible on "
3346 "%d byte page size, fallback to SW ECC\n",
3347 chip->ecc.size, mtd->writesize);
3348 chip->ecc.mode = NAND_ECC_SOFT;
3349
3350 case NAND_ECC_SOFT:
3351 chip->ecc.calculate = nand_calculate_ecc;
3352 chip->ecc.correct = nand_correct_data;
3353 chip->ecc.read_page = nand_read_page_swecc;
3354 chip->ecc.read_subpage = nand_read_subpage;
3355 chip->ecc.write_page = nand_write_page_swecc;
3356 chip->ecc.read_page_raw = nand_read_page_raw;
3357 chip->ecc.write_page_raw = nand_write_page_raw;
3358 chip->ecc.read_oob = nand_read_oob_std;
3359 chip->ecc.write_oob = nand_write_oob_std;
3360 if (!chip->ecc.size)
3361 chip->ecc.size = 256;
3362 chip->ecc.bytes = 3;
3363 chip->ecc.strength = 1;
3364 break;
3365
3366 case NAND_ECC_SOFT_BCH:
3367 if (!mtd_nand_has_bch()) {
3368 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3369 BUG();
3370 }
3371 chip->ecc.calculate = nand_bch_calculate_ecc;
3372 chip->ecc.correct = nand_bch_correct_data;
3373 chip->ecc.read_page = nand_read_page_swecc;
3374 chip->ecc.read_subpage = nand_read_subpage;
3375 chip->ecc.write_page = nand_write_page_swecc;
3376 chip->ecc.read_page_raw = nand_read_page_raw;
3377 chip->ecc.write_page_raw = nand_write_page_raw;
3378 chip->ecc.read_oob = nand_read_oob_std;
3379 chip->ecc.write_oob = nand_write_oob_std;
3380 /*
3381 * Board driver should supply ecc.size and ecc.bytes values to
3382 * select how many bits are correctable; see nand_bch_init()
3383 * for details. Otherwise, default to 4 bits for large page
3384 * devices.
3385 */
3386 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3387 chip->ecc.size = 512;
3388 chip->ecc.bytes = 7;
3389 }
3390 chip->ecc.priv = nand_bch_init(mtd,
3391 chip->ecc.size,
3392 chip->ecc.bytes,
3393 &chip->ecc.layout);
3394 if (!chip->ecc.priv) {
3395 pr_warn("BCH ECC initialization failed!\n");
3396 BUG();
3397 }
3398 chip->ecc.strength =
3399 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3400 break;
3401
3402 case NAND_ECC_NONE:
3403 pr_warn("NAND_ECC_NONE selected by board driver. "
3404 "This is not recommended!\n");
3405 chip->ecc.read_page = nand_read_page_raw;
3406 chip->ecc.write_page = nand_write_page_raw;
3407 chip->ecc.read_oob = nand_read_oob_std;
3408 chip->ecc.read_page_raw = nand_read_page_raw;
3409 chip->ecc.write_page_raw = nand_write_page_raw;
3410 chip->ecc.write_oob = nand_write_oob_std;
3411 chip->ecc.size = mtd->writesize;
3412 chip->ecc.bytes = 0;
3413 chip->ecc.strength = 0;
3414 break;
3415
3416 default:
3417 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3418 BUG();
3419 }
3420
3421 /* For many systems, the standard OOB write also works for raw */
3422 if (!chip->ecc.read_oob_raw)
3423 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3424 if (!chip->ecc.write_oob_raw)
3425 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3426
3427 /*
3428 * The number of bytes available for a client to place data into
3429 * the out of band area.
3430 */
3431 chip->ecc.layout->oobavail = 0;
3432 for (i = 0; chip->ecc.layout->oobfree[i].length
3433 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3434 chip->ecc.layout->oobavail +=
3435 chip->ecc.layout->oobfree[i].length;
3436 mtd->oobavail = chip->ecc.layout->oobavail;
3437
3438 /*
3439 * Set the number of read / write steps for one page depending on ECC
3440 * mode.
3441 */
3442 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3443 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3444 pr_warn("Invalid ECC parameters\n");
3445 BUG();
3446 }
3447 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3448
3449 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3450 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3451 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3452 switch (chip->ecc.steps) {
3453 case 2:
3454 mtd->subpage_sft = 1;
3455 break;
3456 case 4:
3457 case 8:
3458 case 16:
3459 mtd->subpage_sft = 2;
3460 break;
3461 }
3462 }
3463 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3464
3465 /* Initialize state */
3466 chip->state = FL_READY;
3467
3468 /* De-select the device */
3469 chip->select_chip(mtd, -1);
3470
3471 /* Invalidate the pagebuffer reference */
3472 chip->pagebuf = -1;
3473
3474 /* Fill in remaining MTD driver data */
3475 mtd->type = MTD_NANDFLASH;
3476 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3477 MTD_CAP_NANDFLASH;
3478 mtd->_erase = nand_erase;
3479 mtd->_point = NULL;
3480 mtd->_unpoint = NULL;
3481 mtd->_read = nand_read;
3482 mtd->_write = nand_write;
3483 mtd->_panic_write = panic_nand_write;
3484 mtd->_read_oob = nand_read_oob;
3485 mtd->_write_oob = nand_write_oob;
3486 mtd->_sync = nand_sync;
3487 mtd->_lock = NULL;
3488 mtd->_unlock = NULL;
3489 mtd->_suspend = nand_suspend;
3490 mtd->_resume = nand_resume;
3491 mtd->_block_isbad = nand_block_isbad;
3492 mtd->_block_markbad = nand_block_markbad;
3493 mtd->writebufsize = mtd->writesize;
3494
3495 /* propagate ecc info to mtd_info */
3496 mtd->ecclayout = chip->ecc.layout;
3497 mtd->ecc_strength = chip->ecc.strength;
3498 /*
3499 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3500 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3501 * properly set.
3502 */
3503 if (!mtd->bitflip_threshold)
3504 mtd->bitflip_threshold = mtd->ecc_strength;
3505
3506 /* Check, if we should skip the bad block table scan */
3507 if (chip->options & NAND_SKIP_BBTSCAN)
3508 return 0;
3509
3510 /* Build bad block table */
3511 return chip->scan_bbt(mtd);
3512 }
3513 EXPORT_SYMBOL(nand_scan_tail);
3514
3515 /*
3516 * is_module_text_address() isn't exported, and it's mostly a pointless
3517 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3518 * to call us from in-kernel code if the core NAND support is modular.
3519 */
3520 #ifdef MODULE
3521 #define caller_is_module() (1)
3522 #else
3523 #define caller_is_module() \
3524 is_module_text_address((unsigned long)__builtin_return_address(0))
3525 #endif
3526
3527 /**
3528 * nand_scan - [NAND Interface] Scan for the NAND device
3529 * @mtd: MTD device structure
3530 * @maxchips: number of chips to scan for
3531 *
3532 * This fills out all the uninitialized function pointers with the defaults.
3533 * The flash ID is read and the mtd/chip structures are filled with the
3534 * appropriate values. The mtd->owner field must be set to the module of the
3535 * caller.
3536 */
3537 int nand_scan(struct mtd_info *mtd, int maxchips)
3538 {
3539 int ret;
3540
3541 /* Many callers got this wrong, so check for it for a while... */
3542 if (!mtd->owner && caller_is_module()) {
3543 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3544 BUG();
3545 }
3546
3547 ret = nand_scan_ident(mtd, maxchips, NULL);
3548 if (!ret)
3549 ret = nand_scan_tail(mtd);
3550 return ret;
3551 }
3552 EXPORT_SYMBOL(nand_scan);
3553
3554 /**
3555 * nand_release - [NAND Interface] Free resources held by the NAND device
3556 * @mtd: MTD device structure
3557 */
3558 void nand_release(struct mtd_info *mtd)
3559 {
3560 struct nand_chip *chip = mtd->priv;
3561
3562 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3563 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3564
3565 mtd_device_unregister(mtd);
3566
3567 /* Free bad block table memory */
3568 kfree(chip->bbt);
3569 if (!(chip->options & NAND_OWN_BUFFERS))
3570 kfree(chip->buffers);
3571
3572 /* Free bad block descriptor memory */
3573 if (chip->badblock_pattern && chip->badblock_pattern->options
3574 & NAND_BBT_DYNAMICSTRUCT)
3575 kfree(chip->badblock_pattern);
3576 }
3577 EXPORT_SYMBOL_GPL(nand_release);
3578
3579 static int __init nand_base_init(void)
3580 {
3581 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3582 return 0;
3583 }
3584
3585 static void __exit nand_base_exit(void)
3586 {
3587 led_trigger_unregister_simple(nand_led_trigger);
3588 }
3589
3590 module_init(nand_base_init);
3591 module_exit(nand_base_exit);
3592
3593 MODULE_LICENSE("GPL");
3594 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3595 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3596 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
This page took 0.132998 seconds and 5 git commands to generate.