5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8
= {
63 static struct nand_ecclayout nand_oob_16
= {
65 .eccpos
= {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64
= {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128
= {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
,
99 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
100 struct mtd_oob_ops
*ops
);
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
106 DEFINE_LED_TRIGGER(nand_led_trigger
);
108 static int check_offs_len(struct mtd_info
*mtd
,
109 loff_t ofs
, uint64_t len
)
111 struct nand_chip
*chip
= mtd
->priv
;
114 /* Start address must align on block boundary */
115 if (ofs
& ((1 << chip
->phys_erase_shift
) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__
);
120 /* Length must align on block boundary */
121 if (len
& ((1 << chip
->phys_erase_shift
) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__
);
130 * nand_release_device - [GENERIC] release chip
131 * @mtd: MTD device structure
133 * Deselect, release chip lock and wake up anyone waiting on the device.
135 static void nand_release_device(struct mtd_info
*mtd
)
137 struct nand_chip
*chip
= mtd
->priv
;
139 /* De-select the NAND device */
140 chip
->select_chip(mtd
, -1);
142 /* Release the controller and the chip */
143 spin_lock(&chip
->controller
->lock
);
144 chip
->controller
->active
= NULL
;
145 chip
->state
= FL_READY
;
146 wake_up(&chip
->controller
->wq
);
147 spin_unlock(&chip
->controller
->lock
);
151 * nand_read_byte - [DEFAULT] read one byte from the chip
152 * @mtd: MTD device structure
154 * Default read function for 8bit buswidth
156 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
158 struct nand_chip
*chip
= mtd
->priv
;
159 return readb(chip
->IO_ADDR_R
);
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
165 * @mtd: MTD device structure
167 * Default read function for 16bit buswidth with endianness conversion.
170 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd
->priv
;
173 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
177 * nand_read_word - [DEFAULT] read one word from the chip
178 * @mtd: MTD device structure
180 * Default read function for 16bit buswidth without endianness conversion.
182 static u16
nand_read_word(struct mtd_info
*mtd
)
184 struct nand_chip
*chip
= mtd
->priv
;
185 return readw(chip
->IO_ADDR_R
);
189 * nand_select_chip - [DEFAULT] control CE line
190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
193 * Default select function for 1 chip devices.
195 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
197 struct nand_chip
*chip
= mtd
->priv
;
201 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
212 * nand_write_buf - [DEFAULT] write buffer to chip
213 * @mtd: MTD device structure
215 * @len: number of bytes to write
217 * Default write function for 8bit buswidth.
219 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
222 struct nand_chip
*chip
= mtd
->priv
;
224 for (i
= 0; i
< len
; i
++)
225 writeb(buf
[i
], chip
->IO_ADDR_W
);
229 * nand_read_buf - [DEFAULT] read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
234 * Default read function for 8bit buswidth.
236 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
239 struct nand_chip
*chip
= mtd
->priv
;
241 for (i
= 0; i
< len
; i
++)
242 buf
[i
] = readb(chip
->IO_ADDR_R
);
246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
251 * Default verify function for 8bit buswidth.
253 static int nand_verify_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
256 struct nand_chip
*chip
= mtd
->priv
;
258 for (i
= 0; i
< len
; i
++)
259 if (buf
[i
] != readb(chip
->IO_ADDR_R
))
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
266 * @mtd: MTD device structure
268 * @len: number of bytes to write
270 * Default write function for 16bit buswidth.
272 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
275 struct nand_chip
*chip
= mtd
->priv
;
276 u16
*p
= (u16
*) buf
;
279 for (i
= 0; i
< len
; i
++)
280 writew(p
[i
], chip
->IO_ADDR_W
);
285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
290 * Default read function for 16bit buswidth.
292 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
295 struct nand_chip
*chip
= mtd
->priv
;
296 u16
*p
= (u16
*) buf
;
299 for (i
= 0; i
< len
; i
++)
300 p
[i
] = readw(chip
->IO_ADDR_R
);
304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
309 * Default verify function for 16bit buswidth.
311 static int nand_verify_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
314 struct nand_chip
*chip
= mtd
->priv
;
315 u16
*p
= (u16
*) buf
;
318 for (i
= 0; i
< len
; i
++)
319 if (p
[i
] != readw(chip
->IO_ADDR_R
))
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
331 * Check, if the block is bad.
333 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
335 int page
, chipnr
, res
= 0, i
= 0;
336 struct nand_chip
*chip
= mtd
->priv
;
339 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
340 ofs
+= mtd
->erasesize
- mtd
->writesize
;
342 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
345 chipnr
= (int)(ofs
>> chip
->chip_shift
);
347 nand_get_device(chip
, mtd
, FL_READING
);
349 /* Select the NAND device */
350 chip
->select_chip(mtd
, chipnr
);
354 if (chip
->options
& NAND_BUSWIDTH_16
) {
355 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
356 chip
->badblockpos
& 0xFE, page
);
357 bad
= cpu_to_le16(chip
->read_word(mtd
));
358 if (chip
->badblockpos
& 0x1)
363 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
365 bad
= chip
->read_byte(mtd
);
368 if (likely(chip
->badblockbits
== 8))
371 res
= hweight8(bad
) < chip
->badblockbits
;
372 ofs
+= mtd
->writesize
;
373 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
375 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
378 nand_release_device(mtd
);
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
398 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
400 struct nand_chip
*chip
= mtd
->priv
;
401 uint8_t buf
[2] = { 0, 0 };
402 int block
, res
, ret
= 0, i
= 0;
403 int write_oob
= !(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
);
406 struct erase_info einfo
;
408 /* Attempt erase before marking OOB */
409 memset(&einfo
, 0, sizeof(einfo
));
412 einfo
.len
= 1 << chip
->phys_erase_shift
;
413 nand_erase_nand(mtd
, &einfo
, 0);
416 /* Get block number */
417 block
= (int)(ofs
>> chip
->bbt_erase_shift
);
418 /* Mark block bad in memory-based BBT */
420 chip
->bbt
[block
>> 2] |= 0x01 << ((block
& 0x03) << 1);
422 /* Write bad block marker to OOB */
424 struct mtd_oob_ops ops
;
427 nand_get_device(chip
, mtd
, FL_WRITING
);
431 ops
.ooboffs
= chip
->badblockpos
;
432 if (chip
->options
& NAND_BUSWIDTH_16
) {
433 ops
.ooboffs
&= ~0x01;
434 ops
.len
= ops
.ooblen
= 2;
436 ops
.len
= ops
.ooblen
= 1;
438 ops
.mode
= MTD_OPS_PLACE_OOB
;
440 /* Write to first/last page(s) if necessary */
441 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
442 wr_ofs
+= mtd
->erasesize
- mtd
->writesize
;
444 res
= nand_do_write_oob(mtd
, wr_ofs
, &ops
);
449 wr_ofs
+= mtd
->writesize
;
450 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
452 nand_release_device(mtd
);
455 /* Update flash-based bad block table */
456 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
) {
457 res
= nand_update_bbt(mtd
, ofs
);
463 mtd
->ecc_stats
.badblocks
++;
469 * nand_check_wp - [GENERIC] check if the chip is write protected
470 * @mtd: MTD device structure
472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
475 static int nand_check_wp(struct mtd_info
*mtd
)
477 struct nand_chip
*chip
= mtd
->priv
;
479 /* Broken xD cards report WP despite being writable */
480 if (chip
->options
& NAND_BROKEN_XD
)
483 /* Check the WP bit */
484 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
485 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
498 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
501 struct nand_chip
*chip
= mtd
->priv
;
504 return chip
->block_bad(mtd
, ofs
, getchip
);
506 /* Return info from the table */
507 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
512 * @mtd: MTD device structure
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
518 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
520 struct nand_chip
*chip
= mtd
->priv
;
523 /* Wait for the device to get ready */
524 for (i
= 0; i
< timeo
; i
++) {
525 if (chip
->dev_ready(mtd
))
527 touch_softlockup_watchdog();
532 /* Wait for the ready pin, after a command. The timeout is caught later. */
533 void nand_wait_ready(struct mtd_info
*mtd
)
535 struct nand_chip
*chip
= mtd
->priv
;
536 unsigned long timeo
= jiffies
+ 2;
539 if (in_interrupt() || oops_in_progress
)
540 return panic_nand_wait_ready(mtd
, 400);
542 led_trigger_event(nand_led_trigger
, LED_FULL
);
543 /* Wait until command is processed or timeout occurs */
545 if (chip
->dev_ready(mtd
))
547 touch_softlockup_watchdog();
548 } while (time_before(jiffies
, timeo
));
549 led_trigger_event(nand_led_trigger
, LED_OFF
);
551 EXPORT_SYMBOL_GPL(nand_wait_ready
);
554 * nand_command - [DEFAULT] Send command to NAND device
555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
563 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
564 int column
, int page_addr
)
566 register struct nand_chip
*chip
= mtd
->priv
;
567 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
569 /* Write out the command to the device */
570 if (command
== NAND_CMD_SEQIN
) {
573 if (column
>= mtd
->writesize
) {
575 column
-= mtd
->writesize
;
576 readcmd
= NAND_CMD_READOOB
;
577 } else if (column
< 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd
= NAND_CMD_READ0
;
582 readcmd
= NAND_CMD_READ1
;
584 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
585 ctrl
&= ~NAND_CTRL_CHANGE
;
587 chip
->cmd_ctrl(mtd
, command
, ctrl
);
589 /* Address cycle, when necessary */
590 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
591 /* Serially input address */
593 /* Adjust columns for 16 bit buswidth */
594 if (chip
->options
& NAND_BUSWIDTH_16
)
596 chip
->cmd_ctrl(mtd
, column
, ctrl
);
597 ctrl
&= ~NAND_CTRL_CHANGE
;
599 if (page_addr
!= -1) {
600 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
601 ctrl
&= ~NAND_CTRL_CHANGE
;
602 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
603 /* One more address cycle for devices > 32MiB */
604 if (chip
->chipsize
> (32 << 20))
605 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
607 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
610 * Program and erase have their own busy handlers status and sequential
615 case NAND_CMD_PAGEPROG
:
616 case NAND_CMD_ERASE1
:
617 case NAND_CMD_ERASE2
:
619 case NAND_CMD_STATUS
:
625 udelay(chip
->chip_delay
);
626 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
627 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
629 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
630 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
634 /* This applies to read commands */
637 * If we don't have access to the busy pin, we apply the given
640 if (!chip
->dev_ready
) {
641 udelay(chip
->chip_delay
);
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
651 nand_wait_ready(mtd
);
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
661 * Send command to NAND device. This is the version for the new large page
662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
665 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
666 int column
, int page_addr
)
668 register struct nand_chip
*chip
= mtd
->priv
;
670 /* Emulate NAND_CMD_READOOB */
671 if (command
== NAND_CMD_READOOB
) {
672 column
+= mtd
->writesize
;
673 command
= NAND_CMD_READ0
;
676 /* Command latch cycle */
677 chip
->cmd_ctrl(mtd
, command
& 0xff,
678 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
680 if (column
!= -1 || page_addr
!= -1) {
681 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
683 /* Serially input address */
685 /* Adjust columns for 16 bit buswidth */
686 if (chip
->options
& NAND_BUSWIDTH_16
)
688 chip
->cmd_ctrl(mtd
, column
, ctrl
);
689 ctrl
&= ~NAND_CTRL_CHANGE
;
690 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
692 if (page_addr
!= -1) {
693 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
694 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
695 NAND_NCE
| NAND_ALE
);
696 /* One more address cycle for devices > 128MiB */
697 if (chip
->chipsize
> (128 << 20))
698 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
699 NAND_NCE
| NAND_ALE
);
702 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
710 case NAND_CMD_CACHEDPROG
:
711 case NAND_CMD_PAGEPROG
:
712 case NAND_CMD_ERASE1
:
713 case NAND_CMD_ERASE2
:
716 case NAND_CMD_STATUS
:
717 case NAND_CMD_DEPLETE1
:
720 case NAND_CMD_STATUS_ERROR
:
721 case NAND_CMD_STATUS_ERROR0
:
722 case NAND_CMD_STATUS_ERROR1
:
723 case NAND_CMD_STATUS_ERROR2
:
724 case NAND_CMD_STATUS_ERROR3
:
725 /* Read error status commands require only a short delay */
726 udelay(chip
->chip_delay
);
732 udelay(chip
->chip_delay
);
733 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
734 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
735 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
736 NAND_NCE
| NAND_CTRL_CHANGE
);
737 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
741 case NAND_CMD_RNDOUT
:
742 /* No ready / busy check necessary */
743 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
744 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
745 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
746 NAND_NCE
| NAND_CTRL_CHANGE
);
750 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
751 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
752 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
753 NAND_NCE
| NAND_CTRL_CHANGE
);
755 /* This applies to read commands */
758 * If we don't have access to the busy pin, we apply the given
761 if (!chip
->dev_ready
) {
762 udelay(chip
->chip_delay
);
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
773 nand_wait_ready(mtd
);
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
782 * Used when in panic, no locks are taken.
784 static void panic_nand_get_device(struct nand_chip
*chip
,
785 struct mtd_info
*mtd
, int new_state
)
787 /* Hardware controller shared among independent devices */
788 chip
->controller
->active
= chip
;
789 chip
->state
= new_state
;
793 * nand_get_device - [GENERIC] Get chip for selected access
794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
798 * Get the device and lock it for exclusive access
801 nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
, int new_state
)
803 spinlock_t
*lock
= &chip
->controller
->lock
;
804 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
805 DECLARE_WAITQUEUE(wait
, current
);
809 /* Hardware controller shared among independent devices */
810 if (!chip
->controller
->active
)
811 chip
->controller
->active
= chip
;
813 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
814 chip
->state
= new_state
;
818 if (new_state
== FL_PM_SUSPENDED
) {
819 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
820 chip
->state
= FL_PM_SUSPENDED
;
825 set_current_state(TASK_UNINTERRUPTIBLE
);
826 add_wait_queue(wq
, &wait
);
829 remove_wait_queue(wq
, &wait
);
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
843 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
847 for (i
= 0; i
< timeo
; i
++) {
848 if (chip
->dev_ready
) {
849 if (chip
->dev_ready(mtd
))
852 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
868 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
871 unsigned long timeo
= jiffies
;
872 int status
, state
= chip
->state
;
874 if (state
== FL_ERASING
)
875 timeo
+= (HZ
* 400) / 1000;
877 timeo
+= (HZ
* 20) / 1000;
879 led_trigger_event(nand_led_trigger
, LED_FULL
);
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
887 if ((state
== FL_ERASING
) && (chip
->options
& NAND_IS_AND
))
888 chip
->cmdfunc(mtd
, NAND_CMD_STATUS_MULTI
, -1, -1);
890 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
892 if (in_interrupt() || oops_in_progress
)
893 panic_nand_wait(mtd
, chip
, timeo
);
895 while (time_before(jiffies
, timeo
)) {
896 if (chip
->dev_ready
) {
897 if (chip
->dev_ready(mtd
))
900 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
906 led_trigger_event(nand_led_trigger
, LED_OFF
);
908 status
= (int)chip
->read_byte(mtd
);
913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
922 * Returs unlock status.
924 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
925 uint64_t len
, int invert
)
929 struct nand_chip
*chip
= mtd
->priv
;
931 /* Submit address of first page to unlock */
932 page
= ofs
>> chip
->page_shift
;
933 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
935 /* Submit address of last page to unlock */
936 page
= (ofs
+ len
) >> chip
->page_shift
;
937 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
938 (page
| invert
) & chip
->pagemask
);
940 /* Call wait ready function */
941 status
= chip
->waitfunc(mtd
, chip
);
942 /* See if device thinks it succeeded */
944 pr_debug("%s: error status = 0x%08x\n",
953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
958 * Returns unlock status.
960 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
964 struct nand_chip
*chip
= mtd
->priv
;
966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
967 __func__
, (unsigned long long)ofs
, len
);
969 if (check_offs_len(mtd
, ofs
, len
))
972 /* Align to last block address if size addresses end of the device */
973 if (ofs
+ len
== mtd
->size
)
974 len
-= mtd
->erasesize
;
976 nand_get_device(chip
, mtd
, FL_UNLOCKING
);
978 /* Shift to get chip number */
979 chipnr
= ofs
>> chip
->chip_shift
;
981 chip
->select_chip(mtd
, chipnr
);
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd
)) {
985 pr_debug("%s: device is write protected!\n",
991 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
994 nand_release_device(mtd
);
998 EXPORT_SYMBOL(nand_unlock
);
1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1011 * Returns lock status.
1013 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1016 int chipnr
, status
, page
;
1017 struct nand_chip
*chip
= mtd
->priv
;
1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1020 __func__
, (unsigned long long)ofs
, len
);
1022 if (check_offs_len(mtd
, ofs
, len
))
1025 nand_get_device(chip
, mtd
, FL_LOCKING
);
1027 /* Shift to get chip number */
1028 chipnr
= ofs
>> chip
->chip_shift
;
1030 chip
->select_chip(mtd
, chipnr
);
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd
)) {
1034 pr_debug("%s: device is write protected!\n",
1036 status
= MTD_ERASE_FAILED
;
1041 /* Submit address of first page to lock */
1042 page
= ofs
>> chip
->page_shift
;
1043 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1045 /* Call wait ready function */
1046 status
= chip
->waitfunc(mtd
, chip
);
1047 /* See if device thinks it succeeded */
1048 if (status
& 0x01) {
1049 pr_debug("%s: error status = 0x%08x\n",
1055 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1058 nand_release_device(mtd
);
1062 EXPORT_SYMBOL(nand_lock
);
1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @page: page number to read
1071 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1073 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1074 uint8_t *buf
, int page
)
1076 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1077 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1082 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1083 * @mtd: mtd info structure
1084 * @chip: nand chip info structure
1085 * @buf: buffer to store read data
1086 * @page: page number to read
1088 * We need a special oob layout and handling even when OOB isn't used.
1090 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1091 struct nand_chip
*chip
,
1092 uint8_t *buf
, int page
)
1094 int eccsize
= chip
->ecc
.size
;
1095 int eccbytes
= chip
->ecc
.bytes
;
1096 uint8_t *oob
= chip
->oob_poi
;
1099 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1100 chip
->read_buf(mtd
, buf
, eccsize
);
1103 if (chip
->ecc
.prepad
) {
1104 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1105 oob
+= chip
->ecc
.prepad
;
1108 chip
->read_buf(mtd
, oob
, eccbytes
);
1111 if (chip
->ecc
.postpad
) {
1112 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1113 oob
+= chip
->ecc
.postpad
;
1117 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1119 chip
->read_buf(mtd
, oob
, size
);
1125 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1126 * @mtd: mtd info structure
1127 * @chip: nand chip info structure
1128 * @buf: buffer to store read data
1129 * @page: page number to read
1131 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1132 uint8_t *buf
, int page
)
1134 int i
, eccsize
= chip
->ecc
.size
;
1135 int eccbytes
= chip
->ecc
.bytes
;
1136 int eccsteps
= chip
->ecc
.steps
;
1138 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1139 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1140 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1142 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, page
);
1144 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1145 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1147 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1148 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1150 eccsteps
= chip
->ecc
.steps
;
1153 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1156 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1158 mtd
->ecc_stats
.failed
++;
1160 mtd
->ecc_stats
.corrected
+= stat
;
1166 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1167 * @mtd: mtd info structure
1168 * @chip: nand chip info structure
1169 * @data_offs: offset of requested data within the page
1170 * @readlen: data length
1171 * @bufpoi: buffer to store read data
1173 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1174 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
)
1176 int start_step
, end_step
, num_steps
;
1177 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1179 int data_col_addr
, i
, gaps
= 0;
1180 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1181 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1184 /* Column address within the page aligned to ECC size (256bytes) */
1185 start_step
= data_offs
/ chip
->ecc
.size
;
1186 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1187 num_steps
= end_step
- start_step
+ 1;
1189 /* Data size aligned to ECC ecc.size */
1190 datafrag_len
= num_steps
* chip
->ecc
.size
;
1191 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1193 data_col_addr
= start_step
* chip
->ecc
.size
;
1194 /* If we read not a page aligned data */
1195 if (data_col_addr
!= 0)
1196 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1198 p
= bufpoi
+ data_col_addr
;
1199 chip
->read_buf(mtd
, p
, datafrag_len
);
1202 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1203 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1206 * The performance is faster if we position offsets according to
1207 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1209 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1210 if (eccpos
[i
+ start_step
* chip
->ecc
.bytes
] + 1 !=
1211 eccpos
[i
+ start_step
* chip
->ecc
.bytes
+ 1]) {
1217 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1218 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1221 * Send the command to read the particular ECC bytes take care
1222 * about buswidth alignment in read_buf.
1224 index
= start_step
* chip
->ecc
.bytes
;
1226 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1227 aligned_len
= eccfrag_len
;
1228 if (eccpos
[index
] & (busw
- 1))
1230 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1233 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1234 mtd
->writesize
+ aligned_pos
, -1);
1235 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1238 for (i
= 0; i
< eccfrag_len
; i
++)
1239 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1241 p
= bufpoi
+ data_col_addr
;
1242 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1245 stat
= chip
->ecc
.correct(mtd
, p
,
1246 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1248 mtd
->ecc_stats
.failed
++;
1250 mtd
->ecc_stats
.corrected
+= stat
;
1256 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @buf: buffer to store read data
1260 * @page: page number to read
1262 * Not for syndrome calculating ECC controllers which need a special oob layout.
1264 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1265 uint8_t *buf
, int page
)
1267 int i
, eccsize
= chip
->ecc
.size
;
1268 int eccbytes
= chip
->ecc
.bytes
;
1269 int eccsteps
= chip
->ecc
.steps
;
1271 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1272 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1273 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1275 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1276 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1277 chip
->read_buf(mtd
, p
, eccsize
);
1278 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1280 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1282 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1283 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1285 eccsteps
= chip
->ecc
.steps
;
1288 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1291 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1293 mtd
->ecc_stats
.failed
++;
1295 mtd
->ecc_stats
.corrected
+= stat
;
1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1305 * @page: page number to read
1307 * Hardware ECC for large page chips, require OOB to be read first. For this
1308 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1309 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1310 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1311 * the data area, by overwriting the NAND manufacturer bad block markings.
1313 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1314 struct nand_chip
*chip
, uint8_t *buf
, int page
)
1316 int i
, eccsize
= chip
->ecc
.size
;
1317 int eccbytes
= chip
->ecc
.bytes
;
1318 int eccsteps
= chip
->ecc
.steps
;
1320 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1321 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1322 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1324 /* Read the OOB area first */
1325 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1326 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1327 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1329 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1330 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1332 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1335 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1336 chip
->read_buf(mtd
, p
, eccsize
);
1337 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1339 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1341 mtd
->ecc_stats
.failed
++;
1343 mtd
->ecc_stats
.corrected
+= stat
;
1349 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1350 * @mtd: mtd info structure
1351 * @chip: nand chip info structure
1352 * @buf: buffer to store read data
1353 * @page: page number to read
1355 * The hw generator calculates the error syndrome automatically. Therefore we
1356 * need a special oob layout and handling.
1358 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1359 uint8_t *buf
, int page
)
1361 int i
, eccsize
= chip
->ecc
.size
;
1362 int eccbytes
= chip
->ecc
.bytes
;
1363 int eccsteps
= chip
->ecc
.steps
;
1365 uint8_t *oob
= chip
->oob_poi
;
1367 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1370 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1371 chip
->read_buf(mtd
, p
, eccsize
);
1373 if (chip
->ecc
.prepad
) {
1374 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1375 oob
+= chip
->ecc
.prepad
;
1378 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1379 chip
->read_buf(mtd
, oob
, eccbytes
);
1380 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1383 mtd
->ecc_stats
.failed
++;
1385 mtd
->ecc_stats
.corrected
+= stat
;
1389 if (chip
->ecc
.postpad
) {
1390 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1391 oob
+= chip
->ecc
.postpad
;
1395 /* Calculate remaining oob bytes */
1396 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1398 chip
->read_buf(mtd
, oob
, i
);
1404 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1405 * @chip: nand chip structure
1406 * @oob: oob destination address
1407 * @ops: oob ops structure
1408 * @len: size of oob to transfer
1410 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1411 struct mtd_oob_ops
*ops
, size_t len
)
1413 switch (ops
->mode
) {
1415 case MTD_OPS_PLACE_OOB
:
1417 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1420 case MTD_OPS_AUTO_OOB
: {
1421 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1422 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1425 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1426 /* Read request not from offset 0? */
1427 if (unlikely(roffs
)) {
1428 if (roffs
>= free
->length
) {
1429 roffs
-= free
->length
;
1432 boffs
= free
->offset
+ roffs
;
1433 bytes
= min_t(size_t, len
,
1434 (free
->length
- roffs
));
1437 bytes
= min_t(size_t, len
, free
->length
);
1438 boffs
= free
->offset
;
1440 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1452 * nand_do_read_ops - [INTERN] Read data with ECC
1453 * @mtd: MTD device structure
1454 * @from: offset to read from
1455 * @ops: oob ops structure
1457 * Internal function. Called with chip held.
1459 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1460 struct mtd_oob_ops
*ops
)
1462 int chipnr
, page
, realpage
, col
, bytes
, aligned
;
1463 struct nand_chip
*chip
= mtd
->priv
;
1464 struct mtd_ecc_stats stats
;
1465 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1468 uint32_t readlen
= ops
->len
;
1469 uint32_t oobreadlen
= ops
->ooblen
;
1470 uint32_t max_oobsize
= ops
->mode
== MTD_OPS_AUTO_OOB
?
1471 mtd
->oobavail
: mtd
->oobsize
;
1473 uint8_t *bufpoi
, *oob
, *buf
;
1475 stats
= mtd
->ecc_stats
;
1477 chipnr
= (int)(from
>> chip
->chip_shift
);
1478 chip
->select_chip(mtd
, chipnr
);
1480 realpage
= (int)(from
>> chip
->page_shift
);
1481 page
= realpage
& chip
->pagemask
;
1483 col
= (int)(from
& (mtd
->writesize
- 1));
1489 bytes
= min(mtd
->writesize
- col
, readlen
);
1490 aligned
= (bytes
== mtd
->writesize
);
1492 /* Is the current page in the buffer? */
1493 if (realpage
!= chip
->pagebuf
|| oob
) {
1494 bufpoi
= aligned
? buf
: chip
->buffers
->databuf
;
1496 if (likely(sndcmd
)) {
1497 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1501 /* Now read the page into the buffer */
1502 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1503 ret
= chip
->ecc
.read_page_raw(mtd
, chip
,
1505 else if (!aligned
&& NAND_SUBPAGE_READ(chip
) && !oob
)
1506 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1507 col
, bytes
, bufpoi
);
1509 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1513 /* Invalidate page cache */
1518 /* Transfer not aligned data */
1520 if (!NAND_SUBPAGE_READ(chip
) && !oob
&&
1521 !(mtd
->ecc_stats
.failed
- stats
.failed
) &&
1522 (ops
->mode
!= MTD_OPS_RAW
))
1523 chip
->pagebuf
= realpage
;
1525 /* Invalidate page cache */
1527 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1532 if (unlikely(oob
)) {
1534 int toread
= min(oobreadlen
, max_oobsize
);
1537 oob
= nand_transfer_oob(chip
,
1539 oobreadlen
-= toread
;
1543 if (!(chip
->options
& NAND_NO_READRDY
)) {
1545 * Apply delay or wait for ready/busy pin. Do
1546 * this before the AUTOINCR check, so no
1547 * problems arise if a chip which does auto
1548 * increment is marked as NOAUTOINCR by the
1551 if (!chip
->dev_ready
)
1552 udelay(chip
->chip_delay
);
1554 nand_wait_ready(mtd
);
1557 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1566 /* For subsequent reads align to page boundary */
1568 /* Increment page address */
1571 page
= realpage
& chip
->pagemask
;
1572 /* Check, if we cross a chip boundary */
1575 chip
->select_chip(mtd
, -1);
1576 chip
->select_chip(mtd
, chipnr
);
1580 * Check, if the chip supports auto page increment or if we
1581 * have hit a block boundary.
1583 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1587 ops
->retlen
= ops
->len
- (size_t) readlen
;
1589 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1594 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1597 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1601 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1602 * @mtd: MTD device structure
1603 * @from: offset to read from
1604 * @len: number of bytes to read
1605 * @retlen: pointer to variable to store the number of read bytes
1606 * @buf: the databuffer to put data
1608 * Get hold of the chip and call nand_do_read.
1610 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1611 size_t *retlen
, uint8_t *buf
)
1613 struct nand_chip
*chip
= mtd
->priv
;
1614 struct mtd_oob_ops ops
;
1617 nand_get_device(chip
, mtd
, FL_READING
);
1622 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1623 *retlen
= ops
.retlen
;
1624 nand_release_device(mtd
);
1629 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1630 * @mtd: mtd info structure
1631 * @chip: nand chip info structure
1632 * @page: page number to read
1633 * @sndcmd: flag whether to issue read command or not
1635 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1636 int page
, int sndcmd
)
1639 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1642 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1647 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1649 * @mtd: mtd info structure
1650 * @chip: nand chip info structure
1651 * @page: page number to read
1652 * @sndcmd: flag whether to issue read command or not
1654 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1655 int page
, int sndcmd
)
1657 uint8_t *buf
= chip
->oob_poi
;
1658 int length
= mtd
->oobsize
;
1659 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1660 int eccsize
= chip
->ecc
.size
;
1661 uint8_t *bufpoi
= buf
;
1662 int i
, toread
, sndrnd
= 0, pos
;
1664 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1665 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1667 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1668 if (mtd
->writesize
> 512)
1669 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1671 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1674 toread
= min_t(int, length
, chunk
);
1675 chip
->read_buf(mtd
, bufpoi
, toread
);
1680 chip
->read_buf(mtd
, bufpoi
, length
);
1686 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1687 * @mtd: mtd info structure
1688 * @chip: nand chip info structure
1689 * @page: page number to write
1691 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1695 const uint8_t *buf
= chip
->oob_poi
;
1696 int length
= mtd
->oobsize
;
1698 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1699 chip
->write_buf(mtd
, buf
, length
);
1700 /* Send command to program the OOB data */
1701 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1703 status
= chip
->waitfunc(mtd
, chip
);
1705 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1709 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1710 * with syndrome - only for large page flash
1711 * @mtd: mtd info structure
1712 * @chip: nand chip info structure
1713 * @page: page number to write
1715 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1716 struct nand_chip
*chip
, int page
)
1718 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1719 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1720 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1721 const uint8_t *bufpoi
= chip
->oob_poi
;
1724 * data-ecc-data-ecc ... ecc-oob
1726 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1728 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1729 pos
= steps
* (eccsize
+ chunk
);
1734 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1735 for (i
= 0; i
< steps
; i
++) {
1737 if (mtd
->writesize
<= 512) {
1738 uint32_t fill
= 0xFFFFFFFF;
1742 int num
= min_t(int, len
, 4);
1743 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1748 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1749 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1753 len
= min_t(int, length
, chunk
);
1754 chip
->write_buf(mtd
, bufpoi
, len
);
1759 chip
->write_buf(mtd
, bufpoi
, length
);
1761 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1762 status
= chip
->waitfunc(mtd
, chip
);
1764 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1768 * nand_do_read_oob - [INTERN] NAND read out-of-band
1769 * @mtd: MTD device structure
1770 * @from: offset to read from
1771 * @ops: oob operations description structure
1773 * NAND read out-of-band data from the spare area.
1775 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1776 struct mtd_oob_ops
*ops
)
1778 int page
, realpage
, chipnr
, sndcmd
= 1;
1779 struct nand_chip
*chip
= mtd
->priv
;
1780 struct mtd_ecc_stats stats
;
1781 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1782 int readlen
= ops
->ooblen
;
1784 uint8_t *buf
= ops
->oobbuf
;
1786 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1787 __func__
, (unsigned long long)from
, readlen
);
1789 stats
= mtd
->ecc_stats
;
1791 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
1792 len
= chip
->ecc
.layout
->oobavail
;
1796 if (unlikely(ops
->ooboffs
>= len
)) {
1797 pr_debug("%s: attempt to start read outside oob\n",
1802 /* Do not allow reads past end of device */
1803 if (unlikely(from
>= mtd
->size
||
1804 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1805 (from
>> chip
->page_shift
)) * len
)) {
1806 pr_debug("%s: attempt to read beyond end of device\n",
1811 chipnr
= (int)(from
>> chip
->chip_shift
);
1812 chip
->select_chip(mtd
, chipnr
);
1814 /* Shift to get page */
1815 realpage
= (int)(from
>> chip
->page_shift
);
1816 page
= realpage
& chip
->pagemask
;
1819 if (ops
->mode
== MTD_OPS_RAW
)
1820 sndcmd
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
, sndcmd
);
1822 sndcmd
= chip
->ecc
.read_oob(mtd
, chip
, page
, sndcmd
);
1824 len
= min(len
, readlen
);
1825 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1827 if (!(chip
->options
& NAND_NO_READRDY
)) {
1829 * Apply delay or wait for ready/busy pin. Do this
1830 * before the AUTOINCR check, so no problems arise if a
1831 * chip which does auto increment is marked as
1832 * NOAUTOINCR by the board driver.
1834 if (!chip
->dev_ready
)
1835 udelay(chip
->chip_delay
);
1837 nand_wait_ready(mtd
);
1844 /* Increment page address */
1847 page
= realpage
& chip
->pagemask
;
1848 /* Check, if we cross a chip boundary */
1851 chip
->select_chip(mtd
, -1);
1852 chip
->select_chip(mtd
, chipnr
);
1856 * Check, if the chip supports auto page increment or if we
1857 * have hit a block boundary.
1859 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1863 ops
->oobretlen
= ops
->ooblen
;
1865 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1868 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1872 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1873 * @mtd: MTD device structure
1874 * @from: offset to read from
1875 * @ops: oob operation description structure
1877 * NAND read data and/or out-of-band data.
1879 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1880 struct mtd_oob_ops
*ops
)
1882 struct nand_chip
*chip
= mtd
->priv
;
1883 int ret
= -ENOTSUPP
;
1887 /* Do not allow reads past end of device */
1888 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1889 pr_debug("%s: attempt to read beyond end of device\n",
1894 nand_get_device(chip
, mtd
, FL_READING
);
1896 switch (ops
->mode
) {
1897 case MTD_OPS_PLACE_OOB
:
1898 case MTD_OPS_AUTO_OOB
:
1907 ret
= nand_do_read_oob(mtd
, from
, ops
);
1909 ret
= nand_do_read_ops(mtd
, from
, ops
);
1912 nand_release_device(mtd
);
1918 * nand_write_page_raw - [INTERN] raw page write function
1919 * @mtd: mtd info structure
1920 * @chip: nand chip info structure
1923 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1925 static void nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1928 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1929 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1933 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1934 * @mtd: mtd info structure
1935 * @chip: nand chip info structure
1938 * We need a special oob layout and handling even when ECC isn't checked.
1940 static void nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1941 struct nand_chip
*chip
,
1944 int eccsize
= chip
->ecc
.size
;
1945 int eccbytes
= chip
->ecc
.bytes
;
1946 uint8_t *oob
= chip
->oob_poi
;
1949 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1950 chip
->write_buf(mtd
, buf
, eccsize
);
1953 if (chip
->ecc
.prepad
) {
1954 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1955 oob
+= chip
->ecc
.prepad
;
1958 chip
->read_buf(mtd
, oob
, eccbytes
);
1961 if (chip
->ecc
.postpad
) {
1962 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1963 oob
+= chip
->ecc
.postpad
;
1967 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1969 chip
->write_buf(mtd
, oob
, size
);
1972 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1973 * @mtd: mtd info structure
1974 * @chip: nand chip info structure
1977 static void nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1980 int i
, eccsize
= chip
->ecc
.size
;
1981 int eccbytes
= chip
->ecc
.bytes
;
1982 int eccsteps
= chip
->ecc
.steps
;
1983 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1984 const uint8_t *p
= buf
;
1985 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1987 /* Software ECC calculation */
1988 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1989 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1991 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1992 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1994 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
1998 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1999 * @mtd: mtd info structure
2000 * @chip: nand chip info structure
2003 static void nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2006 int i
, eccsize
= chip
->ecc
.size
;
2007 int eccbytes
= chip
->ecc
.bytes
;
2008 int eccsteps
= chip
->ecc
.steps
;
2009 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2010 const uint8_t *p
= buf
;
2011 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2013 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2014 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2015 chip
->write_buf(mtd
, p
, eccsize
);
2016 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2019 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2020 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2022 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2026 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2027 * @mtd: mtd info structure
2028 * @chip: nand chip info structure
2031 * The hw generator calculates the error syndrome automatically. Therefore we
2032 * need a special oob layout and handling.
2034 static void nand_write_page_syndrome(struct mtd_info
*mtd
,
2035 struct nand_chip
*chip
, const uint8_t *buf
)
2037 int i
, eccsize
= chip
->ecc
.size
;
2038 int eccbytes
= chip
->ecc
.bytes
;
2039 int eccsteps
= chip
->ecc
.steps
;
2040 const uint8_t *p
= buf
;
2041 uint8_t *oob
= chip
->oob_poi
;
2043 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2045 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2046 chip
->write_buf(mtd
, p
, eccsize
);
2048 if (chip
->ecc
.prepad
) {
2049 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2050 oob
+= chip
->ecc
.prepad
;
2053 chip
->ecc
.calculate(mtd
, p
, oob
);
2054 chip
->write_buf(mtd
, oob
, eccbytes
);
2057 if (chip
->ecc
.postpad
) {
2058 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2059 oob
+= chip
->ecc
.postpad
;
2063 /* Calculate remaining oob bytes */
2064 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2066 chip
->write_buf(mtd
, oob
, i
);
2070 * nand_write_page - [REPLACEABLE] write one page
2071 * @mtd: MTD device structure
2072 * @chip: NAND chip descriptor
2073 * @buf: the data to write
2074 * @page: page number to write
2075 * @cached: cached programming
2076 * @raw: use _raw version of write_page
2078 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2079 const uint8_t *buf
, int page
, int cached
, int raw
)
2083 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2086 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
2088 chip
->ecc
.write_page(mtd
, chip
, buf
);
2091 * Cached progamming disabled for now. Not sure if it's worth the
2092 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2096 if (!cached
|| !(chip
->options
& NAND_CACHEPRG
)) {
2098 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2099 status
= chip
->waitfunc(mtd
, chip
);
2101 * See if operation failed and additional status checks are
2104 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2105 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2108 if (status
& NAND_STATUS_FAIL
)
2111 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2112 status
= chip
->waitfunc(mtd
, chip
);
2115 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2116 /* Send command to read back the data */
2117 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
2119 if (chip
->verify_buf(mtd
, buf
, mtd
->writesize
))
2126 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2127 * @mtd: MTD device structure
2128 * @oob: oob data buffer
2129 * @len: oob data write length
2130 * @ops: oob ops structure
2132 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2133 struct mtd_oob_ops
*ops
)
2135 struct nand_chip
*chip
= mtd
->priv
;
2138 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2139 * data from a previous OOB read.
2141 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2143 switch (ops
->mode
) {
2145 case MTD_OPS_PLACE_OOB
:
2147 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2150 case MTD_OPS_AUTO_OOB
: {
2151 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2152 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2155 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2156 /* Write request not from offset 0? */
2157 if (unlikely(woffs
)) {
2158 if (woffs
>= free
->length
) {
2159 woffs
-= free
->length
;
2162 boffs
= free
->offset
+ woffs
;
2163 bytes
= min_t(size_t, len
,
2164 (free
->length
- woffs
));
2167 bytes
= min_t(size_t, len
, free
->length
);
2168 boffs
= free
->offset
;
2170 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2181 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2184 * nand_do_write_ops - [INTERN] NAND write with ECC
2185 * @mtd: MTD device structure
2186 * @to: offset to write to
2187 * @ops: oob operations description structure
2189 * NAND write with ECC.
2191 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2192 struct mtd_oob_ops
*ops
)
2194 int chipnr
, realpage
, page
, blockmask
, column
;
2195 struct nand_chip
*chip
= mtd
->priv
;
2196 uint32_t writelen
= ops
->len
;
2198 uint32_t oobwritelen
= ops
->ooblen
;
2199 uint32_t oobmaxlen
= ops
->mode
== MTD_OPS_AUTO_OOB
?
2200 mtd
->oobavail
: mtd
->oobsize
;
2202 uint8_t *oob
= ops
->oobbuf
;
2203 uint8_t *buf
= ops
->datbuf
;
2210 /* Reject writes, which are not page aligned */
2211 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2212 pr_notice("%s: attempt to write non page aligned data\n",
2217 column
= to
& (mtd
->writesize
- 1);
2218 subpage
= column
|| (writelen
& (mtd
->writesize
- 1));
2223 chipnr
= (int)(to
>> chip
->chip_shift
);
2224 chip
->select_chip(mtd
, chipnr
);
2226 /* Check, if it is write protected */
2227 if (nand_check_wp(mtd
))
2230 realpage
= (int)(to
>> chip
->page_shift
);
2231 page
= realpage
& chip
->pagemask
;
2232 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2234 /* Invalidate the page cache, when we write to the cached page */
2235 if (to
<= (chip
->pagebuf
<< chip
->page_shift
) &&
2236 (chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2239 /* Don't allow multipage oob writes with offset */
2240 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
))
2244 int bytes
= mtd
->writesize
;
2245 int cached
= writelen
> bytes
&& page
!= blockmask
;
2246 uint8_t *wbuf
= buf
;
2248 /* Partial page write? */
2249 if (unlikely(column
|| writelen
< (mtd
->writesize
- 1))) {
2251 bytes
= min_t(int, bytes
- column
, (int) writelen
);
2253 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2254 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2255 wbuf
= chip
->buffers
->databuf
;
2258 if (unlikely(oob
)) {
2259 size_t len
= min(oobwritelen
, oobmaxlen
);
2260 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2263 /* We still need to erase leftover OOB data */
2264 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2267 ret
= chip
->write_page(mtd
, chip
, wbuf
, page
, cached
,
2268 (ops
->mode
== MTD_OPS_RAW
));
2280 page
= realpage
& chip
->pagemask
;
2281 /* Check, if we cross a chip boundary */
2284 chip
->select_chip(mtd
, -1);
2285 chip
->select_chip(mtd
, chipnr
);
2289 ops
->retlen
= ops
->len
- writelen
;
2291 ops
->oobretlen
= ops
->ooblen
;
2296 * panic_nand_write - [MTD Interface] NAND write with ECC
2297 * @mtd: MTD device structure
2298 * @to: offset to write to
2299 * @len: number of bytes to write
2300 * @retlen: pointer to variable to store the number of written bytes
2301 * @buf: the data to write
2303 * NAND write with ECC. Used when performing writes in interrupt context, this
2304 * may for example be called by mtdoops when writing an oops while in panic.
2306 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2307 size_t *retlen
, const uint8_t *buf
)
2309 struct nand_chip
*chip
= mtd
->priv
;
2310 struct mtd_oob_ops ops
;
2313 /* Wait for the device to get ready */
2314 panic_nand_wait(mtd
, chip
, 400);
2316 /* Grab the device */
2317 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2320 ops
.datbuf
= (uint8_t *)buf
;
2324 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2326 *retlen
= ops
.retlen
;
2331 * nand_write - [MTD Interface] NAND write with ECC
2332 * @mtd: MTD device structure
2333 * @to: offset to write to
2334 * @len: number of bytes to write
2335 * @retlen: pointer to variable to store the number of written bytes
2336 * @buf: the data to write
2338 * NAND write with ECC.
2340 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2341 size_t *retlen
, const uint8_t *buf
)
2343 struct nand_chip
*chip
= mtd
->priv
;
2344 struct mtd_oob_ops ops
;
2347 nand_get_device(chip
, mtd
, FL_WRITING
);
2349 ops
.datbuf
= (uint8_t *)buf
;
2352 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2353 *retlen
= ops
.retlen
;
2354 nand_release_device(mtd
);
2359 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2360 * @mtd: MTD device structure
2361 * @to: offset to write to
2362 * @ops: oob operation description structure
2364 * NAND write out-of-band.
2366 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2367 struct mtd_oob_ops
*ops
)
2369 int chipnr
, page
, status
, len
;
2370 struct nand_chip
*chip
= mtd
->priv
;
2372 pr_debug("%s: to = 0x%08x, len = %i\n",
2373 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2375 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2376 len
= chip
->ecc
.layout
->oobavail
;
2380 /* Do not allow write past end of page */
2381 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2382 pr_debug("%s: attempt to write past end of page\n",
2387 if (unlikely(ops
->ooboffs
>= len
)) {
2388 pr_debug("%s: attempt to start write outside oob\n",
2393 /* Do not allow write past end of device */
2394 if (unlikely(to
>= mtd
->size
||
2395 ops
->ooboffs
+ ops
->ooblen
>
2396 ((mtd
->size
>> chip
->page_shift
) -
2397 (to
>> chip
->page_shift
)) * len
)) {
2398 pr_debug("%s: attempt to write beyond end of device\n",
2403 chipnr
= (int)(to
>> chip
->chip_shift
);
2404 chip
->select_chip(mtd
, chipnr
);
2406 /* Shift to get page */
2407 page
= (int)(to
>> chip
->page_shift
);
2410 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2411 * of my DiskOnChip 2000 test units) will clear the whole data page too
2412 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2413 * it in the doc2000 driver in August 1999. dwmw2.
2415 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2417 /* Check, if it is write protected */
2418 if (nand_check_wp(mtd
))
2421 /* Invalidate the page cache, if we write to the cached page */
2422 if (page
== chip
->pagebuf
)
2425 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2427 if (ops
->mode
== MTD_OPS_RAW
)
2428 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2430 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2435 ops
->oobretlen
= ops
->ooblen
;
2441 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2442 * @mtd: MTD device structure
2443 * @to: offset to write to
2444 * @ops: oob operation description structure
2446 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2447 struct mtd_oob_ops
*ops
)
2449 struct nand_chip
*chip
= mtd
->priv
;
2450 int ret
= -ENOTSUPP
;
2454 /* Do not allow writes past end of device */
2455 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2456 pr_debug("%s: attempt to write beyond end of device\n",
2461 nand_get_device(chip
, mtd
, FL_WRITING
);
2463 switch (ops
->mode
) {
2464 case MTD_OPS_PLACE_OOB
:
2465 case MTD_OPS_AUTO_OOB
:
2474 ret
= nand_do_write_oob(mtd
, to
, ops
);
2476 ret
= nand_do_write_ops(mtd
, to
, ops
);
2479 nand_release_device(mtd
);
2484 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
2488 * Standard erase command for NAND chips.
2490 static void single_erase_cmd(struct mtd_info
*mtd
, int page
)
2492 struct nand_chip
*chip
= mtd
->priv
;
2493 /* Send commands to erase a block */
2494 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2495 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2499 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2500 * @mtd: MTD device structure
2501 * @page: the page address of the block which will be erased
2503 * AND multi block erase command function. Erase 4 consecutive blocks.
2505 static void multi_erase_cmd(struct mtd_info
*mtd
, int page
)
2507 struct nand_chip
*chip
= mtd
->priv
;
2508 /* Send commands to erase a block */
2509 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2510 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2511 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2512 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2513 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2517 * nand_erase - [MTD Interface] erase block(s)
2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
2521 * Erase one ore more blocks.
2523 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2525 return nand_erase_nand(mtd
, instr
, 0);
2528 #define BBT_PAGE_MASK 0xffffff3f
2530 * nand_erase_nand - [INTERN] erase block(s)
2531 * @mtd: MTD device structure
2532 * @instr: erase instruction
2533 * @allowbbt: allow erasing the bbt area
2535 * Erase one ore more blocks.
2537 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2540 int page
, status
, pages_per_block
, ret
, chipnr
;
2541 struct nand_chip
*chip
= mtd
->priv
;
2542 loff_t rewrite_bbt
[NAND_MAX_CHIPS
] = {0};
2543 unsigned int bbt_masked_page
= 0xffffffff;
2546 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2547 __func__
, (unsigned long long)instr
->addr
,
2548 (unsigned long long)instr
->len
);
2550 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2553 /* Grab the lock and see if the device is available */
2554 nand_get_device(chip
, mtd
, FL_ERASING
);
2556 /* Shift to get first page */
2557 page
= (int)(instr
->addr
>> chip
->page_shift
);
2558 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2560 /* Calculate pages in each block */
2561 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2563 /* Select the NAND device */
2564 chip
->select_chip(mtd
, chipnr
);
2566 /* Check, if it is write protected */
2567 if (nand_check_wp(mtd
)) {
2568 pr_debug("%s: device is write protected!\n",
2570 instr
->state
= MTD_ERASE_FAILED
;
2575 * If BBT requires refresh, set the BBT page mask to see if the BBT
2576 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2577 * can not be matched. This is also done when the bbt is actually
2578 * erased to avoid recursive updates.
2580 if (chip
->options
& BBT_AUTO_REFRESH
&& !allowbbt
)
2581 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] & BBT_PAGE_MASK
;
2583 /* Loop through the pages */
2586 instr
->state
= MTD_ERASING
;
2589 /* Check if we have a bad block, we do not erase bad blocks! */
2590 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2591 chip
->page_shift
, 0, allowbbt
)) {
2592 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2594 instr
->state
= MTD_ERASE_FAILED
;
2599 * Invalidate the page cache, if we erase the block which
2600 * contains the current cached page.
2602 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2603 (page
+ pages_per_block
))
2606 chip
->erase_cmd(mtd
, page
& chip
->pagemask
);
2608 status
= chip
->waitfunc(mtd
, chip
);
2611 * See if operation failed and additional status checks are
2614 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2615 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2618 /* See if block erase succeeded */
2619 if (status
& NAND_STATUS_FAIL
) {
2620 pr_debug("%s: failed erase, page 0x%08x\n",
2622 instr
->state
= MTD_ERASE_FAILED
;
2624 ((loff_t
)page
<< chip
->page_shift
);
2629 * If BBT requires refresh, set the BBT rewrite flag to the
2630 * page being erased.
2632 if (bbt_masked_page
!= 0xffffffff &&
2633 (page
& BBT_PAGE_MASK
) == bbt_masked_page
)
2634 rewrite_bbt
[chipnr
] =
2635 ((loff_t
)page
<< chip
->page_shift
);
2637 /* Increment page address and decrement length */
2638 len
-= (1 << chip
->phys_erase_shift
);
2639 page
+= pages_per_block
;
2641 /* Check, if we cross a chip boundary */
2642 if (len
&& !(page
& chip
->pagemask
)) {
2644 chip
->select_chip(mtd
, -1);
2645 chip
->select_chip(mtd
, chipnr
);
2648 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2649 * page mask to see if this BBT should be rewritten.
2651 if (bbt_masked_page
!= 0xffffffff &&
2652 (chip
->bbt_td
->options
& NAND_BBT_PERCHIP
))
2653 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] &
2657 instr
->state
= MTD_ERASE_DONE
;
2661 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2663 /* Deselect and wake up anyone waiting on the device */
2664 nand_release_device(mtd
);
2666 /* Do call back function */
2668 mtd_erase_callback(instr
);
2671 * If BBT requires refresh and erase was successful, rewrite any
2672 * selected bad block tables.
2674 if (bbt_masked_page
== 0xffffffff || ret
)
2677 for (chipnr
= 0; chipnr
< chip
->numchips
; chipnr
++) {
2678 if (!rewrite_bbt
[chipnr
])
2680 /* Update the BBT for chip */
2681 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2682 __func__
, chipnr
, rewrite_bbt
[chipnr
],
2683 chip
->bbt_td
->pages
[chipnr
]);
2684 nand_update_bbt(mtd
, rewrite_bbt
[chipnr
]);
2687 /* Return more or less happy */
2692 * nand_sync - [MTD Interface] sync
2693 * @mtd: MTD device structure
2695 * Sync is actually a wait for chip ready function.
2697 static void nand_sync(struct mtd_info
*mtd
)
2699 struct nand_chip
*chip
= mtd
->priv
;
2701 pr_debug("%s: called\n", __func__
);
2703 /* Grab the lock and see if the device is available */
2704 nand_get_device(chip
, mtd
, FL_SYNCING
);
2705 /* Release it and go back */
2706 nand_release_device(mtd
);
2710 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2711 * @mtd: MTD device structure
2712 * @offs: offset relative to mtd start
2714 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2716 return nand_block_checkbad(mtd
, offs
, 1, 0);
2720 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2721 * @mtd: MTD device structure
2722 * @ofs: offset relative to mtd start
2724 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2726 struct nand_chip
*chip
= mtd
->priv
;
2729 ret
= nand_block_isbad(mtd
, ofs
);
2731 /* If it was bad already, return success and do nothing */
2737 return chip
->block_markbad(mtd
, ofs
);
2741 * nand_suspend - [MTD Interface] Suspend the NAND flash
2742 * @mtd: MTD device structure
2744 static int nand_suspend(struct mtd_info
*mtd
)
2746 struct nand_chip
*chip
= mtd
->priv
;
2748 return nand_get_device(chip
, mtd
, FL_PM_SUSPENDED
);
2752 * nand_resume - [MTD Interface] Resume the NAND flash
2753 * @mtd: MTD device structure
2755 static void nand_resume(struct mtd_info
*mtd
)
2757 struct nand_chip
*chip
= mtd
->priv
;
2759 if (chip
->state
== FL_PM_SUSPENDED
)
2760 nand_release_device(mtd
);
2762 pr_err("%s called for a chip which is not in suspended state\n",
2766 /* Set default functions */
2767 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2769 /* check for proper chip_delay setup, set 20us if not */
2770 if (!chip
->chip_delay
)
2771 chip
->chip_delay
= 20;
2773 /* check, if a user supplied command function given */
2774 if (chip
->cmdfunc
== NULL
)
2775 chip
->cmdfunc
= nand_command
;
2777 /* check, if a user supplied wait function given */
2778 if (chip
->waitfunc
== NULL
)
2779 chip
->waitfunc
= nand_wait
;
2781 if (!chip
->select_chip
)
2782 chip
->select_chip
= nand_select_chip
;
2783 if (!chip
->read_byte
)
2784 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2785 if (!chip
->read_word
)
2786 chip
->read_word
= nand_read_word
;
2787 if (!chip
->block_bad
)
2788 chip
->block_bad
= nand_block_bad
;
2789 if (!chip
->block_markbad
)
2790 chip
->block_markbad
= nand_default_block_markbad
;
2791 if (!chip
->write_buf
)
2792 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2793 if (!chip
->read_buf
)
2794 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2795 if (!chip
->verify_buf
)
2796 chip
->verify_buf
= busw
? nand_verify_buf16
: nand_verify_buf
;
2797 if (!chip
->scan_bbt
)
2798 chip
->scan_bbt
= nand_default_bbt
;
2800 if (!chip
->controller
) {
2801 chip
->controller
= &chip
->hwcontrol
;
2802 spin_lock_init(&chip
->controller
->lock
);
2803 init_waitqueue_head(&chip
->controller
->wq
);
2808 /* Sanitize ONFI strings so we can safely print them */
2809 static void sanitize_string(uint8_t *s
, size_t len
)
2813 /* Null terminate */
2816 /* Remove non printable chars */
2817 for (i
= 0; i
< len
- 1; i
++) {
2818 if (s
[i
] < ' ' || s
[i
] > 127)
2822 /* Remove trailing spaces */
2826 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2831 for (i
= 0; i
< 8; i
++)
2832 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2839 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2841 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2844 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2848 /* Try ONFI for unknown chip or LP */
2849 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2850 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2851 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2854 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2855 for (i
= 0; i
< 3; i
++) {
2856 chip
->read_buf(mtd
, (uint8_t *)p
, sizeof(*p
));
2857 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2858 le16_to_cpu(p
->crc
)) {
2859 pr_info("ONFI param page %d valid\n", i
);
2868 val
= le16_to_cpu(p
->revision
);
2870 chip
->onfi_version
= 23;
2871 else if (val
& (1 << 4))
2872 chip
->onfi_version
= 22;
2873 else if (val
& (1 << 3))
2874 chip
->onfi_version
= 21;
2875 else if (val
& (1 << 2))
2876 chip
->onfi_version
= 20;
2877 else if (val
& (1 << 1))
2878 chip
->onfi_version
= 10;
2880 chip
->onfi_version
= 0;
2882 if (!chip
->onfi_version
) {
2883 pr_info("%s: unsupported ONFI version: %d\n", __func__
, val
);
2887 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2888 sanitize_string(p
->model
, sizeof(p
->model
));
2890 mtd
->name
= p
->model
;
2891 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
2892 mtd
->erasesize
= le32_to_cpu(p
->pages_per_block
) * mtd
->writesize
;
2893 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
2894 chip
->chipsize
= le32_to_cpu(p
->blocks_per_lun
);
2895 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
2897 if (le16_to_cpu(p
->features
) & 1)
2898 *busw
= NAND_BUSWIDTH_16
;
2900 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
2901 chip
->options
|= (NAND_NO_READRDY
|
2902 NAND_NO_AUTOINCR
) & NAND_CHIPOPTIONS_MSK
;
2904 pr_info("ONFI flash detected\n");
2909 * Get the flash and manufacturer id and lookup if the type is supported.
2911 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
2912 struct nand_chip
*chip
,
2914 int *maf_id
, int *dev_id
,
2915 struct nand_flash_dev
*type
)
2921 /* Select the device */
2922 chip
->select_chip(mtd
, 0);
2925 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2928 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2930 /* Send the command for reading device ID */
2931 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2933 /* Read manufacturer and device IDs */
2934 *maf_id
= chip
->read_byte(mtd
);
2935 *dev_id
= chip
->read_byte(mtd
);
2938 * Try again to make sure, as some systems the bus-hold or other
2939 * interface concerns can cause random data which looks like a
2940 * possibly credible NAND flash to appear. If the two results do
2941 * not match, ignore the device completely.
2944 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2946 for (i
= 0; i
< 2; i
++)
2947 id_data
[i
] = chip
->read_byte(mtd
);
2949 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
2950 pr_info("%s: second ID read did not match "
2951 "%02x,%02x against %02x,%02x\n", __func__
,
2952 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
2953 return ERR_PTR(-ENODEV
);
2957 type
= nand_flash_ids
;
2959 for (; type
->name
!= NULL
; type
++)
2960 if (*dev_id
== type
->id
)
2963 chip
->onfi_version
= 0;
2964 if (!type
->name
|| !type
->pagesize
) {
2965 /* Check is chip is ONFI compliant */
2966 ret
= nand_flash_detect_onfi(mtd
, chip
, &busw
);
2971 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2973 /* Read entire ID string */
2975 for (i
= 0; i
< 8; i
++)
2976 id_data
[i
] = chip
->read_byte(mtd
);
2979 return ERR_PTR(-ENODEV
);
2982 mtd
->name
= type
->name
;
2984 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
2986 if (!type
->pagesize
&& chip
->init_size
) {
2987 /* Set the pagesize, oobsize, erasesize by the driver */
2988 busw
= chip
->init_size(mtd
, chip
, id_data
);
2989 } else if (!type
->pagesize
) {
2991 /* The 3rd id byte holds MLC / multichip data */
2992 chip
->cellinfo
= id_data
[2];
2993 /* The 4th id byte is the important one */
2997 * Field definitions are in the following datasheets:
2998 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2999 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
3001 * Check for wraparound + Samsung ID + nonzero 6th byte
3002 * to decide what to do.
3004 if (id_data
[0] == id_data
[6] && id_data
[1] == id_data
[7] &&
3005 id_data
[0] == NAND_MFR_SAMSUNG
&&
3006 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3007 id_data
[5] != 0x00) {
3009 mtd
->writesize
= 2048 << (extid
& 0x03);
3012 switch (extid
& 0x03) {
3027 /* Calc blocksize */
3028 mtd
->erasesize
= (128 * 1024) <<
3029 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3033 mtd
->writesize
= 1024 << (extid
& 0x03);
3036 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3037 (mtd
->writesize
>> 9);
3039 /* Calc blocksize. Blocksize is multiples of 64KiB */
3040 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3042 /* Get buswidth information */
3043 busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3047 * Old devices have chip data hardcoded in the device id table.
3049 mtd
->erasesize
= type
->erasesize
;
3050 mtd
->writesize
= type
->pagesize
;
3051 mtd
->oobsize
= mtd
->writesize
/ 32;
3052 busw
= type
->options
& NAND_BUSWIDTH_16
;
3055 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3056 * some Spansion chips have erasesize that conflicts with size
3057 * listed in nand_ids table.
3058 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3060 if (*maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 &&
3061 id_data
[5] == 0x00 && id_data
[6] == 0x00 &&
3062 id_data
[7] == 0x00 && mtd
->writesize
== 512) {
3063 mtd
->erasesize
= 128 * 1024;
3064 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3067 /* Get chip options, preserve non chip based options */
3068 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
3069 chip
->options
|= type
->options
& NAND_CHIPOPTIONS_MSK
;
3072 * Check if chip is not a Samsung device. Do not clear the
3073 * options for chips which do not have an extended id.
3075 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3076 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3080 * Set chip as a default. Board drivers can override it, if necessary.
3082 chip
->options
|= NAND_NO_AUTOINCR
;
3084 /* Try to identify manufacturer */
3085 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3086 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3091 * Check, if buswidth is correct. Hardware drivers should set
3094 if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3095 pr_info("NAND device: Manufacturer ID:"
3096 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
,
3097 *dev_id
, nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3098 pr_warn("NAND bus width %d instead %d bit\n",
3099 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3101 return ERR_PTR(-EINVAL
);
3104 /* Calculate the address shift from the page size */
3105 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3106 /* Convert chipsize to number of pages per chip -1 */
3107 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3109 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3110 ffs(mtd
->erasesize
) - 1;
3111 if (chip
->chipsize
& 0xffffffff)
3112 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3114 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3115 chip
->chip_shift
+= 32 - 1;
3118 chip
->badblockbits
= 8;
3120 /* Set the bad block position */
3121 if (mtd
->writesize
> 512 || (busw
& NAND_BUSWIDTH_16
))
3122 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3124 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3127 * Bad block marker is stored in the last page of each block
3128 * on Samsung and Hynix MLC devices; stored in first two pages
3129 * of each block on Micron devices with 2KiB pages and on
3130 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3131 * All others scan only the first page.
3133 if ((chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3134 (*maf_id
== NAND_MFR_SAMSUNG
||
3135 *maf_id
== NAND_MFR_HYNIX
))
3136 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3137 else if ((!(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3138 (*maf_id
== NAND_MFR_SAMSUNG
||
3139 *maf_id
== NAND_MFR_HYNIX
||
3140 *maf_id
== NAND_MFR_TOSHIBA
||
3141 *maf_id
== NAND_MFR_AMD
||
3142 *maf_id
== NAND_MFR_MACRONIX
)) ||
3143 (mtd
->writesize
== 2048 &&
3144 *maf_id
== NAND_MFR_MICRON
))
3145 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3147 /* Check for AND chips with 4 page planes */
3148 if (chip
->options
& NAND_4PAGE_ARRAY
)
3149 chip
->erase_cmd
= multi_erase_cmd
;
3151 chip
->erase_cmd
= single_erase_cmd
;
3153 /* Do not replace user supplied command function! */
3154 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3155 chip
->cmdfunc
= nand_command_lp
;
3157 pr_info("NAND device: Manufacturer ID:"
3158 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
, *dev_id
,
3159 nand_manuf_ids
[maf_idx
].name
,
3160 chip
->onfi_version
? chip
->onfi_params
.model
: type
->name
);
3166 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3167 * @mtd: MTD device structure
3168 * @maxchips: number of chips to scan for
3169 * @table: alternative NAND ID table
3171 * This is the first phase of the normal nand_scan() function. It reads the
3172 * flash ID and sets up MTD fields accordingly.
3174 * The mtd->owner field must be set to the module of the caller.
3176 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3177 struct nand_flash_dev
*table
)
3179 int i
, busw
, nand_maf_id
, nand_dev_id
;
3180 struct nand_chip
*chip
= mtd
->priv
;
3181 struct nand_flash_dev
*type
;
3183 /* Get buswidth to select the correct functions */
3184 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3185 /* Set the default functions */
3186 nand_set_defaults(chip
, busw
);
3188 /* Read the flash type */
3189 type
= nand_get_flash_type(mtd
, chip
, busw
,
3190 &nand_maf_id
, &nand_dev_id
, table
);
3193 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3194 pr_warn("No NAND device found\n");
3195 chip
->select_chip(mtd
, -1);
3196 return PTR_ERR(type
);
3199 /* Check for a chip array */
3200 for (i
= 1; i
< maxchips
; i
++) {
3201 chip
->select_chip(mtd
, i
);
3202 /* See comment in nand_get_flash_type for reset */
3203 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3204 /* Send the command for reading device ID */
3205 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3206 /* Read manufacturer and device IDs */
3207 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3208 nand_dev_id
!= chip
->read_byte(mtd
))
3212 pr_info("%d NAND chips detected\n", i
);
3214 /* Store the number of chips and calc total size for mtd */
3216 mtd
->size
= i
* chip
->chipsize
;
3220 EXPORT_SYMBOL(nand_scan_ident
);
3224 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3225 * @mtd: MTD device structure
3227 * This is the second phase of the normal nand_scan() function. It fills out
3228 * all the uninitialized function pointers with the defaults and scans for a
3229 * bad block table if appropriate.
3231 int nand_scan_tail(struct mtd_info
*mtd
)
3234 struct nand_chip
*chip
= mtd
->priv
;
3236 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3237 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
3238 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
3240 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3241 chip
->buffers
= kmalloc(sizeof(*chip
->buffers
), GFP_KERNEL
);
3245 /* Set the internal oob buffer location, just after the page data */
3246 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3249 * If no default placement scheme is given, select an appropriate one.
3251 if (!chip
->ecc
.layout
&& (chip
->ecc
.mode
!= NAND_ECC_SOFT_BCH
)) {
3252 switch (mtd
->oobsize
) {
3254 chip
->ecc
.layout
= &nand_oob_8
;
3257 chip
->ecc
.layout
= &nand_oob_16
;
3260 chip
->ecc
.layout
= &nand_oob_64
;
3263 chip
->ecc
.layout
= &nand_oob_128
;
3266 pr_warn("No oob scheme defined for oobsize %d\n",
3272 if (!chip
->write_page
)
3273 chip
->write_page
= nand_write_page
;
3276 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3277 * selected and we have 256 byte pagesize fallback to software ECC
3280 switch (chip
->ecc
.mode
) {
3281 case NAND_ECC_HW_OOB_FIRST
:
3282 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3283 if (!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3285 pr_warn("No ECC functions supplied; "
3286 "hardware ECC not possible\n");
3289 if (!chip
->ecc
.read_page
)
3290 chip
->ecc
.read_page
= nand_read_page_hwecc_oob_first
;
3293 /* Use standard hwecc read page function? */
3294 if (!chip
->ecc
.read_page
)
3295 chip
->ecc
.read_page
= nand_read_page_hwecc
;
3296 if (!chip
->ecc
.write_page
)
3297 chip
->ecc
.write_page
= nand_write_page_hwecc
;
3298 if (!chip
->ecc
.read_page_raw
)
3299 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3300 if (!chip
->ecc
.write_page_raw
)
3301 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3302 if (!chip
->ecc
.read_oob
)
3303 chip
->ecc
.read_oob
= nand_read_oob_std
;
3304 if (!chip
->ecc
.write_oob
)
3305 chip
->ecc
.write_oob
= nand_write_oob_std
;
3307 case NAND_ECC_HW_SYNDROME
:
3308 if ((!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3309 !chip
->ecc
.hwctl
) &&
3310 (!chip
->ecc
.read_page
||
3311 chip
->ecc
.read_page
== nand_read_page_hwecc
||
3312 !chip
->ecc
.write_page
||
3313 chip
->ecc
.write_page
== nand_write_page_hwecc
)) {
3314 pr_warn("No ECC functions supplied; "
3315 "hardware ECC not possible\n");
3318 /* Use standard syndrome read/write page function? */
3319 if (!chip
->ecc
.read_page
)
3320 chip
->ecc
.read_page
= nand_read_page_syndrome
;
3321 if (!chip
->ecc
.write_page
)
3322 chip
->ecc
.write_page
= nand_write_page_syndrome
;
3323 if (!chip
->ecc
.read_page_raw
)
3324 chip
->ecc
.read_page_raw
= nand_read_page_raw_syndrome
;
3325 if (!chip
->ecc
.write_page_raw
)
3326 chip
->ecc
.write_page_raw
= nand_write_page_raw_syndrome
;
3327 if (!chip
->ecc
.read_oob
)
3328 chip
->ecc
.read_oob
= nand_read_oob_syndrome
;
3329 if (!chip
->ecc
.write_oob
)
3330 chip
->ecc
.write_oob
= nand_write_oob_syndrome
;
3332 if (mtd
->writesize
>= chip
->ecc
.size
)
3334 pr_warn("%d byte HW ECC not possible on "
3335 "%d byte page size, fallback to SW ECC\n",
3336 chip
->ecc
.size
, mtd
->writesize
);
3337 chip
->ecc
.mode
= NAND_ECC_SOFT
;
3340 chip
->ecc
.calculate
= nand_calculate_ecc
;
3341 chip
->ecc
.correct
= nand_correct_data
;
3342 chip
->ecc
.read_page
= nand_read_page_swecc
;
3343 chip
->ecc
.read_subpage
= nand_read_subpage
;
3344 chip
->ecc
.write_page
= nand_write_page_swecc
;
3345 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3346 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3347 chip
->ecc
.read_oob
= nand_read_oob_std
;
3348 chip
->ecc
.write_oob
= nand_write_oob_std
;
3349 if (!chip
->ecc
.size
)
3350 chip
->ecc
.size
= 256;
3351 chip
->ecc
.bytes
= 3;
3352 chip
->ecc
.strength
= 1;
3355 case NAND_ECC_SOFT_BCH
:
3356 if (!mtd_nand_has_bch()) {
3357 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3360 chip
->ecc
.calculate
= nand_bch_calculate_ecc
;
3361 chip
->ecc
.correct
= nand_bch_correct_data
;
3362 chip
->ecc
.read_page
= nand_read_page_swecc
;
3363 chip
->ecc
.read_subpage
= nand_read_subpage
;
3364 chip
->ecc
.write_page
= nand_write_page_swecc
;
3365 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3366 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3367 chip
->ecc
.read_oob
= nand_read_oob_std
;
3368 chip
->ecc
.write_oob
= nand_write_oob_std
;
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
3372 * for details. Otherwise, default to 4 bits for large page
3375 if (!chip
->ecc
.size
&& (mtd
->oobsize
>= 64)) {
3376 chip
->ecc
.size
= 512;
3377 chip
->ecc
.bytes
= 7;
3379 chip
->ecc
.priv
= nand_bch_init(mtd
,
3383 if (!chip
->ecc
.priv
) {
3384 pr_warn("BCH ECC initialization failed!\n");
3387 chip
->ecc
.strength
=
3388 chip
->ecc
.bytes
*8 / fls(8*chip
->ecc
.size
);
3392 pr_warn("NAND_ECC_NONE selected by board driver. "
3393 "This is not recommended!\n");
3394 chip
->ecc
.read_page
= nand_read_page_raw
;
3395 chip
->ecc
.write_page
= nand_write_page_raw
;
3396 chip
->ecc
.read_oob
= nand_read_oob_std
;
3397 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3398 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3399 chip
->ecc
.write_oob
= nand_write_oob_std
;
3400 chip
->ecc
.size
= mtd
->writesize
;
3401 chip
->ecc
.bytes
= 0;
3402 chip
->ecc
.strength
= 0;
3406 pr_warn("Invalid NAND_ECC_MODE %d\n", chip
->ecc
.mode
);
3410 /* For many systems, the standard OOB write also works for raw */
3411 if (!chip
->ecc
.read_oob_raw
)
3412 chip
->ecc
.read_oob_raw
= chip
->ecc
.read_oob
;
3413 if (!chip
->ecc
.write_oob_raw
)
3414 chip
->ecc
.write_oob_raw
= chip
->ecc
.write_oob
;
3417 * The number of bytes available for a client to place data into
3418 * the out of band area.
3420 chip
->ecc
.layout
->oobavail
= 0;
3421 for (i
= 0; chip
->ecc
.layout
->oobfree
[i
].length
3422 && i
< ARRAY_SIZE(chip
->ecc
.layout
->oobfree
); i
++)
3423 chip
->ecc
.layout
->oobavail
+=
3424 chip
->ecc
.layout
->oobfree
[i
].length
;
3425 mtd
->oobavail
= chip
->ecc
.layout
->oobavail
;
3428 * Set the number of read / write steps for one page depending on ECC
3431 chip
->ecc
.steps
= mtd
->writesize
/ chip
->ecc
.size
;
3432 if (chip
->ecc
.steps
* chip
->ecc
.size
!= mtd
->writesize
) {
3433 pr_warn("Invalid ECC parameters\n");
3436 chip
->ecc
.total
= chip
->ecc
.steps
* chip
->ecc
.bytes
;
3438 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3439 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
3440 !(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3441 switch (chip
->ecc
.steps
) {
3443 mtd
->subpage_sft
= 1;
3448 mtd
->subpage_sft
= 2;
3452 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3454 /* Initialize state */
3455 chip
->state
= FL_READY
;
3457 /* De-select the device */
3458 chip
->select_chip(mtd
, -1);
3460 /* Invalidate the pagebuffer reference */
3463 /* Fill in remaining MTD driver data */
3464 mtd
->type
= MTD_NANDFLASH
;
3465 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3467 mtd
->_erase
= nand_erase
;
3469 mtd
->_unpoint
= NULL
;
3470 mtd
->_read
= nand_read
;
3471 mtd
->_write
= nand_write
;
3472 mtd
->_panic_write
= panic_nand_write
;
3473 mtd
->_read_oob
= nand_read_oob
;
3474 mtd
->_write_oob
= nand_write_oob
;
3475 mtd
->_sync
= nand_sync
;
3477 mtd
->_unlock
= NULL
;
3478 mtd
->_suspend
= nand_suspend
;
3479 mtd
->_resume
= nand_resume
;
3480 mtd
->_block_isbad
= nand_block_isbad
;
3481 mtd
->_block_markbad
= nand_block_markbad
;
3482 mtd
->writebufsize
= mtd
->writesize
;
3484 /* propagate ecc info to mtd_info */
3485 mtd
->ecclayout
= chip
->ecc
.layout
;
3486 mtd
->ecc_strength
= chip
->ecc
.strength
* chip
->ecc
.steps
;
3488 /* Check, if we should skip the bad block table scan */
3489 if (chip
->options
& NAND_SKIP_BBTSCAN
)
3492 /* Build bad block table */
3493 return chip
->scan_bbt(mtd
);
3495 EXPORT_SYMBOL(nand_scan_tail
);
3498 * is_module_text_address() isn't exported, and it's mostly a pointless
3499 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3500 * to call us from in-kernel code if the core NAND support is modular.
3503 #define caller_is_module() (1)
3505 #define caller_is_module() \
3506 is_module_text_address((unsigned long)__builtin_return_address(0))
3510 * nand_scan - [NAND Interface] Scan for the NAND device
3511 * @mtd: MTD device structure
3512 * @maxchips: number of chips to scan for
3514 * This fills out all the uninitialized function pointers with the defaults.
3515 * The flash ID is read and the mtd/chip structures are filled with the
3516 * appropriate values. The mtd->owner field must be set to the module of the
3519 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
3523 /* Many callers got this wrong, so check for it for a while... */
3524 if (!mtd
->owner
&& caller_is_module()) {
3525 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
3529 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
3531 ret
= nand_scan_tail(mtd
);
3534 EXPORT_SYMBOL(nand_scan
);
3537 * nand_release - [NAND Interface] Free resources held by the NAND device
3538 * @mtd: MTD device structure
3540 void nand_release(struct mtd_info
*mtd
)
3542 struct nand_chip
*chip
= mtd
->priv
;
3544 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
3545 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
3547 mtd_device_unregister(mtd
);
3549 /* Free bad block table memory */
3551 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3552 kfree(chip
->buffers
);
3554 /* Free bad block descriptor memory */
3555 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
3556 & NAND_BBT_DYNAMICSTRUCT
)
3557 kfree(chip
->badblock_pattern
);
3559 EXPORT_SYMBOL_GPL(nand_release
);
3561 static int __init
nand_base_init(void)
3563 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
3567 static void __exit
nand_base_exit(void)
3569 led_trigger_unregister_simple(nand_led_trigger
);
3572 module_init(nand_base_init
);
3573 module_exit(nand_base_exit
);
3575 MODULE_LICENSE("GPL");
3576 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3577 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3578 MODULE_DESCRIPTION("Generic NAND flash driver code");