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mtd: nand: refactor chip->block_markbad interface
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 *
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
10 *
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 *
14 * Credits:
15 * David Woodhouse for adding multichip support
16 *
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
20 * TODO:
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #include <linux/interrupt.h>
44 #include <linux/bitops.h>
45 #include <linux/leds.h>
46 #include <linux/io.h>
47 #include <linux/mtd/partitions.h>
48
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
57 .length = 2} }
58 };
59
60 static struct nand_ecclayout nand_oob_16 = {
61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
63 .oobfree = {
64 {.offset = 8,
65 . length = 8} }
66 };
67
68 static struct nand_ecclayout nand_oob_64 = {
69 .eccbytes = 24,
70 .eccpos = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
74 .oobfree = {
75 {.offset = 2,
76 .length = 38} }
77 };
78
79 static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
90 .length = 78} }
91 };
92
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
94
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
98 /*
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
101 */
102 DEFINE_LED_TRIGGER(nand_led_trigger);
103
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106 {
107 struct nand_chip *chip = mtd->priv;
108 int ret = 0;
109
110 /* Start address must align on block boundary */
111 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
117 if (len & ((1 << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
119 ret = -EINVAL;
120 }
121
122 return ret;
123 }
124
125 /**
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
128 *
129 * Release chip lock and wake up anyone waiting on the device.
130 */
131 static void nand_release_device(struct mtd_info *mtd)
132 {
133 struct nand_chip *chip = mtd->priv;
134
135 /* Release the controller and the chip */
136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
141 }
142
143 /**
144 * nand_read_byte - [DEFAULT] read one byte from the chip
145 * @mtd: MTD device structure
146 *
147 * Default read function for 8bit buswidth
148 */
149 static uint8_t nand_read_byte(struct mtd_info *mtd)
150 {
151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
153 }
154
155 /**
156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
158 * @mtd: MTD device structure
159 *
160 * Default read function for 16bit buswidth with endianness conversion.
161 *
162 */
163 static uint8_t nand_read_byte16(struct mtd_info *mtd)
164 {
165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
167 }
168
169 /**
170 * nand_read_word - [DEFAULT] read one word from the chip
171 * @mtd: MTD device structure
172 *
173 * Default read function for 16bit buswidth without endianness conversion.
174 */
175 static u16 nand_read_word(struct mtd_info *mtd)
176 {
177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
179 }
180
181 /**
182 * nand_select_chip - [DEFAULT] control CE line
183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
185 *
186 * Default select function for 1 chip devices.
187 */
188 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
189 {
190 struct nand_chip *chip = mtd->priv;
191
192 switch (chipnr) {
193 case -1:
194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
195 break;
196 case 0:
197 break;
198
199 default:
200 BUG();
201 }
202 }
203
204 /**
205 * nand_write_buf - [DEFAULT] write buffer to chip
206 * @mtd: MTD device structure
207 * @buf: data buffer
208 * @len: number of bytes to write
209 *
210 * Default write function for 8bit buswidth.
211 */
212 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
213 {
214 struct nand_chip *chip = mtd->priv;
215
216 iowrite8_rep(chip->IO_ADDR_W, buf, len);
217 }
218
219 /**
220 * nand_read_buf - [DEFAULT] read chip data into buffer
221 * @mtd: MTD device structure
222 * @buf: buffer to store date
223 * @len: number of bytes to read
224 *
225 * Default read function for 8bit buswidth.
226 */
227 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
228 {
229 struct nand_chip *chip = mtd->priv;
230
231 ioread8_rep(chip->IO_ADDR_R, buf, len);
232 }
233
234 /**
235 * nand_write_buf16 - [DEFAULT] write buffer to chip
236 * @mtd: MTD device structure
237 * @buf: data buffer
238 * @len: number of bytes to write
239 *
240 * Default write function for 16bit buswidth.
241 */
242 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
243 {
244 struct nand_chip *chip = mtd->priv;
245 u16 *p = (u16 *) buf;
246
247 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
248 }
249
250 /**
251 * nand_read_buf16 - [DEFAULT] read chip data into buffer
252 * @mtd: MTD device structure
253 * @buf: buffer to store date
254 * @len: number of bytes to read
255 *
256 * Default read function for 16bit buswidth.
257 */
258 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
259 {
260 struct nand_chip *chip = mtd->priv;
261 u16 *p = (u16 *) buf;
262
263 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
264 }
265
266 /**
267 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
268 * @mtd: MTD device structure
269 * @ofs: offset from device start
270 * @getchip: 0, if the chip is already selected
271 *
272 * Check, if the block is bad.
273 */
274 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
275 {
276 int page, chipnr, res = 0, i = 0;
277 struct nand_chip *chip = mtd->priv;
278 u16 bad;
279
280 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
281 ofs += mtd->erasesize - mtd->writesize;
282
283 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
284
285 if (getchip) {
286 chipnr = (int)(ofs >> chip->chip_shift);
287
288 nand_get_device(mtd, FL_READING);
289
290 /* Select the NAND device */
291 chip->select_chip(mtd, chipnr);
292 }
293
294 do {
295 if (chip->options & NAND_BUSWIDTH_16) {
296 chip->cmdfunc(mtd, NAND_CMD_READOOB,
297 chip->badblockpos & 0xFE, page);
298 bad = cpu_to_le16(chip->read_word(mtd));
299 if (chip->badblockpos & 0x1)
300 bad >>= 8;
301 else
302 bad &= 0xFF;
303 } else {
304 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
305 page);
306 bad = chip->read_byte(mtd);
307 }
308
309 if (likely(chip->badblockbits == 8))
310 res = bad != 0xFF;
311 else
312 res = hweight8(bad) < chip->badblockbits;
313 ofs += mtd->writesize;
314 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
315 i++;
316 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
317
318 if (getchip) {
319 chip->select_chip(mtd, -1);
320 nand_release_device(mtd);
321 }
322
323 return res;
324 }
325
326 /**
327 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
328 * @mtd: MTD device structure
329 * @ofs: offset from device start
330 *
331 * This is the default implementation, which can be overridden by a hardware
332 * specific driver. It provides the details for writing a bad block marker to a
333 * block.
334 */
335 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
336 {
337 struct nand_chip *chip = mtd->priv;
338 struct mtd_oob_ops ops;
339 uint8_t buf[2] = { 0, 0 };
340 int ret = 0, res, i = 0;
341
342 ops.datbuf = NULL;
343 ops.oobbuf = buf;
344 ops.ooboffs = chip->badblockpos;
345 if (chip->options & NAND_BUSWIDTH_16) {
346 ops.ooboffs &= ~0x01;
347 ops.len = ops.ooblen = 2;
348 } else {
349 ops.len = ops.ooblen = 1;
350 }
351 ops.mode = MTD_OPS_PLACE_OOB;
352
353 /* Write to first/last page(s) if necessary */
354 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
355 ofs += mtd->erasesize - mtd->writesize;
356 do {
357 res = nand_do_write_oob(mtd, ofs, &ops);
358 if (!ret)
359 ret = res;
360
361 i++;
362 ofs += mtd->writesize;
363 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
364
365 return ret;
366 }
367
368 /**
369 * nand_block_markbad_lowlevel - mark a block bad
370 * @mtd: MTD device structure
371 * @ofs: offset from device start
372 *
373 * This function performs the generic NAND bad block marking steps (i.e., bad
374 * block table(s) and/or marker(s)). We only allow the hardware driver to
375 * specify how to write bad block markers to OOB (chip->block_markbad).
376 *
377 * We try operations in the following order, according to our bbt_options
378 * (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
379 * (1) erase the affected block, to allow OOB marker to be written cleanly
380 * (2) update in-memory BBT
381 * (3) write bad block marker to OOB area of affected block
382 * (4) update flash-based BBT
383 * Note that we retain the first error encountered in (3) or (4), finish the
384 * procedures, and dump the error in the end.
385 */
386 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
387 {
388 struct nand_chip *chip = mtd->priv;
389 int block, res, ret = 0;
390 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
391
392 if (write_oob) {
393 struct erase_info einfo;
394
395 /* Attempt erase before marking OOB */
396 memset(&einfo, 0, sizeof(einfo));
397 einfo.mtd = mtd;
398 einfo.addr = ofs;
399 einfo.len = 1 << chip->phys_erase_shift;
400 nand_erase_nand(mtd, &einfo, 0);
401 }
402
403 /* Get block number */
404 block = (int)(ofs >> chip->bbt_erase_shift);
405 /* Mark block bad in memory-based BBT */
406 if (chip->bbt)
407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
408
409 /* Write bad block marker to OOB */
410 if (write_oob) {
411 nand_get_device(mtd, FL_WRITING);
412 ret = chip->block_markbad(mtd, ofs);
413 nand_release_device(mtd);
414 }
415
416 /* Update flash-based bad block table */
417 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
418 res = nand_update_bbt(mtd, ofs);
419 if (!ret)
420 ret = res;
421 }
422
423 if (!ret)
424 mtd->ecc_stats.badblocks++;
425
426 return ret;
427 }
428
429 /**
430 * nand_check_wp - [GENERIC] check if the chip is write protected
431 * @mtd: MTD device structure
432 *
433 * Check, if the device is write protected. The function expects, that the
434 * device is already selected.
435 */
436 static int nand_check_wp(struct mtd_info *mtd)
437 {
438 struct nand_chip *chip = mtd->priv;
439
440 /* Broken xD cards report WP despite being writable */
441 if (chip->options & NAND_BROKEN_XD)
442 return 0;
443
444 /* Check the WP bit */
445 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
446 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
447 }
448
449 /**
450 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
451 * @mtd: MTD device structure
452 * @ofs: offset from device start
453 * @getchip: 0, if the chip is already selected
454 * @allowbbt: 1, if its allowed to access the bbt area
455 *
456 * Check, if the block is bad. Either by reading the bad block table or
457 * calling of the scan function.
458 */
459 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
460 int allowbbt)
461 {
462 struct nand_chip *chip = mtd->priv;
463
464 if (!chip->bbt)
465 return chip->block_bad(mtd, ofs, getchip);
466
467 /* Return info from the table */
468 return nand_isbad_bbt(mtd, ofs, allowbbt);
469 }
470
471 /**
472 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
473 * @mtd: MTD device structure
474 * @timeo: Timeout
475 *
476 * Helper function for nand_wait_ready used when needing to wait in interrupt
477 * context.
478 */
479 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
480 {
481 struct nand_chip *chip = mtd->priv;
482 int i;
483
484 /* Wait for the device to get ready */
485 for (i = 0; i < timeo; i++) {
486 if (chip->dev_ready(mtd))
487 break;
488 touch_softlockup_watchdog();
489 mdelay(1);
490 }
491 }
492
493 /* Wait for the ready pin, after a command. The timeout is caught later. */
494 void nand_wait_ready(struct mtd_info *mtd)
495 {
496 struct nand_chip *chip = mtd->priv;
497 unsigned long timeo = jiffies + msecs_to_jiffies(20);
498
499 /* 400ms timeout */
500 if (in_interrupt() || oops_in_progress)
501 return panic_nand_wait_ready(mtd, 400);
502
503 led_trigger_event(nand_led_trigger, LED_FULL);
504 /* Wait until command is processed or timeout occurs */
505 do {
506 if (chip->dev_ready(mtd))
507 break;
508 touch_softlockup_watchdog();
509 } while (time_before(jiffies, timeo));
510 led_trigger_event(nand_led_trigger, LED_OFF);
511 }
512 EXPORT_SYMBOL_GPL(nand_wait_ready);
513
514 /**
515 * nand_command - [DEFAULT] Send command to NAND device
516 * @mtd: MTD device structure
517 * @command: the command to be sent
518 * @column: the column address for this command, -1 if none
519 * @page_addr: the page address for this command, -1 if none
520 *
521 * Send command to NAND device. This function is used for small page devices
522 * (512 Bytes per page).
523 */
524 static void nand_command(struct mtd_info *mtd, unsigned int command,
525 int column, int page_addr)
526 {
527 register struct nand_chip *chip = mtd->priv;
528 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
529
530 /* Write out the command to the device */
531 if (command == NAND_CMD_SEQIN) {
532 int readcmd;
533
534 if (column >= mtd->writesize) {
535 /* OOB area */
536 column -= mtd->writesize;
537 readcmd = NAND_CMD_READOOB;
538 } else if (column < 256) {
539 /* First 256 bytes --> READ0 */
540 readcmd = NAND_CMD_READ0;
541 } else {
542 column -= 256;
543 readcmd = NAND_CMD_READ1;
544 }
545 chip->cmd_ctrl(mtd, readcmd, ctrl);
546 ctrl &= ~NAND_CTRL_CHANGE;
547 }
548 chip->cmd_ctrl(mtd, command, ctrl);
549
550 /* Address cycle, when necessary */
551 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
552 /* Serially input address */
553 if (column != -1) {
554 /* Adjust columns for 16 bit buswidth */
555 if (chip->options & NAND_BUSWIDTH_16)
556 column >>= 1;
557 chip->cmd_ctrl(mtd, column, ctrl);
558 ctrl &= ~NAND_CTRL_CHANGE;
559 }
560 if (page_addr != -1) {
561 chip->cmd_ctrl(mtd, page_addr, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
563 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
564 /* One more address cycle for devices > 32MiB */
565 if (chip->chipsize > (32 << 20))
566 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
567 }
568 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
569
570 /*
571 * Program and erase have their own busy handlers status and sequential
572 * in needs no delay
573 */
574 switch (command) {
575
576 case NAND_CMD_PAGEPROG:
577 case NAND_CMD_ERASE1:
578 case NAND_CMD_ERASE2:
579 case NAND_CMD_SEQIN:
580 case NAND_CMD_STATUS:
581 return;
582
583 case NAND_CMD_RESET:
584 if (chip->dev_ready)
585 break;
586 udelay(chip->chip_delay);
587 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
588 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
589 chip->cmd_ctrl(mtd,
590 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
591 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
592 ;
593 return;
594
595 /* This applies to read commands */
596 default:
597 /*
598 * If we don't have access to the busy pin, we apply the given
599 * command delay
600 */
601 if (!chip->dev_ready) {
602 udelay(chip->chip_delay);
603 return;
604 }
605 }
606 /*
607 * Apply this short delay always to ensure that we do wait tWB in
608 * any case on any machine.
609 */
610 ndelay(100);
611
612 nand_wait_ready(mtd);
613 }
614
615 /**
616 * nand_command_lp - [DEFAULT] Send command to NAND large page device
617 * @mtd: MTD device structure
618 * @command: the command to be sent
619 * @column: the column address for this command, -1 if none
620 * @page_addr: the page address for this command, -1 if none
621 *
622 * Send command to NAND device. This is the version for the new large page
623 * devices. We don't have the separate regions as we have in the small page
624 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
625 */
626 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
627 int column, int page_addr)
628 {
629 register struct nand_chip *chip = mtd->priv;
630
631 /* Emulate NAND_CMD_READOOB */
632 if (command == NAND_CMD_READOOB) {
633 column += mtd->writesize;
634 command = NAND_CMD_READ0;
635 }
636
637 /* Command latch cycle */
638 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
639
640 if (column != -1 || page_addr != -1) {
641 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
642
643 /* Serially input address */
644 if (column != -1) {
645 /* Adjust columns for 16 bit buswidth */
646 if (chip->options & NAND_BUSWIDTH_16)
647 column >>= 1;
648 chip->cmd_ctrl(mtd, column, ctrl);
649 ctrl &= ~NAND_CTRL_CHANGE;
650 chip->cmd_ctrl(mtd, column >> 8, ctrl);
651 }
652 if (page_addr != -1) {
653 chip->cmd_ctrl(mtd, page_addr, ctrl);
654 chip->cmd_ctrl(mtd, page_addr >> 8,
655 NAND_NCE | NAND_ALE);
656 /* One more address cycle for devices > 128MiB */
657 if (chip->chipsize > (128 << 20))
658 chip->cmd_ctrl(mtd, page_addr >> 16,
659 NAND_NCE | NAND_ALE);
660 }
661 }
662 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
663
664 /*
665 * Program and erase have their own busy handlers status, sequential
666 * in, and deplete1 need no delay.
667 */
668 switch (command) {
669
670 case NAND_CMD_CACHEDPROG:
671 case NAND_CMD_PAGEPROG:
672 case NAND_CMD_ERASE1:
673 case NAND_CMD_ERASE2:
674 case NAND_CMD_SEQIN:
675 case NAND_CMD_RNDIN:
676 case NAND_CMD_STATUS:
677 return;
678
679 case NAND_CMD_RESET:
680 if (chip->dev_ready)
681 break;
682 udelay(chip->chip_delay);
683 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
684 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
685 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
686 NAND_NCE | NAND_CTRL_CHANGE);
687 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
688 ;
689 return;
690
691 case NAND_CMD_RNDOUT:
692 /* No ready / busy check necessary */
693 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
694 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
696 NAND_NCE | NAND_CTRL_CHANGE);
697 return;
698
699 case NAND_CMD_READ0:
700 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
701 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
703 NAND_NCE | NAND_CTRL_CHANGE);
704
705 /* This applies to read commands */
706 default:
707 /*
708 * If we don't have access to the busy pin, we apply the given
709 * command delay.
710 */
711 if (!chip->dev_ready) {
712 udelay(chip->chip_delay);
713 return;
714 }
715 }
716
717 /*
718 * Apply this short delay always to ensure that we do wait tWB in
719 * any case on any machine.
720 */
721 ndelay(100);
722
723 nand_wait_ready(mtd);
724 }
725
726 /**
727 * panic_nand_get_device - [GENERIC] Get chip for selected access
728 * @chip: the nand chip descriptor
729 * @mtd: MTD device structure
730 * @new_state: the state which is requested
731 *
732 * Used when in panic, no locks are taken.
733 */
734 static void panic_nand_get_device(struct nand_chip *chip,
735 struct mtd_info *mtd, int new_state)
736 {
737 /* Hardware controller shared among independent devices */
738 chip->controller->active = chip;
739 chip->state = new_state;
740 }
741
742 /**
743 * nand_get_device - [GENERIC] Get chip for selected access
744 * @mtd: MTD device structure
745 * @new_state: the state which is requested
746 *
747 * Get the device and lock it for exclusive access
748 */
749 static int
750 nand_get_device(struct mtd_info *mtd, int new_state)
751 {
752 struct nand_chip *chip = mtd->priv;
753 spinlock_t *lock = &chip->controller->lock;
754 wait_queue_head_t *wq = &chip->controller->wq;
755 DECLARE_WAITQUEUE(wait, current);
756 retry:
757 spin_lock(lock);
758
759 /* Hardware controller shared among independent devices */
760 if (!chip->controller->active)
761 chip->controller->active = chip;
762
763 if (chip->controller->active == chip && chip->state == FL_READY) {
764 chip->state = new_state;
765 spin_unlock(lock);
766 return 0;
767 }
768 if (new_state == FL_PM_SUSPENDED) {
769 if (chip->controller->active->state == FL_PM_SUSPENDED) {
770 chip->state = FL_PM_SUSPENDED;
771 spin_unlock(lock);
772 return 0;
773 }
774 }
775 set_current_state(TASK_UNINTERRUPTIBLE);
776 add_wait_queue(wq, &wait);
777 spin_unlock(lock);
778 schedule();
779 remove_wait_queue(wq, &wait);
780 goto retry;
781 }
782
783 /**
784 * panic_nand_wait - [GENERIC] wait until the command is done
785 * @mtd: MTD device structure
786 * @chip: NAND chip structure
787 * @timeo: timeout
788 *
789 * Wait for command done. This is a helper function for nand_wait used when
790 * we are in interrupt context. May happen when in panic and trying to write
791 * an oops through mtdoops.
792 */
793 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
794 unsigned long timeo)
795 {
796 int i;
797 for (i = 0; i < timeo; i++) {
798 if (chip->dev_ready) {
799 if (chip->dev_ready(mtd))
800 break;
801 } else {
802 if (chip->read_byte(mtd) & NAND_STATUS_READY)
803 break;
804 }
805 mdelay(1);
806 }
807 }
808
809 /**
810 * nand_wait - [DEFAULT] wait until the command is done
811 * @mtd: MTD device structure
812 * @chip: NAND chip structure
813 *
814 * Wait for command done. This applies to erase and program only. Erase can
815 * take up to 400ms and program up to 20ms according to general NAND and
816 * SmartMedia specs.
817 */
818 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
819 {
820
821 int status, state = chip->state;
822 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
823
824 led_trigger_event(nand_led_trigger, LED_FULL);
825
826 /*
827 * Apply this short delay always to ensure that we do wait tWB in any
828 * case on any machine.
829 */
830 ndelay(100);
831
832 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
833
834 if (in_interrupt() || oops_in_progress)
835 panic_nand_wait(mtd, chip, timeo);
836 else {
837 timeo = jiffies + msecs_to_jiffies(timeo);
838 while (time_before(jiffies, timeo)) {
839 if (chip->dev_ready) {
840 if (chip->dev_ready(mtd))
841 break;
842 } else {
843 if (chip->read_byte(mtd) & NAND_STATUS_READY)
844 break;
845 }
846 cond_resched();
847 }
848 }
849 led_trigger_event(nand_led_trigger, LED_OFF);
850
851 status = (int)chip->read_byte(mtd);
852 /* This can happen if in case of timeout or buggy dev_ready */
853 WARN_ON(!(status & NAND_STATUS_READY));
854 return status;
855 }
856
857 /**
858 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
859 * @mtd: mtd info
860 * @ofs: offset to start unlock from
861 * @len: length to unlock
862 * @invert: when = 0, unlock the range of blocks within the lower and
863 * upper boundary address
864 * when = 1, unlock the range of blocks outside the boundaries
865 * of the lower and upper boundary address
866 *
867 * Returs unlock status.
868 */
869 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
870 uint64_t len, int invert)
871 {
872 int ret = 0;
873 int status, page;
874 struct nand_chip *chip = mtd->priv;
875
876 /* Submit address of first page to unlock */
877 page = ofs >> chip->page_shift;
878 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
879
880 /* Submit address of last page to unlock */
881 page = (ofs + len) >> chip->page_shift;
882 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
883 (page | invert) & chip->pagemask);
884
885 /* Call wait ready function */
886 status = chip->waitfunc(mtd, chip);
887 /* See if device thinks it succeeded */
888 if (status & NAND_STATUS_FAIL) {
889 pr_debug("%s: error status = 0x%08x\n",
890 __func__, status);
891 ret = -EIO;
892 }
893
894 return ret;
895 }
896
897 /**
898 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
899 * @mtd: mtd info
900 * @ofs: offset to start unlock from
901 * @len: length to unlock
902 *
903 * Returns unlock status.
904 */
905 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
906 {
907 int ret = 0;
908 int chipnr;
909 struct nand_chip *chip = mtd->priv;
910
911 pr_debug("%s: start = 0x%012llx, len = %llu\n",
912 __func__, (unsigned long long)ofs, len);
913
914 if (check_offs_len(mtd, ofs, len))
915 ret = -EINVAL;
916
917 /* Align to last block address if size addresses end of the device */
918 if (ofs + len == mtd->size)
919 len -= mtd->erasesize;
920
921 nand_get_device(mtd, FL_UNLOCKING);
922
923 /* Shift to get chip number */
924 chipnr = ofs >> chip->chip_shift;
925
926 chip->select_chip(mtd, chipnr);
927
928 /* Check, if it is write protected */
929 if (nand_check_wp(mtd)) {
930 pr_debug("%s: device is write protected!\n",
931 __func__);
932 ret = -EIO;
933 goto out;
934 }
935
936 ret = __nand_unlock(mtd, ofs, len, 0);
937
938 out:
939 chip->select_chip(mtd, -1);
940 nand_release_device(mtd);
941
942 return ret;
943 }
944 EXPORT_SYMBOL(nand_unlock);
945
946 /**
947 * nand_lock - [REPLACEABLE] locks all blocks present in the device
948 * @mtd: mtd info
949 * @ofs: offset to start unlock from
950 * @len: length to unlock
951 *
952 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
953 * have this feature, but it allows only to lock all blocks, not for specified
954 * range for block. Implementing 'lock' feature by making use of 'unlock', for
955 * now.
956 *
957 * Returns lock status.
958 */
959 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
960 {
961 int ret = 0;
962 int chipnr, status, page;
963 struct nand_chip *chip = mtd->priv;
964
965 pr_debug("%s: start = 0x%012llx, len = %llu\n",
966 __func__, (unsigned long long)ofs, len);
967
968 if (check_offs_len(mtd, ofs, len))
969 ret = -EINVAL;
970
971 nand_get_device(mtd, FL_LOCKING);
972
973 /* Shift to get chip number */
974 chipnr = ofs >> chip->chip_shift;
975
976 chip->select_chip(mtd, chipnr);
977
978 /* Check, if it is write protected */
979 if (nand_check_wp(mtd)) {
980 pr_debug("%s: device is write protected!\n",
981 __func__);
982 status = MTD_ERASE_FAILED;
983 ret = -EIO;
984 goto out;
985 }
986
987 /* Submit address of first page to lock */
988 page = ofs >> chip->page_shift;
989 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
990
991 /* Call wait ready function */
992 status = chip->waitfunc(mtd, chip);
993 /* See if device thinks it succeeded */
994 if (status & NAND_STATUS_FAIL) {
995 pr_debug("%s: error status = 0x%08x\n",
996 __func__, status);
997 ret = -EIO;
998 goto out;
999 }
1000
1001 ret = __nand_unlock(mtd, ofs, len, 0x1);
1002
1003 out:
1004 chip->select_chip(mtd, -1);
1005 nand_release_device(mtd);
1006
1007 return ret;
1008 }
1009 EXPORT_SYMBOL(nand_lock);
1010
1011 /**
1012 * nand_read_page_raw - [INTERN] read raw page data without ecc
1013 * @mtd: mtd info structure
1014 * @chip: nand chip info structure
1015 * @buf: buffer to store read data
1016 * @oob_required: caller requires OOB data read to chip->oob_poi
1017 * @page: page number to read
1018 *
1019 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1020 */
1021 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1022 uint8_t *buf, int oob_required, int page)
1023 {
1024 chip->read_buf(mtd, buf, mtd->writesize);
1025 if (oob_required)
1026 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1027 return 0;
1028 }
1029
1030 /**
1031 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1032 * @mtd: mtd info structure
1033 * @chip: nand chip info structure
1034 * @buf: buffer to store read data
1035 * @oob_required: caller requires OOB data read to chip->oob_poi
1036 * @page: page number to read
1037 *
1038 * We need a special oob layout and handling even when OOB isn't used.
1039 */
1040 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1041 struct nand_chip *chip, uint8_t *buf,
1042 int oob_required, int page)
1043 {
1044 int eccsize = chip->ecc.size;
1045 int eccbytes = chip->ecc.bytes;
1046 uint8_t *oob = chip->oob_poi;
1047 int steps, size;
1048
1049 for (steps = chip->ecc.steps; steps > 0; steps--) {
1050 chip->read_buf(mtd, buf, eccsize);
1051 buf += eccsize;
1052
1053 if (chip->ecc.prepad) {
1054 chip->read_buf(mtd, oob, chip->ecc.prepad);
1055 oob += chip->ecc.prepad;
1056 }
1057
1058 chip->read_buf(mtd, oob, eccbytes);
1059 oob += eccbytes;
1060
1061 if (chip->ecc.postpad) {
1062 chip->read_buf(mtd, oob, chip->ecc.postpad);
1063 oob += chip->ecc.postpad;
1064 }
1065 }
1066
1067 size = mtd->oobsize - (oob - chip->oob_poi);
1068 if (size)
1069 chip->read_buf(mtd, oob, size);
1070
1071 return 0;
1072 }
1073
1074 /**
1075 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1076 * @mtd: mtd info structure
1077 * @chip: nand chip info structure
1078 * @buf: buffer to store read data
1079 * @oob_required: caller requires OOB data read to chip->oob_poi
1080 * @page: page number to read
1081 */
1082 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1083 uint8_t *buf, int oob_required, int page)
1084 {
1085 int i, eccsize = chip->ecc.size;
1086 int eccbytes = chip->ecc.bytes;
1087 int eccsteps = chip->ecc.steps;
1088 uint8_t *p = buf;
1089 uint8_t *ecc_calc = chip->buffers->ecccalc;
1090 uint8_t *ecc_code = chip->buffers->ecccode;
1091 uint32_t *eccpos = chip->ecc.layout->eccpos;
1092 unsigned int max_bitflips = 0;
1093
1094 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1095
1096 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1097 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1098
1099 for (i = 0; i < chip->ecc.total; i++)
1100 ecc_code[i] = chip->oob_poi[eccpos[i]];
1101
1102 eccsteps = chip->ecc.steps;
1103 p = buf;
1104
1105 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1106 int stat;
1107
1108 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1109 if (stat < 0) {
1110 mtd->ecc_stats.failed++;
1111 } else {
1112 mtd->ecc_stats.corrected += stat;
1113 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1114 }
1115 }
1116 return max_bitflips;
1117 }
1118
1119 /**
1120 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1121 * @mtd: mtd info structure
1122 * @chip: nand chip info structure
1123 * @data_offs: offset of requested data within the page
1124 * @readlen: data length
1125 * @bufpoi: buffer to store read data
1126 */
1127 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1128 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1129 {
1130 int start_step, end_step, num_steps;
1131 uint32_t *eccpos = chip->ecc.layout->eccpos;
1132 uint8_t *p;
1133 int data_col_addr, i, gaps = 0;
1134 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1135 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1136 int index = 0;
1137 unsigned int max_bitflips = 0;
1138
1139 /* Column address within the page aligned to ECC size (256bytes) */
1140 start_step = data_offs / chip->ecc.size;
1141 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1142 num_steps = end_step - start_step + 1;
1143
1144 /* Data size aligned to ECC ecc.size */
1145 datafrag_len = num_steps * chip->ecc.size;
1146 eccfrag_len = num_steps * chip->ecc.bytes;
1147
1148 data_col_addr = start_step * chip->ecc.size;
1149 /* If we read not a page aligned data */
1150 if (data_col_addr != 0)
1151 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1152
1153 p = bufpoi + data_col_addr;
1154 chip->read_buf(mtd, p, datafrag_len);
1155
1156 /* Calculate ECC */
1157 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1158 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1159
1160 /*
1161 * The performance is faster if we position offsets according to
1162 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1163 */
1164 for (i = 0; i < eccfrag_len - 1; i++) {
1165 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1166 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1167 gaps = 1;
1168 break;
1169 }
1170 }
1171 if (gaps) {
1172 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1173 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1174 } else {
1175 /*
1176 * Send the command to read the particular ECC bytes take care
1177 * about buswidth alignment in read_buf.
1178 */
1179 index = start_step * chip->ecc.bytes;
1180
1181 aligned_pos = eccpos[index] & ~(busw - 1);
1182 aligned_len = eccfrag_len;
1183 if (eccpos[index] & (busw - 1))
1184 aligned_len++;
1185 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1186 aligned_len++;
1187
1188 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1189 mtd->writesize + aligned_pos, -1);
1190 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1191 }
1192
1193 for (i = 0; i < eccfrag_len; i++)
1194 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1195
1196 p = bufpoi + data_col_addr;
1197 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1198 int stat;
1199
1200 stat = chip->ecc.correct(mtd, p,
1201 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1202 if (stat < 0) {
1203 mtd->ecc_stats.failed++;
1204 } else {
1205 mtd->ecc_stats.corrected += stat;
1206 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1207 }
1208 }
1209 return max_bitflips;
1210 }
1211
1212 /**
1213 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1214 * @mtd: mtd info structure
1215 * @chip: nand chip info structure
1216 * @buf: buffer to store read data
1217 * @oob_required: caller requires OOB data read to chip->oob_poi
1218 * @page: page number to read
1219 *
1220 * Not for syndrome calculating ECC controllers which need a special oob layout.
1221 */
1222 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1223 uint8_t *buf, int oob_required, int page)
1224 {
1225 int i, eccsize = chip->ecc.size;
1226 int eccbytes = chip->ecc.bytes;
1227 int eccsteps = chip->ecc.steps;
1228 uint8_t *p = buf;
1229 uint8_t *ecc_calc = chip->buffers->ecccalc;
1230 uint8_t *ecc_code = chip->buffers->ecccode;
1231 uint32_t *eccpos = chip->ecc.layout->eccpos;
1232 unsigned int max_bitflips = 0;
1233
1234 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1235 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1236 chip->read_buf(mtd, p, eccsize);
1237 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1238 }
1239 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1240
1241 for (i = 0; i < chip->ecc.total; i++)
1242 ecc_code[i] = chip->oob_poi[eccpos[i]];
1243
1244 eccsteps = chip->ecc.steps;
1245 p = buf;
1246
1247 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248 int stat;
1249
1250 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1251 if (stat < 0) {
1252 mtd->ecc_stats.failed++;
1253 } else {
1254 mtd->ecc_stats.corrected += stat;
1255 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1256 }
1257 }
1258 return max_bitflips;
1259 }
1260
1261 /**
1262 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1263 * @mtd: mtd info structure
1264 * @chip: nand chip info structure
1265 * @buf: buffer to store read data
1266 * @oob_required: caller requires OOB data read to chip->oob_poi
1267 * @page: page number to read
1268 *
1269 * Hardware ECC for large page chips, require OOB to be read first. For this
1270 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1271 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1272 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1273 * the data area, by overwriting the NAND manufacturer bad block markings.
1274 */
1275 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1276 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1277 {
1278 int i, eccsize = chip->ecc.size;
1279 int eccbytes = chip->ecc.bytes;
1280 int eccsteps = chip->ecc.steps;
1281 uint8_t *p = buf;
1282 uint8_t *ecc_code = chip->buffers->ecccode;
1283 uint32_t *eccpos = chip->ecc.layout->eccpos;
1284 uint8_t *ecc_calc = chip->buffers->ecccalc;
1285 unsigned int max_bitflips = 0;
1286
1287 /* Read the OOB area first */
1288 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1289 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1290 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1291
1292 for (i = 0; i < chip->ecc.total; i++)
1293 ecc_code[i] = chip->oob_poi[eccpos[i]];
1294
1295 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1296 int stat;
1297
1298 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1299 chip->read_buf(mtd, p, eccsize);
1300 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1301
1302 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1303 if (stat < 0) {
1304 mtd->ecc_stats.failed++;
1305 } else {
1306 mtd->ecc_stats.corrected += stat;
1307 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1308 }
1309 }
1310 return max_bitflips;
1311 }
1312
1313 /**
1314 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1315 * @mtd: mtd info structure
1316 * @chip: nand chip info structure
1317 * @buf: buffer to store read data
1318 * @oob_required: caller requires OOB data read to chip->oob_poi
1319 * @page: page number to read
1320 *
1321 * The hw generator calculates the error syndrome automatically. Therefore we
1322 * need a special oob layout and handling.
1323 */
1324 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1325 uint8_t *buf, int oob_required, int page)
1326 {
1327 int i, eccsize = chip->ecc.size;
1328 int eccbytes = chip->ecc.bytes;
1329 int eccsteps = chip->ecc.steps;
1330 uint8_t *p = buf;
1331 uint8_t *oob = chip->oob_poi;
1332 unsigned int max_bitflips = 0;
1333
1334 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1335 int stat;
1336
1337 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1338 chip->read_buf(mtd, p, eccsize);
1339
1340 if (chip->ecc.prepad) {
1341 chip->read_buf(mtd, oob, chip->ecc.prepad);
1342 oob += chip->ecc.prepad;
1343 }
1344
1345 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1346 chip->read_buf(mtd, oob, eccbytes);
1347 stat = chip->ecc.correct(mtd, p, oob, NULL);
1348
1349 if (stat < 0) {
1350 mtd->ecc_stats.failed++;
1351 } else {
1352 mtd->ecc_stats.corrected += stat;
1353 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1354 }
1355
1356 oob += eccbytes;
1357
1358 if (chip->ecc.postpad) {
1359 chip->read_buf(mtd, oob, chip->ecc.postpad);
1360 oob += chip->ecc.postpad;
1361 }
1362 }
1363
1364 /* Calculate remaining oob bytes */
1365 i = mtd->oobsize - (oob - chip->oob_poi);
1366 if (i)
1367 chip->read_buf(mtd, oob, i);
1368
1369 return max_bitflips;
1370 }
1371
1372 /**
1373 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1374 * @chip: nand chip structure
1375 * @oob: oob destination address
1376 * @ops: oob ops structure
1377 * @len: size of oob to transfer
1378 */
1379 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1380 struct mtd_oob_ops *ops, size_t len)
1381 {
1382 switch (ops->mode) {
1383
1384 case MTD_OPS_PLACE_OOB:
1385 case MTD_OPS_RAW:
1386 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1387 return oob + len;
1388
1389 case MTD_OPS_AUTO_OOB: {
1390 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1391 uint32_t boffs = 0, roffs = ops->ooboffs;
1392 size_t bytes = 0;
1393
1394 for (; free->length && len; free++, len -= bytes) {
1395 /* Read request not from offset 0? */
1396 if (unlikely(roffs)) {
1397 if (roffs >= free->length) {
1398 roffs -= free->length;
1399 continue;
1400 }
1401 boffs = free->offset + roffs;
1402 bytes = min_t(size_t, len,
1403 (free->length - roffs));
1404 roffs = 0;
1405 } else {
1406 bytes = min_t(size_t, len, free->length);
1407 boffs = free->offset;
1408 }
1409 memcpy(oob, chip->oob_poi + boffs, bytes);
1410 oob += bytes;
1411 }
1412 return oob;
1413 }
1414 default:
1415 BUG();
1416 }
1417 return NULL;
1418 }
1419
1420 /**
1421 * nand_do_read_ops - [INTERN] Read data with ECC
1422 * @mtd: MTD device structure
1423 * @from: offset to read from
1424 * @ops: oob ops structure
1425 *
1426 * Internal function. Called with chip held.
1427 */
1428 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1429 struct mtd_oob_ops *ops)
1430 {
1431 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1432 struct nand_chip *chip = mtd->priv;
1433 struct mtd_ecc_stats stats;
1434 int ret = 0;
1435 uint32_t readlen = ops->len;
1436 uint32_t oobreadlen = ops->ooblen;
1437 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1438 mtd->oobavail : mtd->oobsize;
1439
1440 uint8_t *bufpoi, *oob, *buf;
1441 unsigned int max_bitflips = 0;
1442
1443 stats = mtd->ecc_stats;
1444
1445 chipnr = (int)(from >> chip->chip_shift);
1446 chip->select_chip(mtd, chipnr);
1447
1448 realpage = (int)(from >> chip->page_shift);
1449 page = realpage & chip->pagemask;
1450
1451 col = (int)(from & (mtd->writesize - 1));
1452
1453 buf = ops->datbuf;
1454 oob = ops->oobbuf;
1455 oob_required = oob ? 1 : 0;
1456
1457 while (1) {
1458 bytes = min(mtd->writesize - col, readlen);
1459 aligned = (bytes == mtd->writesize);
1460
1461 /* Is the current page in the buffer? */
1462 if (realpage != chip->pagebuf || oob) {
1463 bufpoi = aligned ? buf : chip->buffers->databuf;
1464
1465 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1466
1467 /*
1468 * Now read the page into the buffer. Absent an error,
1469 * the read methods return max bitflips per ecc step.
1470 */
1471 if (unlikely(ops->mode == MTD_OPS_RAW))
1472 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1473 oob_required,
1474 page);
1475 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1476 !oob)
1477 ret = chip->ecc.read_subpage(mtd, chip,
1478 col, bytes, bufpoi);
1479 else
1480 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1481 oob_required, page);
1482 if (ret < 0) {
1483 if (!aligned)
1484 /* Invalidate page cache */
1485 chip->pagebuf = -1;
1486 break;
1487 }
1488
1489 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1490
1491 /* Transfer not aligned data */
1492 if (!aligned) {
1493 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1494 !(mtd->ecc_stats.failed - stats.failed) &&
1495 (ops->mode != MTD_OPS_RAW)) {
1496 chip->pagebuf = realpage;
1497 chip->pagebuf_bitflips = ret;
1498 } else {
1499 /* Invalidate page cache */
1500 chip->pagebuf = -1;
1501 }
1502 memcpy(buf, chip->buffers->databuf + col, bytes);
1503 }
1504
1505 buf += bytes;
1506
1507 if (unlikely(oob)) {
1508 int toread = min(oobreadlen, max_oobsize);
1509
1510 if (toread) {
1511 oob = nand_transfer_oob(chip,
1512 oob, ops, toread);
1513 oobreadlen -= toread;
1514 }
1515 }
1516
1517 if (chip->options & NAND_NEED_READRDY) {
1518 /* Apply delay or wait for ready/busy pin */
1519 if (!chip->dev_ready)
1520 udelay(chip->chip_delay);
1521 else
1522 nand_wait_ready(mtd);
1523 }
1524 } else {
1525 memcpy(buf, chip->buffers->databuf + col, bytes);
1526 buf += bytes;
1527 max_bitflips = max_t(unsigned int, max_bitflips,
1528 chip->pagebuf_bitflips);
1529 }
1530
1531 readlen -= bytes;
1532
1533 if (!readlen)
1534 break;
1535
1536 /* For subsequent reads align to page boundary */
1537 col = 0;
1538 /* Increment page address */
1539 realpage++;
1540
1541 page = realpage & chip->pagemask;
1542 /* Check, if we cross a chip boundary */
1543 if (!page) {
1544 chipnr++;
1545 chip->select_chip(mtd, -1);
1546 chip->select_chip(mtd, chipnr);
1547 }
1548 }
1549 chip->select_chip(mtd, -1);
1550
1551 ops->retlen = ops->len - (size_t) readlen;
1552 if (oob)
1553 ops->oobretlen = ops->ooblen - oobreadlen;
1554
1555 if (ret < 0)
1556 return ret;
1557
1558 if (mtd->ecc_stats.failed - stats.failed)
1559 return -EBADMSG;
1560
1561 return max_bitflips;
1562 }
1563
1564 /**
1565 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1566 * @mtd: MTD device structure
1567 * @from: offset to read from
1568 * @len: number of bytes to read
1569 * @retlen: pointer to variable to store the number of read bytes
1570 * @buf: the databuffer to put data
1571 *
1572 * Get hold of the chip and call nand_do_read.
1573 */
1574 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1575 size_t *retlen, uint8_t *buf)
1576 {
1577 struct mtd_oob_ops ops;
1578 int ret;
1579
1580 nand_get_device(mtd, FL_READING);
1581 ops.len = len;
1582 ops.datbuf = buf;
1583 ops.oobbuf = NULL;
1584 ops.mode = MTD_OPS_PLACE_OOB;
1585 ret = nand_do_read_ops(mtd, from, &ops);
1586 *retlen = ops.retlen;
1587 nand_release_device(mtd);
1588 return ret;
1589 }
1590
1591 /**
1592 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1593 * @mtd: mtd info structure
1594 * @chip: nand chip info structure
1595 * @page: page number to read
1596 */
1597 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1598 int page)
1599 {
1600 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1601 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1602 return 0;
1603 }
1604
1605 /**
1606 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1607 * with syndromes
1608 * @mtd: mtd info structure
1609 * @chip: nand chip info structure
1610 * @page: page number to read
1611 */
1612 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1613 int page)
1614 {
1615 uint8_t *buf = chip->oob_poi;
1616 int length = mtd->oobsize;
1617 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1618 int eccsize = chip->ecc.size;
1619 uint8_t *bufpoi = buf;
1620 int i, toread, sndrnd = 0, pos;
1621
1622 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1623 for (i = 0; i < chip->ecc.steps; i++) {
1624 if (sndrnd) {
1625 pos = eccsize + i * (eccsize + chunk);
1626 if (mtd->writesize > 512)
1627 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1628 else
1629 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1630 } else
1631 sndrnd = 1;
1632 toread = min_t(int, length, chunk);
1633 chip->read_buf(mtd, bufpoi, toread);
1634 bufpoi += toread;
1635 length -= toread;
1636 }
1637 if (length > 0)
1638 chip->read_buf(mtd, bufpoi, length);
1639
1640 return 0;
1641 }
1642
1643 /**
1644 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1645 * @mtd: mtd info structure
1646 * @chip: nand chip info structure
1647 * @page: page number to write
1648 */
1649 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1650 int page)
1651 {
1652 int status = 0;
1653 const uint8_t *buf = chip->oob_poi;
1654 int length = mtd->oobsize;
1655
1656 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1657 chip->write_buf(mtd, buf, length);
1658 /* Send command to program the OOB data */
1659 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1660
1661 status = chip->waitfunc(mtd, chip);
1662
1663 return status & NAND_STATUS_FAIL ? -EIO : 0;
1664 }
1665
1666 /**
1667 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1668 * with syndrome - only for large page flash
1669 * @mtd: mtd info structure
1670 * @chip: nand chip info structure
1671 * @page: page number to write
1672 */
1673 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1674 struct nand_chip *chip, int page)
1675 {
1676 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1677 int eccsize = chip->ecc.size, length = mtd->oobsize;
1678 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1679 const uint8_t *bufpoi = chip->oob_poi;
1680
1681 /*
1682 * data-ecc-data-ecc ... ecc-oob
1683 * or
1684 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1685 */
1686 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1687 pos = steps * (eccsize + chunk);
1688 steps = 0;
1689 } else
1690 pos = eccsize;
1691
1692 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1693 for (i = 0; i < steps; i++) {
1694 if (sndcmd) {
1695 if (mtd->writesize <= 512) {
1696 uint32_t fill = 0xFFFFFFFF;
1697
1698 len = eccsize;
1699 while (len > 0) {
1700 int num = min_t(int, len, 4);
1701 chip->write_buf(mtd, (uint8_t *)&fill,
1702 num);
1703 len -= num;
1704 }
1705 } else {
1706 pos = eccsize + i * (eccsize + chunk);
1707 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1708 }
1709 } else
1710 sndcmd = 1;
1711 len = min_t(int, length, chunk);
1712 chip->write_buf(mtd, bufpoi, len);
1713 bufpoi += len;
1714 length -= len;
1715 }
1716 if (length > 0)
1717 chip->write_buf(mtd, bufpoi, length);
1718
1719 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1720 status = chip->waitfunc(mtd, chip);
1721
1722 return status & NAND_STATUS_FAIL ? -EIO : 0;
1723 }
1724
1725 /**
1726 * nand_do_read_oob - [INTERN] NAND read out-of-band
1727 * @mtd: MTD device structure
1728 * @from: offset to read from
1729 * @ops: oob operations description structure
1730 *
1731 * NAND read out-of-band data from the spare area.
1732 */
1733 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1734 struct mtd_oob_ops *ops)
1735 {
1736 int page, realpage, chipnr;
1737 struct nand_chip *chip = mtd->priv;
1738 struct mtd_ecc_stats stats;
1739 int readlen = ops->ooblen;
1740 int len;
1741 uint8_t *buf = ops->oobbuf;
1742 int ret = 0;
1743
1744 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1745 __func__, (unsigned long long)from, readlen);
1746
1747 stats = mtd->ecc_stats;
1748
1749 if (ops->mode == MTD_OPS_AUTO_OOB)
1750 len = chip->ecc.layout->oobavail;
1751 else
1752 len = mtd->oobsize;
1753
1754 if (unlikely(ops->ooboffs >= len)) {
1755 pr_debug("%s: attempt to start read outside oob\n",
1756 __func__);
1757 return -EINVAL;
1758 }
1759
1760 /* Do not allow reads past end of device */
1761 if (unlikely(from >= mtd->size ||
1762 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1763 (from >> chip->page_shift)) * len)) {
1764 pr_debug("%s: attempt to read beyond end of device\n",
1765 __func__);
1766 return -EINVAL;
1767 }
1768
1769 chipnr = (int)(from >> chip->chip_shift);
1770 chip->select_chip(mtd, chipnr);
1771
1772 /* Shift to get page */
1773 realpage = (int)(from >> chip->page_shift);
1774 page = realpage & chip->pagemask;
1775
1776 while (1) {
1777 if (ops->mode == MTD_OPS_RAW)
1778 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1779 else
1780 ret = chip->ecc.read_oob(mtd, chip, page);
1781
1782 if (ret < 0)
1783 break;
1784
1785 len = min(len, readlen);
1786 buf = nand_transfer_oob(chip, buf, ops, len);
1787
1788 if (chip->options & NAND_NEED_READRDY) {
1789 /* Apply delay or wait for ready/busy pin */
1790 if (!chip->dev_ready)
1791 udelay(chip->chip_delay);
1792 else
1793 nand_wait_ready(mtd);
1794 }
1795
1796 readlen -= len;
1797 if (!readlen)
1798 break;
1799
1800 /* Increment page address */
1801 realpage++;
1802
1803 page = realpage & chip->pagemask;
1804 /* Check, if we cross a chip boundary */
1805 if (!page) {
1806 chipnr++;
1807 chip->select_chip(mtd, -1);
1808 chip->select_chip(mtd, chipnr);
1809 }
1810 }
1811 chip->select_chip(mtd, -1);
1812
1813 ops->oobretlen = ops->ooblen - readlen;
1814
1815 if (ret < 0)
1816 return ret;
1817
1818 if (mtd->ecc_stats.failed - stats.failed)
1819 return -EBADMSG;
1820
1821 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1822 }
1823
1824 /**
1825 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1826 * @mtd: MTD device structure
1827 * @from: offset to read from
1828 * @ops: oob operation description structure
1829 *
1830 * NAND read data and/or out-of-band data.
1831 */
1832 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1833 struct mtd_oob_ops *ops)
1834 {
1835 int ret = -ENOTSUPP;
1836
1837 ops->retlen = 0;
1838
1839 /* Do not allow reads past end of device */
1840 if (ops->datbuf && (from + ops->len) > mtd->size) {
1841 pr_debug("%s: attempt to read beyond end of device\n",
1842 __func__);
1843 return -EINVAL;
1844 }
1845
1846 nand_get_device(mtd, FL_READING);
1847
1848 switch (ops->mode) {
1849 case MTD_OPS_PLACE_OOB:
1850 case MTD_OPS_AUTO_OOB:
1851 case MTD_OPS_RAW:
1852 break;
1853
1854 default:
1855 goto out;
1856 }
1857
1858 if (!ops->datbuf)
1859 ret = nand_do_read_oob(mtd, from, ops);
1860 else
1861 ret = nand_do_read_ops(mtd, from, ops);
1862
1863 out:
1864 nand_release_device(mtd);
1865 return ret;
1866 }
1867
1868
1869 /**
1870 * nand_write_page_raw - [INTERN] raw page write function
1871 * @mtd: mtd info structure
1872 * @chip: nand chip info structure
1873 * @buf: data buffer
1874 * @oob_required: must write chip->oob_poi to OOB
1875 *
1876 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1877 */
1878 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1879 const uint8_t *buf, int oob_required)
1880 {
1881 chip->write_buf(mtd, buf, mtd->writesize);
1882 if (oob_required)
1883 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1884
1885 return 0;
1886 }
1887
1888 /**
1889 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1890 * @mtd: mtd info structure
1891 * @chip: nand chip info structure
1892 * @buf: data buffer
1893 * @oob_required: must write chip->oob_poi to OOB
1894 *
1895 * We need a special oob layout and handling even when ECC isn't checked.
1896 */
1897 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1898 struct nand_chip *chip,
1899 const uint8_t *buf, int oob_required)
1900 {
1901 int eccsize = chip->ecc.size;
1902 int eccbytes = chip->ecc.bytes;
1903 uint8_t *oob = chip->oob_poi;
1904 int steps, size;
1905
1906 for (steps = chip->ecc.steps; steps > 0; steps--) {
1907 chip->write_buf(mtd, buf, eccsize);
1908 buf += eccsize;
1909
1910 if (chip->ecc.prepad) {
1911 chip->write_buf(mtd, oob, chip->ecc.prepad);
1912 oob += chip->ecc.prepad;
1913 }
1914
1915 chip->read_buf(mtd, oob, eccbytes);
1916 oob += eccbytes;
1917
1918 if (chip->ecc.postpad) {
1919 chip->write_buf(mtd, oob, chip->ecc.postpad);
1920 oob += chip->ecc.postpad;
1921 }
1922 }
1923
1924 size = mtd->oobsize - (oob - chip->oob_poi);
1925 if (size)
1926 chip->write_buf(mtd, oob, size);
1927
1928 return 0;
1929 }
1930 /**
1931 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1932 * @mtd: mtd info structure
1933 * @chip: nand chip info structure
1934 * @buf: data buffer
1935 * @oob_required: must write chip->oob_poi to OOB
1936 */
1937 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1938 const uint8_t *buf, int oob_required)
1939 {
1940 int i, eccsize = chip->ecc.size;
1941 int eccbytes = chip->ecc.bytes;
1942 int eccsteps = chip->ecc.steps;
1943 uint8_t *ecc_calc = chip->buffers->ecccalc;
1944 const uint8_t *p = buf;
1945 uint32_t *eccpos = chip->ecc.layout->eccpos;
1946
1947 /* Software ECC calculation */
1948 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1949 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1950
1951 for (i = 0; i < chip->ecc.total; i++)
1952 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1953
1954 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1955 }
1956
1957 /**
1958 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1959 * @mtd: mtd info structure
1960 * @chip: nand chip info structure
1961 * @buf: data buffer
1962 * @oob_required: must write chip->oob_poi to OOB
1963 */
1964 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1965 const uint8_t *buf, int oob_required)
1966 {
1967 int i, eccsize = chip->ecc.size;
1968 int eccbytes = chip->ecc.bytes;
1969 int eccsteps = chip->ecc.steps;
1970 uint8_t *ecc_calc = chip->buffers->ecccalc;
1971 const uint8_t *p = buf;
1972 uint32_t *eccpos = chip->ecc.layout->eccpos;
1973
1974 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1975 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1976 chip->write_buf(mtd, p, eccsize);
1977 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1978 }
1979
1980 for (i = 0; i < chip->ecc.total; i++)
1981 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1982
1983 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1984
1985 return 0;
1986 }
1987
1988
1989 /**
1990 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1991 * @mtd: mtd info structure
1992 * @chip: nand chip info structure
1993 * @column: column address of subpage within the page
1994 * @data_len: data length
1995 * @oob_required: must write chip->oob_poi to OOB
1996 */
1997 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1998 struct nand_chip *chip, uint32_t offset,
1999 uint32_t data_len, const uint8_t *data_buf,
2000 int oob_required)
2001 {
2002 uint8_t *oob_buf = chip->oob_poi;
2003 uint8_t *ecc_calc = chip->buffers->ecccalc;
2004 int ecc_size = chip->ecc.size;
2005 int ecc_bytes = chip->ecc.bytes;
2006 int ecc_steps = chip->ecc.steps;
2007 uint32_t *eccpos = chip->ecc.layout->eccpos;
2008 uint32_t start_step = offset / ecc_size;
2009 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2010 int oob_bytes = mtd->oobsize / ecc_steps;
2011 int step, i;
2012
2013 for (step = 0; step < ecc_steps; step++) {
2014 /* configure controller for WRITE access */
2015 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2016
2017 /* write data (untouched subpages already masked by 0xFF) */
2018 chip->write_buf(mtd, data_buf, ecc_size);
2019
2020 /* mask ECC of un-touched subpages by padding 0xFF */
2021 if ((step < start_step) || (step > end_step))
2022 memset(ecc_calc, 0xff, ecc_bytes);
2023 else
2024 chip->ecc.calculate(mtd, data_buf, ecc_calc);
2025
2026 /* mask OOB of un-touched subpages by padding 0xFF */
2027 /* if oob_required, preserve OOB metadata of written subpage */
2028 if (!oob_required || (step < start_step) || (step > end_step))
2029 memset(oob_buf, 0xff, oob_bytes);
2030
2031 data_buf += ecc_size;
2032 ecc_calc += ecc_bytes;
2033 oob_buf += oob_bytes;
2034 }
2035
2036 /* copy calculated ECC for whole page to chip->buffer->oob */
2037 /* this include masked-value(0xFF) for unwritten subpages */
2038 ecc_calc = chip->buffers->ecccalc;
2039 for (i = 0; i < chip->ecc.total; i++)
2040 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2041
2042 /* write OOB buffer to NAND device */
2043 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2044
2045 return 0;
2046 }
2047
2048
2049 /**
2050 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2051 * @mtd: mtd info structure
2052 * @chip: nand chip info structure
2053 * @buf: data buffer
2054 * @oob_required: must write chip->oob_poi to OOB
2055 *
2056 * The hw generator calculates the error syndrome automatically. Therefore we
2057 * need a special oob layout and handling.
2058 */
2059 static int nand_write_page_syndrome(struct mtd_info *mtd,
2060 struct nand_chip *chip,
2061 const uint8_t *buf, int oob_required)
2062 {
2063 int i, eccsize = chip->ecc.size;
2064 int eccbytes = chip->ecc.bytes;
2065 int eccsteps = chip->ecc.steps;
2066 const uint8_t *p = buf;
2067 uint8_t *oob = chip->oob_poi;
2068
2069 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2070
2071 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2072 chip->write_buf(mtd, p, eccsize);
2073
2074 if (chip->ecc.prepad) {
2075 chip->write_buf(mtd, oob, chip->ecc.prepad);
2076 oob += chip->ecc.prepad;
2077 }
2078
2079 chip->ecc.calculate(mtd, p, oob);
2080 chip->write_buf(mtd, oob, eccbytes);
2081 oob += eccbytes;
2082
2083 if (chip->ecc.postpad) {
2084 chip->write_buf(mtd, oob, chip->ecc.postpad);
2085 oob += chip->ecc.postpad;
2086 }
2087 }
2088
2089 /* Calculate remaining oob bytes */
2090 i = mtd->oobsize - (oob - chip->oob_poi);
2091 if (i)
2092 chip->write_buf(mtd, oob, i);
2093
2094 return 0;
2095 }
2096
2097 /**
2098 * nand_write_page - [REPLACEABLE] write one page
2099 * @mtd: MTD device structure
2100 * @chip: NAND chip descriptor
2101 * @offset: address offset within the page
2102 * @data_len: length of actual data to be written
2103 * @buf: the data to write
2104 * @oob_required: must write chip->oob_poi to OOB
2105 * @page: page number to write
2106 * @cached: cached programming
2107 * @raw: use _raw version of write_page
2108 */
2109 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2110 uint32_t offset, int data_len, const uint8_t *buf,
2111 int oob_required, int page, int cached, int raw)
2112 {
2113 int status, subpage;
2114
2115 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2116 chip->ecc.write_subpage)
2117 subpage = offset || (data_len < mtd->writesize);
2118 else
2119 subpage = 0;
2120
2121 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2122
2123 if (unlikely(raw))
2124 status = chip->ecc.write_page_raw(mtd, chip, buf,
2125 oob_required);
2126 else if (subpage)
2127 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2128 buf, oob_required);
2129 else
2130 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2131
2132 if (status < 0)
2133 return status;
2134
2135 /*
2136 * Cached progamming disabled for now. Not sure if it's worth the
2137 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2138 */
2139 cached = 0;
2140
2141 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2142
2143 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2144 status = chip->waitfunc(mtd, chip);
2145 /*
2146 * See if operation failed and additional status checks are
2147 * available.
2148 */
2149 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2150 status = chip->errstat(mtd, chip, FL_WRITING, status,
2151 page);
2152
2153 if (status & NAND_STATUS_FAIL)
2154 return -EIO;
2155 } else {
2156 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2157 status = chip->waitfunc(mtd, chip);
2158 }
2159
2160 return 0;
2161 }
2162
2163 /**
2164 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2165 * @mtd: MTD device structure
2166 * @oob: oob data buffer
2167 * @len: oob data write length
2168 * @ops: oob ops structure
2169 */
2170 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2171 struct mtd_oob_ops *ops)
2172 {
2173 struct nand_chip *chip = mtd->priv;
2174
2175 /*
2176 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2177 * data from a previous OOB read.
2178 */
2179 memset(chip->oob_poi, 0xff, mtd->oobsize);
2180
2181 switch (ops->mode) {
2182
2183 case MTD_OPS_PLACE_OOB:
2184 case MTD_OPS_RAW:
2185 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2186 return oob + len;
2187
2188 case MTD_OPS_AUTO_OOB: {
2189 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2190 uint32_t boffs = 0, woffs = ops->ooboffs;
2191 size_t bytes = 0;
2192
2193 for (; free->length && len; free++, len -= bytes) {
2194 /* Write request not from offset 0? */
2195 if (unlikely(woffs)) {
2196 if (woffs >= free->length) {
2197 woffs -= free->length;
2198 continue;
2199 }
2200 boffs = free->offset + woffs;
2201 bytes = min_t(size_t, len,
2202 (free->length - woffs));
2203 woffs = 0;
2204 } else {
2205 bytes = min_t(size_t, len, free->length);
2206 boffs = free->offset;
2207 }
2208 memcpy(chip->oob_poi + boffs, oob, bytes);
2209 oob += bytes;
2210 }
2211 return oob;
2212 }
2213 default:
2214 BUG();
2215 }
2216 return NULL;
2217 }
2218
2219 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2220
2221 /**
2222 * nand_do_write_ops - [INTERN] NAND write with ECC
2223 * @mtd: MTD device structure
2224 * @to: offset to write to
2225 * @ops: oob operations description structure
2226 *
2227 * NAND write with ECC.
2228 */
2229 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2230 struct mtd_oob_ops *ops)
2231 {
2232 int chipnr, realpage, page, blockmask, column;
2233 struct nand_chip *chip = mtd->priv;
2234 uint32_t writelen = ops->len;
2235
2236 uint32_t oobwritelen = ops->ooblen;
2237 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2238 mtd->oobavail : mtd->oobsize;
2239
2240 uint8_t *oob = ops->oobbuf;
2241 uint8_t *buf = ops->datbuf;
2242 int ret;
2243 int oob_required = oob ? 1 : 0;
2244
2245 ops->retlen = 0;
2246 if (!writelen)
2247 return 0;
2248
2249 /* Reject writes, which are not page aligned */
2250 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2251 pr_notice("%s: attempt to write non page aligned data\n",
2252 __func__);
2253 return -EINVAL;
2254 }
2255
2256 column = to & (mtd->writesize - 1);
2257
2258 chipnr = (int)(to >> chip->chip_shift);
2259 chip->select_chip(mtd, chipnr);
2260
2261 /* Check, if it is write protected */
2262 if (nand_check_wp(mtd)) {
2263 ret = -EIO;
2264 goto err_out;
2265 }
2266
2267 realpage = (int)(to >> chip->page_shift);
2268 page = realpage & chip->pagemask;
2269 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2270
2271 /* Invalidate the page cache, when we write to the cached page */
2272 if (to <= (chip->pagebuf << chip->page_shift) &&
2273 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2274 chip->pagebuf = -1;
2275
2276 /* Don't allow multipage oob writes with offset */
2277 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2278 ret = -EINVAL;
2279 goto err_out;
2280 }
2281
2282 while (1) {
2283 int bytes = mtd->writesize;
2284 int cached = writelen > bytes && page != blockmask;
2285 uint8_t *wbuf = buf;
2286
2287 /* Partial page write? */
2288 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2289 cached = 0;
2290 bytes = min_t(int, bytes - column, (int) writelen);
2291 chip->pagebuf = -1;
2292 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2293 memcpy(&chip->buffers->databuf[column], buf, bytes);
2294 wbuf = chip->buffers->databuf;
2295 }
2296
2297 if (unlikely(oob)) {
2298 size_t len = min(oobwritelen, oobmaxlen);
2299 oob = nand_fill_oob(mtd, oob, len, ops);
2300 oobwritelen -= len;
2301 } else {
2302 /* We still need to erase leftover OOB data */
2303 memset(chip->oob_poi, 0xff, mtd->oobsize);
2304 }
2305 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2306 oob_required, page, cached,
2307 (ops->mode == MTD_OPS_RAW));
2308 if (ret)
2309 break;
2310
2311 writelen -= bytes;
2312 if (!writelen)
2313 break;
2314
2315 column = 0;
2316 buf += bytes;
2317 realpage++;
2318
2319 page = realpage & chip->pagemask;
2320 /* Check, if we cross a chip boundary */
2321 if (!page) {
2322 chipnr++;
2323 chip->select_chip(mtd, -1);
2324 chip->select_chip(mtd, chipnr);
2325 }
2326 }
2327
2328 ops->retlen = ops->len - writelen;
2329 if (unlikely(oob))
2330 ops->oobretlen = ops->ooblen;
2331
2332 err_out:
2333 chip->select_chip(mtd, -1);
2334 return ret;
2335 }
2336
2337 /**
2338 * panic_nand_write - [MTD Interface] NAND write with ECC
2339 * @mtd: MTD device structure
2340 * @to: offset to write to
2341 * @len: number of bytes to write
2342 * @retlen: pointer to variable to store the number of written bytes
2343 * @buf: the data to write
2344 *
2345 * NAND write with ECC. Used when performing writes in interrupt context, this
2346 * may for example be called by mtdoops when writing an oops while in panic.
2347 */
2348 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2349 size_t *retlen, const uint8_t *buf)
2350 {
2351 struct nand_chip *chip = mtd->priv;
2352 struct mtd_oob_ops ops;
2353 int ret;
2354
2355 /* Wait for the device to get ready */
2356 panic_nand_wait(mtd, chip, 400);
2357
2358 /* Grab the device */
2359 panic_nand_get_device(chip, mtd, FL_WRITING);
2360
2361 ops.len = len;
2362 ops.datbuf = (uint8_t *)buf;
2363 ops.oobbuf = NULL;
2364 ops.mode = MTD_OPS_PLACE_OOB;
2365
2366 ret = nand_do_write_ops(mtd, to, &ops);
2367
2368 *retlen = ops.retlen;
2369 return ret;
2370 }
2371
2372 /**
2373 * nand_write - [MTD Interface] NAND write with ECC
2374 * @mtd: MTD device structure
2375 * @to: offset to write to
2376 * @len: number of bytes to write
2377 * @retlen: pointer to variable to store the number of written bytes
2378 * @buf: the data to write
2379 *
2380 * NAND write with ECC.
2381 */
2382 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2383 size_t *retlen, const uint8_t *buf)
2384 {
2385 struct mtd_oob_ops ops;
2386 int ret;
2387
2388 nand_get_device(mtd, FL_WRITING);
2389 ops.len = len;
2390 ops.datbuf = (uint8_t *)buf;
2391 ops.oobbuf = NULL;
2392 ops.mode = MTD_OPS_PLACE_OOB;
2393 ret = nand_do_write_ops(mtd, to, &ops);
2394 *retlen = ops.retlen;
2395 nand_release_device(mtd);
2396 return ret;
2397 }
2398
2399 /**
2400 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2401 * @mtd: MTD device structure
2402 * @to: offset to write to
2403 * @ops: oob operation description structure
2404 *
2405 * NAND write out-of-band.
2406 */
2407 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2408 struct mtd_oob_ops *ops)
2409 {
2410 int chipnr, page, status, len;
2411 struct nand_chip *chip = mtd->priv;
2412
2413 pr_debug("%s: to = 0x%08x, len = %i\n",
2414 __func__, (unsigned int)to, (int)ops->ooblen);
2415
2416 if (ops->mode == MTD_OPS_AUTO_OOB)
2417 len = chip->ecc.layout->oobavail;
2418 else
2419 len = mtd->oobsize;
2420
2421 /* Do not allow write past end of page */
2422 if ((ops->ooboffs + ops->ooblen) > len) {
2423 pr_debug("%s: attempt to write past end of page\n",
2424 __func__);
2425 return -EINVAL;
2426 }
2427
2428 if (unlikely(ops->ooboffs >= len)) {
2429 pr_debug("%s: attempt to start write outside oob\n",
2430 __func__);
2431 return -EINVAL;
2432 }
2433
2434 /* Do not allow write past end of device */
2435 if (unlikely(to >= mtd->size ||
2436 ops->ooboffs + ops->ooblen >
2437 ((mtd->size >> chip->page_shift) -
2438 (to >> chip->page_shift)) * len)) {
2439 pr_debug("%s: attempt to write beyond end of device\n",
2440 __func__);
2441 return -EINVAL;
2442 }
2443
2444 chipnr = (int)(to >> chip->chip_shift);
2445 chip->select_chip(mtd, chipnr);
2446
2447 /* Shift to get page */
2448 page = (int)(to >> chip->page_shift);
2449
2450 /*
2451 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2452 * of my DiskOnChip 2000 test units) will clear the whole data page too
2453 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2454 * it in the doc2000 driver in August 1999. dwmw2.
2455 */
2456 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2457
2458 /* Check, if it is write protected */
2459 if (nand_check_wp(mtd)) {
2460 chip->select_chip(mtd, -1);
2461 return -EROFS;
2462 }
2463
2464 /* Invalidate the page cache, if we write to the cached page */
2465 if (page == chip->pagebuf)
2466 chip->pagebuf = -1;
2467
2468 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2469
2470 if (ops->mode == MTD_OPS_RAW)
2471 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2472 else
2473 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2474
2475 chip->select_chip(mtd, -1);
2476
2477 if (status)
2478 return status;
2479
2480 ops->oobretlen = ops->ooblen;
2481
2482 return 0;
2483 }
2484
2485 /**
2486 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2487 * @mtd: MTD device structure
2488 * @to: offset to write to
2489 * @ops: oob operation description structure
2490 */
2491 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2492 struct mtd_oob_ops *ops)
2493 {
2494 int ret = -ENOTSUPP;
2495
2496 ops->retlen = 0;
2497
2498 /* Do not allow writes past end of device */
2499 if (ops->datbuf && (to + ops->len) > mtd->size) {
2500 pr_debug("%s: attempt to write beyond end of device\n",
2501 __func__);
2502 return -EINVAL;
2503 }
2504
2505 nand_get_device(mtd, FL_WRITING);
2506
2507 switch (ops->mode) {
2508 case MTD_OPS_PLACE_OOB:
2509 case MTD_OPS_AUTO_OOB:
2510 case MTD_OPS_RAW:
2511 break;
2512
2513 default:
2514 goto out;
2515 }
2516
2517 if (!ops->datbuf)
2518 ret = nand_do_write_oob(mtd, to, ops);
2519 else
2520 ret = nand_do_write_ops(mtd, to, ops);
2521
2522 out:
2523 nand_release_device(mtd);
2524 return ret;
2525 }
2526
2527 /**
2528 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2529 * @mtd: MTD device structure
2530 * @page: the page address of the block which will be erased
2531 *
2532 * Standard erase command for NAND chips.
2533 */
2534 static void single_erase_cmd(struct mtd_info *mtd, int page)
2535 {
2536 struct nand_chip *chip = mtd->priv;
2537 /* Send commands to erase a block */
2538 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2539 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2540 }
2541
2542 /**
2543 * nand_erase - [MTD Interface] erase block(s)
2544 * @mtd: MTD device structure
2545 * @instr: erase instruction
2546 *
2547 * Erase one ore more blocks.
2548 */
2549 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2550 {
2551 return nand_erase_nand(mtd, instr, 0);
2552 }
2553
2554 /**
2555 * nand_erase_nand - [INTERN] erase block(s)
2556 * @mtd: MTD device structure
2557 * @instr: erase instruction
2558 * @allowbbt: allow erasing the bbt area
2559 *
2560 * Erase one ore more blocks.
2561 */
2562 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2563 int allowbbt)
2564 {
2565 int page, status, pages_per_block, ret, chipnr;
2566 struct nand_chip *chip = mtd->priv;
2567 loff_t len;
2568
2569 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2570 __func__, (unsigned long long)instr->addr,
2571 (unsigned long long)instr->len);
2572
2573 if (check_offs_len(mtd, instr->addr, instr->len))
2574 return -EINVAL;
2575
2576 /* Grab the lock and see if the device is available */
2577 nand_get_device(mtd, FL_ERASING);
2578
2579 /* Shift to get first page */
2580 page = (int)(instr->addr >> chip->page_shift);
2581 chipnr = (int)(instr->addr >> chip->chip_shift);
2582
2583 /* Calculate pages in each block */
2584 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2585
2586 /* Select the NAND device */
2587 chip->select_chip(mtd, chipnr);
2588
2589 /* Check, if it is write protected */
2590 if (nand_check_wp(mtd)) {
2591 pr_debug("%s: device is write protected!\n",
2592 __func__);
2593 instr->state = MTD_ERASE_FAILED;
2594 goto erase_exit;
2595 }
2596
2597 /* Loop through the pages */
2598 len = instr->len;
2599
2600 instr->state = MTD_ERASING;
2601
2602 while (len) {
2603 /* Check if we have a bad block, we do not erase bad blocks! */
2604 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2605 chip->page_shift, 0, allowbbt)) {
2606 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2607 __func__, page);
2608 instr->state = MTD_ERASE_FAILED;
2609 goto erase_exit;
2610 }
2611
2612 /*
2613 * Invalidate the page cache, if we erase the block which
2614 * contains the current cached page.
2615 */
2616 if (page <= chip->pagebuf && chip->pagebuf <
2617 (page + pages_per_block))
2618 chip->pagebuf = -1;
2619
2620 chip->erase_cmd(mtd, page & chip->pagemask);
2621
2622 status = chip->waitfunc(mtd, chip);
2623
2624 /*
2625 * See if operation failed and additional status checks are
2626 * available
2627 */
2628 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2629 status = chip->errstat(mtd, chip, FL_ERASING,
2630 status, page);
2631
2632 /* See if block erase succeeded */
2633 if (status & NAND_STATUS_FAIL) {
2634 pr_debug("%s: failed erase, page 0x%08x\n",
2635 __func__, page);
2636 instr->state = MTD_ERASE_FAILED;
2637 instr->fail_addr =
2638 ((loff_t)page << chip->page_shift);
2639 goto erase_exit;
2640 }
2641
2642 /* Increment page address and decrement length */
2643 len -= (1 << chip->phys_erase_shift);
2644 page += pages_per_block;
2645
2646 /* Check, if we cross a chip boundary */
2647 if (len && !(page & chip->pagemask)) {
2648 chipnr++;
2649 chip->select_chip(mtd, -1);
2650 chip->select_chip(mtd, chipnr);
2651 }
2652 }
2653 instr->state = MTD_ERASE_DONE;
2654
2655 erase_exit:
2656
2657 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2658
2659 /* Deselect and wake up anyone waiting on the device */
2660 chip->select_chip(mtd, -1);
2661 nand_release_device(mtd);
2662
2663 /* Do call back function */
2664 if (!ret)
2665 mtd_erase_callback(instr);
2666
2667 /* Return more or less happy */
2668 return ret;
2669 }
2670
2671 /**
2672 * nand_sync - [MTD Interface] sync
2673 * @mtd: MTD device structure
2674 *
2675 * Sync is actually a wait for chip ready function.
2676 */
2677 static void nand_sync(struct mtd_info *mtd)
2678 {
2679 pr_debug("%s: called\n", __func__);
2680
2681 /* Grab the lock and see if the device is available */
2682 nand_get_device(mtd, FL_SYNCING);
2683 /* Release it and go back */
2684 nand_release_device(mtd);
2685 }
2686
2687 /**
2688 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2689 * @mtd: MTD device structure
2690 * @offs: offset relative to mtd start
2691 */
2692 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2693 {
2694 return nand_block_checkbad(mtd, offs, 1, 0);
2695 }
2696
2697 /**
2698 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2699 * @mtd: MTD device structure
2700 * @ofs: offset relative to mtd start
2701 */
2702 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2703 {
2704 int ret;
2705
2706 ret = nand_block_isbad(mtd, ofs);
2707 if (ret) {
2708 /* If it was bad already, return success and do nothing */
2709 if (ret > 0)
2710 return 0;
2711 return ret;
2712 }
2713
2714 return nand_block_markbad_lowlevel(mtd, ofs);
2715 }
2716
2717 /**
2718 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2719 * @mtd: MTD device structure
2720 * @chip: nand chip info structure
2721 * @addr: feature address.
2722 * @subfeature_param: the subfeature parameters, a four bytes array.
2723 */
2724 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2725 int addr, uint8_t *subfeature_param)
2726 {
2727 int status;
2728
2729 if (!chip->onfi_version ||
2730 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2731 & ONFI_OPT_CMD_SET_GET_FEATURES))
2732 return -EINVAL;
2733
2734 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2735 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2736 status = chip->waitfunc(mtd, chip);
2737 if (status & NAND_STATUS_FAIL)
2738 return -EIO;
2739 return 0;
2740 }
2741
2742 /**
2743 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2744 * @mtd: MTD device structure
2745 * @chip: nand chip info structure
2746 * @addr: feature address.
2747 * @subfeature_param: the subfeature parameters, a four bytes array.
2748 */
2749 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2750 int addr, uint8_t *subfeature_param)
2751 {
2752 if (!chip->onfi_version ||
2753 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2754 & ONFI_OPT_CMD_SET_GET_FEATURES))
2755 return -EINVAL;
2756
2757 /* clear the sub feature parameters */
2758 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2759
2760 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2761 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2762 return 0;
2763 }
2764
2765 /**
2766 * nand_suspend - [MTD Interface] Suspend the NAND flash
2767 * @mtd: MTD device structure
2768 */
2769 static int nand_suspend(struct mtd_info *mtd)
2770 {
2771 return nand_get_device(mtd, FL_PM_SUSPENDED);
2772 }
2773
2774 /**
2775 * nand_resume - [MTD Interface] Resume the NAND flash
2776 * @mtd: MTD device structure
2777 */
2778 static void nand_resume(struct mtd_info *mtd)
2779 {
2780 struct nand_chip *chip = mtd->priv;
2781
2782 if (chip->state == FL_PM_SUSPENDED)
2783 nand_release_device(mtd);
2784 else
2785 pr_err("%s called for a chip which is not in suspended state\n",
2786 __func__);
2787 }
2788
2789 /* Set default functions */
2790 static void nand_set_defaults(struct nand_chip *chip, int busw)
2791 {
2792 /* check for proper chip_delay setup, set 20us if not */
2793 if (!chip->chip_delay)
2794 chip->chip_delay = 20;
2795
2796 /* check, if a user supplied command function given */
2797 if (chip->cmdfunc == NULL)
2798 chip->cmdfunc = nand_command;
2799
2800 /* check, if a user supplied wait function given */
2801 if (chip->waitfunc == NULL)
2802 chip->waitfunc = nand_wait;
2803
2804 if (!chip->select_chip)
2805 chip->select_chip = nand_select_chip;
2806
2807 /* If called twice, pointers that depend on busw may need to be reset */
2808 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2809 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2810 if (!chip->read_word)
2811 chip->read_word = nand_read_word;
2812 if (!chip->block_bad)
2813 chip->block_bad = nand_block_bad;
2814 if (!chip->block_markbad)
2815 chip->block_markbad = nand_default_block_markbad;
2816 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2817 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2818 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2819 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2820 if (!chip->scan_bbt)
2821 chip->scan_bbt = nand_default_bbt;
2822
2823 if (!chip->controller) {
2824 chip->controller = &chip->hwcontrol;
2825 spin_lock_init(&chip->controller->lock);
2826 init_waitqueue_head(&chip->controller->wq);
2827 }
2828
2829 }
2830
2831 /* Sanitize ONFI strings so we can safely print them */
2832 static void sanitize_string(uint8_t *s, size_t len)
2833 {
2834 ssize_t i;
2835
2836 /* Null terminate */
2837 s[len - 1] = 0;
2838
2839 /* Remove non printable chars */
2840 for (i = 0; i < len - 1; i++) {
2841 if (s[i] < ' ' || s[i] > 127)
2842 s[i] = '?';
2843 }
2844
2845 /* Remove trailing spaces */
2846 strim(s);
2847 }
2848
2849 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2850 {
2851 int i;
2852 while (len--) {
2853 crc ^= *p++ << 8;
2854 for (i = 0; i < 8; i++)
2855 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2856 }
2857
2858 return crc;
2859 }
2860
2861 /*
2862 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2863 */
2864 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2865 int *busw)
2866 {
2867 struct nand_onfi_params *p = &chip->onfi_params;
2868 int i;
2869 int val;
2870
2871 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2872 if (chip->options & NAND_BUSWIDTH_16) {
2873 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2874 return 0;
2875 }
2876 /* Try ONFI for unknown chip or LP */
2877 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2878 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2879 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2880 return 0;
2881
2882 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2883 for (i = 0; i < 3; i++) {
2884 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2885 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2886 le16_to_cpu(p->crc)) {
2887 pr_info("ONFI param page %d valid\n", i);
2888 break;
2889 }
2890 }
2891
2892 if (i == 3)
2893 return 0;
2894
2895 /* Check version */
2896 val = le16_to_cpu(p->revision);
2897 if (val & (1 << 5))
2898 chip->onfi_version = 23;
2899 else if (val & (1 << 4))
2900 chip->onfi_version = 22;
2901 else if (val & (1 << 3))
2902 chip->onfi_version = 21;
2903 else if (val & (1 << 2))
2904 chip->onfi_version = 20;
2905 else if (val & (1 << 1))
2906 chip->onfi_version = 10;
2907
2908 if (!chip->onfi_version) {
2909 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2910 return 0;
2911 }
2912
2913 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2914 sanitize_string(p->model, sizeof(p->model));
2915 if (!mtd->name)
2916 mtd->name = p->model;
2917 mtd->writesize = le32_to_cpu(p->byte_per_page);
2918 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2919 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2920 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2921 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2922 *busw = 0;
2923 if (le16_to_cpu(p->features) & 1)
2924 *busw = NAND_BUSWIDTH_16;
2925
2926 pr_info("ONFI flash detected\n");
2927 return 1;
2928 }
2929
2930 /*
2931 * nand_id_has_period - Check if an ID string has a given wraparound period
2932 * @id_data: the ID string
2933 * @arrlen: the length of the @id_data array
2934 * @period: the period of repitition
2935 *
2936 * Check if an ID string is repeated within a given sequence of bytes at
2937 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2938 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2939 * if the repetition has a period of @period; otherwise, returns zero.
2940 */
2941 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2942 {
2943 int i, j;
2944 for (i = 0; i < period; i++)
2945 for (j = i + period; j < arrlen; j += period)
2946 if (id_data[i] != id_data[j])
2947 return 0;
2948 return 1;
2949 }
2950
2951 /*
2952 * nand_id_len - Get the length of an ID string returned by CMD_READID
2953 * @id_data: the ID string
2954 * @arrlen: the length of the @id_data array
2955
2956 * Returns the length of the ID string, according to known wraparound/trailing
2957 * zero patterns. If no pattern exists, returns the length of the array.
2958 */
2959 static int nand_id_len(u8 *id_data, int arrlen)
2960 {
2961 int last_nonzero, period;
2962
2963 /* Find last non-zero byte */
2964 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2965 if (id_data[last_nonzero])
2966 break;
2967
2968 /* All zeros */
2969 if (last_nonzero < 0)
2970 return 0;
2971
2972 /* Calculate wraparound period */
2973 for (period = 1; period < arrlen; period++)
2974 if (nand_id_has_period(id_data, arrlen, period))
2975 break;
2976
2977 /* There's a repeated pattern */
2978 if (period < arrlen)
2979 return period;
2980
2981 /* There are trailing zeros */
2982 if (last_nonzero < arrlen - 1)
2983 return last_nonzero + 1;
2984
2985 /* No pattern detected */
2986 return arrlen;
2987 }
2988
2989 /*
2990 * Many new NAND share similar device ID codes, which represent the size of the
2991 * chip. The rest of the parameters must be decoded according to generic or
2992 * manufacturer-specific "extended ID" decoding patterns.
2993 */
2994 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2995 u8 id_data[8], int *busw)
2996 {
2997 int extid, id_len;
2998 /* The 3rd id byte holds MLC / multichip data */
2999 chip->cellinfo = id_data[2];
3000 /* The 4th id byte is the important one */
3001 extid = id_data[3];
3002
3003 id_len = nand_id_len(id_data, 8);
3004
3005 /*
3006 * Field definitions are in the following datasheets:
3007 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3008 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3009 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3010 *
3011 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3012 * ID to decide what to do.
3013 */
3014 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3015 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3016 id_data[5] != 0x00) {
3017 /* Calc pagesize */
3018 mtd->writesize = 2048 << (extid & 0x03);
3019 extid >>= 2;
3020 /* Calc oobsize */
3021 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3022 case 1:
3023 mtd->oobsize = 128;
3024 break;
3025 case 2:
3026 mtd->oobsize = 218;
3027 break;
3028 case 3:
3029 mtd->oobsize = 400;
3030 break;
3031 case 4:
3032 mtd->oobsize = 436;
3033 break;
3034 case 5:
3035 mtd->oobsize = 512;
3036 break;
3037 case 6:
3038 default: /* Other cases are "reserved" (unknown) */
3039 mtd->oobsize = 640;
3040 break;
3041 }
3042 extid >>= 2;
3043 /* Calc blocksize */
3044 mtd->erasesize = (128 * 1024) <<
3045 (((extid >> 1) & 0x04) | (extid & 0x03));
3046 *busw = 0;
3047 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3048 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3049 unsigned int tmp;
3050
3051 /* Calc pagesize */
3052 mtd->writesize = 2048 << (extid & 0x03);
3053 extid >>= 2;
3054 /* Calc oobsize */
3055 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3056 case 0:
3057 mtd->oobsize = 128;
3058 break;
3059 case 1:
3060 mtd->oobsize = 224;
3061 break;
3062 case 2:
3063 mtd->oobsize = 448;
3064 break;
3065 case 3:
3066 mtd->oobsize = 64;
3067 break;
3068 case 4:
3069 mtd->oobsize = 32;
3070 break;
3071 case 5:
3072 mtd->oobsize = 16;
3073 break;
3074 default:
3075 mtd->oobsize = 640;
3076 break;
3077 }
3078 extid >>= 2;
3079 /* Calc blocksize */
3080 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3081 if (tmp < 0x03)
3082 mtd->erasesize = (128 * 1024) << tmp;
3083 else if (tmp == 0x03)
3084 mtd->erasesize = 768 * 1024;
3085 else
3086 mtd->erasesize = (64 * 1024) << tmp;
3087 *busw = 0;
3088 } else {
3089 /* Calc pagesize */
3090 mtd->writesize = 1024 << (extid & 0x03);
3091 extid >>= 2;
3092 /* Calc oobsize */
3093 mtd->oobsize = (8 << (extid & 0x01)) *
3094 (mtd->writesize >> 9);
3095 extid >>= 2;
3096 /* Calc blocksize. Blocksize is multiples of 64KiB */
3097 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3098 extid >>= 2;
3099 /* Get buswidth information */
3100 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3101
3102 /*
3103 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3104 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3105 * follows:
3106 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3107 * 110b -> 24nm
3108 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3109 */
3110 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3111 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3112 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3113 !(id_data[4] & 0x80) /* !BENAND */) {
3114 mtd->oobsize = 32 * mtd->writesize >> 9;
3115 }
3116
3117 }
3118 }
3119
3120 /*
3121 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3122 * decodes a matching ID table entry and assigns the MTD size parameters for
3123 * the chip.
3124 */
3125 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3126 struct nand_flash_dev *type, u8 id_data[8],
3127 int *busw)
3128 {
3129 int maf_id = id_data[0];
3130
3131 mtd->erasesize = type->erasesize;
3132 mtd->writesize = type->pagesize;
3133 mtd->oobsize = mtd->writesize / 32;
3134 *busw = type->options & NAND_BUSWIDTH_16;
3135
3136 /*
3137 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3138 * some Spansion chips have erasesize that conflicts with size
3139 * listed in nand_ids table.
3140 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3141 */
3142 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3143 && id_data[6] == 0x00 && id_data[7] == 0x00
3144 && mtd->writesize == 512) {
3145 mtd->erasesize = 128 * 1024;
3146 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3147 }
3148 }
3149
3150 /*
3151 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3152 * heuristic patterns using various detected parameters (e.g., manufacturer,
3153 * page size, cell-type information).
3154 */
3155 static void nand_decode_bbm_options(struct mtd_info *mtd,
3156 struct nand_chip *chip, u8 id_data[8])
3157 {
3158 int maf_id = id_data[0];
3159
3160 /* Set the bad block position */
3161 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3162 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3163 else
3164 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3165
3166 /*
3167 * Bad block marker is stored in the last page of each block on Samsung
3168 * and Hynix MLC devices; stored in first two pages of each block on
3169 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3170 * AMD/Spansion, and Macronix. All others scan only the first page.
3171 */
3172 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3173 (maf_id == NAND_MFR_SAMSUNG ||
3174 maf_id == NAND_MFR_HYNIX))
3175 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3176 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3177 (maf_id == NAND_MFR_SAMSUNG ||
3178 maf_id == NAND_MFR_HYNIX ||
3179 maf_id == NAND_MFR_TOSHIBA ||
3180 maf_id == NAND_MFR_AMD ||
3181 maf_id == NAND_MFR_MACRONIX)) ||
3182 (mtd->writesize == 2048 &&
3183 maf_id == NAND_MFR_MICRON))
3184 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3185 }
3186
3187 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3188 {
3189 return type->id_len;
3190 }
3191
3192 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3193 struct nand_flash_dev *type, u8 *id_data, int *busw)
3194 {
3195 if (!strncmp(type->id, id_data, type->id_len)) {
3196 mtd->writesize = type->pagesize;
3197 mtd->erasesize = type->erasesize;
3198 mtd->oobsize = type->oobsize;
3199
3200 chip->cellinfo = id_data[2];
3201 chip->chipsize = (uint64_t)type->chipsize << 20;
3202 chip->options |= type->options;
3203
3204 *busw = type->options & NAND_BUSWIDTH_16;
3205
3206 return true;
3207 }
3208 return false;
3209 }
3210
3211 /*
3212 * Get the flash and manufacturer id and lookup if the type is supported.
3213 */
3214 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3215 struct nand_chip *chip,
3216 int busw,
3217 int *maf_id, int *dev_id,
3218 struct nand_flash_dev *type)
3219 {
3220 int i, maf_idx;
3221 u8 id_data[8];
3222
3223 /* Select the device */
3224 chip->select_chip(mtd, 0);
3225
3226 /*
3227 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3228 * after power-up.
3229 */
3230 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3231
3232 /* Send the command for reading device ID */
3233 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3234
3235 /* Read manufacturer and device IDs */
3236 *maf_id = chip->read_byte(mtd);
3237 *dev_id = chip->read_byte(mtd);
3238
3239 /*
3240 * Try again to make sure, as some systems the bus-hold or other
3241 * interface concerns can cause random data which looks like a
3242 * possibly credible NAND flash to appear. If the two results do
3243 * not match, ignore the device completely.
3244 */
3245
3246 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3247
3248 /* Read entire ID string */
3249 for (i = 0; i < 8; i++)
3250 id_data[i] = chip->read_byte(mtd);
3251
3252 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3253 pr_info("%s: second ID read did not match "
3254 "%02x,%02x against %02x,%02x\n", __func__,
3255 *maf_id, *dev_id, id_data[0], id_data[1]);
3256 return ERR_PTR(-ENODEV);
3257 }
3258
3259 if (!type)
3260 type = nand_flash_ids;
3261
3262 for (; type->name != NULL; type++) {
3263 if (is_full_id_nand(type)) {
3264 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3265 goto ident_done;
3266 } else if (*dev_id == type->dev_id) {
3267 break;
3268 }
3269 }
3270
3271 chip->onfi_version = 0;
3272 if (!type->name || !type->pagesize) {
3273 /* Check is chip is ONFI compliant */
3274 if (nand_flash_detect_onfi(mtd, chip, &busw))
3275 goto ident_done;
3276 }
3277
3278 if (!type->name)
3279 return ERR_PTR(-ENODEV);
3280
3281 if (!mtd->name)
3282 mtd->name = type->name;
3283
3284 chip->chipsize = (uint64_t)type->chipsize << 20;
3285
3286 if (!type->pagesize && chip->init_size) {
3287 /* Set the pagesize, oobsize, erasesize by the driver */
3288 busw = chip->init_size(mtd, chip, id_data);
3289 } else if (!type->pagesize) {
3290 /* Decode parameters from extended ID */
3291 nand_decode_ext_id(mtd, chip, id_data, &busw);
3292 } else {
3293 nand_decode_id(mtd, chip, type, id_data, &busw);
3294 }
3295 /* Get chip options */
3296 chip->options |= type->options;
3297
3298 /*
3299 * Check if chip is not a Samsung device. Do not clear the
3300 * options for chips which do not have an extended id.
3301 */
3302 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3303 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3304 ident_done:
3305
3306 /* Try to identify manufacturer */
3307 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3308 if (nand_manuf_ids[maf_idx].id == *maf_id)
3309 break;
3310 }
3311
3312 if (chip->options & NAND_BUSWIDTH_AUTO) {
3313 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3314 chip->options |= busw;
3315 nand_set_defaults(chip, busw);
3316 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3317 /*
3318 * Check, if buswidth is correct. Hardware drivers should set
3319 * chip correct!
3320 */
3321 pr_info("NAND device: Manufacturer ID:"
3322 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3323 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3324 pr_warn("NAND bus width %d instead %d bit\n",
3325 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3326 busw ? 16 : 8);
3327 return ERR_PTR(-EINVAL);
3328 }
3329
3330 nand_decode_bbm_options(mtd, chip, id_data);
3331
3332 /* Calculate the address shift from the page size */
3333 chip->page_shift = ffs(mtd->writesize) - 1;
3334 /* Convert chipsize to number of pages per chip -1 */
3335 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3336
3337 chip->bbt_erase_shift = chip->phys_erase_shift =
3338 ffs(mtd->erasesize) - 1;
3339 if (chip->chipsize & 0xffffffff)
3340 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3341 else {
3342 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3343 chip->chip_shift += 32 - 1;
3344 }
3345
3346 chip->badblockbits = 8;
3347 chip->erase_cmd = single_erase_cmd;
3348
3349 /* Do not replace user supplied command function! */
3350 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3351 chip->cmdfunc = nand_command_lp;
3352
3353 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3354 " %dMiB, page size: %d, OOB size: %d\n",
3355 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3356 chip->onfi_version ? chip->onfi_params.model : type->name,
3357 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3358
3359 return type;
3360 }
3361
3362 /**
3363 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3364 * @mtd: MTD device structure
3365 * @maxchips: number of chips to scan for
3366 * @table: alternative NAND ID table
3367 *
3368 * This is the first phase of the normal nand_scan() function. It reads the
3369 * flash ID and sets up MTD fields accordingly.
3370 *
3371 * The mtd->owner field must be set to the module of the caller.
3372 */
3373 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3374 struct nand_flash_dev *table)
3375 {
3376 int i, busw, nand_maf_id, nand_dev_id;
3377 struct nand_chip *chip = mtd->priv;
3378 struct nand_flash_dev *type;
3379
3380 /* Get buswidth to select the correct functions */
3381 busw = chip->options & NAND_BUSWIDTH_16;
3382 /* Set the default functions */
3383 nand_set_defaults(chip, busw);
3384
3385 /* Read the flash type */
3386 type = nand_get_flash_type(mtd, chip, busw,
3387 &nand_maf_id, &nand_dev_id, table);
3388
3389 if (IS_ERR(type)) {
3390 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3391 pr_warn("No NAND device found\n");
3392 chip->select_chip(mtd, -1);
3393 return PTR_ERR(type);
3394 }
3395
3396 chip->select_chip(mtd, -1);
3397
3398 /* Check for a chip array */
3399 for (i = 1; i < maxchips; i++) {
3400 chip->select_chip(mtd, i);
3401 /* See comment in nand_get_flash_type for reset */
3402 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3403 /* Send the command for reading device ID */
3404 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3405 /* Read manufacturer and device IDs */
3406 if (nand_maf_id != chip->read_byte(mtd) ||
3407 nand_dev_id != chip->read_byte(mtd)) {
3408 chip->select_chip(mtd, -1);
3409 break;
3410 }
3411 chip->select_chip(mtd, -1);
3412 }
3413 if (i > 1)
3414 pr_info("%d NAND chips detected\n", i);
3415
3416 /* Store the number of chips and calc total size for mtd */
3417 chip->numchips = i;
3418 mtd->size = i * chip->chipsize;
3419
3420 return 0;
3421 }
3422 EXPORT_SYMBOL(nand_scan_ident);
3423
3424
3425 /**
3426 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3427 * @mtd: MTD device structure
3428 *
3429 * This is the second phase of the normal nand_scan() function. It fills out
3430 * all the uninitialized function pointers with the defaults and scans for a
3431 * bad block table if appropriate.
3432 */
3433 int nand_scan_tail(struct mtd_info *mtd)
3434 {
3435 int i;
3436 struct nand_chip *chip = mtd->priv;
3437
3438 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3439 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3440 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3441
3442 if (!(chip->options & NAND_OWN_BUFFERS))
3443 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3444 if (!chip->buffers)
3445 return -ENOMEM;
3446
3447 /* Set the internal oob buffer location, just after the page data */
3448 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3449
3450 /*
3451 * If no default placement scheme is given, select an appropriate one.
3452 */
3453 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3454 switch (mtd->oobsize) {
3455 case 8:
3456 chip->ecc.layout = &nand_oob_8;
3457 break;
3458 case 16:
3459 chip->ecc.layout = &nand_oob_16;
3460 break;
3461 case 64:
3462 chip->ecc.layout = &nand_oob_64;
3463 break;
3464 case 128:
3465 chip->ecc.layout = &nand_oob_128;
3466 break;
3467 default:
3468 pr_warn("No oob scheme defined for oobsize %d\n",
3469 mtd->oobsize);
3470 BUG();
3471 }
3472 }
3473
3474 if (!chip->write_page)
3475 chip->write_page = nand_write_page;
3476
3477 /* set for ONFI nand */
3478 if (!chip->onfi_set_features)
3479 chip->onfi_set_features = nand_onfi_set_features;
3480 if (!chip->onfi_get_features)
3481 chip->onfi_get_features = nand_onfi_get_features;
3482
3483 /*
3484 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3485 * selected and we have 256 byte pagesize fallback to software ECC
3486 */
3487
3488 switch (chip->ecc.mode) {
3489 case NAND_ECC_HW_OOB_FIRST:
3490 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3491 if (!chip->ecc.calculate || !chip->ecc.correct ||
3492 !chip->ecc.hwctl) {
3493 pr_warn("No ECC functions supplied; "
3494 "hardware ECC not possible\n");
3495 BUG();
3496 }
3497 if (!chip->ecc.read_page)
3498 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3499
3500 case NAND_ECC_HW:
3501 /* Use standard hwecc read page function? */
3502 if (!chip->ecc.read_page)
3503 chip->ecc.read_page = nand_read_page_hwecc;
3504 if (!chip->ecc.write_page)
3505 chip->ecc.write_page = nand_write_page_hwecc;
3506 if (!chip->ecc.read_page_raw)
3507 chip->ecc.read_page_raw = nand_read_page_raw;
3508 if (!chip->ecc.write_page_raw)
3509 chip->ecc.write_page_raw = nand_write_page_raw;
3510 if (!chip->ecc.read_oob)
3511 chip->ecc.read_oob = nand_read_oob_std;
3512 if (!chip->ecc.write_oob)
3513 chip->ecc.write_oob = nand_write_oob_std;
3514 if (!chip->ecc.read_subpage)
3515 chip->ecc.read_subpage = nand_read_subpage;
3516 if (!chip->ecc.write_subpage)
3517 chip->ecc.write_subpage = nand_write_subpage_hwecc;
3518
3519 case NAND_ECC_HW_SYNDROME:
3520 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3521 !chip->ecc.hwctl) &&
3522 (!chip->ecc.read_page ||
3523 chip->ecc.read_page == nand_read_page_hwecc ||
3524 !chip->ecc.write_page ||
3525 chip->ecc.write_page == nand_write_page_hwecc)) {
3526 pr_warn("No ECC functions supplied; "
3527 "hardware ECC not possible\n");
3528 BUG();
3529 }
3530 /* Use standard syndrome read/write page function? */
3531 if (!chip->ecc.read_page)
3532 chip->ecc.read_page = nand_read_page_syndrome;
3533 if (!chip->ecc.write_page)
3534 chip->ecc.write_page = nand_write_page_syndrome;
3535 if (!chip->ecc.read_page_raw)
3536 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3537 if (!chip->ecc.write_page_raw)
3538 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3539 if (!chip->ecc.read_oob)
3540 chip->ecc.read_oob = nand_read_oob_syndrome;
3541 if (!chip->ecc.write_oob)
3542 chip->ecc.write_oob = nand_write_oob_syndrome;
3543
3544 if (mtd->writesize >= chip->ecc.size) {
3545 if (!chip->ecc.strength) {
3546 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3547 BUG();
3548 }
3549 break;
3550 }
3551 pr_warn("%d byte HW ECC not possible on "
3552 "%d byte page size, fallback to SW ECC\n",
3553 chip->ecc.size, mtd->writesize);
3554 chip->ecc.mode = NAND_ECC_SOFT;
3555
3556 case NAND_ECC_SOFT:
3557 chip->ecc.calculate = nand_calculate_ecc;
3558 chip->ecc.correct = nand_correct_data;
3559 chip->ecc.read_page = nand_read_page_swecc;
3560 chip->ecc.read_subpage = nand_read_subpage;
3561 chip->ecc.write_page = nand_write_page_swecc;
3562 chip->ecc.read_page_raw = nand_read_page_raw;
3563 chip->ecc.write_page_raw = nand_write_page_raw;
3564 chip->ecc.read_oob = nand_read_oob_std;
3565 chip->ecc.write_oob = nand_write_oob_std;
3566 if (!chip->ecc.size)
3567 chip->ecc.size = 256;
3568 chip->ecc.bytes = 3;
3569 chip->ecc.strength = 1;
3570 break;
3571
3572 case NAND_ECC_SOFT_BCH:
3573 if (!mtd_nand_has_bch()) {
3574 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3575 BUG();
3576 }
3577 chip->ecc.calculate = nand_bch_calculate_ecc;
3578 chip->ecc.correct = nand_bch_correct_data;
3579 chip->ecc.read_page = nand_read_page_swecc;
3580 chip->ecc.read_subpage = nand_read_subpage;
3581 chip->ecc.write_page = nand_write_page_swecc;
3582 chip->ecc.read_page_raw = nand_read_page_raw;
3583 chip->ecc.write_page_raw = nand_write_page_raw;
3584 chip->ecc.read_oob = nand_read_oob_std;
3585 chip->ecc.write_oob = nand_write_oob_std;
3586 /*
3587 * Board driver should supply ecc.size and ecc.bytes values to
3588 * select how many bits are correctable; see nand_bch_init()
3589 * for details. Otherwise, default to 4 bits for large page
3590 * devices.
3591 */
3592 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3593 chip->ecc.size = 512;
3594 chip->ecc.bytes = 7;
3595 }
3596 chip->ecc.priv = nand_bch_init(mtd,
3597 chip->ecc.size,
3598 chip->ecc.bytes,
3599 &chip->ecc.layout);
3600 if (!chip->ecc.priv) {
3601 pr_warn("BCH ECC initialization failed!\n");
3602 BUG();
3603 }
3604 chip->ecc.strength =
3605 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3606 break;
3607
3608 case NAND_ECC_NONE:
3609 pr_warn("NAND_ECC_NONE selected by board driver. "
3610 "This is not recommended!\n");
3611 chip->ecc.read_page = nand_read_page_raw;
3612 chip->ecc.write_page = nand_write_page_raw;
3613 chip->ecc.read_oob = nand_read_oob_std;
3614 chip->ecc.read_page_raw = nand_read_page_raw;
3615 chip->ecc.write_page_raw = nand_write_page_raw;
3616 chip->ecc.write_oob = nand_write_oob_std;
3617 chip->ecc.size = mtd->writesize;
3618 chip->ecc.bytes = 0;
3619 chip->ecc.strength = 0;
3620 break;
3621
3622 default:
3623 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3624 BUG();
3625 }
3626
3627 /* For many systems, the standard OOB write also works for raw */
3628 if (!chip->ecc.read_oob_raw)
3629 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3630 if (!chip->ecc.write_oob_raw)
3631 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3632
3633 /*
3634 * The number of bytes available for a client to place data into
3635 * the out of band area.
3636 */
3637 chip->ecc.layout->oobavail = 0;
3638 for (i = 0; chip->ecc.layout->oobfree[i].length
3639 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3640 chip->ecc.layout->oobavail +=
3641 chip->ecc.layout->oobfree[i].length;
3642 mtd->oobavail = chip->ecc.layout->oobavail;
3643
3644 /*
3645 * Set the number of read / write steps for one page depending on ECC
3646 * mode.
3647 */
3648 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3649 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3650 pr_warn("Invalid ECC parameters\n");
3651 BUG();
3652 }
3653 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3654
3655 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3656 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3657 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3658 switch (chip->ecc.steps) {
3659 case 2:
3660 mtd->subpage_sft = 1;
3661 break;
3662 case 4:
3663 case 8:
3664 case 16:
3665 mtd->subpage_sft = 2;
3666 break;
3667 }
3668 }
3669 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3670
3671 /* Initialize state */
3672 chip->state = FL_READY;
3673
3674 /* Invalidate the pagebuffer reference */
3675 chip->pagebuf = -1;
3676
3677 /* Large page NAND with SOFT_ECC should support subpage reads */
3678 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3679 chip->options |= NAND_SUBPAGE_READ;
3680
3681 /* Fill in remaining MTD driver data */
3682 mtd->type = MTD_NANDFLASH;
3683 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3684 MTD_CAP_NANDFLASH;
3685 mtd->_erase = nand_erase;
3686 mtd->_point = NULL;
3687 mtd->_unpoint = NULL;
3688 mtd->_read = nand_read;
3689 mtd->_write = nand_write;
3690 mtd->_panic_write = panic_nand_write;
3691 mtd->_read_oob = nand_read_oob;
3692 mtd->_write_oob = nand_write_oob;
3693 mtd->_sync = nand_sync;
3694 mtd->_lock = NULL;
3695 mtd->_unlock = NULL;
3696 mtd->_suspend = nand_suspend;
3697 mtd->_resume = nand_resume;
3698 mtd->_block_isbad = nand_block_isbad;
3699 mtd->_block_markbad = nand_block_markbad;
3700 mtd->writebufsize = mtd->writesize;
3701
3702 /* propagate ecc info to mtd_info */
3703 mtd->ecclayout = chip->ecc.layout;
3704 mtd->ecc_strength = chip->ecc.strength;
3705 /*
3706 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3707 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3708 * properly set.
3709 */
3710 if (!mtd->bitflip_threshold)
3711 mtd->bitflip_threshold = mtd->ecc_strength;
3712
3713 /* Check, if we should skip the bad block table scan */
3714 if (chip->options & NAND_SKIP_BBTSCAN)
3715 return 0;
3716
3717 /* Build bad block table */
3718 return chip->scan_bbt(mtd);
3719 }
3720 EXPORT_SYMBOL(nand_scan_tail);
3721
3722 /*
3723 * is_module_text_address() isn't exported, and it's mostly a pointless
3724 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3725 * to call us from in-kernel code if the core NAND support is modular.
3726 */
3727 #ifdef MODULE
3728 #define caller_is_module() (1)
3729 #else
3730 #define caller_is_module() \
3731 is_module_text_address((unsigned long)__builtin_return_address(0))
3732 #endif
3733
3734 /**
3735 * nand_scan - [NAND Interface] Scan for the NAND device
3736 * @mtd: MTD device structure
3737 * @maxchips: number of chips to scan for
3738 *
3739 * This fills out all the uninitialized function pointers with the defaults.
3740 * The flash ID is read and the mtd/chip structures are filled with the
3741 * appropriate values. The mtd->owner field must be set to the module of the
3742 * caller.
3743 */
3744 int nand_scan(struct mtd_info *mtd, int maxchips)
3745 {
3746 int ret;
3747
3748 /* Many callers got this wrong, so check for it for a while... */
3749 if (!mtd->owner && caller_is_module()) {
3750 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3751 BUG();
3752 }
3753
3754 ret = nand_scan_ident(mtd, maxchips, NULL);
3755 if (!ret)
3756 ret = nand_scan_tail(mtd);
3757 return ret;
3758 }
3759 EXPORT_SYMBOL(nand_scan);
3760
3761 /**
3762 * nand_release - [NAND Interface] Free resources held by the NAND device
3763 * @mtd: MTD device structure
3764 */
3765 void nand_release(struct mtd_info *mtd)
3766 {
3767 struct nand_chip *chip = mtd->priv;
3768
3769 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3770 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3771
3772 mtd_device_unregister(mtd);
3773
3774 /* Free bad block table memory */
3775 kfree(chip->bbt);
3776 if (!(chip->options & NAND_OWN_BUFFERS))
3777 kfree(chip->buffers);
3778
3779 /* Free bad block descriptor memory */
3780 if (chip->badblock_pattern && chip->badblock_pattern->options
3781 & NAND_BBT_DYNAMICSTRUCT)
3782 kfree(chip->badblock_pattern);
3783 }
3784 EXPORT_SYMBOL_GPL(nand_release);
3785
3786 static int __init nand_base_init(void)
3787 {
3788 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3789 return 0;
3790 }
3791
3792 static void __exit nand_base_exit(void)
3793 {
3794 led_trigger_unregister_simple(nand_led_trigger);
3795 }
3796
3797 module_init(nand_base_init);
3798 module_exit(nand_base_exit);
3799
3800 MODULE_LICENSE("GPL");
3801 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3802 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3803 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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