3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
47 #include <linux/mtd/partitions.h>
48 #include <linux/of_mtd.h>
50 /* Define default oob placement schemes for large and small page devices */
51 static struct nand_ecclayout nand_oob_8
= {
61 static struct nand_ecclayout nand_oob_16
= {
63 .eccpos
= {0, 1, 2, 3, 6, 7},
69 static struct nand_ecclayout nand_oob_64
= {
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63},
80 static struct nand_ecclayout nand_oob_128
= {
83 80, 81, 82, 83, 84, 85, 86, 87,
84 88, 89, 90, 91, 92, 93, 94, 95,
85 96, 97, 98, 99, 100, 101, 102, 103,
86 104, 105, 106, 107, 108, 109, 110, 111,
87 112, 113, 114, 115, 116, 117, 118, 119,
88 120, 121, 122, 123, 124, 125, 126, 127},
94 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
96 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
97 struct mtd_oob_ops
*ops
);
99 static int check_offs_len(struct mtd_info
*mtd
,
100 loff_t ofs
, uint64_t len
)
102 struct nand_chip
*chip
= mtd_to_nand(mtd
);
105 /* Start address must align on block boundary */
106 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
107 pr_debug("%s: unaligned address\n", __func__
);
111 /* Length must align on block boundary */
112 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
113 pr_debug("%s: length not block aligned\n", __func__
);
121 * nand_release_device - [GENERIC] release chip
122 * @mtd: MTD device structure
124 * Release chip lock and wake up anyone waiting on the device.
126 static void nand_release_device(struct mtd_info
*mtd
)
128 struct nand_chip
*chip
= mtd_to_nand(mtd
);
130 /* Release the controller and the chip */
131 spin_lock(&chip
->controller
->lock
);
132 chip
->controller
->active
= NULL
;
133 chip
->state
= FL_READY
;
134 wake_up(&chip
->controller
->wq
);
135 spin_unlock(&chip
->controller
->lock
);
139 * nand_read_byte - [DEFAULT] read one byte from the chip
140 * @mtd: MTD device structure
142 * Default read function for 8bit buswidth
144 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
146 struct nand_chip
*chip
= mtd_to_nand(mtd
);
147 return readb(chip
->IO_ADDR_R
);
151 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
152 * @mtd: MTD device structure
154 * Default read function for 16bit buswidth with endianness conversion.
157 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
159 struct nand_chip
*chip
= mtd_to_nand(mtd
);
160 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
164 * nand_read_word - [DEFAULT] read one word from the chip
165 * @mtd: MTD device structure
167 * Default read function for 16bit buswidth without endianness conversion.
169 static u16
nand_read_word(struct mtd_info
*mtd
)
171 struct nand_chip
*chip
= mtd_to_nand(mtd
);
172 return readw(chip
->IO_ADDR_R
);
176 * nand_select_chip - [DEFAULT] control CE line
177 * @mtd: MTD device structure
178 * @chipnr: chipnumber to select, -1 for deselect
180 * Default select function for 1 chip devices.
182 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
184 struct nand_chip
*chip
= mtd_to_nand(mtd
);
188 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
199 * nand_write_byte - [DEFAULT] write single byte to chip
200 * @mtd: MTD device structure
201 * @byte: value to write
203 * Default function to write a byte to I/O[7:0]
205 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
207 struct nand_chip
*chip
= mtd_to_nand(mtd
);
209 chip
->write_buf(mtd
, &byte
, 1);
213 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
214 * @mtd: MTD device structure
215 * @byte: value to write
217 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
219 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
221 struct nand_chip
*chip
= mtd_to_nand(mtd
);
222 uint16_t word
= byte
;
225 * It's not entirely clear what should happen to I/O[15:8] when writing
226 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
228 * When the host supports a 16-bit bus width, only data is
229 * transferred at the 16-bit width. All address and command line
230 * transfers shall use only the lower 8-bits of the data bus. During
231 * command transfers, the host may place any value on the upper
232 * 8-bits of the data bus. During address transfers, the host shall
233 * set the upper 8-bits of the data bus to 00h.
235 * One user of the write_byte callback is nand_onfi_set_features. The
236 * four parameters are specified to be written to I/O[7:0], but this is
237 * neither an address nor a command transfer. Let's assume a 0 on the
238 * upper I/O lines is OK.
240 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 * nand_write_buf - [DEFAULT] write buffer to chip
245 * @mtd: MTD device structure
247 * @len: number of bytes to write
249 * Default write function for 8bit buswidth.
251 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
253 struct nand_chip
*chip
= mtd_to_nand(mtd
);
255 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
259 * nand_read_buf - [DEFAULT] read chip data into buffer
260 * @mtd: MTD device structure
261 * @buf: buffer to store date
262 * @len: number of bytes to read
264 * Default read function for 8bit buswidth.
266 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
268 struct nand_chip
*chip
= mtd_to_nand(mtd
);
270 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
274 * nand_write_buf16 - [DEFAULT] write buffer to chip
275 * @mtd: MTD device structure
277 * @len: number of bytes to write
279 * Default write function for 16bit buswidth.
281 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
283 struct nand_chip
*chip
= mtd_to_nand(mtd
);
284 u16
*p
= (u16
*) buf
;
286 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
290 * nand_read_buf16 - [DEFAULT] read chip data into buffer
291 * @mtd: MTD device structure
292 * @buf: buffer to store date
293 * @len: number of bytes to read
295 * Default read function for 16bit buswidth.
297 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
299 struct nand_chip
*chip
= mtd_to_nand(mtd
);
300 u16
*p
= (u16
*) buf
;
302 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
310 * Check, if the block is bad.
312 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
314 int page
, res
= 0, i
= 0;
315 struct nand_chip
*chip
= mtd_to_nand(mtd
);
318 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
319 ofs
+= mtd
->erasesize
- mtd
->writesize
;
321 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
324 if (chip
->options
& NAND_BUSWIDTH_16
) {
325 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
326 chip
->badblockpos
& 0xFE, page
);
327 bad
= cpu_to_le16(chip
->read_word(mtd
));
328 if (chip
->badblockpos
& 0x1)
333 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
335 bad
= chip
->read_byte(mtd
);
338 if (likely(chip
->badblockbits
== 8))
341 res
= hweight8(bad
) < chip
->badblockbits
;
342 ofs
+= mtd
->writesize
;
343 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
345 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
351 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by a hardware
356 * specific driver. It provides the details for writing a bad block marker to a
359 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
361 struct nand_chip
*chip
= mtd_to_nand(mtd
);
362 struct mtd_oob_ops ops
;
363 uint8_t buf
[2] = { 0, 0 };
364 int ret
= 0, res
, i
= 0;
366 memset(&ops
, 0, sizeof(ops
));
368 ops
.ooboffs
= chip
->badblockpos
;
369 if (chip
->options
& NAND_BUSWIDTH_16
) {
370 ops
.ooboffs
&= ~0x01;
371 ops
.len
= ops
.ooblen
= 2;
373 ops
.len
= ops
.ooblen
= 1;
375 ops
.mode
= MTD_OPS_PLACE_OOB
;
377 /* Write to first/last page(s) if necessary */
378 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
379 ofs
+= mtd
->erasesize
- mtd
->writesize
;
381 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
386 ofs
+= mtd
->writesize
;
387 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
393 * nand_block_markbad_lowlevel - mark a block bad
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
397 * This function performs the generic NAND bad block marking steps (i.e., bad
398 * block table(s) and/or marker(s)). We only allow the hardware driver to
399 * specify how to write bad block markers to OOB (chip->block_markbad).
401 * We try operations in the following order:
402 * (1) erase the affected block, to allow OOB marker to be written cleanly
403 * (2) write bad block marker to OOB area of affected block (unless flag
404 * NAND_BBT_NO_OOB_BBM is present)
406 * Note that we retain the first error encountered in (2) or (3), finish the
407 * procedures, and dump the error in the end.
409 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
411 struct nand_chip
*chip
= mtd_to_nand(mtd
);
414 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
415 struct erase_info einfo
;
417 /* Attempt erase before marking OOB */
418 memset(&einfo
, 0, sizeof(einfo
));
421 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
422 nand_erase_nand(mtd
, &einfo
, 0);
424 /* Write bad block marker to OOB */
425 nand_get_device(mtd
, FL_WRITING
);
426 ret
= chip
->block_markbad(mtd
, ofs
);
427 nand_release_device(mtd
);
430 /* Mark block bad in BBT */
432 res
= nand_markbad_bbt(mtd
, ofs
);
438 mtd
->ecc_stats
.badblocks
++;
444 * nand_check_wp - [GENERIC] check if the chip is write protected
445 * @mtd: MTD device structure
447 * Check, if the device is write protected. The function expects, that the
448 * device is already selected.
450 static int nand_check_wp(struct mtd_info
*mtd
)
452 struct nand_chip
*chip
= mtd_to_nand(mtd
);
454 /* Broken xD cards report WP despite being writable */
455 if (chip
->options
& NAND_BROKEN_XD
)
458 /* Check the WP bit */
459 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
460 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
464 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
465 * @mtd: MTD device structure
466 * @ofs: offset from device start
468 * Check if the block is marked as reserved.
470 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
472 struct nand_chip
*chip
= mtd_to_nand(mtd
);
476 /* Return info from the table */
477 return nand_isreserved_bbt(mtd
, ofs
);
481 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
482 * @mtd: MTD device structure
483 * @ofs: offset from device start
484 * @allowbbt: 1, if its allowed to access the bbt area
486 * Check, if the block is bad. Either by reading the bad block table or
487 * calling of the scan function.
489 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
491 struct nand_chip
*chip
= mtd_to_nand(mtd
);
494 return chip
->block_bad(mtd
, ofs
);
496 /* Return info from the table */
497 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
501 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
502 * @mtd: MTD device structure
505 * Helper function for nand_wait_ready used when needing to wait in interrupt
508 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
510 struct nand_chip
*chip
= mtd_to_nand(mtd
);
513 /* Wait for the device to get ready */
514 for (i
= 0; i
< timeo
; i
++) {
515 if (chip
->dev_ready(mtd
))
517 touch_softlockup_watchdog();
523 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
524 * @mtd: MTD device structure
526 * Wait for the ready pin after a command, and warn if a timeout occurs.
528 void nand_wait_ready(struct mtd_info
*mtd
)
530 struct nand_chip
*chip
= mtd_to_nand(mtd
);
531 unsigned long timeo
= 400;
533 if (in_interrupt() || oops_in_progress
)
534 return panic_nand_wait_ready(mtd
, timeo
);
536 /* Wait until command is processed or timeout occurs */
537 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
539 if (chip
->dev_ready(mtd
))
542 } while (time_before(jiffies
, timeo
));
544 if (!chip
->dev_ready(mtd
))
545 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
547 EXPORT_SYMBOL_GPL(nand_wait_ready
);
550 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
551 * @mtd: MTD device structure
552 * @timeo: Timeout in ms
554 * Wait for status ready (i.e. command done) or timeout.
556 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
558 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
560 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
562 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
564 touch_softlockup_watchdog();
565 } while (time_before(jiffies
, timeo
));
569 * nand_command - [DEFAULT] Send command to NAND device
570 * @mtd: MTD device structure
571 * @command: the command to be sent
572 * @column: the column address for this command, -1 if none
573 * @page_addr: the page address for this command, -1 if none
575 * Send command to NAND device. This function is used for small page devices
576 * (512 Bytes per page).
578 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
579 int column
, int page_addr
)
581 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
582 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
584 /* Write out the command to the device */
585 if (command
== NAND_CMD_SEQIN
) {
588 if (column
>= mtd
->writesize
) {
590 column
-= mtd
->writesize
;
591 readcmd
= NAND_CMD_READOOB
;
592 } else if (column
< 256) {
593 /* First 256 bytes --> READ0 */
594 readcmd
= NAND_CMD_READ0
;
597 readcmd
= NAND_CMD_READ1
;
599 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
600 ctrl
&= ~NAND_CTRL_CHANGE
;
602 chip
->cmd_ctrl(mtd
, command
, ctrl
);
604 /* Address cycle, when necessary */
605 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
606 /* Serially input address */
608 /* Adjust columns for 16 bit buswidth */
609 if (chip
->options
& NAND_BUSWIDTH_16
&&
610 !nand_opcode_8bits(command
))
612 chip
->cmd_ctrl(mtd
, column
, ctrl
);
613 ctrl
&= ~NAND_CTRL_CHANGE
;
615 if (page_addr
!= -1) {
616 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
617 ctrl
&= ~NAND_CTRL_CHANGE
;
618 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
619 /* One more address cycle for devices > 32MiB */
620 if (chip
->chipsize
> (32 << 20))
621 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
623 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
626 * Program and erase have their own busy handlers status and sequential
631 case NAND_CMD_PAGEPROG
:
632 case NAND_CMD_ERASE1
:
633 case NAND_CMD_ERASE2
:
635 case NAND_CMD_STATUS
:
641 udelay(chip
->chip_delay
);
642 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
643 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
645 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
646 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
647 nand_wait_status_ready(mtd
, 250);
650 /* This applies to read commands */
653 * If we don't have access to the busy pin, we apply the given
656 if (!chip
->dev_ready
) {
657 udelay(chip
->chip_delay
);
662 * Apply this short delay always to ensure that we do wait tWB in
663 * any case on any machine.
667 nand_wait_ready(mtd
);
671 * nand_command_lp - [DEFAULT] Send command to NAND large page device
672 * @mtd: MTD device structure
673 * @command: the command to be sent
674 * @column: the column address for this command, -1 if none
675 * @page_addr: the page address for this command, -1 if none
677 * Send command to NAND device. This is the version for the new large page
678 * devices. We don't have the separate regions as we have in the small page
679 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
681 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
682 int column
, int page_addr
)
684 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
686 /* Emulate NAND_CMD_READOOB */
687 if (command
== NAND_CMD_READOOB
) {
688 column
+= mtd
->writesize
;
689 command
= NAND_CMD_READ0
;
692 /* Command latch cycle */
693 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
695 if (column
!= -1 || page_addr
!= -1) {
696 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
698 /* Serially input address */
700 /* Adjust columns for 16 bit buswidth */
701 if (chip
->options
& NAND_BUSWIDTH_16
&&
702 !nand_opcode_8bits(command
))
704 chip
->cmd_ctrl(mtd
, column
, ctrl
);
705 ctrl
&= ~NAND_CTRL_CHANGE
;
706 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
708 if (page_addr
!= -1) {
709 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
710 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
711 NAND_NCE
| NAND_ALE
);
712 /* One more address cycle for devices > 128MiB */
713 if (chip
->chipsize
> (128 << 20))
714 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
715 NAND_NCE
| NAND_ALE
);
718 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
721 * Program and erase have their own busy handlers status, sequential
722 * in and status need no delay.
726 case NAND_CMD_CACHEDPROG
:
727 case NAND_CMD_PAGEPROG
:
728 case NAND_CMD_ERASE1
:
729 case NAND_CMD_ERASE2
:
732 case NAND_CMD_STATUS
:
738 udelay(chip
->chip_delay
);
739 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
740 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
741 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
742 NAND_NCE
| NAND_CTRL_CHANGE
);
743 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
744 nand_wait_status_ready(mtd
, 250);
747 case NAND_CMD_RNDOUT
:
748 /* No ready / busy check necessary */
749 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
750 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
751 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
752 NAND_NCE
| NAND_CTRL_CHANGE
);
756 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
757 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
758 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
759 NAND_NCE
| NAND_CTRL_CHANGE
);
761 /* This applies to read commands */
764 * If we don't have access to the busy pin, we apply the given
767 if (!chip
->dev_ready
) {
768 udelay(chip
->chip_delay
);
774 * Apply this short delay always to ensure that we do wait tWB in
775 * any case on any machine.
779 nand_wait_ready(mtd
);
783 * panic_nand_get_device - [GENERIC] Get chip for selected access
784 * @chip: the nand chip descriptor
785 * @mtd: MTD device structure
786 * @new_state: the state which is requested
788 * Used when in panic, no locks are taken.
790 static void panic_nand_get_device(struct nand_chip
*chip
,
791 struct mtd_info
*mtd
, int new_state
)
793 /* Hardware controller shared among independent devices */
794 chip
->controller
->active
= chip
;
795 chip
->state
= new_state
;
799 * nand_get_device - [GENERIC] Get chip for selected access
800 * @mtd: MTD device structure
801 * @new_state: the state which is requested
803 * Get the device and lock it for exclusive access
806 nand_get_device(struct mtd_info
*mtd
, int new_state
)
808 struct nand_chip
*chip
= mtd_to_nand(mtd
);
809 spinlock_t
*lock
= &chip
->controller
->lock
;
810 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
811 DECLARE_WAITQUEUE(wait
, current
);
815 /* Hardware controller shared among independent devices */
816 if (!chip
->controller
->active
)
817 chip
->controller
->active
= chip
;
819 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
820 chip
->state
= new_state
;
824 if (new_state
== FL_PM_SUSPENDED
) {
825 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
826 chip
->state
= FL_PM_SUSPENDED
;
831 set_current_state(TASK_UNINTERRUPTIBLE
);
832 add_wait_queue(wq
, &wait
);
835 remove_wait_queue(wq
, &wait
);
840 * panic_nand_wait - [GENERIC] wait until the command is done
841 * @mtd: MTD device structure
842 * @chip: NAND chip structure
845 * Wait for command done. This is a helper function for nand_wait used when
846 * we are in interrupt context. May happen when in panic and trying to write
847 * an oops through mtdoops.
849 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
853 for (i
= 0; i
< timeo
; i
++) {
854 if (chip
->dev_ready
) {
855 if (chip
->dev_ready(mtd
))
858 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
866 * nand_wait - [DEFAULT] wait until the command is done
867 * @mtd: MTD device structure
868 * @chip: NAND chip structure
870 * Wait for command done. This applies to erase and program only.
872 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
876 unsigned long timeo
= 400;
879 * Apply this short delay always to ensure that we do wait tWB in any
880 * case on any machine.
884 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
886 if (in_interrupt() || oops_in_progress
)
887 panic_nand_wait(mtd
, chip
, timeo
);
889 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
891 if (chip
->dev_ready
) {
892 if (chip
->dev_ready(mtd
))
895 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
899 } while (time_before(jiffies
, timeo
));
902 status
= (int)chip
->read_byte(mtd
);
903 /* This can happen if in case of timeout or buggy dev_ready */
904 WARN_ON(!(status
& NAND_STATUS_READY
));
909 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
911 * @ofs: offset to start unlock from
912 * @len: length to unlock
913 * @invert: when = 0, unlock the range of blocks within the lower and
914 * upper boundary address
915 * when = 1, unlock the range of blocks outside the boundaries
916 * of the lower and upper boundary address
918 * Returs unlock status.
920 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
921 uint64_t len
, int invert
)
925 struct nand_chip
*chip
= mtd_to_nand(mtd
);
927 /* Submit address of first page to unlock */
928 page
= ofs
>> chip
->page_shift
;
929 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
931 /* Submit address of last page to unlock */
932 page
= (ofs
+ len
) >> chip
->page_shift
;
933 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
934 (page
| invert
) & chip
->pagemask
);
936 /* Call wait ready function */
937 status
= chip
->waitfunc(mtd
, chip
);
938 /* See if device thinks it succeeded */
939 if (status
& NAND_STATUS_FAIL
) {
940 pr_debug("%s: error status = 0x%08x\n",
949 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
951 * @ofs: offset to start unlock from
952 * @len: length to unlock
954 * Returns unlock status.
956 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
960 struct nand_chip
*chip
= mtd_to_nand(mtd
);
962 pr_debug("%s: start = 0x%012llx, len = %llu\n",
963 __func__
, (unsigned long long)ofs
, len
);
965 if (check_offs_len(mtd
, ofs
, len
))
968 /* Align to last block address if size addresses end of the device */
969 if (ofs
+ len
== mtd
->size
)
970 len
-= mtd
->erasesize
;
972 nand_get_device(mtd
, FL_UNLOCKING
);
974 /* Shift to get chip number */
975 chipnr
= ofs
>> chip
->chip_shift
;
977 chip
->select_chip(mtd
, chipnr
);
981 * If we want to check the WP through READ STATUS and check the bit 7
982 * we must reset the chip
983 * some operation can also clear the bit 7 of status register
984 * eg. erase/program a locked block
986 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
988 /* Check, if it is write protected */
989 if (nand_check_wp(mtd
)) {
990 pr_debug("%s: device is write protected!\n",
996 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
999 chip
->select_chip(mtd
, -1);
1000 nand_release_device(mtd
);
1004 EXPORT_SYMBOL(nand_unlock
);
1007 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1009 * @ofs: offset to start unlock from
1010 * @len: length to unlock
1012 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1013 * have this feature, but it allows only to lock all blocks, not for specified
1014 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1017 * Returns lock status.
1019 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1022 int chipnr
, status
, page
;
1023 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1025 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1026 __func__
, (unsigned long long)ofs
, len
);
1028 if (check_offs_len(mtd
, ofs
, len
))
1031 nand_get_device(mtd
, FL_LOCKING
);
1033 /* Shift to get chip number */
1034 chipnr
= ofs
>> chip
->chip_shift
;
1036 chip
->select_chip(mtd
, chipnr
);
1040 * If we want to check the WP through READ STATUS and check the bit 7
1041 * we must reset the chip
1042 * some operation can also clear the bit 7 of status register
1043 * eg. erase/program a locked block
1045 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1047 /* Check, if it is write protected */
1048 if (nand_check_wp(mtd
)) {
1049 pr_debug("%s: device is write protected!\n",
1051 status
= MTD_ERASE_FAILED
;
1056 /* Submit address of first page to lock */
1057 page
= ofs
>> chip
->page_shift
;
1058 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1060 /* Call wait ready function */
1061 status
= chip
->waitfunc(mtd
, chip
);
1062 /* See if device thinks it succeeded */
1063 if (status
& NAND_STATUS_FAIL
) {
1064 pr_debug("%s: error status = 0x%08x\n",
1070 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1073 chip
->select_chip(mtd
, -1);
1074 nand_release_device(mtd
);
1078 EXPORT_SYMBOL(nand_lock
);
1081 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1082 * @buf: buffer to test
1083 * @len: buffer length
1084 * @bitflips_threshold: maximum number of bitflips
1086 * Check if a buffer contains only 0xff, which means the underlying region
1087 * has been erased and is ready to be programmed.
1088 * The bitflips_threshold specify the maximum number of bitflips before
1089 * considering the region is not erased.
1090 * Note: The logic of this function has been extracted from the memweight
1091 * implementation, except that nand_check_erased_buf function exit before
1092 * testing the whole buffer if the number of bitflips exceed the
1093 * bitflips_threshold value.
1095 * Returns a positive number of bitflips less than or equal to
1096 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1099 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1101 const unsigned char *bitmap
= buf
;
1105 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1107 weight
= hweight8(*bitmap
);
1108 bitflips
+= BITS_PER_BYTE
- weight
;
1109 if (unlikely(bitflips
> bitflips_threshold
))
1113 for (; len
>= sizeof(long);
1114 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1115 weight
= hweight_long(*((unsigned long *)bitmap
));
1116 bitflips
+= BITS_PER_LONG
- weight
;
1117 if (unlikely(bitflips
> bitflips_threshold
))
1121 for (; len
> 0; len
--, bitmap
++) {
1122 weight
= hweight8(*bitmap
);
1123 bitflips
+= BITS_PER_BYTE
- weight
;
1124 if (unlikely(bitflips
> bitflips_threshold
))
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1134 * @data: data buffer to test
1135 * @datalen: data length
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1170 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1171 void *ecc
, int ecclen
,
1172 void *extraoob
, int extraooblen
,
1173 int bitflips_threshold
)
1175 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1177 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1178 bitflips_threshold
);
1179 if (data_bitflips
< 0)
1180 return data_bitflips
;
1182 bitflips_threshold
-= data_bitflips
;
1184 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1185 if (ecc_bitflips
< 0)
1186 return ecc_bitflips
;
1188 bitflips_threshold
-= ecc_bitflips
;
1190 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1191 bitflips_threshold
);
1192 if (extraoob_bitflips
< 0)
1193 return extraoob_bitflips
;
1196 memset(data
, 0xff, datalen
);
1199 memset(ecc
, 0xff, ecclen
);
1201 if (extraoob_bitflips
)
1202 memset(extraoob
, 0xff, extraooblen
);
1204 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1206 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1213 * @oob_required: caller requires OOB data read to chip->oob_poi
1214 * @page: page number to read
1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1218 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1219 uint8_t *buf
, int oob_required
, int page
)
1221 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1223 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @oob_required: caller requires OOB data read to chip->oob_poi
1233 * @page: page number to read
1235 * We need a special oob layout and handling even when OOB isn't used.
1237 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1238 struct nand_chip
*chip
, uint8_t *buf
,
1239 int oob_required
, int page
)
1241 int eccsize
= chip
->ecc
.size
;
1242 int eccbytes
= chip
->ecc
.bytes
;
1243 uint8_t *oob
= chip
->oob_poi
;
1246 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1247 chip
->read_buf(mtd
, buf
, eccsize
);
1250 if (chip
->ecc
.prepad
) {
1251 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1252 oob
+= chip
->ecc
.prepad
;
1255 chip
->read_buf(mtd
, oob
, eccbytes
);
1258 if (chip
->ecc
.postpad
) {
1259 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1260 oob
+= chip
->ecc
.postpad
;
1264 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1266 chip
->read_buf(mtd
, oob
, size
);
1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1279 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1280 uint8_t *buf
, int oob_required
, int page
)
1282 int i
, eccsize
= chip
->ecc
.size
;
1283 int eccbytes
= chip
->ecc
.bytes
;
1284 int eccsteps
= chip
->ecc
.steps
;
1286 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1287 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1288 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1289 unsigned int max_bitflips
= 0;
1291 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1293 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1294 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1296 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1297 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1299 eccsteps
= chip
->ecc
.steps
;
1302 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1305 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1307 mtd
->ecc_stats
.failed
++;
1309 mtd
->ecc_stats
.corrected
+= stat
;
1310 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1313 return max_bitflips
;
1317 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @data_offs: offset of requested data within the page
1321 * @readlen: data length
1322 * @bufpoi: buffer to store read data
1323 * @page: page number to read
1325 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1326 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1329 int start_step
, end_step
, num_steps
;
1330 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1332 int data_col_addr
, i
, gaps
= 0;
1333 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1334 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1336 unsigned int max_bitflips
= 0;
1338 /* Column address within the page aligned to ECC size (256bytes) */
1339 start_step
= data_offs
/ chip
->ecc
.size
;
1340 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1341 num_steps
= end_step
- start_step
+ 1;
1342 index
= start_step
* chip
->ecc
.bytes
;
1344 /* Data size aligned to ECC ecc.size */
1345 datafrag_len
= num_steps
* chip
->ecc
.size
;
1346 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1348 data_col_addr
= start_step
* chip
->ecc
.size
;
1349 /* If we read not a page aligned data */
1350 if (data_col_addr
!= 0)
1351 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1353 p
= bufpoi
+ data_col_addr
;
1354 chip
->read_buf(mtd
, p
, datafrag_len
);
1357 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1358 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1361 * The performance is faster if we position offsets according to
1362 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1364 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1365 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1371 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1372 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1375 * Send the command to read the particular ECC bytes take care
1376 * about buswidth alignment in read_buf.
1378 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1379 aligned_len
= eccfrag_len
;
1380 if (eccpos
[index
] & (busw
- 1))
1382 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1385 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1386 mtd
->writesize
+ aligned_pos
, -1);
1387 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1390 for (i
= 0; i
< eccfrag_len
; i
++)
1391 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1393 p
= bufpoi
+ data_col_addr
;
1394 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1397 stat
= chip
->ecc
.correct(mtd
, p
,
1398 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1399 if (stat
== -EBADMSG
&&
1400 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1401 /* check for empty pages with bitflips */
1402 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1403 &chip
->buffers
->ecccode
[i
],
1406 chip
->ecc
.strength
);
1410 mtd
->ecc_stats
.failed
++;
1412 mtd
->ecc_stats
.corrected
+= stat
;
1413 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1416 return max_bitflips
;
1420 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1424 * @oob_required: caller requires OOB data read to chip->oob_poi
1425 * @page: page number to read
1427 * Not for syndrome calculating ECC controllers which need a special oob layout.
1429 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1430 uint8_t *buf
, int oob_required
, int page
)
1432 int i
, eccsize
= chip
->ecc
.size
;
1433 int eccbytes
= chip
->ecc
.bytes
;
1434 int eccsteps
= chip
->ecc
.steps
;
1436 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1437 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1438 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1439 unsigned int max_bitflips
= 0;
1441 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1442 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1443 chip
->read_buf(mtd
, p
, eccsize
);
1444 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1446 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1448 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1449 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1451 eccsteps
= chip
->ecc
.steps
;
1454 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1457 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1458 if (stat
== -EBADMSG
&&
1459 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1460 /* check for empty pages with bitflips */
1461 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1462 &ecc_code
[i
], eccbytes
,
1464 chip
->ecc
.strength
);
1468 mtd
->ecc_stats
.failed
++;
1470 mtd
->ecc_stats
.corrected
+= stat
;
1471 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1474 return max_bitflips
;
1478 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @buf: buffer to store read data
1482 * @oob_required: caller requires OOB data read to chip->oob_poi
1483 * @page: page number to read
1485 * Hardware ECC for large page chips, require OOB to be read first. For this
1486 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1487 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1488 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1489 * the data area, by overwriting the NAND manufacturer bad block markings.
1491 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1492 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1494 int i
, eccsize
= chip
->ecc
.size
;
1495 int eccbytes
= chip
->ecc
.bytes
;
1496 int eccsteps
= chip
->ecc
.steps
;
1498 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1499 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1500 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1501 unsigned int max_bitflips
= 0;
1503 /* Read the OOB area first */
1504 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1505 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1506 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1508 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1509 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1511 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1514 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1515 chip
->read_buf(mtd
, p
, eccsize
);
1516 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1518 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1519 if (stat
== -EBADMSG
&&
1520 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1521 /* check for empty pages with bitflips */
1522 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1523 &ecc_code
[i
], eccbytes
,
1525 chip
->ecc
.strength
);
1529 mtd
->ecc_stats
.failed
++;
1531 mtd
->ecc_stats
.corrected
+= stat
;
1532 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1535 return max_bitflips
;
1539 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: buffer to store read data
1543 * @oob_required: caller requires OOB data read to chip->oob_poi
1544 * @page: page number to read
1546 * The hw generator calculates the error syndrome automatically. Therefore we
1547 * need a special oob layout and handling.
1549 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1550 uint8_t *buf
, int oob_required
, int page
)
1552 int i
, eccsize
= chip
->ecc
.size
;
1553 int eccbytes
= chip
->ecc
.bytes
;
1554 int eccsteps
= chip
->ecc
.steps
;
1555 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1557 uint8_t *oob
= chip
->oob_poi
;
1558 unsigned int max_bitflips
= 0;
1560 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1563 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1564 chip
->read_buf(mtd
, p
, eccsize
);
1566 if (chip
->ecc
.prepad
) {
1567 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1568 oob
+= chip
->ecc
.prepad
;
1571 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1572 chip
->read_buf(mtd
, oob
, eccbytes
);
1573 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1577 if (chip
->ecc
.postpad
) {
1578 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1579 oob
+= chip
->ecc
.postpad
;
1582 if (stat
== -EBADMSG
&&
1583 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1584 /* check for empty pages with bitflips */
1585 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1589 chip
->ecc
.strength
);
1593 mtd
->ecc_stats
.failed
++;
1595 mtd
->ecc_stats
.corrected
+= stat
;
1596 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1600 /* Calculate remaining oob bytes */
1601 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1603 chip
->read_buf(mtd
, oob
, i
);
1605 return max_bitflips
;
1609 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1610 * @chip: nand chip structure
1611 * @oob: oob destination address
1612 * @ops: oob ops structure
1613 * @len: size of oob to transfer
1615 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1616 struct mtd_oob_ops
*ops
, size_t len
)
1618 switch (ops
->mode
) {
1620 case MTD_OPS_PLACE_OOB
:
1622 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1625 case MTD_OPS_AUTO_OOB
: {
1626 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1627 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1630 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1631 /* Read request not from offset 0? */
1632 if (unlikely(roffs
)) {
1633 if (roffs
>= free
->length
) {
1634 roffs
-= free
->length
;
1637 boffs
= free
->offset
+ roffs
;
1638 bytes
= min_t(size_t, len
,
1639 (free
->length
- roffs
));
1642 bytes
= min_t(size_t, len
, free
->length
);
1643 boffs
= free
->offset
;
1645 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1657 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1658 * @mtd: MTD device structure
1659 * @retry_mode: the retry mode to use
1661 * Some vendors supply a special command to shift the Vt threshold, to be used
1662 * when there are too many bitflips in a page (i.e., ECC error). After setting
1663 * a new threshold, the host should retry reading the page.
1665 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1667 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1669 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1671 if (retry_mode
>= chip
->read_retries
)
1674 if (!chip
->setup_read_retry
)
1677 return chip
->setup_read_retry(mtd
, retry_mode
);
1681 * nand_do_read_ops - [INTERN] Read data with ECC
1682 * @mtd: MTD device structure
1683 * @from: offset to read from
1684 * @ops: oob ops structure
1686 * Internal function. Called with chip held.
1688 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1689 struct mtd_oob_ops
*ops
)
1691 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1692 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1694 uint32_t readlen
= ops
->len
;
1695 uint32_t oobreadlen
= ops
->ooblen
;
1696 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1698 uint8_t *bufpoi
, *oob
, *buf
;
1700 unsigned int max_bitflips
= 0;
1702 bool ecc_fail
= false;
1704 chipnr
= (int)(from
>> chip
->chip_shift
);
1705 chip
->select_chip(mtd
, chipnr
);
1707 realpage
= (int)(from
>> chip
->page_shift
);
1708 page
= realpage
& chip
->pagemask
;
1710 col
= (int)(from
& (mtd
->writesize
- 1));
1714 oob_required
= oob
? 1 : 0;
1717 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1719 bytes
= min(mtd
->writesize
- col
, readlen
);
1720 aligned
= (bytes
== mtd
->writesize
);
1724 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1725 use_bufpoi
= !virt_addr_valid(buf
);
1729 /* Is the current page in the buffer? */
1730 if (realpage
!= chip
->pagebuf
|| oob
) {
1731 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1733 if (use_bufpoi
&& aligned
)
1734 pr_debug("%s: using read bounce buffer for buf@%p\n",
1738 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1741 * Now read the page into the buffer. Absent an error,
1742 * the read methods return max bitflips per ecc step.
1744 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1745 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1748 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1750 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1754 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1755 oob_required
, page
);
1758 /* Invalidate page cache */
1763 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1765 /* Transfer not aligned data */
1767 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1768 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1769 (ops
->mode
!= MTD_OPS_RAW
)) {
1770 chip
->pagebuf
= realpage
;
1771 chip
->pagebuf_bitflips
= ret
;
1773 /* Invalidate page cache */
1776 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1779 if (unlikely(oob
)) {
1780 int toread
= min(oobreadlen
, max_oobsize
);
1783 oob
= nand_transfer_oob(chip
,
1785 oobreadlen
-= toread
;
1789 if (chip
->options
& NAND_NEED_READRDY
) {
1790 /* Apply delay or wait for ready/busy pin */
1791 if (!chip
->dev_ready
)
1792 udelay(chip
->chip_delay
);
1794 nand_wait_ready(mtd
);
1797 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1798 if (retry_mode
+ 1 < chip
->read_retries
) {
1800 ret
= nand_setup_read_retry(mtd
,
1805 /* Reset failures; retry */
1806 mtd
->ecc_stats
.failed
= ecc_failures
;
1809 /* No more retry modes; real failure */
1816 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1818 max_bitflips
= max_t(unsigned int, max_bitflips
,
1819 chip
->pagebuf_bitflips
);
1824 /* Reset to retry mode 0 */
1826 ret
= nand_setup_read_retry(mtd
, 0);
1835 /* For subsequent reads align to page boundary */
1837 /* Increment page address */
1840 page
= realpage
& chip
->pagemask
;
1841 /* Check, if we cross a chip boundary */
1844 chip
->select_chip(mtd
, -1);
1845 chip
->select_chip(mtd
, chipnr
);
1848 chip
->select_chip(mtd
, -1);
1850 ops
->retlen
= ops
->len
- (size_t) readlen
;
1852 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1860 return max_bitflips
;
1864 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1865 * @mtd: MTD device structure
1866 * @from: offset to read from
1867 * @len: number of bytes to read
1868 * @retlen: pointer to variable to store the number of read bytes
1869 * @buf: the databuffer to put data
1871 * Get hold of the chip and call nand_do_read.
1873 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1874 size_t *retlen
, uint8_t *buf
)
1876 struct mtd_oob_ops ops
;
1879 nand_get_device(mtd
, FL_READING
);
1880 memset(&ops
, 0, sizeof(ops
));
1883 ops
.mode
= MTD_OPS_PLACE_OOB
;
1884 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1885 *retlen
= ops
.retlen
;
1886 nand_release_device(mtd
);
1891 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1892 * @mtd: mtd info structure
1893 * @chip: nand chip info structure
1894 * @page: page number to read
1896 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1899 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1900 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1905 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @page: page number to read
1911 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1914 int length
= mtd
->oobsize
;
1915 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1916 int eccsize
= chip
->ecc
.size
;
1917 uint8_t *bufpoi
= chip
->oob_poi
;
1918 int i
, toread
, sndrnd
= 0, pos
;
1920 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1921 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1923 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1924 if (mtd
->writesize
> 512)
1925 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1927 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1930 toread
= min_t(int, length
, chunk
);
1931 chip
->read_buf(mtd
, bufpoi
, toread
);
1936 chip
->read_buf(mtd
, bufpoi
, length
);
1942 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1943 * @mtd: mtd info structure
1944 * @chip: nand chip info structure
1945 * @page: page number to write
1947 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1951 const uint8_t *buf
= chip
->oob_poi
;
1952 int length
= mtd
->oobsize
;
1954 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1955 chip
->write_buf(mtd
, buf
, length
);
1956 /* Send command to program the OOB data */
1957 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1959 status
= chip
->waitfunc(mtd
, chip
);
1961 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1965 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1966 * with syndrome - only for large page flash
1967 * @mtd: mtd info structure
1968 * @chip: nand chip info structure
1969 * @page: page number to write
1971 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1972 struct nand_chip
*chip
, int page
)
1974 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1975 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1976 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1977 const uint8_t *bufpoi
= chip
->oob_poi
;
1980 * data-ecc-data-ecc ... ecc-oob
1982 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1984 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1985 pos
= steps
* (eccsize
+ chunk
);
1990 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1991 for (i
= 0; i
< steps
; i
++) {
1993 if (mtd
->writesize
<= 512) {
1994 uint32_t fill
= 0xFFFFFFFF;
1998 int num
= min_t(int, len
, 4);
1999 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2004 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2005 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2009 len
= min_t(int, length
, chunk
);
2010 chip
->write_buf(mtd
, bufpoi
, len
);
2015 chip
->write_buf(mtd
, bufpoi
, length
);
2017 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2018 status
= chip
->waitfunc(mtd
, chip
);
2020 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2024 * nand_do_read_oob - [INTERN] NAND read out-of-band
2025 * @mtd: MTD device structure
2026 * @from: offset to read from
2027 * @ops: oob operations description structure
2029 * NAND read out-of-band data from the spare area.
2031 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2032 struct mtd_oob_ops
*ops
)
2034 int page
, realpage
, chipnr
;
2035 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2036 struct mtd_ecc_stats stats
;
2037 int readlen
= ops
->ooblen
;
2039 uint8_t *buf
= ops
->oobbuf
;
2042 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2043 __func__
, (unsigned long long)from
, readlen
);
2045 stats
= mtd
->ecc_stats
;
2047 len
= mtd_oobavail(mtd
, ops
);
2049 if (unlikely(ops
->ooboffs
>= len
)) {
2050 pr_debug("%s: attempt to start read outside oob\n",
2055 /* Do not allow reads past end of device */
2056 if (unlikely(from
>= mtd
->size
||
2057 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2058 (from
>> chip
->page_shift
)) * len
)) {
2059 pr_debug("%s: attempt to read beyond end of device\n",
2064 chipnr
= (int)(from
>> chip
->chip_shift
);
2065 chip
->select_chip(mtd
, chipnr
);
2067 /* Shift to get page */
2068 realpage
= (int)(from
>> chip
->page_shift
);
2069 page
= realpage
& chip
->pagemask
;
2072 if (ops
->mode
== MTD_OPS_RAW
)
2073 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2075 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2080 len
= min(len
, readlen
);
2081 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
2083 if (chip
->options
& NAND_NEED_READRDY
) {
2084 /* Apply delay or wait for ready/busy pin */
2085 if (!chip
->dev_ready
)
2086 udelay(chip
->chip_delay
);
2088 nand_wait_ready(mtd
);
2095 /* Increment page address */
2098 page
= realpage
& chip
->pagemask
;
2099 /* Check, if we cross a chip boundary */
2102 chip
->select_chip(mtd
, -1);
2103 chip
->select_chip(mtd
, chipnr
);
2106 chip
->select_chip(mtd
, -1);
2108 ops
->oobretlen
= ops
->ooblen
- readlen
;
2113 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2116 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2120 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2121 * @mtd: MTD device structure
2122 * @from: offset to read from
2123 * @ops: oob operation description structure
2125 * NAND read data and/or out-of-band data.
2127 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2128 struct mtd_oob_ops
*ops
)
2130 int ret
= -ENOTSUPP
;
2134 /* Do not allow reads past end of device */
2135 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2136 pr_debug("%s: attempt to read beyond end of device\n",
2141 nand_get_device(mtd
, FL_READING
);
2143 switch (ops
->mode
) {
2144 case MTD_OPS_PLACE_OOB
:
2145 case MTD_OPS_AUTO_OOB
:
2154 ret
= nand_do_read_oob(mtd
, from
, ops
);
2156 ret
= nand_do_read_ops(mtd
, from
, ops
);
2159 nand_release_device(mtd
);
2165 * nand_write_page_raw - [INTERN] raw page write function
2166 * @mtd: mtd info structure
2167 * @chip: nand chip info structure
2169 * @oob_required: must write chip->oob_poi to OOB
2170 * @page: page number to write
2172 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2174 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2175 const uint8_t *buf
, int oob_required
, int page
)
2177 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2179 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2185 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2186 * @mtd: mtd info structure
2187 * @chip: nand chip info structure
2189 * @oob_required: must write chip->oob_poi to OOB
2190 * @page: page number to write
2192 * We need a special oob layout and handling even when ECC isn't checked.
2194 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2195 struct nand_chip
*chip
,
2196 const uint8_t *buf
, int oob_required
,
2199 int eccsize
= chip
->ecc
.size
;
2200 int eccbytes
= chip
->ecc
.bytes
;
2201 uint8_t *oob
= chip
->oob_poi
;
2204 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2205 chip
->write_buf(mtd
, buf
, eccsize
);
2208 if (chip
->ecc
.prepad
) {
2209 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2210 oob
+= chip
->ecc
.prepad
;
2213 chip
->write_buf(mtd
, oob
, eccbytes
);
2216 if (chip
->ecc
.postpad
) {
2217 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2218 oob
+= chip
->ecc
.postpad
;
2222 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2224 chip
->write_buf(mtd
, oob
, size
);
2229 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2230 * @mtd: mtd info structure
2231 * @chip: nand chip info structure
2233 * @oob_required: must write chip->oob_poi to OOB
2234 * @page: page number to write
2236 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2237 const uint8_t *buf
, int oob_required
,
2240 int i
, eccsize
= chip
->ecc
.size
;
2241 int eccbytes
= chip
->ecc
.bytes
;
2242 int eccsteps
= chip
->ecc
.steps
;
2243 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2244 const uint8_t *p
= buf
;
2245 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2247 /* Software ECC calculation */
2248 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2249 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2251 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2252 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2254 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2258 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2259 * @mtd: mtd info structure
2260 * @chip: nand chip info structure
2262 * @oob_required: must write chip->oob_poi to OOB
2263 * @page: page number to write
2265 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2266 const uint8_t *buf
, int oob_required
,
2269 int i
, eccsize
= chip
->ecc
.size
;
2270 int eccbytes
= chip
->ecc
.bytes
;
2271 int eccsteps
= chip
->ecc
.steps
;
2272 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2273 const uint8_t *p
= buf
;
2274 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2276 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2277 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2278 chip
->write_buf(mtd
, p
, eccsize
);
2279 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2282 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2283 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2285 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2292 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2293 * @mtd: mtd info structure
2294 * @chip: nand chip info structure
2295 * @offset: column address of subpage within the page
2296 * @data_len: data length
2298 * @oob_required: must write chip->oob_poi to OOB
2299 * @page: page number to write
2301 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2302 struct nand_chip
*chip
, uint32_t offset
,
2303 uint32_t data_len
, const uint8_t *buf
,
2304 int oob_required
, int page
)
2306 uint8_t *oob_buf
= chip
->oob_poi
;
2307 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2308 int ecc_size
= chip
->ecc
.size
;
2309 int ecc_bytes
= chip
->ecc
.bytes
;
2310 int ecc_steps
= chip
->ecc
.steps
;
2311 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2312 uint32_t start_step
= offset
/ ecc_size
;
2313 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2314 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2317 for (step
= 0; step
< ecc_steps
; step
++) {
2318 /* configure controller for WRITE access */
2319 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2321 /* write data (untouched subpages already masked by 0xFF) */
2322 chip
->write_buf(mtd
, buf
, ecc_size
);
2324 /* mask ECC of un-touched subpages by padding 0xFF */
2325 if ((step
< start_step
) || (step
> end_step
))
2326 memset(ecc_calc
, 0xff, ecc_bytes
);
2328 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2330 /* mask OOB of un-touched subpages by padding 0xFF */
2331 /* if oob_required, preserve OOB metadata of written subpage */
2332 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2333 memset(oob_buf
, 0xff, oob_bytes
);
2336 ecc_calc
+= ecc_bytes
;
2337 oob_buf
+= oob_bytes
;
2340 /* copy calculated ECC for whole page to chip->buffer->oob */
2341 /* this include masked-value(0xFF) for unwritten subpages */
2342 ecc_calc
= chip
->buffers
->ecccalc
;
2343 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2344 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2346 /* write OOB buffer to NAND device */
2347 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2354 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2355 * @mtd: mtd info structure
2356 * @chip: nand chip info structure
2358 * @oob_required: must write chip->oob_poi to OOB
2359 * @page: page number to write
2361 * The hw generator calculates the error syndrome automatically. Therefore we
2362 * need a special oob layout and handling.
2364 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2365 struct nand_chip
*chip
,
2366 const uint8_t *buf
, int oob_required
,
2369 int i
, eccsize
= chip
->ecc
.size
;
2370 int eccbytes
= chip
->ecc
.bytes
;
2371 int eccsteps
= chip
->ecc
.steps
;
2372 const uint8_t *p
= buf
;
2373 uint8_t *oob
= chip
->oob_poi
;
2375 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2377 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2378 chip
->write_buf(mtd
, p
, eccsize
);
2380 if (chip
->ecc
.prepad
) {
2381 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2382 oob
+= chip
->ecc
.prepad
;
2385 chip
->ecc
.calculate(mtd
, p
, oob
);
2386 chip
->write_buf(mtd
, oob
, eccbytes
);
2389 if (chip
->ecc
.postpad
) {
2390 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2391 oob
+= chip
->ecc
.postpad
;
2395 /* Calculate remaining oob bytes */
2396 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2398 chip
->write_buf(mtd
, oob
, i
);
2404 * nand_write_page - [REPLACEABLE] write one page
2405 * @mtd: MTD device structure
2406 * @chip: NAND chip descriptor
2407 * @offset: address offset within the page
2408 * @data_len: length of actual data to be written
2409 * @buf: the data to write
2410 * @oob_required: must write chip->oob_poi to OOB
2411 * @page: page number to write
2412 * @cached: cached programming
2413 * @raw: use _raw version of write_page
2415 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2416 uint32_t offset
, int data_len
, const uint8_t *buf
,
2417 int oob_required
, int page
, int cached
, int raw
)
2419 int status
, subpage
;
2421 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2422 chip
->ecc
.write_subpage
)
2423 subpage
= offset
|| (data_len
< mtd
->writesize
);
2427 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2430 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2431 oob_required
, page
);
2433 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2434 buf
, oob_required
, page
);
2436 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2443 * Cached progamming disabled for now. Not sure if it's worth the
2444 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2448 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2450 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2451 status
= chip
->waitfunc(mtd
, chip
);
2453 * See if operation failed and additional status checks are
2456 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2457 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2460 if (status
& NAND_STATUS_FAIL
)
2463 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2464 status
= chip
->waitfunc(mtd
, chip
);
2471 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2472 * @mtd: MTD device structure
2473 * @oob: oob data buffer
2474 * @len: oob data write length
2475 * @ops: oob ops structure
2477 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2478 struct mtd_oob_ops
*ops
)
2480 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2483 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2484 * data from a previous OOB read.
2486 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2488 switch (ops
->mode
) {
2490 case MTD_OPS_PLACE_OOB
:
2492 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2495 case MTD_OPS_AUTO_OOB
: {
2496 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2497 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2500 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2501 /* Write request not from offset 0? */
2502 if (unlikely(woffs
)) {
2503 if (woffs
>= free
->length
) {
2504 woffs
-= free
->length
;
2507 boffs
= free
->offset
+ woffs
;
2508 bytes
= min_t(size_t, len
,
2509 (free
->length
- woffs
));
2512 bytes
= min_t(size_t, len
, free
->length
);
2513 boffs
= free
->offset
;
2515 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2526 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2529 * nand_do_write_ops - [INTERN] NAND write with ECC
2530 * @mtd: MTD device structure
2531 * @to: offset to write to
2532 * @ops: oob operations description structure
2534 * NAND write with ECC.
2536 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2537 struct mtd_oob_ops
*ops
)
2539 int chipnr
, realpage
, page
, blockmask
, column
;
2540 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2541 uint32_t writelen
= ops
->len
;
2543 uint32_t oobwritelen
= ops
->ooblen
;
2544 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2546 uint8_t *oob
= ops
->oobbuf
;
2547 uint8_t *buf
= ops
->datbuf
;
2549 int oob_required
= oob
? 1 : 0;
2555 /* Reject writes, which are not page aligned */
2556 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2557 pr_notice("%s: attempt to write non page aligned data\n",
2562 column
= to
& (mtd
->writesize
- 1);
2564 chipnr
= (int)(to
>> chip
->chip_shift
);
2565 chip
->select_chip(mtd
, chipnr
);
2567 /* Check, if it is write protected */
2568 if (nand_check_wp(mtd
)) {
2573 realpage
= (int)(to
>> chip
->page_shift
);
2574 page
= realpage
& chip
->pagemask
;
2575 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2577 /* Invalidate the page cache, when we write to the cached page */
2578 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2579 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2582 /* Don't allow multipage oob writes with offset */
2583 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2589 int bytes
= mtd
->writesize
;
2590 int cached
= writelen
> bytes
&& page
!= blockmask
;
2591 uint8_t *wbuf
= buf
;
2593 int part_pagewr
= (column
|| writelen
< (mtd
->writesize
- 1));
2597 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2598 use_bufpoi
= !virt_addr_valid(buf
);
2602 /* Partial page write?, or need to use bounce buffer */
2604 pr_debug("%s: using write bounce buffer for buf@%p\n",
2608 bytes
= min_t(int, bytes
- column
, writelen
);
2610 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2611 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2612 wbuf
= chip
->buffers
->databuf
;
2615 if (unlikely(oob
)) {
2616 size_t len
= min(oobwritelen
, oobmaxlen
);
2617 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2620 /* We still need to erase leftover OOB data */
2621 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2623 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2624 oob_required
, page
, cached
,
2625 (ops
->mode
== MTD_OPS_RAW
));
2637 page
= realpage
& chip
->pagemask
;
2638 /* Check, if we cross a chip boundary */
2641 chip
->select_chip(mtd
, -1);
2642 chip
->select_chip(mtd
, chipnr
);
2646 ops
->retlen
= ops
->len
- writelen
;
2648 ops
->oobretlen
= ops
->ooblen
;
2651 chip
->select_chip(mtd
, -1);
2656 * panic_nand_write - [MTD Interface] NAND write with ECC
2657 * @mtd: MTD device structure
2658 * @to: offset to write to
2659 * @len: number of bytes to write
2660 * @retlen: pointer to variable to store the number of written bytes
2661 * @buf: the data to write
2663 * NAND write with ECC. Used when performing writes in interrupt context, this
2664 * may for example be called by mtdoops when writing an oops while in panic.
2666 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2667 size_t *retlen
, const uint8_t *buf
)
2669 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2670 struct mtd_oob_ops ops
;
2673 /* Wait for the device to get ready */
2674 panic_nand_wait(mtd
, chip
, 400);
2676 /* Grab the device */
2677 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2679 memset(&ops
, 0, sizeof(ops
));
2681 ops
.datbuf
= (uint8_t *)buf
;
2682 ops
.mode
= MTD_OPS_PLACE_OOB
;
2684 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2686 *retlen
= ops
.retlen
;
2691 * nand_write - [MTD Interface] NAND write with ECC
2692 * @mtd: MTD device structure
2693 * @to: offset to write to
2694 * @len: number of bytes to write
2695 * @retlen: pointer to variable to store the number of written bytes
2696 * @buf: the data to write
2698 * NAND write with ECC.
2700 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2701 size_t *retlen
, const uint8_t *buf
)
2703 struct mtd_oob_ops ops
;
2706 nand_get_device(mtd
, FL_WRITING
);
2707 memset(&ops
, 0, sizeof(ops
));
2709 ops
.datbuf
= (uint8_t *)buf
;
2710 ops
.mode
= MTD_OPS_PLACE_OOB
;
2711 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2712 *retlen
= ops
.retlen
;
2713 nand_release_device(mtd
);
2718 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2719 * @mtd: MTD device structure
2720 * @to: offset to write to
2721 * @ops: oob operation description structure
2723 * NAND write out-of-band.
2725 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2726 struct mtd_oob_ops
*ops
)
2728 int chipnr
, page
, status
, len
;
2729 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2731 pr_debug("%s: to = 0x%08x, len = %i\n",
2732 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2734 len
= mtd_oobavail(mtd
, ops
);
2736 /* Do not allow write past end of page */
2737 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2738 pr_debug("%s: attempt to write past end of page\n",
2743 if (unlikely(ops
->ooboffs
>= len
)) {
2744 pr_debug("%s: attempt to start write outside oob\n",
2749 /* Do not allow write past end of device */
2750 if (unlikely(to
>= mtd
->size
||
2751 ops
->ooboffs
+ ops
->ooblen
>
2752 ((mtd
->size
>> chip
->page_shift
) -
2753 (to
>> chip
->page_shift
)) * len
)) {
2754 pr_debug("%s: attempt to write beyond end of device\n",
2759 chipnr
= (int)(to
>> chip
->chip_shift
);
2760 chip
->select_chip(mtd
, chipnr
);
2762 /* Shift to get page */
2763 page
= (int)(to
>> chip
->page_shift
);
2766 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2767 * of my DiskOnChip 2000 test units) will clear the whole data page too
2768 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2769 * it in the doc2000 driver in August 1999. dwmw2.
2771 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2773 /* Check, if it is write protected */
2774 if (nand_check_wp(mtd
)) {
2775 chip
->select_chip(mtd
, -1);
2779 /* Invalidate the page cache, if we write to the cached page */
2780 if (page
== chip
->pagebuf
)
2783 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2785 if (ops
->mode
== MTD_OPS_RAW
)
2786 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2788 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2790 chip
->select_chip(mtd
, -1);
2795 ops
->oobretlen
= ops
->ooblen
;
2801 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2802 * @mtd: MTD device structure
2803 * @to: offset to write to
2804 * @ops: oob operation description structure
2806 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2807 struct mtd_oob_ops
*ops
)
2809 int ret
= -ENOTSUPP
;
2813 /* Do not allow writes past end of device */
2814 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2815 pr_debug("%s: attempt to write beyond end of device\n",
2820 nand_get_device(mtd
, FL_WRITING
);
2822 switch (ops
->mode
) {
2823 case MTD_OPS_PLACE_OOB
:
2824 case MTD_OPS_AUTO_OOB
:
2833 ret
= nand_do_write_oob(mtd
, to
, ops
);
2835 ret
= nand_do_write_ops(mtd
, to
, ops
);
2838 nand_release_device(mtd
);
2843 * single_erase - [GENERIC] NAND standard block erase command function
2844 * @mtd: MTD device structure
2845 * @page: the page address of the block which will be erased
2847 * Standard erase command for NAND chips. Returns NAND status.
2849 static int single_erase(struct mtd_info
*mtd
, int page
)
2851 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2852 /* Send commands to erase a block */
2853 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2854 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2856 return chip
->waitfunc(mtd
, chip
);
2860 * nand_erase - [MTD Interface] erase block(s)
2861 * @mtd: MTD device structure
2862 * @instr: erase instruction
2864 * Erase one ore more blocks.
2866 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2868 return nand_erase_nand(mtd
, instr
, 0);
2872 * nand_erase_nand - [INTERN] erase block(s)
2873 * @mtd: MTD device structure
2874 * @instr: erase instruction
2875 * @allowbbt: allow erasing the bbt area
2877 * Erase one ore more blocks.
2879 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2882 int page
, status
, pages_per_block
, ret
, chipnr
;
2883 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2886 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2887 __func__
, (unsigned long long)instr
->addr
,
2888 (unsigned long long)instr
->len
);
2890 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2893 /* Grab the lock and see if the device is available */
2894 nand_get_device(mtd
, FL_ERASING
);
2896 /* Shift to get first page */
2897 page
= (int)(instr
->addr
>> chip
->page_shift
);
2898 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2900 /* Calculate pages in each block */
2901 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2903 /* Select the NAND device */
2904 chip
->select_chip(mtd
, chipnr
);
2906 /* Check, if it is write protected */
2907 if (nand_check_wp(mtd
)) {
2908 pr_debug("%s: device is write protected!\n",
2910 instr
->state
= MTD_ERASE_FAILED
;
2914 /* Loop through the pages */
2917 instr
->state
= MTD_ERASING
;
2920 /* Check if we have a bad block, we do not erase bad blocks! */
2921 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2922 chip
->page_shift
, allowbbt
)) {
2923 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2925 instr
->state
= MTD_ERASE_FAILED
;
2930 * Invalidate the page cache, if we erase the block which
2931 * contains the current cached page.
2933 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2934 (page
+ pages_per_block
))
2937 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2940 * See if operation failed and additional status checks are
2943 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2944 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2947 /* See if block erase succeeded */
2948 if (status
& NAND_STATUS_FAIL
) {
2949 pr_debug("%s: failed erase, page 0x%08x\n",
2951 instr
->state
= MTD_ERASE_FAILED
;
2953 ((loff_t
)page
<< chip
->page_shift
);
2957 /* Increment page address and decrement length */
2958 len
-= (1ULL << chip
->phys_erase_shift
);
2959 page
+= pages_per_block
;
2961 /* Check, if we cross a chip boundary */
2962 if (len
&& !(page
& chip
->pagemask
)) {
2964 chip
->select_chip(mtd
, -1);
2965 chip
->select_chip(mtd
, chipnr
);
2968 instr
->state
= MTD_ERASE_DONE
;
2972 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2974 /* Deselect and wake up anyone waiting on the device */
2975 chip
->select_chip(mtd
, -1);
2976 nand_release_device(mtd
);
2978 /* Do call back function */
2980 mtd_erase_callback(instr
);
2982 /* Return more or less happy */
2987 * nand_sync - [MTD Interface] sync
2988 * @mtd: MTD device structure
2990 * Sync is actually a wait for chip ready function.
2992 static void nand_sync(struct mtd_info
*mtd
)
2994 pr_debug("%s: called\n", __func__
);
2996 /* Grab the lock and see if the device is available */
2997 nand_get_device(mtd
, FL_SYNCING
);
2998 /* Release it and go back */
2999 nand_release_device(mtd
);
3003 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3004 * @mtd: MTD device structure
3005 * @offs: offset relative to mtd start
3007 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3009 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3010 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3013 /* Select the NAND device */
3014 nand_get_device(mtd
, FL_READING
);
3015 chip
->select_chip(mtd
, chipnr
);
3017 ret
= nand_block_checkbad(mtd
, offs
, 0);
3019 chip
->select_chip(mtd
, -1);
3020 nand_release_device(mtd
);
3026 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3027 * @mtd: MTD device structure
3028 * @ofs: offset relative to mtd start
3030 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3034 ret
= nand_block_isbad(mtd
, ofs
);
3036 /* If it was bad already, return success and do nothing */
3042 return nand_block_markbad_lowlevel(mtd
, ofs
);
3046 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3047 * @mtd: MTD device structure
3048 * @chip: nand chip info structure
3049 * @addr: feature address.
3050 * @subfeature_param: the subfeature parameters, a four bytes array.
3052 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3053 int addr
, uint8_t *subfeature_param
)
3058 if (!chip
->onfi_version
||
3059 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3060 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3063 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3064 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3065 chip
->write_byte(mtd
, subfeature_param
[i
]);
3067 status
= chip
->waitfunc(mtd
, chip
);
3068 if (status
& NAND_STATUS_FAIL
)
3074 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3075 * @mtd: MTD device structure
3076 * @chip: nand chip info structure
3077 * @addr: feature address.
3078 * @subfeature_param: the subfeature parameters, a four bytes array.
3080 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3081 int addr
, uint8_t *subfeature_param
)
3085 if (!chip
->onfi_version
||
3086 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3087 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3090 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3091 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3092 *subfeature_param
++ = chip
->read_byte(mtd
);
3097 * nand_suspend - [MTD Interface] Suspend the NAND flash
3098 * @mtd: MTD device structure
3100 static int nand_suspend(struct mtd_info
*mtd
)
3102 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3106 * nand_resume - [MTD Interface] Resume the NAND flash
3107 * @mtd: MTD device structure
3109 static void nand_resume(struct mtd_info
*mtd
)
3111 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3113 if (chip
->state
== FL_PM_SUSPENDED
)
3114 nand_release_device(mtd
);
3116 pr_err("%s called for a chip which is not in suspended state\n",
3121 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3122 * prevent further operations
3123 * @mtd: MTD device structure
3125 static void nand_shutdown(struct mtd_info
*mtd
)
3127 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3130 /* Set default functions */
3131 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3133 /* check for proper chip_delay setup, set 20us if not */
3134 if (!chip
->chip_delay
)
3135 chip
->chip_delay
= 20;
3137 /* check, if a user supplied command function given */
3138 if (chip
->cmdfunc
== NULL
)
3139 chip
->cmdfunc
= nand_command
;
3141 /* check, if a user supplied wait function given */
3142 if (chip
->waitfunc
== NULL
)
3143 chip
->waitfunc
= nand_wait
;
3145 if (!chip
->select_chip
)
3146 chip
->select_chip
= nand_select_chip
;
3148 /* set for ONFI nand */
3149 if (!chip
->onfi_set_features
)
3150 chip
->onfi_set_features
= nand_onfi_set_features
;
3151 if (!chip
->onfi_get_features
)
3152 chip
->onfi_get_features
= nand_onfi_get_features
;
3154 /* If called twice, pointers that depend on busw may need to be reset */
3155 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3156 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3157 if (!chip
->read_word
)
3158 chip
->read_word
= nand_read_word
;
3159 if (!chip
->block_bad
)
3160 chip
->block_bad
= nand_block_bad
;
3161 if (!chip
->block_markbad
)
3162 chip
->block_markbad
= nand_default_block_markbad
;
3163 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3164 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3165 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3166 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3167 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3168 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3169 if (!chip
->scan_bbt
)
3170 chip
->scan_bbt
= nand_default_bbt
;
3172 if (!chip
->controller
) {
3173 chip
->controller
= &chip
->hwcontrol
;
3174 spin_lock_init(&chip
->controller
->lock
);
3175 init_waitqueue_head(&chip
->controller
->wq
);
3180 /* Sanitize ONFI strings so we can safely print them */
3181 static void sanitize_string(uint8_t *s
, size_t len
)
3185 /* Null terminate */
3188 /* Remove non printable chars */
3189 for (i
= 0; i
< len
- 1; i
++) {
3190 if (s
[i
] < ' ' || s
[i
] > 127)
3194 /* Remove trailing spaces */
3198 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3203 for (i
= 0; i
< 8; i
++)
3204 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3210 /* Parse the Extended Parameter Page. */
3211 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3212 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3214 struct onfi_ext_param_page
*ep
;
3215 struct onfi_ext_section
*s
;
3216 struct onfi_ext_ecc_info
*ecc
;
3222 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3223 ep
= kmalloc(len
, GFP_KERNEL
);
3227 /* Send our own NAND_CMD_PARAM. */
3228 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3230 /* Use the Change Read Column command to skip the ONFI param pages. */
3231 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3232 sizeof(*p
) * p
->num_of_param_pages
, -1);
3234 /* Read out the Extended Parameter Page. */
3235 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3236 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3237 != le16_to_cpu(ep
->crc
))) {
3238 pr_debug("fail in the CRC.\n");
3243 * Check the signature.
3244 * Do not strictly follow the ONFI spec, maybe changed in future.
3246 if (strncmp(ep
->sig
, "EPPS", 4)) {
3247 pr_debug("The signature is invalid.\n");
3251 /* find the ECC section. */
3252 cursor
= (uint8_t *)(ep
+ 1);
3253 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3254 s
= ep
->sections
+ i
;
3255 if (s
->type
== ONFI_SECTION_TYPE_2
)
3257 cursor
+= s
->length
* 16;
3259 if (i
== ONFI_EXT_SECTION_MAX
) {
3260 pr_debug("We can not find the ECC section.\n");
3264 /* get the info we want. */
3265 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3267 if (!ecc
->codeword_size
) {
3268 pr_debug("Invalid codeword size\n");
3272 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3273 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3281 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3283 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3284 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3286 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3291 * Configure chip properties from Micron vendor-specific ONFI table
3293 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3294 struct nand_onfi_params
*p
)
3296 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3298 if (le16_to_cpu(p
->vendor_revision
) < 1)
3301 chip
->read_retries
= micron
->read_retry_options
;
3302 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3306 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3308 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3311 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3315 /* Try ONFI for unknown chip or LP */
3316 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3317 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3318 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3321 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3322 for (i
= 0; i
< 3; i
++) {
3323 for (j
= 0; j
< sizeof(*p
); j
++)
3324 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3325 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3326 le16_to_cpu(p
->crc
)) {
3332 pr_err("Could not find valid ONFI parameter page; aborting\n");
3337 val
= le16_to_cpu(p
->revision
);
3339 chip
->onfi_version
= 23;
3340 else if (val
& (1 << 4))
3341 chip
->onfi_version
= 22;
3342 else if (val
& (1 << 3))
3343 chip
->onfi_version
= 21;
3344 else if (val
& (1 << 2))
3345 chip
->onfi_version
= 20;
3346 else if (val
& (1 << 1))
3347 chip
->onfi_version
= 10;
3349 if (!chip
->onfi_version
) {
3350 pr_info("unsupported ONFI version: %d\n", val
);
3354 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3355 sanitize_string(p
->model
, sizeof(p
->model
));
3357 mtd
->name
= p
->model
;
3359 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3362 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3363 * (don't ask me who thought of this...). MTD assumes that these
3364 * dimensions will be power-of-2, so just truncate the remaining area.
3366 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3367 mtd
->erasesize
*= mtd
->writesize
;
3369 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3371 /* See erasesize comment */
3372 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3373 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3374 chip
->bits_per_cell
= p
->bits_per_cell
;
3376 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3377 *busw
= NAND_BUSWIDTH_16
;
3381 if (p
->ecc_bits
!= 0xff) {
3382 chip
->ecc_strength_ds
= p
->ecc_bits
;
3383 chip
->ecc_step_ds
= 512;
3384 } else if (chip
->onfi_version
>= 21 &&
3385 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3388 * The nand_flash_detect_ext_param_page() uses the
3389 * Change Read Column command which maybe not supported
3390 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3391 * now. We do not replace user supplied command function.
3393 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3394 chip
->cmdfunc
= nand_command_lp
;
3396 /* The Extended Parameter Page is supported since ONFI 2.1. */
3397 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3398 pr_warn("Failed to detect ONFI extended param page\n");
3400 pr_warn("Could not retrieve ONFI ECC requirements\n");
3403 if (p
->jedec_id
== NAND_MFR_MICRON
)
3404 nand_onfi_detect_micron(chip
, p
);
3410 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3412 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3415 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3416 struct jedec_ecc_info
*ecc
;
3420 /* Try JEDEC for unknown chip or LP */
3421 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3422 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3423 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3424 chip
->read_byte(mtd
) != 'C')
3427 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3428 for (i
= 0; i
< 3; i
++) {
3429 for (j
= 0; j
< sizeof(*p
); j
++)
3430 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3432 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3433 le16_to_cpu(p
->crc
))
3438 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3443 val
= le16_to_cpu(p
->revision
);
3445 chip
->jedec_version
= 10;
3446 else if (val
& (1 << 1))
3447 chip
->jedec_version
= 1; /* vendor specific version */
3449 if (!chip
->jedec_version
) {
3450 pr_info("unsupported JEDEC version: %d\n", val
);
3454 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3455 sanitize_string(p
->model
, sizeof(p
->model
));
3457 mtd
->name
= p
->model
;
3459 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3461 /* Please reference to the comment for nand_flash_detect_onfi. */
3462 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3463 mtd
->erasesize
*= mtd
->writesize
;
3465 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3467 /* Please reference to the comment for nand_flash_detect_onfi. */
3468 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3469 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3470 chip
->bits_per_cell
= p
->bits_per_cell
;
3472 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3473 *busw
= NAND_BUSWIDTH_16
;
3478 ecc
= &p
->ecc_info
[0];
3480 if (ecc
->codeword_size
>= 9) {
3481 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3482 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3484 pr_warn("Invalid codeword size\n");
3491 * nand_id_has_period - Check if an ID string has a given wraparound period
3492 * @id_data: the ID string
3493 * @arrlen: the length of the @id_data array
3494 * @period: the period of repitition
3496 * Check if an ID string is repeated within a given sequence of bytes at
3497 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3498 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3499 * if the repetition has a period of @period; otherwise, returns zero.
3501 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3504 for (i
= 0; i
< period
; i
++)
3505 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3506 if (id_data
[i
] != id_data
[j
])
3512 * nand_id_len - Get the length of an ID string returned by CMD_READID
3513 * @id_data: the ID string
3514 * @arrlen: the length of the @id_data array
3516 * Returns the length of the ID string, according to known wraparound/trailing
3517 * zero patterns. If no pattern exists, returns the length of the array.
3519 static int nand_id_len(u8
*id_data
, int arrlen
)
3521 int last_nonzero
, period
;
3523 /* Find last non-zero byte */
3524 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3525 if (id_data
[last_nonzero
])
3529 if (last_nonzero
< 0)
3532 /* Calculate wraparound period */
3533 for (period
= 1; period
< arrlen
; period
++)
3534 if (nand_id_has_period(id_data
, arrlen
, period
))
3537 /* There's a repeated pattern */
3538 if (period
< arrlen
)
3541 /* There are trailing zeros */
3542 if (last_nonzero
< arrlen
- 1)
3543 return last_nonzero
+ 1;
3545 /* No pattern detected */
3549 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3550 static int nand_get_bits_per_cell(u8 cellinfo
)
3554 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3555 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3560 * Many new NAND share similar device ID codes, which represent the size of the
3561 * chip. The rest of the parameters must be decoded according to generic or
3562 * manufacturer-specific "extended ID" decoding patterns.
3564 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3565 u8 id_data
[8], int *busw
)
3568 /* The 3rd id byte holds MLC / multichip data */
3569 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3570 /* The 4th id byte is the important one */
3573 id_len
= nand_id_len(id_data
, 8);
3576 * Field definitions are in the following datasheets:
3577 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3578 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3579 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3581 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3582 * ID to decide what to do.
3584 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3585 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3587 mtd
->writesize
= 2048 << (extid
& 0x03);
3590 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3610 default: /* Other cases are "reserved" (unknown) */
3611 mtd
->oobsize
= 1024;
3615 /* Calc blocksize */
3616 mtd
->erasesize
= (128 * 1024) <<
3617 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3619 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3620 !nand_is_slc(chip
)) {
3624 mtd
->writesize
= 2048 << (extid
& 0x03);
3627 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3651 /* Calc blocksize */
3652 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3654 mtd
->erasesize
= (128 * 1024) << tmp
;
3655 else if (tmp
== 0x03)
3656 mtd
->erasesize
= 768 * 1024;
3658 mtd
->erasesize
= (64 * 1024) << tmp
;
3662 mtd
->writesize
= 1024 << (extid
& 0x03);
3665 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3666 (mtd
->writesize
>> 9);
3668 /* Calc blocksize. Blocksize is multiples of 64KiB */
3669 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3671 /* Get buswidth information */
3672 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3675 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3676 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3678 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3680 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3682 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3683 nand_is_slc(chip
) &&
3684 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3685 !(id_data
[4] & 0x80) /* !BENAND */) {
3686 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3693 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3694 * decodes a matching ID table entry and assigns the MTD size parameters for
3697 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3698 struct nand_flash_dev
*type
, u8 id_data
[8],
3701 int maf_id
= id_data
[0];
3703 mtd
->erasesize
= type
->erasesize
;
3704 mtd
->writesize
= type
->pagesize
;
3705 mtd
->oobsize
= mtd
->writesize
/ 32;
3706 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3708 /* All legacy ID NAND are small-page, SLC */
3709 chip
->bits_per_cell
= 1;
3712 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3713 * some Spansion chips have erasesize that conflicts with size
3714 * listed in nand_ids table.
3715 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3717 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3718 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3719 && mtd
->writesize
== 512) {
3720 mtd
->erasesize
= 128 * 1024;
3721 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3726 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3727 * heuristic patterns using various detected parameters (e.g., manufacturer,
3728 * page size, cell-type information).
3730 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3731 struct nand_chip
*chip
, u8 id_data
[8])
3733 int maf_id
= id_data
[0];
3735 /* Set the bad block position */
3736 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3737 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3739 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3742 * Bad block marker is stored in the last page of each block on Samsung
3743 * and Hynix MLC devices; stored in first two pages of each block on
3744 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3745 * AMD/Spansion, and Macronix. All others scan only the first page.
3747 if (!nand_is_slc(chip
) &&
3748 (maf_id
== NAND_MFR_SAMSUNG
||
3749 maf_id
== NAND_MFR_HYNIX
))
3750 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3751 else if ((nand_is_slc(chip
) &&
3752 (maf_id
== NAND_MFR_SAMSUNG
||
3753 maf_id
== NAND_MFR_HYNIX
||
3754 maf_id
== NAND_MFR_TOSHIBA
||
3755 maf_id
== NAND_MFR_AMD
||
3756 maf_id
== NAND_MFR_MACRONIX
)) ||
3757 (mtd
->writesize
== 2048 &&
3758 maf_id
== NAND_MFR_MICRON
))
3759 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3762 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3764 return type
->id_len
;
3767 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3768 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3770 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3771 mtd
->writesize
= type
->pagesize
;
3772 mtd
->erasesize
= type
->erasesize
;
3773 mtd
->oobsize
= type
->oobsize
;
3775 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3776 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3777 chip
->options
|= type
->options
;
3778 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3779 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3780 chip
->onfi_timing_mode_default
=
3781 type
->onfi_timing_mode_default
;
3783 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3786 mtd
->name
= type
->name
;
3794 * Get the flash and manufacturer id and lookup if the type is supported.
3796 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3797 struct nand_chip
*chip
,
3798 int *maf_id
, int *dev_id
,
3799 struct nand_flash_dev
*type
)
3805 /* Select the device */
3806 chip
->select_chip(mtd
, 0);
3809 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3812 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3814 /* Send the command for reading device ID */
3815 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3817 /* Read manufacturer and device IDs */
3818 *maf_id
= chip
->read_byte(mtd
);
3819 *dev_id
= chip
->read_byte(mtd
);
3822 * Try again to make sure, as some systems the bus-hold or other
3823 * interface concerns can cause random data which looks like a
3824 * possibly credible NAND flash to appear. If the two results do
3825 * not match, ignore the device completely.
3828 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3830 /* Read entire ID string */
3831 for (i
= 0; i
< 8; i
++)
3832 id_data
[i
] = chip
->read_byte(mtd
);
3834 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3835 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3836 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3837 return ERR_PTR(-ENODEV
);
3841 type
= nand_flash_ids
;
3843 for (; type
->name
!= NULL
; type
++) {
3844 if (is_full_id_nand(type
)) {
3845 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3847 } else if (*dev_id
== type
->dev_id
) {
3852 chip
->onfi_version
= 0;
3853 if (!type
->name
|| !type
->pagesize
) {
3854 /* Check if the chip is ONFI compliant */
3855 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3858 /* Check if the chip is JEDEC compliant */
3859 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3864 return ERR_PTR(-ENODEV
);
3867 mtd
->name
= type
->name
;
3869 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3871 if (!type
->pagesize
) {
3872 /* Decode parameters from extended ID */
3873 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3875 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3877 /* Get chip options */
3878 chip
->options
|= type
->options
;
3881 * Check if chip is not a Samsung device. Do not clear the
3882 * options for chips which do not have an extended id.
3884 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3885 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3888 /* Try to identify manufacturer */
3889 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3890 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3894 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3895 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3896 chip
->options
|= busw
;
3897 nand_set_defaults(chip
, busw
);
3898 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3900 * Check, if buswidth is correct. Hardware drivers should set
3903 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3905 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3906 pr_warn("bus width %d instead %d bit\n",
3907 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3909 return ERR_PTR(-EINVAL
);
3912 nand_decode_bbm_options(mtd
, chip
, id_data
);
3914 /* Calculate the address shift from the page size */
3915 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3916 /* Convert chipsize to number of pages per chip -1 */
3917 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3919 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3920 ffs(mtd
->erasesize
) - 1;
3921 if (chip
->chipsize
& 0xffffffff)
3922 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3924 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3925 chip
->chip_shift
+= 32 - 1;
3928 chip
->badblockbits
= 8;
3929 chip
->erase
= single_erase
;
3931 /* Do not replace user supplied command function! */
3932 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3933 chip
->cmdfunc
= nand_command_lp
;
3935 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3938 if (chip
->onfi_version
)
3939 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3940 chip
->onfi_params
.model
);
3941 else if (chip
->jedec_version
)
3942 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3943 chip
->jedec_params
.model
);
3945 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3948 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3949 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3950 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3954 static int nand_dt_init(struct nand_chip
*chip
)
3956 struct device_node
*dn
= nand_get_flash_node(chip
);
3957 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
3962 if (of_get_nand_bus_width(dn
) == 16)
3963 chip
->options
|= NAND_BUSWIDTH_16
;
3965 if (of_get_nand_on_flash_bbt(dn
))
3966 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3968 ecc_mode
= of_get_nand_ecc_mode(dn
);
3969 ecc_algo
= of_get_nand_ecc_algo(dn
);
3970 ecc_strength
= of_get_nand_ecc_strength(dn
);
3971 ecc_step
= of_get_nand_ecc_step_size(dn
);
3973 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3974 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3975 pr_err("must set both strength and step size in DT\n");
3980 chip
->ecc
.mode
= ecc_mode
;
3983 chip
->ecc
.algo
= ecc_algo
;
3985 if (ecc_strength
>= 0)
3986 chip
->ecc
.strength
= ecc_strength
;
3989 chip
->ecc
.size
= ecc_step
;
3995 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3996 * @mtd: MTD device structure
3997 * @maxchips: number of chips to scan for
3998 * @table: alternative NAND ID table
4000 * This is the first phase of the normal nand_scan() function. It reads the
4001 * flash ID and sets up MTD fields accordingly.
4003 * The mtd->owner field must be set to the module of the caller.
4005 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4006 struct nand_flash_dev
*table
)
4008 int i
, nand_maf_id
, nand_dev_id
;
4009 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4010 struct nand_flash_dev
*type
;
4013 ret
= nand_dt_init(chip
);
4017 if (!mtd
->name
&& mtd
->dev
.parent
)
4018 mtd
->name
= dev_name(mtd
->dev
.parent
);
4020 /* Set the default functions */
4021 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4023 /* Read the flash type */
4024 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4025 &nand_dev_id
, table
);
4028 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4029 pr_warn("No NAND device found\n");
4030 chip
->select_chip(mtd
, -1);
4031 return PTR_ERR(type
);
4034 chip
->select_chip(mtd
, -1);
4036 /* Check for a chip array */
4037 for (i
= 1; i
< maxchips
; i
++) {
4038 chip
->select_chip(mtd
, i
);
4039 /* See comment in nand_get_flash_type for reset */
4040 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
4041 /* Send the command for reading device ID */
4042 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4043 /* Read manufacturer and device IDs */
4044 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4045 nand_dev_id
!= chip
->read_byte(mtd
)) {
4046 chip
->select_chip(mtd
, -1);
4049 chip
->select_chip(mtd
, -1);
4052 pr_info("%d chips detected\n", i
);
4054 /* Store the number of chips and calc total size for mtd */
4056 mtd
->size
= i
* chip
->chipsize
;
4060 EXPORT_SYMBOL(nand_scan_ident
);
4063 * Check if the chip configuration meet the datasheet requirements.
4065 * If our configuration corrects A bits per B bytes and the minimum
4066 * required correction level is X bits per Y bytes, then we must ensure
4067 * both of the following are true:
4069 * (1) A / B >= X / Y
4072 * Requirement (1) ensures we can correct for the required bitflip density.
4073 * Requirement (2) ensures we can correct even when all bitflips are clumped
4074 * in the same sector.
4076 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4078 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4079 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4082 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4083 /* Not enough information */
4087 * We get the number of corrected bits per page to compare
4088 * the correction density.
4090 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4091 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4093 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4097 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4098 * @mtd: MTD device structure
4100 * This is the second phase of the normal nand_scan() function. It fills out
4101 * all the uninitialized function pointers with the defaults and scans for a
4102 * bad block table if appropriate.
4104 int nand_scan_tail(struct mtd_info
*mtd
)
4107 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4108 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4109 struct nand_buffers
*nbuf
;
4111 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4112 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4113 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
4115 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4116 nbuf
= kzalloc(sizeof(*nbuf
) + mtd
->writesize
4117 + mtd
->oobsize
* 3, GFP_KERNEL
);
4120 nbuf
->ecccalc
= (uint8_t *)(nbuf
+ 1);
4121 nbuf
->ecccode
= nbuf
->ecccalc
+ mtd
->oobsize
;
4122 nbuf
->databuf
= nbuf
->ecccode
+ mtd
->oobsize
;
4124 chip
->buffers
= nbuf
;
4130 /* Set the internal oob buffer location, just after the page data */
4131 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4134 * If no default placement scheme is given, select an appropriate one.
4136 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4137 switch (mtd
->oobsize
) {
4139 ecc
->layout
= &nand_oob_8
;
4142 ecc
->layout
= &nand_oob_16
;
4145 ecc
->layout
= &nand_oob_64
;
4148 ecc
->layout
= &nand_oob_128
;
4151 pr_warn("No oob scheme defined for oobsize %d\n",
4157 if (!chip
->write_page
)
4158 chip
->write_page
= nand_write_page
;
4161 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4162 * selected and we have 256 byte pagesize fallback to software ECC
4165 switch (ecc
->mode
) {
4166 case NAND_ECC_HW_OOB_FIRST
:
4167 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4168 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4169 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4172 if (!ecc
->read_page
)
4173 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4176 /* Use standard hwecc read page function? */
4177 if (!ecc
->read_page
)
4178 ecc
->read_page
= nand_read_page_hwecc
;
4179 if (!ecc
->write_page
)
4180 ecc
->write_page
= nand_write_page_hwecc
;
4181 if (!ecc
->read_page_raw
)
4182 ecc
->read_page_raw
= nand_read_page_raw
;
4183 if (!ecc
->write_page_raw
)
4184 ecc
->write_page_raw
= nand_write_page_raw
;
4186 ecc
->read_oob
= nand_read_oob_std
;
4187 if (!ecc
->write_oob
)
4188 ecc
->write_oob
= nand_write_oob_std
;
4189 if (!ecc
->read_subpage
)
4190 ecc
->read_subpage
= nand_read_subpage
;
4191 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4192 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4194 case NAND_ECC_HW_SYNDROME
:
4195 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4197 ecc
->read_page
== nand_read_page_hwecc
||
4199 ecc
->write_page
== nand_write_page_hwecc
)) {
4200 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4203 /* Use standard syndrome read/write page function? */
4204 if (!ecc
->read_page
)
4205 ecc
->read_page
= nand_read_page_syndrome
;
4206 if (!ecc
->write_page
)
4207 ecc
->write_page
= nand_write_page_syndrome
;
4208 if (!ecc
->read_page_raw
)
4209 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4210 if (!ecc
->write_page_raw
)
4211 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4213 ecc
->read_oob
= nand_read_oob_syndrome
;
4214 if (!ecc
->write_oob
)
4215 ecc
->write_oob
= nand_write_oob_syndrome
;
4217 if (mtd
->writesize
>= ecc
->size
) {
4218 if (!ecc
->strength
) {
4219 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4224 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4225 ecc
->size
, mtd
->writesize
);
4226 ecc
->mode
= NAND_ECC_SOFT
;
4229 ecc
->calculate
= nand_calculate_ecc
;
4230 ecc
->correct
= nand_correct_data
;
4231 ecc
->read_page
= nand_read_page_swecc
;
4232 ecc
->read_subpage
= nand_read_subpage
;
4233 ecc
->write_page
= nand_write_page_swecc
;
4234 ecc
->read_page_raw
= nand_read_page_raw
;
4235 ecc
->write_page_raw
= nand_write_page_raw
;
4236 ecc
->read_oob
= nand_read_oob_std
;
4237 ecc
->write_oob
= nand_write_oob_std
;
4244 case NAND_ECC_SOFT_BCH
:
4245 if (!mtd_nand_has_bch()) {
4246 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4249 ecc
->calculate
= nand_bch_calculate_ecc
;
4250 ecc
->correct
= nand_bch_correct_data
;
4251 ecc
->read_page
= nand_read_page_swecc
;
4252 ecc
->read_subpage
= nand_read_subpage
;
4253 ecc
->write_page
= nand_write_page_swecc
;
4254 ecc
->read_page_raw
= nand_read_page_raw
;
4255 ecc
->write_page_raw
= nand_write_page_raw
;
4256 ecc
->read_oob
= nand_read_oob_std
;
4257 ecc
->write_oob
= nand_write_oob_std
;
4259 * Board driver should supply ecc.size and ecc.strength values
4260 * to select how many bits are correctable. Otherwise, default
4261 * to 4 bits for large page devices.
4263 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4268 /* See nand_bch_init() for details. */
4270 ecc
->priv
= nand_bch_init(mtd
);
4272 pr_warn("BCH ECC initialization failed!\n");
4278 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4279 ecc
->read_page
= nand_read_page_raw
;
4280 ecc
->write_page
= nand_write_page_raw
;
4281 ecc
->read_oob
= nand_read_oob_std
;
4282 ecc
->read_page_raw
= nand_read_page_raw
;
4283 ecc
->write_page_raw
= nand_write_page_raw
;
4284 ecc
->write_oob
= nand_write_oob_std
;
4285 ecc
->size
= mtd
->writesize
;
4291 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4295 /* For many systems, the standard OOB write also works for raw */
4296 if (!ecc
->read_oob_raw
)
4297 ecc
->read_oob_raw
= ecc
->read_oob
;
4298 if (!ecc
->write_oob_raw
)
4299 ecc
->write_oob_raw
= ecc
->write_oob
;
4302 * The number of bytes available for a client to place data into
4303 * the out of band area.
4307 for (i
= 0; ecc
->layout
->oobfree
[i
].length
; i
++)
4308 mtd
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4311 /* ECC sanity check: warn if it's too weak */
4312 if (!nand_ecc_strength_good(mtd
))
4313 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4317 * Set the number of read / write steps for one page depending on ECC
4320 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4321 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4322 pr_warn("Invalid ECC parameters\n");
4325 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4327 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4328 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4329 switch (ecc
->steps
) {
4331 mtd
->subpage_sft
= 1;
4336 mtd
->subpage_sft
= 2;
4340 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4342 /* Initialize state */
4343 chip
->state
= FL_READY
;
4345 /* Invalidate the pagebuffer reference */
4348 /* Large page NAND with SOFT_ECC should support subpage reads */
4349 switch (ecc
->mode
) {
4351 case NAND_ECC_SOFT_BCH
:
4352 if (chip
->page_shift
> 9)
4353 chip
->options
|= NAND_SUBPAGE_READ
;
4360 /* Fill in remaining MTD driver data */
4361 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4362 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4364 mtd
->_erase
= nand_erase
;
4366 mtd
->_unpoint
= NULL
;
4367 mtd
->_read
= nand_read
;
4368 mtd
->_write
= nand_write
;
4369 mtd
->_panic_write
= panic_nand_write
;
4370 mtd
->_read_oob
= nand_read_oob
;
4371 mtd
->_write_oob
= nand_write_oob
;
4372 mtd
->_sync
= nand_sync
;
4374 mtd
->_unlock
= NULL
;
4375 mtd
->_suspend
= nand_suspend
;
4376 mtd
->_resume
= nand_resume
;
4377 mtd
->_reboot
= nand_shutdown
;
4378 mtd
->_block_isreserved
= nand_block_isreserved
;
4379 mtd
->_block_isbad
= nand_block_isbad
;
4380 mtd
->_block_markbad
= nand_block_markbad
;
4381 mtd
->writebufsize
= mtd
->writesize
;
4383 /* propagate ecc info to mtd_info */
4384 mtd
->ecclayout
= ecc
->layout
;
4385 mtd
->ecc_strength
= ecc
->strength
;
4386 mtd
->ecc_step_size
= ecc
->size
;
4388 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4389 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4392 if (!mtd
->bitflip_threshold
)
4393 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4395 /* Check, if we should skip the bad block table scan */
4396 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4399 /* Build bad block table */
4400 return chip
->scan_bbt(mtd
);
4402 EXPORT_SYMBOL(nand_scan_tail
);
4405 * is_module_text_address() isn't exported, and it's mostly a pointless
4406 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4407 * to call us from in-kernel code if the core NAND support is modular.
4410 #define caller_is_module() (1)
4412 #define caller_is_module() \
4413 is_module_text_address((unsigned long)__builtin_return_address(0))
4417 * nand_scan - [NAND Interface] Scan for the NAND device
4418 * @mtd: MTD device structure
4419 * @maxchips: number of chips to scan for
4421 * This fills out all the uninitialized function pointers with the defaults.
4422 * The flash ID is read and the mtd/chip structures are filled with the
4423 * appropriate values. The mtd->owner field must be set to the module of the
4426 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4430 /* Many callers got this wrong, so check for it for a while... */
4431 if (!mtd
->owner
&& caller_is_module()) {
4432 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
4436 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4438 ret
= nand_scan_tail(mtd
);
4441 EXPORT_SYMBOL(nand_scan
);
4444 * nand_release - [NAND Interface] Free resources held by the NAND device
4445 * @mtd: MTD device structure
4447 void nand_release(struct mtd_info
*mtd
)
4449 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4451 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
4452 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
4454 mtd_device_unregister(mtd
);
4456 /* Free bad block table memory */
4458 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4459 kfree(chip
->buffers
);
4461 /* Free bad block descriptor memory */
4462 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
4463 & NAND_BBT_DYNAMICSTRUCT
)
4464 kfree(chip
->badblock_pattern
);
4466 EXPORT_SYMBOL_GPL(nand_release
);
4468 MODULE_LICENSE("GPL");
4469 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4470 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4471 MODULE_DESCRIPTION("Generic NAND flash driver code");