3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
47 #include <linux/mtd/partitions.h>
48 #include <linux/of_mtd.h>
50 /* Define default oob placement schemes for large and small page devices */
51 static struct nand_ecclayout nand_oob_8
= {
61 static struct nand_ecclayout nand_oob_16
= {
63 .eccpos
= {0, 1, 2, 3, 6, 7},
69 static struct nand_ecclayout nand_oob_64
= {
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63},
80 static struct nand_ecclayout nand_oob_128
= {
83 80, 81, 82, 83, 84, 85, 86, 87,
84 88, 89, 90, 91, 92, 93, 94, 95,
85 96, 97, 98, 99, 100, 101, 102, 103,
86 104, 105, 106, 107, 108, 109, 110, 111,
87 112, 113, 114, 115, 116, 117, 118, 119,
88 120, 121, 122, 123, 124, 125, 126, 127},
94 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
96 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
97 struct mtd_oob_ops
*ops
);
99 static int check_offs_len(struct mtd_info
*mtd
,
100 loff_t ofs
, uint64_t len
)
102 struct nand_chip
*chip
= mtd_to_nand(mtd
);
105 /* Start address must align on block boundary */
106 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
107 pr_debug("%s: unaligned address\n", __func__
);
111 /* Length must align on block boundary */
112 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
113 pr_debug("%s: length not block aligned\n", __func__
);
121 * nand_release_device - [GENERIC] release chip
122 * @mtd: MTD device structure
124 * Release chip lock and wake up anyone waiting on the device.
126 static void nand_release_device(struct mtd_info
*mtd
)
128 struct nand_chip
*chip
= mtd_to_nand(mtd
);
130 /* Release the controller and the chip */
131 spin_lock(&chip
->controller
->lock
);
132 chip
->controller
->active
= NULL
;
133 chip
->state
= FL_READY
;
134 wake_up(&chip
->controller
->wq
);
135 spin_unlock(&chip
->controller
->lock
);
139 * nand_read_byte - [DEFAULT] read one byte from the chip
140 * @mtd: MTD device structure
142 * Default read function for 8bit buswidth
144 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
146 struct nand_chip
*chip
= mtd_to_nand(mtd
);
147 return readb(chip
->IO_ADDR_R
);
151 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
152 * @mtd: MTD device structure
154 * Default read function for 16bit buswidth with endianness conversion.
157 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
159 struct nand_chip
*chip
= mtd_to_nand(mtd
);
160 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
164 * nand_read_word - [DEFAULT] read one word from the chip
165 * @mtd: MTD device structure
167 * Default read function for 16bit buswidth without endianness conversion.
169 static u16
nand_read_word(struct mtd_info
*mtd
)
171 struct nand_chip
*chip
= mtd_to_nand(mtd
);
172 return readw(chip
->IO_ADDR_R
);
176 * nand_select_chip - [DEFAULT] control CE line
177 * @mtd: MTD device structure
178 * @chipnr: chipnumber to select, -1 for deselect
180 * Default select function for 1 chip devices.
182 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
184 struct nand_chip
*chip
= mtd_to_nand(mtd
);
188 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
199 * nand_write_byte - [DEFAULT] write single byte to chip
200 * @mtd: MTD device structure
201 * @byte: value to write
203 * Default function to write a byte to I/O[7:0]
205 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
207 struct nand_chip
*chip
= mtd_to_nand(mtd
);
209 chip
->write_buf(mtd
, &byte
, 1);
213 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
214 * @mtd: MTD device structure
215 * @byte: value to write
217 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
219 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
221 struct nand_chip
*chip
= mtd_to_nand(mtd
);
222 uint16_t word
= byte
;
225 * It's not entirely clear what should happen to I/O[15:8] when writing
226 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
228 * When the host supports a 16-bit bus width, only data is
229 * transferred at the 16-bit width. All address and command line
230 * transfers shall use only the lower 8-bits of the data bus. During
231 * command transfers, the host may place any value on the upper
232 * 8-bits of the data bus. During address transfers, the host shall
233 * set the upper 8-bits of the data bus to 00h.
235 * One user of the write_byte callback is nand_onfi_set_features. The
236 * four parameters are specified to be written to I/O[7:0], but this is
237 * neither an address nor a command transfer. Let's assume a 0 on the
238 * upper I/O lines is OK.
240 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 * nand_write_buf - [DEFAULT] write buffer to chip
245 * @mtd: MTD device structure
247 * @len: number of bytes to write
249 * Default write function for 8bit buswidth.
251 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
253 struct nand_chip
*chip
= mtd_to_nand(mtd
);
255 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
259 * nand_read_buf - [DEFAULT] read chip data into buffer
260 * @mtd: MTD device structure
261 * @buf: buffer to store date
262 * @len: number of bytes to read
264 * Default read function for 8bit buswidth.
266 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
268 struct nand_chip
*chip
= mtd_to_nand(mtd
);
270 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
274 * nand_write_buf16 - [DEFAULT] write buffer to chip
275 * @mtd: MTD device structure
277 * @len: number of bytes to write
279 * Default write function for 16bit buswidth.
281 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
283 struct nand_chip
*chip
= mtd_to_nand(mtd
);
284 u16
*p
= (u16
*) buf
;
286 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
290 * nand_read_buf16 - [DEFAULT] read chip data into buffer
291 * @mtd: MTD device structure
292 * @buf: buffer to store date
293 * @len: number of bytes to read
295 * Default read function for 16bit buswidth.
297 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
299 struct nand_chip
*chip
= mtd_to_nand(mtd
);
300 u16
*p
= (u16
*) buf
;
302 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
310 * Check, if the block is bad.
312 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
314 int page
, res
= 0, i
= 0;
315 struct nand_chip
*chip
= mtd_to_nand(mtd
);
318 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
319 ofs
+= mtd
->erasesize
- mtd
->writesize
;
321 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
324 if (chip
->options
& NAND_BUSWIDTH_16
) {
325 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
326 chip
->badblockpos
& 0xFE, page
);
327 bad
= cpu_to_le16(chip
->read_word(mtd
));
328 if (chip
->badblockpos
& 0x1)
333 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
335 bad
= chip
->read_byte(mtd
);
338 if (likely(chip
->badblockbits
== 8))
341 res
= hweight8(bad
) < chip
->badblockbits
;
342 ofs
+= mtd
->writesize
;
343 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
345 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
351 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by a hardware
356 * specific driver. It provides the details for writing a bad block marker to a
359 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
361 struct nand_chip
*chip
= mtd_to_nand(mtd
);
362 struct mtd_oob_ops ops
;
363 uint8_t buf
[2] = { 0, 0 };
364 int ret
= 0, res
, i
= 0;
366 memset(&ops
, 0, sizeof(ops
));
368 ops
.ooboffs
= chip
->badblockpos
;
369 if (chip
->options
& NAND_BUSWIDTH_16
) {
370 ops
.ooboffs
&= ~0x01;
371 ops
.len
= ops
.ooblen
= 2;
373 ops
.len
= ops
.ooblen
= 1;
375 ops
.mode
= MTD_OPS_PLACE_OOB
;
377 /* Write to first/last page(s) if necessary */
378 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
379 ofs
+= mtd
->erasesize
- mtd
->writesize
;
381 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
386 ofs
+= mtd
->writesize
;
387 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
393 * nand_block_markbad_lowlevel - mark a block bad
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
397 * This function performs the generic NAND bad block marking steps (i.e., bad
398 * block table(s) and/or marker(s)). We only allow the hardware driver to
399 * specify how to write bad block markers to OOB (chip->block_markbad).
401 * We try operations in the following order:
402 * (1) erase the affected block, to allow OOB marker to be written cleanly
403 * (2) write bad block marker to OOB area of affected block (unless flag
404 * NAND_BBT_NO_OOB_BBM is present)
406 * Note that we retain the first error encountered in (2) or (3), finish the
407 * procedures, and dump the error in the end.
409 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
411 struct nand_chip
*chip
= mtd_to_nand(mtd
);
414 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
415 struct erase_info einfo
;
417 /* Attempt erase before marking OOB */
418 memset(&einfo
, 0, sizeof(einfo
));
421 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
422 nand_erase_nand(mtd
, &einfo
, 0);
424 /* Write bad block marker to OOB */
425 nand_get_device(mtd
, FL_WRITING
);
426 ret
= chip
->block_markbad(mtd
, ofs
);
427 nand_release_device(mtd
);
430 /* Mark block bad in BBT */
432 res
= nand_markbad_bbt(mtd
, ofs
);
438 mtd
->ecc_stats
.badblocks
++;
444 * nand_check_wp - [GENERIC] check if the chip is write protected
445 * @mtd: MTD device structure
447 * Check, if the device is write protected. The function expects, that the
448 * device is already selected.
450 static int nand_check_wp(struct mtd_info
*mtd
)
452 struct nand_chip
*chip
= mtd_to_nand(mtd
);
454 /* Broken xD cards report WP despite being writable */
455 if (chip
->options
& NAND_BROKEN_XD
)
458 /* Check the WP bit */
459 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
460 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
464 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
465 * @mtd: MTD device structure
466 * @ofs: offset from device start
468 * Check if the block is marked as reserved.
470 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
472 struct nand_chip
*chip
= mtd_to_nand(mtd
);
476 /* Return info from the table */
477 return nand_isreserved_bbt(mtd
, ofs
);
481 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
482 * @mtd: MTD device structure
483 * @ofs: offset from device start
484 * @allowbbt: 1, if its allowed to access the bbt area
486 * Check, if the block is bad. Either by reading the bad block table or
487 * calling of the scan function.
489 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
491 struct nand_chip
*chip
= mtd_to_nand(mtd
);
494 return chip
->block_bad(mtd
, ofs
);
496 /* Return info from the table */
497 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
501 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
502 * @mtd: MTD device structure
505 * Helper function for nand_wait_ready used when needing to wait in interrupt
508 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
510 struct nand_chip
*chip
= mtd_to_nand(mtd
);
513 /* Wait for the device to get ready */
514 for (i
= 0; i
< timeo
; i
++) {
515 if (chip
->dev_ready(mtd
))
517 touch_softlockup_watchdog();
523 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
524 * @mtd: MTD device structure
526 * Wait for the ready pin after a command, and warn if a timeout occurs.
528 void nand_wait_ready(struct mtd_info
*mtd
)
530 struct nand_chip
*chip
= mtd_to_nand(mtd
);
531 unsigned long timeo
= 400;
533 if (in_interrupt() || oops_in_progress
)
534 return panic_nand_wait_ready(mtd
, timeo
);
536 /* Wait until command is processed or timeout occurs */
537 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
539 if (chip
->dev_ready(mtd
))
542 } while (time_before(jiffies
, timeo
));
544 if (!chip
->dev_ready(mtd
))
545 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
547 EXPORT_SYMBOL_GPL(nand_wait_ready
);
550 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
551 * @mtd: MTD device structure
552 * @timeo: Timeout in ms
554 * Wait for status ready (i.e. command done) or timeout.
556 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
558 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
560 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
562 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
564 touch_softlockup_watchdog();
565 } while (time_before(jiffies
, timeo
));
569 * nand_command - [DEFAULT] Send command to NAND device
570 * @mtd: MTD device structure
571 * @command: the command to be sent
572 * @column: the column address for this command, -1 if none
573 * @page_addr: the page address for this command, -1 if none
575 * Send command to NAND device. This function is used for small page devices
576 * (512 Bytes per page).
578 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
579 int column
, int page_addr
)
581 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
582 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
584 /* Write out the command to the device */
585 if (command
== NAND_CMD_SEQIN
) {
588 if (column
>= mtd
->writesize
) {
590 column
-= mtd
->writesize
;
591 readcmd
= NAND_CMD_READOOB
;
592 } else if (column
< 256) {
593 /* First 256 bytes --> READ0 */
594 readcmd
= NAND_CMD_READ0
;
597 readcmd
= NAND_CMD_READ1
;
599 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
600 ctrl
&= ~NAND_CTRL_CHANGE
;
602 chip
->cmd_ctrl(mtd
, command
, ctrl
);
604 /* Address cycle, when necessary */
605 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
606 /* Serially input address */
608 /* Adjust columns for 16 bit buswidth */
609 if (chip
->options
& NAND_BUSWIDTH_16
&&
610 !nand_opcode_8bits(command
))
612 chip
->cmd_ctrl(mtd
, column
, ctrl
);
613 ctrl
&= ~NAND_CTRL_CHANGE
;
615 if (page_addr
!= -1) {
616 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
617 ctrl
&= ~NAND_CTRL_CHANGE
;
618 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
619 /* One more address cycle for devices > 32MiB */
620 if (chip
->chipsize
> (32 << 20))
621 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
623 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
626 * Program and erase have their own busy handlers status and sequential
631 case NAND_CMD_PAGEPROG
:
632 case NAND_CMD_ERASE1
:
633 case NAND_CMD_ERASE2
:
635 case NAND_CMD_STATUS
:
641 udelay(chip
->chip_delay
);
642 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
643 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
645 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
646 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
647 nand_wait_status_ready(mtd
, 250);
650 /* This applies to read commands */
653 * If we don't have access to the busy pin, we apply the given
656 if (!chip
->dev_ready
) {
657 udelay(chip
->chip_delay
);
662 * Apply this short delay always to ensure that we do wait tWB in
663 * any case on any machine.
667 nand_wait_ready(mtd
);
671 * nand_command_lp - [DEFAULT] Send command to NAND large page device
672 * @mtd: MTD device structure
673 * @command: the command to be sent
674 * @column: the column address for this command, -1 if none
675 * @page_addr: the page address for this command, -1 if none
677 * Send command to NAND device. This is the version for the new large page
678 * devices. We don't have the separate regions as we have in the small page
679 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
681 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
682 int column
, int page_addr
)
684 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
686 /* Emulate NAND_CMD_READOOB */
687 if (command
== NAND_CMD_READOOB
) {
688 column
+= mtd
->writesize
;
689 command
= NAND_CMD_READ0
;
692 /* Command latch cycle */
693 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
695 if (column
!= -1 || page_addr
!= -1) {
696 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
698 /* Serially input address */
700 /* Adjust columns for 16 bit buswidth */
701 if (chip
->options
& NAND_BUSWIDTH_16
&&
702 !nand_opcode_8bits(command
))
704 chip
->cmd_ctrl(mtd
, column
, ctrl
);
705 ctrl
&= ~NAND_CTRL_CHANGE
;
706 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
708 if (page_addr
!= -1) {
709 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
710 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
711 NAND_NCE
| NAND_ALE
);
712 /* One more address cycle for devices > 128MiB */
713 if (chip
->chipsize
> (128 << 20))
714 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
715 NAND_NCE
| NAND_ALE
);
718 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
721 * Program and erase have their own busy handlers status, sequential
722 * in and status need no delay.
726 case NAND_CMD_CACHEDPROG
:
727 case NAND_CMD_PAGEPROG
:
728 case NAND_CMD_ERASE1
:
729 case NAND_CMD_ERASE2
:
732 case NAND_CMD_STATUS
:
738 udelay(chip
->chip_delay
);
739 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
740 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
741 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
742 NAND_NCE
| NAND_CTRL_CHANGE
);
743 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
744 nand_wait_status_ready(mtd
, 250);
747 case NAND_CMD_RNDOUT
:
748 /* No ready / busy check necessary */
749 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
750 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
751 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
752 NAND_NCE
| NAND_CTRL_CHANGE
);
756 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
757 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
758 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
759 NAND_NCE
| NAND_CTRL_CHANGE
);
761 /* This applies to read commands */
764 * If we don't have access to the busy pin, we apply the given
767 if (!chip
->dev_ready
) {
768 udelay(chip
->chip_delay
);
774 * Apply this short delay always to ensure that we do wait tWB in
775 * any case on any machine.
779 nand_wait_ready(mtd
);
783 * panic_nand_get_device - [GENERIC] Get chip for selected access
784 * @chip: the nand chip descriptor
785 * @mtd: MTD device structure
786 * @new_state: the state which is requested
788 * Used when in panic, no locks are taken.
790 static void panic_nand_get_device(struct nand_chip
*chip
,
791 struct mtd_info
*mtd
, int new_state
)
793 /* Hardware controller shared among independent devices */
794 chip
->controller
->active
= chip
;
795 chip
->state
= new_state
;
799 * nand_get_device - [GENERIC] Get chip for selected access
800 * @mtd: MTD device structure
801 * @new_state: the state which is requested
803 * Get the device and lock it for exclusive access
806 nand_get_device(struct mtd_info
*mtd
, int new_state
)
808 struct nand_chip
*chip
= mtd_to_nand(mtd
);
809 spinlock_t
*lock
= &chip
->controller
->lock
;
810 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
811 DECLARE_WAITQUEUE(wait
, current
);
815 /* Hardware controller shared among independent devices */
816 if (!chip
->controller
->active
)
817 chip
->controller
->active
= chip
;
819 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
820 chip
->state
= new_state
;
824 if (new_state
== FL_PM_SUSPENDED
) {
825 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
826 chip
->state
= FL_PM_SUSPENDED
;
831 set_current_state(TASK_UNINTERRUPTIBLE
);
832 add_wait_queue(wq
, &wait
);
835 remove_wait_queue(wq
, &wait
);
840 * panic_nand_wait - [GENERIC] wait until the command is done
841 * @mtd: MTD device structure
842 * @chip: NAND chip structure
845 * Wait for command done. This is a helper function for nand_wait used when
846 * we are in interrupt context. May happen when in panic and trying to write
847 * an oops through mtdoops.
849 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
853 for (i
= 0; i
< timeo
; i
++) {
854 if (chip
->dev_ready
) {
855 if (chip
->dev_ready(mtd
))
858 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
866 * nand_wait - [DEFAULT] wait until the command is done
867 * @mtd: MTD device structure
868 * @chip: NAND chip structure
870 * Wait for command done. This applies to erase and program only.
872 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
876 unsigned long timeo
= 400;
879 * Apply this short delay always to ensure that we do wait tWB in any
880 * case on any machine.
884 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
886 if (in_interrupt() || oops_in_progress
)
887 panic_nand_wait(mtd
, chip
, timeo
);
889 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
891 if (chip
->dev_ready
) {
892 if (chip
->dev_ready(mtd
))
895 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
899 } while (time_before(jiffies
, timeo
));
902 status
= (int)chip
->read_byte(mtd
);
903 /* This can happen if in case of timeout or buggy dev_ready */
904 WARN_ON(!(status
& NAND_STATUS_READY
));
909 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
911 * @ofs: offset to start unlock from
912 * @len: length to unlock
913 * @invert: when = 0, unlock the range of blocks within the lower and
914 * upper boundary address
915 * when = 1, unlock the range of blocks outside the boundaries
916 * of the lower and upper boundary address
918 * Returs unlock status.
920 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
921 uint64_t len
, int invert
)
925 struct nand_chip
*chip
= mtd_to_nand(mtd
);
927 /* Submit address of first page to unlock */
928 page
= ofs
>> chip
->page_shift
;
929 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
931 /* Submit address of last page to unlock */
932 page
= (ofs
+ len
) >> chip
->page_shift
;
933 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
934 (page
| invert
) & chip
->pagemask
);
936 /* Call wait ready function */
937 status
= chip
->waitfunc(mtd
, chip
);
938 /* See if device thinks it succeeded */
939 if (status
& NAND_STATUS_FAIL
) {
940 pr_debug("%s: error status = 0x%08x\n",
949 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
951 * @ofs: offset to start unlock from
952 * @len: length to unlock
954 * Returns unlock status.
956 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
960 struct nand_chip
*chip
= mtd_to_nand(mtd
);
962 pr_debug("%s: start = 0x%012llx, len = %llu\n",
963 __func__
, (unsigned long long)ofs
, len
);
965 if (check_offs_len(mtd
, ofs
, len
))
968 /* Align to last block address if size addresses end of the device */
969 if (ofs
+ len
== mtd
->size
)
970 len
-= mtd
->erasesize
;
972 nand_get_device(mtd
, FL_UNLOCKING
);
974 /* Shift to get chip number */
975 chipnr
= ofs
>> chip
->chip_shift
;
977 chip
->select_chip(mtd
, chipnr
);
981 * If we want to check the WP through READ STATUS and check the bit 7
982 * we must reset the chip
983 * some operation can also clear the bit 7 of status register
984 * eg. erase/program a locked block
986 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
988 /* Check, if it is write protected */
989 if (nand_check_wp(mtd
)) {
990 pr_debug("%s: device is write protected!\n",
996 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
999 chip
->select_chip(mtd
, -1);
1000 nand_release_device(mtd
);
1004 EXPORT_SYMBOL(nand_unlock
);
1007 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1009 * @ofs: offset to start unlock from
1010 * @len: length to unlock
1012 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1013 * have this feature, but it allows only to lock all blocks, not for specified
1014 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1017 * Returns lock status.
1019 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1022 int chipnr
, status
, page
;
1023 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1025 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1026 __func__
, (unsigned long long)ofs
, len
);
1028 if (check_offs_len(mtd
, ofs
, len
))
1031 nand_get_device(mtd
, FL_LOCKING
);
1033 /* Shift to get chip number */
1034 chipnr
= ofs
>> chip
->chip_shift
;
1036 chip
->select_chip(mtd
, chipnr
);
1040 * If we want to check the WP through READ STATUS and check the bit 7
1041 * we must reset the chip
1042 * some operation can also clear the bit 7 of status register
1043 * eg. erase/program a locked block
1045 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1047 /* Check, if it is write protected */
1048 if (nand_check_wp(mtd
)) {
1049 pr_debug("%s: device is write protected!\n",
1051 status
= MTD_ERASE_FAILED
;
1056 /* Submit address of first page to lock */
1057 page
= ofs
>> chip
->page_shift
;
1058 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1060 /* Call wait ready function */
1061 status
= chip
->waitfunc(mtd
, chip
);
1062 /* See if device thinks it succeeded */
1063 if (status
& NAND_STATUS_FAIL
) {
1064 pr_debug("%s: error status = 0x%08x\n",
1070 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1073 chip
->select_chip(mtd
, -1);
1074 nand_release_device(mtd
);
1078 EXPORT_SYMBOL(nand_lock
);
1081 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1082 * @buf: buffer to test
1083 * @len: buffer length
1084 * @bitflips_threshold: maximum number of bitflips
1086 * Check if a buffer contains only 0xff, which means the underlying region
1087 * has been erased and is ready to be programmed.
1088 * The bitflips_threshold specify the maximum number of bitflips before
1089 * considering the region is not erased.
1090 * Note: The logic of this function has been extracted from the memweight
1091 * implementation, except that nand_check_erased_buf function exit before
1092 * testing the whole buffer if the number of bitflips exceed the
1093 * bitflips_threshold value.
1095 * Returns a positive number of bitflips less than or equal to
1096 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1099 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1101 const unsigned char *bitmap
= buf
;
1105 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1107 weight
= hweight8(*bitmap
);
1108 bitflips
+= BITS_PER_BYTE
- weight
;
1109 if (unlikely(bitflips
> bitflips_threshold
))
1113 for (; len
>= sizeof(long);
1114 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1115 weight
= hweight_long(*((unsigned long *)bitmap
));
1116 bitflips
+= BITS_PER_LONG
- weight
;
1117 if (unlikely(bitflips
> bitflips_threshold
))
1121 for (; len
> 0; len
--, bitmap
++) {
1122 weight
= hweight8(*bitmap
);
1123 bitflips
+= BITS_PER_BYTE
- weight
;
1124 if (unlikely(bitflips
> bitflips_threshold
))
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1134 * @data: data buffer to test
1135 * @datalen: data length
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1170 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1171 void *ecc
, int ecclen
,
1172 void *extraoob
, int extraooblen
,
1173 int bitflips_threshold
)
1175 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1177 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1178 bitflips_threshold
);
1179 if (data_bitflips
< 0)
1180 return data_bitflips
;
1182 bitflips_threshold
-= data_bitflips
;
1184 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1185 if (ecc_bitflips
< 0)
1186 return ecc_bitflips
;
1188 bitflips_threshold
-= ecc_bitflips
;
1190 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1191 bitflips_threshold
);
1192 if (extraoob_bitflips
< 0)
1193 return extraoob_bitflips
;
1196 memset(data
, 0xff, datalen
);
1199 memset(ecc
, 0xff, ecclen
);
1201 if (extraoob_bitflips
)
1202 memset(extraoob
, 0xff, extraooblen
);
1204 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1206 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1213 * @oob_required: caller requires OOB data read to chip->oob_poi
1214 * @page: page number to read
1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1218 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1219 uint8_t *buf
, int oob_required
, int page
)
1221 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1223 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @oob_required: caller requires OOB data read to chip->oob_poi
1233 * @page: page number to read
1235 * We need a special oob layout and handling even when OOB isn't used.
1237 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1238 struct nand_chip
*chip
, uint8_t *buf
,
1239 int oob_required
, int page
)
1241 int eccsize
= chip
->ecc
.size
;
1242 int eccbytes
= chip
->ecc
.bytes
;
1243 uint8_t *oob
= chip
->oob_poi
;
1246 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1247 chip
->read_buf(mtd
, buf
, eccsize
);
1250 if (chip
->ecc
.prepad
) {
1251 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1252 oob
+= chip
->ecc
.prepad
;
1255 chip
->read_buf(mtd
, oob
, eccbytes
);
1258 if (chip
->ecc
.postpad
) {
1259 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1260 oob
+= chip
->ecc
.postpad
;
1264 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1266 chip
->read_buf(mtd
, oob
, size
);
1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1279 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1280 uint8_t *buf
, int oob_required
, int page
)
1282 int i
, eccsize
= chip
->ecc
.size
, ret
;
1283 int eccbytes
= chip
->ecc
.bytes
;
1284 int eccsteps
= chip
->ecc
.steps
;
1286 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1287 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1288 unsigned int max_bitflips
= 0;
1290 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1292 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1293 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1295 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1300 eccsteps
= chip
->ecc
.steps
;
1303 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1306 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1308 mtd
->ecc_stats
.failed
++;
1310 mtd
->ecc_stats
.corrected
+= stat
;
1311 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1314 return max_bitflips
;
1318 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1319 * @mtd: mtd info structure
1320 * @chip: nand chip info structure
1321 * @data_offs: offset of requested data within the page
1322 * @readlen: data length
1323 * @bufpoi: buffer to store read data
1324 * @page: page number to read
1326 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1327 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1330 int start_step
, end_step
, num_steps
, ret
;
1332 int data_col_addr
, i
, gaps
= 0;
1333 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1334 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1335 int index
, section
= 0;
1336 unsigned int max_bitflips
= 0;
1337 struct mtd_oob_region oobregion
= { };
1339 /* Column address within the page aligned to ECC size (256bytes) */
1340 start_step
= data_offs
/ chip
->ecc
.size
;
1341 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1342 num_steps
= end_step
- start_step
+ 1;
1343 index
= start_step
* chip
->ecc
.bytes
;
1345 /* Data size aligned to ECC ecc.size */
1346 datafrag_len
= num_steps
* chip
->ecc
.size
;
1347 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1349 data_col_addr
= start_step
* chip
->ecc
.size
;
1350 /* If we read not a page aligned data */
1351 if (data_col_addr
!= 0)
1352 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1354 p
= bufpoi
+ data_col_addr
;
1355 chip
->read_buf(mtd
, p
, datafrag_len
);
1358 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1359 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1362 * The performance is faster if we position offsets according to
1363 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1365 ret
= mtd_ooblayout_find_eccregion(mtd
, index
, §ion
, &oobregion
);
1369 if (oobregion
.length
< eccfrag_len
)
1373 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1374 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1377 * Send the command to read the particular ECC bytes take care
1378 * about buswidth alignment in read_buf.
1380 aligned_pos
= oobregion
.offset
& ~(busw
- 1);
1381 aligned_len
= eccfrag_len
;
1382 if (oobregion
.offset
& (busw
- 1))
1384 if ((oobregion
.offset
+ (num_steps
* chip
->ecc
.bytes
)) &
1388 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1389 mtd
->writesize
+ aligned_pos
, -1);
1390 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1393 ret
= mtd_ooblayout_get_eccbytes(mtd
, chip
->buffers
->ecccode
,
1394 chip
->oob_poi
, index
, eccfrag_len
);
1398 p
= bufpoi
+ data_col_addr
;
1399 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1402 stat
= chip
->ecc
.correct(mtd
, p
,
1403 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1404 if (stat
== -EBADMSG
&&
1405 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1406 /* check for empty pages with bitflips */
1407 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1408 &chip
->buffers
->ecccode
[i
],
1411 chip
->ecc
.strength
);
1415 mtd
->ecc_stats
.failed
++;
1417 mtd
->ecc_stats
.corrected
+= stat
;
1418 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1421 return max_bitflips
;
1425 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1426 * @mtd: mtd info structure
1427 * @chip: nand chip info structure
1428 * @buf: buffer to store read data
1429 * @oob_required: caller requires OOB data read to chip->oob_poi
1430 * @page: page number to read
1432 * Not for syndrome calculating ECC controllers which need a special oob layout.
1434 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1435 uint8_t *buf
, int oob_required
, int page
)
1437 int i
, eccsize
= chip
->ecc
.size
, ret
;
1438 int eccbytes
= chip
->ecc
.bytes
;
1439 int eccsteps
= chip
->ecc
.steps
;
1441 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1442 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1443 unsigned int max_bitflips
= 0;
1445 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1446 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1447 chip
->read_buf(mtd
, p
, eccsize
);
1448 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1450 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1452 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1457 eccsteps
= chip
->ecc
.steps
;
1460 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1463 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1464 if (stat
== -EBADMSG
&&
1465 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1466 /* check for empty pages with bitflips */
1467 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1468 &ecc_code
[i
], eccbytes
,
1470 chip
->ecc
.strength
);
1474 mtd
->ecc_stats
.failed
++;
1476 mtd
->ecc_stats
.corrected
+= stat
;
1477 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1480 return max_bitflips
;
1484 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1485 * @mtd: mtd info structure
1486 * @chip: nand chip info structure
1487 * @buf: buffer to store read data
1488 * @oob_required: caller requires OOB data read to chip->oob_poi
1489 * @page: page number to read
1491 * Hardware ECC for large page chips, require OOB to be read first. For this
1492 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1493 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1494 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1495 * the data area, by overwriting the NAND manufacturer bad block markings.
1497 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1498 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1500 int i
, eccsize
= chip
->ecc
.size
, ret
;
1501 int eccbytes
= chip
->ecc
.bytes
;
1502 int eccsteps
= chip
->ecc
.steps
;
1504 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1505 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1506 unsigned int max_bitflips
= 0;
1508 /* Read the OOB area first */
1509 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1510 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1511 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1513 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1518 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1521 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1522 chip
->read_buf(mtd
, p
, eccsize
);
1523 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1525 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1526 if (stat
== -EBADMSG
&&
1527 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1528 /* check for empty pages with bitflips */
1529 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1530 &ecc_code
[i
], eccbytes
,
1532 chip
->ecc
.strength
);
1536 mtd
->ecc_stats
.failed
++;
1538 mtd
->ecc_stats
.corrected
+= stat
;
1539 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1542 return max_bitflips
;
1546 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1547 * @mtd: mtd info structure
1548 * @chip: nand chip info structure
1549 * @buf: buffer to store read data
1550 * @oob_required: caller requires OOB data read to chip->oob_poi
1551 * @page: page number to read
1553 * The hw generator calculates the error syndrome automatically. Therefore we
1554 * need a special oob layout and handling.
1556 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1557 uint8_t *buf
, int oob_required
, int page
)
1559 int i
, eccsize
= chip
->ecc
.size
;
1560 int eccbytes
= chip
->ecc
.bytes
;
1561 int eccsteps
= chip
->ecc
.steps
;
1562 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1564 uint8_t *oob
= chip
->oob_poi
;
1565 unsigned int max_bitflips
= 0;
1567 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1570 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1571 chip
->read_buf(mtd
, p
, eccsize
);
1573 if (chip
->ecc
.prepad
) {
1574 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1575 oob
+= chip
->ecc
.prepad
;
1578 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1579 chip
->read_buf(mtd
, oob
, eccbytes
);
1580 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1584 if (chip
->ecc
.postpad
) {
1585 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1586 oob
+= chip
->ecc
.postpad
;
1589 if (stat
== -EBADMSG
&&
1590 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1591 /* check for empty pages with bitflips */
1592 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1596 chip
->ecc
.strength
);
1600 mtd
->ecc_stats
.failed
++;
1602 mtd
->ecc_stats
.corrected
+= stat
;
1603 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1607 /* Calculate remaining oob bytes */
1608 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1610 chip
->read_buf(mtd
, oob
, i
);
1612 return max_bitflips
;
1616 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1617 * @mtd: mtd info structure
1618 * @oob: oob destination address
1619 * @ops: oob ops structure
1620 * @len: size of oob to transfer
1622 static uint8_t *nand_transfer_oob(struct mtd_info
*mtd
, uint8_t *oob
,
1623 struct mtd_oob_ops
*ops
, size_t len
)
1625 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1628 switch (ops
->mode
) {
1630 case MTD_OPS_PLACE_OOB
:
1632 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1635 case MTD_OPS_AUTO_OOB
:
1636 ret
= mtd_ooblayout_get_databytes(mtd
, oob
, chip
->oob_poi
,
1648 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1649 * @mtd: MTD device structure
1650 * @retry_mode: the retry mode to use
1652 * Some vendors supply a special command to shift the Vt threshold, to be used
1653 * when there are too many bitflips in a page (i.e., ECC error). After setting
1654 * a new threshold, the host should retry reading the page.
1656 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1658 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1660 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1662 if (retry_mode
>= chip
->read_retries
)
1665 if (!chip
->setup_read_retry
)
1668 return chip
->setup_read_retry(mtd
, retry_mode
);
1672 * nand_do_read_ops - [INTERN] Read data with ECC
1673 * @mtd: MTD device structure
1674 * @from: offset to read from
1675 * @ops: oob ops structure
1677 * Internal function. Called with chip held.
1679 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1680 struct mtd_oob_ops
*ops
)
1682 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1683 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1685 uint32_t readlen
= ops
->len
;
1686 uint32_t oobreadlen
= ops
->ooblen
;
1687 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1689 uint8_t *bufpoi
, *oob
, *buf
;
1691 unsigned int max_bitflips
= 0;
1693 bool ecc_fail
= false;
1695 chipnr
= (int)(from
>> chip
->chip_shift
);
1696 chip
->select_chip(mtd
, chipnr
);
1698 realpage
= (int)(from
>> chip
->page_shift
);
1699 page
= realpage
& chip
->pagemask
;
1701 col
= (int)(from
& (mtd
->writesize
- 1));
1705 oob_required
= oob
? 1 : 0;
1708 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1710 bytes
= min(mtd
->writesize
- col
, readlen
);
1711 aligned
= (bytes
== mtd
->writesize
);
1715 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1716 use_bufpoi
= !virt_addr_valid(buf
);
1720 /* Is the current page in the buffer? */
1721 if (realpage
!= chip
->pagebuf
|| oob
) {
1722 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1724 if (use_bufpoi
&& aligned
)
1725 pr_debug("%s: using read bounce buffer for buf@%p\n",
1729 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1732 * Now read the page into the buffer. Absent an error,
1733 * the read methods return max bitflips per ecc step.
1735 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1736 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1739 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1741 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1745 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1746 oob_required
, page
);
1749 /* Invalidate page cache */
1754 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1756 /* Transfer not aligned data */
1758 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1759 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1760 (ops
->mode
!= MTD_OPS_RAW
)) {
1761 chip
->pagebuf
= realpage
;
1762 chip
->pagebuf_bitflips
= ret
;
1764 /* Invalidate page cache */
1767 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1770 if (unlikely(oob
)) {
1771 int toread
= min(oobreadlen
, max_oobsize
);
1774 oob
= nand_transfer_oob(mtd
,
1776 oobreadlen
-= toread
;
1780 if (chip
->options
& NAND_NEED_READRDY
) {
1781 /* Apply delay or wait for ready/busy pin */
1782 if (!chip
->dev_ready
)
1783 udelay(chip
->chip_delay
);
1785 nand_wait_ready(mtd
);
1788 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1789 if (retry_mode
+ 1 < chip
->read_retries
) {
1791 ret
= nand_setup_read_retry(mtd
,
1796 /* Reset failures; retry */
1797 mtd
->ecc_stats
.failed
= ecc_failures
;
1800 /* No more retry modes; real failure */
1807 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1809 max_bitflips
= max_t(unsigned int, max_bitflips
,
1810 chip
->pagebuf_bitflips
);
1815 /* Reset to retry mode 0 */
1817 ret
= nand_setup_read_retry(mtd
, 0);
1826 /* For subsequent reads align to page boundary */
1828 /* Increment page address */
1831 page
= realpage
& chip
->pagemask
;
1832 /* Check, if we cross a chip boundary */
1835 chip
->select_chip(mtd
, -1);
1836 chip
->select_chip(mtd
, chipnr
);
1839 chip
->select_chip(mtd
, -1);
1841 ops
->retlen
= ops
->len
- (size_t) readlen
;
1843 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1851 return max_bitflips
;
1855 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1856 * @mtd: MTD device structure
1857 * @from: offset to read from
1858 * @len: number of bytes to read
1859 * @retlen: pointer to variable to store the number of read bytes
1860 * @buf: the databuffer to put data
1862 * Get hold of the chip and call nand_do_read.
1864 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1865 size_t *retlen
, uint8_t *buf
)
1867 struct mtd_oob_ops ops
;
1870 nand_get_device(mtd
, FL_READING
);
1871 memset(&ops
, 0, sizeof(ops
));
1874 ops
.mode
= MTD_OPS_PLACE_OOB
;
1875 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1876 *retlen
= ops
.retlen
;
1877 nand_release_device(mtd
);
1882 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1883 * @mtd: mtd info structure
1884 * @chip: nand chip info structure
1885 * @page: page number to read
1887 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
1889 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1890 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1893 EXPORT_SYMBOL(nand_read_oob_std
);
1896 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1898 * @mtd: mtd info structure
1899 * @chip: nand chip info structure
1900 * @page: page number to read
1902 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1905 int length
= mtd
->oobsize
;
1906 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1907 int eccsize
= chip
->ecc
.size
;
1908 uint8_t *bufpoi
= chip
->oob_poi
;
1909 int i
, toread
, sndrnd
= 0, pos
;
1911 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1912 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1914 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1915 if (mtd
->writesize
> 512)
1916 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1918 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1921 toread
= min_t(int, length
, chunk
);
1922 chip
->read_buf(mtd
, bufpoi
, toread
);
1927 chip
->read_buf(mtd
, bufpoi
, length
);
1931 EXPORT_SYMBOL(nand_read_oob_syndrome
);
1934 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1935 * @mtd: mtd info structure
1936 * @chip: nand chip info structure
1937 * @page: page number to write
1939 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
1942 const uint8_t *buf
= chip
->oob_poi
;
1943 int length
= mtd
->oobsize
;
1945 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1946 chip
->write_buf(mtd
, buf
, length
);
1947 /* Send command to program the OOB data */
1948 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1950 status
= chip
->waitfunc(mtd
, chip
);
1952 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1954 EXPORT_SYMBOL(nand_write_oob_std
);
1957 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1958 * with syndrome - only for large page flash
1959 * @mtd: mtd info structure
1960 * @chip: nand chip info structure
1961 * @page: page number to write
1963 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1966 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1967 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1968 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1969 const uint8_t *bufpoi
= chip
->oob_poi
;
1972 * data-ecc-data-ecc ... ecc-oob
1974 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1976 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1977 pos
= steps
* (eccsize
+ chunk
);
1982 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1983 for (i
= 0; i
< steps
; i
++) {
1985 if (mtd
->writesize
<= 512) {
1986 uint32_t fill
= 0xFFFFFFFF;
1990 int num
= min_t(int, len
, 4);
1991 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1996 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1997 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2001 len
= min_t(int, length
, chunk
);
2002 chip
->write_buf(mtd
, bufpoi
, len
);
2007 chip
->write_buf(mtd
, bufpoi
, length
);
2009 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2010 status
= chip
->waitfunc(mtd
, chip
);
2012 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2014 EXPORT_SYMBOL(nand_write_oob_syndrome
);
2017 * nand_do_read_oob - [INTERN] NAND read out-of-band
2018 * @mtd: MTD device structure
2019 * @from: offset to read from
2020 * @ops: oob operations description structure
2022 * NAND read out-of-band data from the spare area.
2024 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2025 struct mtd_oob_ops
*ops
)
2027 int page
, realpage
, chipnr
;
2028 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2029 struct mtd_ecc_stats stats
;
2030 int readlen
= ops
->ooblen
;
2032 uint8_t *buf
= ops
->oobbuf
;
2035 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2036 __func__
, (unsigned long long)from
, readlen
);
2038 stats
= mtd
->ecc_stats
;
2040 len
= mtd_oobavail(mtd
, ops
);
2042 if (unlikely(ops
->ooboffs
>= len
)) {
2043 pr_debug("%s: attempt to start read outside oob\n",
2048 /* Do not allow reads past end of device */
2049 if (unlikely(from
>= mtd
->size
||
2050 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2051 (from
>> chip
->page_shift
)) * len
)) {
2052 pr_debug("%s: attempt to read beyond end of device\n",
2057 chipnr
= (int)(from
>> chip
->chip_shift
);
2058 chip
->select_chip(mtd
, chipnr
);
2060 /* Shift to get page */
2061 realpage
= (int)(from
>> chip
->page_shift
);
2062 page
= realpage
& chip
->pagemask
;
2065 if (ops
->mode
== MTD_OPS_RAW
)
2066 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2068 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2073 len
= min(len
, readlen
);
2074 buf
= nand_transfer_oob(mtd
, buf
, ops
, len
);
2076 if (chip
->options
& NAND_NEED_READRDY
) {
2077 /* Apply delay or wait for ready/busy pin */
2078 if (!chip
->dev_ready
)
2079 udelay(chip
->chip_delay
);
2081 nand_wait_ready(mtd
);
2088 /* Increment page address */
2091 page
= realpage
& chip
->pagemask
;
2092 /* Check, if we cross a chip boundary */
2095 chip
->select_chip(mtd
, -1);
2096 chip
->select_chip(mtd
, chipnr
);
2099 chip
->select_chip(mtd
, -1);
2101 ops
->oobretlen
= ops
->ooblen
- readlen
;
2106 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2109 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2113 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2114 * @mtd: MTD device structure
2115 * @from: offset to read from
2116 * @ops: oob operation description structure
2118 * NAND read data and/or out-of-band data.
2120 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2121 struct mtd_oob_ops
*ops
)
2123 int ret
= -ENOTSUPP
;
2127 /* Do not allow reads past end of device */
2128 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2129 pr_debug("%s: attempt to read beyond end of device\n",
2134 nand_get_device(mtd
, FL_READING
);
2136 switch (ops
->mode
) {
2137 case MTD_OPS_PLACE_OOB
:
2138 case MTD_OPS_AUTO_OOB
:
2147 ret
= nand_do_read_oob(mtd
, from
, ops
);
2149 ret
= nand_do_read_ops(mtd
, from
, ops
);
2152 nand_release_device(mtd
);
2158 * nand_write_page_raw - [INTERN] raw page write function
2159 * @mtd: mtd info structure
2160 * @chip: nand chip info structure
2162 * @oob_required: must write chip->oob_poi to OOB
2163 * @page: page number to write
2165 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2167 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2168 const uint8_t *buf
, int oob_required
, int page
)
2170 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2172 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2178 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2179 * @mtd: mtd info structure
2180 * @chip: nand chip info structure
2182 * @oob_required: must write chip->oob_poi to OOB
2183 * @page: page number to write
2185 * We need a special oob layout and handling even when ECC isn't checked.
2187 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2188 struct nand_chip
*chip
,
2189 const uint8_t *buf
, int oob_required
,
2192 int eccsize
= chip
->ecc
.size
;
2193 int eccbytes
= chip
->ecc
.bytes
;
2194 uint8_t *oob
= chip
->oob_poi
;
2197 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2198 chip
->write_buf(mtd
, buf
, eccsize
);
2201 if (chip
->ecc
.prepad
) {
2202 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2203 oob
+= chip
->ecc
.prepad
;
2206 chip
->write_buf(mtd
, oob
, eccbytes
);
2209 if (chip
->ecc
.postpad
) {
2210 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2211 oob
+= chip
->ecc
.postpad
;
2215 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2217 chip
->write_buf(mtd
, oob
, size
);
2222 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2223 * @mtd: mtd info structure
2224 * @chip: nand chip info structure
2226 * @oob_required: must write chip->oob_poi to OOB
2227 * @page: page number to write
2229 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2230 const uint8_t *buf
, int oob_required
,
2233 int i
, eccsize
= chip
->ecc
.size
, ret
;
2234 int eccbytes
= chip
->ecc
.bytes
;
2235 int eccsteps
= chip
->ecc
.steps
;
2236 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2237 const uint8_t *p
= buf
;
2239 /* Software ECC calculation */
2240 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2241 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2243 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2248 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2252 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2253 * @mtd: mtd info structure
2254 * @chip: nand chip info structure
2256 * @oob_required: must write chip->oob_poi to OOB
2257 * @page: page number to write
2259 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2260 const uint8_t *buf
, int oob_required
,
2263 int i
, eccsize
= chip
->ecc
.size
, ret
;
2264 int eccbytes
= chip
->ecc
.bytes
;
2265 int eccsteps
= chip
->ecc
.steps
;
2266 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2267 const uint8_t *p
= buf
;
2269 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2270 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2271 chip
->write_buf(mtd
, p
, eccsize
);
2272 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2275 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2280 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2287 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2288 * @mtd: mtd info structure
2289 * @chip: nand chip info structure
2290 * @offset: column address of subpage within the page
2291 * @data_len: data length
2293 * @oob_required: must write chip->oob_poi to OOB
2294 * @page: page number to write
2296 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2297 struct nand_chip
*chip
, uint32_t offset
,
2298 uint32_t data_len
, const uint8_t *buf
,
2299 int oob_required
, int page
)
2301 uint8_t *oob_buf
= chip
->oob_poi
;
2302 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2303 int ecc_size
= chip
->ecc
.size
;
2304 int ecc_bytes
= chip
->ecc
.bytes
;
2305 int ecc_steps
= chip
->ecc
.steps
;
2306 uint32_t start_step
= offset
/ ecc_size
;
2307 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2308 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2311 for (step
= 0; step
< ecc_steps
; step
++) {
2312 /* configure controller for WRITE access */
2313 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2315 /* write data (untouched subpages already masked by 0xFF) */
2316 chip
->write_buf(mtd
, buf
, ecc_size
);
2318 /* mask ECC of un-touched subpages by padding 0xFF */
2319 if ((step
< start_step
) || (step
> end_step
))
2320 memset(ecc_calc
, 0xff, ecc_bytes
);
2322 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2324 /* mask OOB of un-touched subpages by padding 0xFF */
2325 /* if oob_required, preserve OOB metadata of written subpage */
2326 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2327 memset(oob_buf
, 0xff, oob_bytes
);
2330 ecc_calc
+= ecc_bytes
;
2331 oob_buf
+= oob_bytes
;
2334 /* copy calculated ECC for whole page to chip->buffer->oob */
2335 /* this include masked-value(0xFF) for unwritten subpages */
2336 ecc_calc
= chip
->buffers
->ecccalc
;
2337 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2342 /* write OOB buffer to NAND device */
2343 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2350 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2351 * @mtd: mtd info structure
2352 * @chip: nand chip info structure
2354 * @oob_required: must write chip->oob_poi to OOB
2355 * @page: page number to write
2357 * The hw generator calculates the error syndrome automatically. Therefore we
2358 * need a special oob layout and handling.
2360 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2361 struct nand_chip
*chip
,
2362 const uint8_t *buf
, int oob_required
,
2365 int i
, eccsize
= chip
->ecc
.size
;
2366 int eccbytes
= chip
->ecc
.bytes
;
2367 int eccsteps
= chip
->ecc
.steps
;
2368 const uint8_t *p
= buf
;
2369 uint8_t *oob
= chip
->oob_poi
;
2371 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2373 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2374 chip
->write_buf(mtd
, p
, eccsize
);
2376 if (chip
->ecc
.prepad
) {
2377 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2378 oob
+= chip
->ecc
.prepad
;
2381 chip
->ecc
.calculate(mtd
, p
, oob
);
2382 chip
->write_buf(mtd
, oob
, eccbytes
);
2385 if (chip
->ecc
.postpad
) {
2386 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2387 oob
+= chip
->ecc
.postpad
;
2391 /* Calculate remaining oob bytes */
2392 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2394 chip
->write_buf(mtd
, oob
, i
);
2400 * nand_write_page - [REPLACEABLE] write one page
2401 * @mtd: MTD device structure
2402 * @chip: NAND chip descriptor
2403 * @offset: address offset within the page
2404 * @data_len: length of actual data to be written
2405 * @buf: the data to write
2406 * @oob_required: must write chip->oob_poi to OOB
2407 * @page: page number to write
2408 * @cached: cached programming
2409 * @raw: use _raw version of write_page
2411 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2412 uint32_t offset
, int data_len
, const uint8_t *buf
,
2413 int oob_required
, int page
, int cached
, int raw
)
2415 int status
, subpage
;
2417 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2418 chip
->ecc
.write_subpage
)
2419 subpage
= offset
|| (data_len
< mtd
->writesize
);
2423 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2426 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2427 oob_required
, page
);
2429 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2430 buf
, oob_required
, page
);
2432 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2439 * Cached progamming disabled for now. Not sure if it's worth the
2440 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2444 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2446 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2447 status
= chip
->waitfunc(mtd
, chip
);
2449 * See if operation failed and additional status checks are
2452 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2453 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2456 if (status
& NAND_STATUS_FAIL
)
2459 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2460 status
= chip
->waitfunc(mtd
, chip
);
2467 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2468 * @mtd: MTD device structure
2469 * @oob: oob data buffer
2470 * @len: oob data write length
2471 * @ops: oob ops structure
2473 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2474 struct mtd_oob_ops
*ops
)
2476 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2480 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2481 * data from a previous OOB read.
2483 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2485 switch (ops
->mode
) {
2487 case MTD_OPS_PLACE_OOB
:
2489 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2492 case MTD_OPS_AUTO_OOB
:
2493 ret
= mtd_ooblayout_set_databytes(mtd
, oob
, chip
->oob_poi
,
2504 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2507 * nand_do_write_ops - [INTERN] NAND write with ECC
2508 * @mtd: MTD device structure
2509 * @to: offset to write to
2510 * @ops: oob operations description structure
2512 * NAND write with ECC.
2514 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2515 struct mtd_oob_ops
*ops
)
2517 int chipnr
, realpage
, page
, blockmask
, column
;
2518 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2519 uint32_t writelen
= ops
->len
;
2521 uint32_t oobwritelen
= ops
->ooblen
;
2522 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2524 uint8_t *oob
= ops
->oobbuf
;
2525 uint8_t *buf
= ops
->datbuf
;
2527 int oob_required
= oob
? 1 : 0;
2533 /* Reject writes, which are not page aligned */
2534 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2535 pr_notice("%s: attempt to write non page aligned data\n",
2540 column
= to
& (mtd
->writesize
- 1);
2542 chipnr
= (int)(to
>> chip
->chip_shift
);
2543 chip
->select_chip(mtd
, chipnr
);
2545 /* Check, if it is write protected */
2546 if (nand_check_wp(mtd
)) {
2551 realpage
= (int)(to
>> chip
->page_shift
);
2552 page
= realpage
& chip
->pagemask
;
2553 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2555 /* Invalidate the page cache, when we write to the cached page */
2556 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2557 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2560 /* Don't allow multipage oob writes with offset */
2561 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2567 int bytes
= mtd
->writesize
;
2568 int cached
= writelen
> bytes
&& page
!= blockmask
;
2569 uint8_t *wbuf
= buf
;
2571 int part_pagewr
= (column
|| writelen
< (mtd
->writesize
- 1));
2575 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2576 use_bufpoi
= !virt_addr_valid(buf
);
2580 /* Partial page write?, or need to use bounce buffer */
2582 pr_debug("%s: using write bounce buffer for buf@%p\n",
2586 bytes
= min_t(int, bytes
- column
, writelen
);
2588 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2589 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2590 wbuf
= chip
->buffers
->databuf
;
2593 if (unlikely(oob
)) {
2594 size_t len
= min(oobwritelen
, oobmaxlen
);
2595 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2598 /* We still need to erase leftover OOB data */
2599 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2601 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2602 oob_required
, page
, cached
,
2603 (ops
->mode
== MTD_OPS_RAW
));
2615 page
= realpage
& chip
->pagemask
;
2616 /* Check, if we cross a chip boundary */
2619 chip
->select_chip(mtd
, -1);
2620 chip
->select_chip(mtd
, chipnr
);
2624 ops
->retlen
= ops
->len
- writelen
;
2626 ops
->oobretlen
= ops
->ooblen
;
2629 chip
->select_chip(mtd
, -1);
2634 * panic_nand_write - [MTD Interface] NAND write with ECC
2635 * @mtd: MTD device structure
2636 * @to: offset to write to
2637 * @len: number of bytes to write
2638 * @retlen: pointer to variable to store the number of written bytes
2639 * @buf: the data to write
2641 * NAND write with ECC. Used when performing writes in interrupt context, this
2642 * may for example be called by mtdoops when writing an oops while in panic.
2644 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2645 size_t *retlen
, const uint8_t *buf
)
2647 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2648 struct mtd_oob_ops ops
;
2651 /* Wait for the device to get ready */
2652 panic_nand_wait(mtd
, chip
, 400);
2654 /* Grab the device */
2655 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2657 memset(&ops
, 0, sizeof(ops
));
2659 ops
.datbuf
= (uint8_t *)buf
;
2660 ops
.mode
= MTD_OPS_PLACE_OOB
;
2662 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2664 *retlen
= ops
.retlen
;
2669 * nand_write - [MTD Interface] NAND write with ECC
2670 * @mtd: MTD device structure
2671 * @to: offset to write to
2672 * @len: number of bytes to write
2673 * @retlen: pointer to variable to store the number of written bytes
2674 * @buf: the data to write
2676 * NAND write with ECC.
2678 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2679 size_t *retlen
, const uint8_t *buf
)
2681 struct mtd_oob_ops ops
;
2684 nand_get_device(mtd
, FL_WRITING
);
2685 memset(&ops
, 0, sizeof(ops
));
2687 ops
.datbuf
= (uint8_t *)buf
;
2688 ops
.mode
= MTD_OPS_PLACE_OOB
;
2689 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2690 *retlen
= ops
.retlen
;
2691 nand_release_device(mtd
);
2696 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2697 * @mtd: MTD device structure
2698 * @to: offset to write to
2699 * @ops: oob operation description structure
2701 * NAND write out-of-band.
2703 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2704 struct mtd_oob_ops
*ops
)
2706 int chipnr
, page
, status
, len
;
2707 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2709 pr_debug("%s: to = 0x%08x, len = %i\n",
2710 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2712 len
= mtd_oobavail(mtd
, ops
);
2714 /* Do not allow write past end of page */
2715 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2716 pr_debug("%s: attempt to write past end of page\n",
2721 if (unlikely(ops
->ooboffs
>= len
)) {
2722 pr_debug("%s: attempt to start write outside oob\n",
2727 /* Do not allow write past end of device */
2728 if (unlikely(to
>= mtd
->size
||
2729 ops
->ooboffs
+ ops
->ooblen
>
2730 ((mtd
->size
>> chip
->page_shift
) -
2731 (to
>> chip
->page_shift
)) * len
)) {
2732 pr_debug("%s: attempt to write beyond end of device\n",
2737 chipnr
= (int)(to
>> chip
->chip_shift
);
2738 chip
->select_chip(mtd
, chipnr
);
2740 /* Shift to get page */
2741 page
= (int)(to
>> chip
->page_shift
);
2744 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2745 * of my DiskOnChip 2000 test units) will clear the whole data page too
2746 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2747 * it in the doc2000 driver in August 1999. dwmw2.
2749 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2751 /* Check, if it is write protected */
2752 if (nand_check_wp(mtd
)) {
2753 chip
->select_chip(mtd
, -1);
2757 /* Invalidate the page cache, if we write to the cached page */
2758 if (page
== chip
->pagebuf
)
2761 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2763 if (ops
->mode
== MTD_OPS_RAW
)
2764 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2766 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2768 chip
->select_chip(mtd
, -1);
2773 ops
->oobretlen
= ops
->ooblen
;
2779 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2780 * @mtd: MTD device structure
2781 * @to: offset to write to
2782 * @ops: oob operation description structure
2784 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2785 struct mtd_oob_ops
*ops
)
2787 int ret
= -ENOTSUPP
;
2791 /* Do not allow writes past end of device */
2792 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2793 pr_debug("%s: attempt to write beyond end of device\n",
2798 nand_get_device(mtd
, FL_WRITING
);
2800 switch (ops
->mode
) {
2801 case MTD_OPS_PLACE_OOB
:
2802 case MTD_OPS_AUTO_OOB
:
2811 ret
= nand_do_write_oob(mtd
, to
, ops
);
2813 ret
= nand_do_write_ops(mtd
, to
, ops
);
2816 nand_release_device(mtd
);
2821 * single_erase - [GENERIC] NAND standard block erase command function
2822 * @mtd: MTD device structure
2823 * @page: the page address of the block which will be erased
2825 * Standard erase command for NAND chips. Returns NAND status.
2827 static int single_erase(struct mtd_info
*mtd
, int page
)
2829 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2830 /* Send commands to erase a block */
2831 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2832 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2834 return chip
->waitfunc(mtd
, chip
);
2838 * nand_erase - [MTD Interface] erase block(s)
2839 * @mtd: MTD device structure
2840 * @instr: erase instruction
2842 * Erase one ore more blocks.
2844 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2846 return nand_erase_nand(mtd
, instr
, 0);
2850 * nand_erase_nand - [INTERN] erase block(s)
2851 * @mtd: MTD device structure
2852 * @instr: erase instruction
2853 * @allowbbt: allow erasing the bbt area
2855 * Erase one ore more blocks.
2857 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2860 int page
, status
, pages_per_block
, ret
, chipnr
;
2861 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2864 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2865 __func__
, (unsigned long long)instr
->addr
,
2866 (unsigned long long)instr
->len
);
2868 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2871 /* Grab the lock and see if the device is available */
2872 nand_get_device(mtd
, FL_ERASING
);
2874 /* Shift to get first page */
2875 page
= (int)(instr
->addr
>> chip
->page_shift
);
2876 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2878 /* Calculate pages in each block */
2879 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2881 /* Select the NAND device */
2882 chip
->select_chip(mtd
, chipnr
);
2884 /* Check, if it is write protected */
2885 if (nand_check_wp(mtd
)) {
2886 pr_debug("%s: device is write protected!\n",
2888 instr
->state
= MTD_ERASE_FAILED
;
2892 /* Loop through the pages */
2895 instr
->state
= MTD_ERASING
;
2898 /* Check if we have a bad block, we do not erase bad blocks! */
2899 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2900 chip
->page_shift
, allowbbt
)) {
2901 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2903 instr
->state
= MTD_ERASE_FAILED
;
2908 * Invalidate the page cache, if we erase the block which
2909 * contains the current cached page.
2911 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2912 (page
+ pages_per_block
))
2915 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2918 * See if operation failed and additional status checks are
2921 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2922 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2925 /* See if block erase succeeded */
2926 if (status
& NAND_STATUS_FAIL
) {
2927 pr_debug("%s: failed erase, page 0x%08x\n",
2929 instr
->state
= MTD_ERASE_FAILED
;
2931 ((loff_t
)page
<< chip
->page_shift
);
2935 /* Increment page address and decrement length */
2936 len
-= (1ULL << chip
->phys_erase_shift
);
2937 page
+= pages_per_block
;
2939 /* Check, if we cross a chip boundary */
2940 if (len
&& !(page
& chip
->pagemask
)) {
2942 chip
->select_chip(mtd
, -1);
2943 chip
->select_chip(mtd
, chipnr
);
2946 instr
->state
= MTD_ERASE_DONE
;
2950 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2952 /* Deselect and wake up anyone waiting on the device */
2953 chip
->select_chip(mtd
, -1);
2954 nand_release_device(mtd
);
2956 /* Do call back function */
2958 mtd_erase_callback(instr
);
2960 /* Return more or less happy */
2965 * nand_sync - [MTD Interface] sync
2966 * @mtd: MTD device structure
2968 * Sync is actually a wait for chip ready function.
2970 static void nand_sync(struct mtd_info
*mtd
)
2972 pr_debug("%s: called\n", __func__
);
2974 /* Grab the lock and see if the device is available */
2975 nand_get_device(mtd
, FL_SYNCING
);
2976 /* Release it and go back */
2977 nand_release_device(mtd
);
2981 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2982 * @mtd: MTD device structure
2983 * @offs: offset relative to mtd start
2985 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2987 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2988 int chipnr
= (int)(offs
>> chip
->chip_shift
);
2991 /* Select the NAND device */
2992 nand_get_device(mtd
, FL_READING
);
2993 chip
->select_chip(mtd
, chipnr
);
2995 ret
= nand_block_checkbad(mtd
, offs
, 0);
2997 chip
->select_chip(mtd
, -1);
2998 nand_release_device(mtd
);
3004 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3005 * @mtd: MTD device structure
3006 * @ofs: offset relative to mtd start
3008 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3012 ret
= nand_block_isbad(mtd
, ofs
);
3014 /* If it was bad already, return success and do nothing */
3020 return nand_block_markbad_lowlevel(mtd
, ofs
);
3024 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3025 * @mtd: MTD device structure
3026 * @chip: nand chip info structure
3027 * @addr: feature address.
3028 * @subfeature_param: the subfeature parameters, a four bytes array.
3030 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3031 int addr
, uint8_t *subfeature_param
)
3036 if (!chip
->onfi_version
||
3037 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3038 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3041 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3042 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3043 chip
->write_byte(mtd
, subfeature_param
[i
]);
3045 status
= chip
->waitfunc(mtd
, chip
);
3046 if (status
& NAND_STATUS_FAIL
)
3052 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3053 * @mtd: MTD device structure
3054 * @chip: nand chip info structure
3055 * @addr: feature address.
3056 * @subfeature_param: the subfeature parameters, a four bytes array.
3058 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3059 int addr
, uint8_t *subfeature_param
)
3063 if (!chip
->onfi_version
||
3064 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3065 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3068 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3069 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3070 *subfeature_param
++ = chip
->read_byte(mtd
);
3075 * nand_suspend - [MTD Interface] Suspend the NAND flash
3076 * @mtd: MTD device structure
3078 static int nand_suspend(struct mtd_info
*mtd
)
3080 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3084 * nand_resume - [MTD Interface] Resume the NAND flash
3085 * @mtd: MTD device structure
3087 static void nand_resume(struct mtd_info
*mtd
)
3089 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3091 if (chip
->state
== FL_PM_SUSPENDED
)
3092 nand_release_device(mtd
);
3094 pr_err("%s called for a chip which is not in suspended state\n",
3099 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3100 * prevent further operations
3101 * @mtd: MTD device structure
3103 static void nand_shutdown(struct mtd_info
*mtd
)
3105 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3108 /* Set default functions */
3109 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3111 /* check for proper chip_delay setup, set 20us if not */
3112 if (!chip
->chip_delay
)
3113 chip
->chip_delay
= 20;
3115 /* check, if a user supplied command function given */
3116 if (chip
->cmdfunc
== NULL
)
3117 chip
->cmdfunc
= nand_command
;
3119 /* check, if a user supplied wait function given */
3120 if (chip
->waitfunc
== NULL
)
3121 chip
->waitfunc
= nand_wait
;
3123 if (!chip
->select_chip
)
3124 chip
->select_chip
= nand_select_chip
;
3126 /* set for ONFI nand */
3127 if (!chip
->onfi_set_features
)
3128 chip
->onfi_set_features
= nand_onfi_set_features
;
3129 if (!chip
->onfi_get_features
)
3130 chip
->onfi_get_features
= nand_onfi_get_features
;
3132 /* If called twice, pointers that depend on busw may need to be reset */
3133 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3134 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3135 if (!chip
->read_word
)
3136 chip
->read_word
= nand_read_word
;
3137 if (!chip
->block_bad
)
3138 chip
->block_bad
= nand_block_bad
;
3139 if (!chip
->block_markbad
)
3140 chip
->block_markbad
= nand_default_block_markbad
;
3141 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3142 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3143 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3144 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3145 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3146 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3147 if (!chip
->scan_bbt
)
3148 chip
->scan_bbt
= nand_default_bbt
;
3150 if (!chip
->controller
) {
3151 chip
->controller
= &chip
->hwcontrol
;
3152 spin_lock_init(&chip
->controller
->lock
);
3153 init_waitqueue_head(&chip
->controller
->wq
);
3158 /* Sanitize ONFI strings so we can safely print them */
3159 static void sanitize_string(uint8_t *s
, size_t len
)
3163 /* Null terminate */
3166 /* Remove non printable chars */
3167 for (i
= 0; i
< len
- 1; i
++) {
3168 if (s
[i
] < ' ' || s
[i
] > 127)
3172 /* Remove trailing spaces */
3176 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3181 for (i
= 0; i
< 8; i
++)
3182 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3188 /* Parse the Extended Parameter Page. */
3189 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3190 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3192 struct onfi_ext_param_page
*ep
;
3193 struct onfi_ext_section
*s
;
3194 struct onfi_ext_ecc_info
*ecc
;
3200 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3201 ep
= kmalloc(len
, GFP_KERNEL
);
3205 /* Send our own NAND_CMD_PARAM. */
3206 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3208 /* Use the Change Read Column command to skip the ONFI param pages. */
3209 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3210 sizeof(*p
) * p
->num_of_param_pages
, -1);
3212 /* Read out the Extended Parameter Page. */
3213 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3214 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3215 != le16_to_cpu(ep
->crc
))) {
3216 pr_debug("fail in the CRC.\n");
3221 * Check the signature.
3222 * Do not strictly follow the ONFI spec, maybe changed in future.
3224 if (strncmp(ep
->sig
, "EPPS", 4)) {
3225 pr_debug("The signature is invalid.\n");
3229 /* find the ECC section. */
3230 cursor
= (uint8_t *)(ep
+ 1);
3231 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3232 s
= ep
->sections
+ i
;
3233 if (s
->type
== ONFI_SECTION_TYPE_2
)
3235 cursor
+= s
->length
* 16;
3237 if (i
== ONFI_EXT_SECTION_MAX
) {
3238 pr_debug("We can not find the ECC section.\n");
3242 /* get the info we want. */
3243 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3245 if (!ecc
->codeword_size
) {
3246 pr_debug("Invalid codeword size\n");
3250 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3251 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3259 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3261 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3262 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3264 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3269 * Configure chip properties from Micron vendor-specific ONFI table
3271 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3272 struct nand_onfi_params
*p
)
3274 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3276 if (le16_to_cpu(p
->vendor_revision
) < 1)
3279 chip
->read_retries
= micron
->read_retry_options
;
3280 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3284 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3286 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3289 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3293 /* Try ONFI for unknown chip or LP */
3294 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3295 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3296 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3299 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3300 for (i
= 0; i
< 3; i
++) {
3301 for (j
= 0; j
< sizeof(*p
); j
++)
3302 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3303 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3304 le16_to_cpu(p
->crc
)) {
3310 pr_err("Could not find valid ONFI parameter page; aborting\n");
3315 val
= le16_to_cpu(p
->revision
);
3317 chip
->onfi_version
= 23;
3318 else if (val
& (1 << 4))
3319 chip
->onfi_version
= 22;
3320 else if (val
& (1 << 3))
3321 chip
->onfi_version
= 21;
3322 else if (val
& (1 << 2))
3323 chip
->onfi_version
= 20;
3324 else if (val
& (1 << 1))
3325 chip
->onfi_version
= 10;
3327 if (!chip
->onfi_version
) {
3328 pr_info("unsupported ONFI version: %d\n", val
);
3332 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3333 sanitize_string(p
->model
, sizeof(p
->model
));
3335 mtd
->name
= p
->model
;
3337 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3340 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3341 * (don't ask me who thought of this...). MTD assumes that these
3342 * dimensions will be power-of-2, so just truncate the remaining area.
3344 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3345 mtd
->erasesize
*= mtd
->writesize
;
3347 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3349 /* See erasesize comment */
3350 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3351 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3352 chip
->bits_per_cell
= p
->bits_per_cell
;
3354 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3355 *busw
= NAND_BUSWIDTH_16
;
3359 if (p
->ecc_bits
!= 0xff) {
3360 chip
->ecc_strength_ds
= p
->ecc_bits
;
3361 chip
->ecc_step_ds
= 512;
3362 } else if (chip
->onfi_version
>= 21 &&
3363 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3366 * The nand_flash_detect_ext_param_page() uses the
3367 * Change Read Column command which maybe not supported
3368 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3369 * now. We do not replace user supplied command function.
3371 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3372 chip
->cmdfunc
= nand_command_lp
;
3374 /* The Extended Parameter Page is supported since ONFI 2.1. */
3375 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3376 pr_warn("Failed to detect ONFI extended param page\n");
3378 pr_warn("Could not retrieve ONFI ECC requirements\n");
3381 if (p
->jedec_id
== NAND_MFR_MICRON
)
3382 nand_onfi_detect_micron(chip
, p
);
3388 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3390 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3393 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3394 struct jedec_ecc_info
*ecc
;
3398 /* Try JEDEC for unknown chip or LP */
3399 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3400 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3401 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3402 chip
->read_byte(mtd
) != 'C')
3405 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3406 for (i
= 0; i
< 3; i
++) {
3407 for (j
= 0; j
< sizeof(*p
); j
++)
3408 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3410 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3411 le16_to_cpu(p
->crc
))
3416 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3421 val
= le16_to_cpu(p
->revision
);
3423 chip
->jedec_version
= 10;
3424 else if (val
& (1 << 1))
3425 chip
->jedec_version
= 1; /* vendor specific version */
3427 if (!chip
->jedec_version
) {
3428 pr_info("unsupported JEDEC version: %d\n", val
);
3432 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3433 sanitize_string(p
->model
, sizeof(p
->model
));
3435 mtd
->name
= p
->model
;
3437 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3439 /* Please reference to the comment for nand_flash_detect_onfi. */
3440 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3441 mtd
->erasesize
*= mtd
->writesize
;
3443 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3445 /* Please reference to the comment for nand_flash_detect_onfi. */
3446 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3447 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3448 chip
->bits_per_cell
= p
->bits_per_cell
;
3450 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3451 *busw
= NAND_BUSWIDTH_16
;
3456 ecc
= &p
->ecc_info
[0];
3458 if (ecc
->codeword_size
>= 9) {
3459 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3460 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3462 pr_warn("Invalid codeword size\n");
3469 * nand_id_has_period - Check if an ID string has a given wraparound period
3470 * @id_data: the ID string
3471 * @arrlen: the length of the @id_data array
3472 * @period: the period of repitition
3474 * Check if an ID string is repeated within a given sequence of bytes at
3475 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3476 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3477 * if the repetition has a period of @period; otherwise, returns zero.
3479 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3482 for (i
= 0; i
< period
; i
++)
3483 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3484 if (id_data
[i
] != id_data
[j
])
3490 * nand_id_len - Get the length of an ID string returned by CMD_READID
3491 * @id_data: the ID string
3492 * @arrlen: the length of the @id_data array
3494 * Returns the length of the ID string, according to known wraparound/trailing
3495 * zero patterns. If no pattern exists, returns the length of the array.
3497 static int nand_id_len(u8
*id_data
, int arrlen
)
3499 int last_nonzero
, period
;
3501 /* Find last non-zero byte */
3502 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3503 if (id_data
[last_nonzero
])
3507 if (last_nonzero
< 0)
3510 /* Calculate wraparound period */
3511 for (period
= 1; period
< arrlen
; period
++)
3512 if (nand_id_has_period(id_data
, arrlen
, period
))
3515 /* There's a repeated pattern */
3516 if (period
< arrlen
)
3519 /* There are trailing zeros */
3520 if (last_nonzero
< arrlen
- 1)
3521 return last_nonzero
+ 1;
3523 /* No pattern detected */
3527 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3528 static int nand_get_bits_per_cell(u8 cellinfo
)
3532 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3533 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3538 * Many new NAND share similar device ID codes, which represent the size of the
3539 * chip. The rest of the parameters must be decoded according to generic or
3540 * manufacturer-specific "extended ID" decoding patterns.
3542 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3543 u8 id_data
[8], int *busw
)
3546 /* The 3rd id byte holds MLC / multichip data */
3547 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3548 /* The 4th id byte is the important one */
3551 id_len
= nand_id_len(id_data
, 8);
3554 * Field definitions are in the following datasheets:
3555 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3556 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3557 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3559 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3560 * ID to decide what to do.
3562 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3563 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3565 mtd
->writesize
= 2048 << (extid
& 0x03);
3568 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3588 default: /* Other cases are "reserved" (unknown) */
3589 mtd
->oobsize
= 1024;
3593 /* Calc blocksize */
3594 mtd
->erasesize
= (128 * 1024) <<
3595 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3597 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3598 !nand_is_slc(chip
)) {
3602 mtd
->writesize
= 2048 << (extid
& 0x03);
3605 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3629 /* Calc blocksize */
3630 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3632 mtd
->erasesize
= (128 * 1024) << tmp
;
3633 else if (tmp
== 0x03)
3634 mtd
->erasesize
= 768 * 1024;
3636 mtd
->erasesize
= (64 * 1024) << tmp
;
3640 mtd
->writesize
= 1024 << (extid
& 0x03);
3643 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3644 (mtd
->writesize
>> 9);
3646 /* Calc blocksize. Blocksize is multiples of 64KiB */
3647 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3649 /* Get buswidth information */
3650 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3653 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3654 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3656 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3658 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3660 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3661 nand_is_slc(chip
) &&
3662 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3663 !(id_data
[4] & 0x80) /* !BENAND */) {
3664 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3671 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3672 * decodes a matching ID table entry and assigns the MTD size parameters for
3675 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3676 struct nand_flash_dev
*type
, u8 id_data
[8],
3679 int maf_id
= id_data
[0];
3681 mtd
->erasesize
= type
->erasesize
;
3682 mtd
->writesize
= type
->pagesize
;
3683 mtd
->oobsize
= mtd
->writesize
/ 32;
3684 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3686 /* All legacy ID NAND are small-page, SLC */
3687 chip
->bits_per_cell
= 1;
3690 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3691 * some Spansion chips have erasesize that conflicts with size
3692 * listed in nand_ids table.
3693 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3695 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3696 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3697 && mtd
->writesize
== 512) {
3698 mtd
->erasesize
= 128 * 1024;
3699 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3704 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3705 * heuristic patterns using various detected parameters (e.g., manufacturer,
3706 * page size, cell-type information).
3708 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3709 struct nand_chip
*chip
, u8 id_data
[8])
3711 int maf_id
= id_data
[0];
3713 /* Set the bad block position */
3714 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3715 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3717 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3720 * Bad block marker is stored in the last page of each block on Samsung
3721 * and Hynix MLC devices; stored in first two pages of each block on
3722 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3723 * AMD/Spansion, and Macronix. All others scan only the first page.
3725 if (!nand_is_slc(chip
) &&
3726 (maf_id
== NAND_MFR_SAMSUNG
||
3727 maf_id
== NAND_MFR_HYNIX
))
3728 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3729 else if ((nand_is_slc(chip
) &&
3730 (maf_id
== NAND_MFR_SAMSUNG
||
3731 maf_id
== NAND_MFR_HYNIX
||
3732 maf_id
== NAND_MFR_TOSHIBA
||
3733 maf_id
== NAND_MFR_AMD
||
3734 maf_id
== NAND_MFR_MACRONIX
)) ||
3735 (mtd
->writesize
== 2048 &&
3736 maf_id
== NAND_MFR_MICRON
))
3737 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3740 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3742 return type
->id_len
;
3745 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3746 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3748 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3749 mtd
->writesize
= type
->pagesize
;
3750 mtd
->erasesize
= type
->erasesize
;
3751 mtd
->oobsize
= type
->oobsize
;
3753 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3754 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3755 chip
->options
|= type
->options
;
3756 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3757 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3758 chip
->onfi_timing_mode_default
=
3759 type
->onfi_timing_mode_default
;
3761 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3764 mtd
->name
= type
->name
;
3772 * Get the flash and manufacturer id and lookup if the type is supported.
3774 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3775 struct nand_chip
*chip
,
3776 int *maf_id
, int *dev_id
,
3777 struct nand_flash_dev
*type
)
3783 /* Select the device */
3784 chip
->select_chip(mtd
, 0);
3787 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3790 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3792 /* Send the command for reading device ID */
3793 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3795 /* Read manufacturer and device IDs */
3796 *maf_id
= chip
->read_byte(mtd
);
3797 *dev_id
= chip
->read_byte(mtd
);
3800 * Try again to make sure, as some systems the bus-hold or other
3801 * interface concerns can cause random data which looks like a
3802 * possibly credible NAND flash to appear. If the two results do
3803 * not match, ignore the device completely.
3806 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3808 /* Read entire ID string */
3809 for (i
= 0; i
< 8; i
++)
3810 id_data
[i
] = chip
->read_byte(mtd
);
3812 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3813 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3814 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3815 return ERR_PTR(-ENODEV
);
3819 type
= nand_flash_ids
;
3821 for (; type
->name
!= NULL
; type
++) {
3822 if (is_full_id_nand(type
)) {
3823 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3825 } else if (*dev_id
== type
->dev_id
) {
3830 chip
->onfi_version
= 0;
3831 if (!type
->name
|| !type
->pagesize
) {
3832 /* Check if the chip is ONFI compliant */
3833 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3836 /* Check if the chip is JEDEC compliant */
3837 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3842 return ERR_PTR(-ENODEV
);
3845 mtd
->name
= type
->name
;
3847 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3849 if (!type
->pagesize
) {
3850 /* Decode parameters from extended ID */
3851 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3853 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3855 /* Get chip options */
3856 chip
->options
|= type
->options
;
3859 * Check if chip is not a Samsung device. Do not clear the
3860 * options for chips which do not have an extended id.
3862 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3863 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3866 /* Try to identify manufacturer */
3867 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3868 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3872 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3873 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3874 chip
->options
|= busw
;
3875 nand_set_defaults(chip
, busw
);
3876 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3878 * Check, if buswidth is correct. Hardware drivers should set
3881 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3883 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3884 pr_warn("bus width %d instead %d bit\n",
3885 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3887 return ERR_PTR(-EINVAL
);
3890 nand_decode_bbm_options(mtd
, chip
, id_data
);
3892 /* Calculate the address shift from the page size */
3893 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3894 /* Convert chipsize to number of pages per chip -1 */
3895 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3897 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3898 ffs(mtd
->erasesize
) - 1;
3899 if (chip
->chipsize
& 0xffffffff)
3900 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3902 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3903 chip
->chip_shift
+= 32 - 1;
3906 chip
->badblockbits
= 8;
3907 chip
->erase
= single_erase
;
3909 /* Do not replace user supplied command function! */
3910 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3911 chip
->cmdfunc
= nand_command_lp
;
3913 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3916 if (chip
->onfi_version
)
3917 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3918 chip
->onfi_params
.model
);
3919 else if (chip
->jedec_version
)
3920 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3921 chip
->jedec_params
.model
);
3923 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3926 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3927 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3928 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3932 static int nand_dt_init(struct nand_chip
*chip
)
3934 struct device_node
*dn
= nand_get_flash_node(chip
);
3935 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
3940 if (of_get_nand_bus_width(dn
) == 16)
3941 chip
->options
|= NAND_BUSWIDTH_16
;
3943 if (of_get_nand_on_flash_bbt(dn
))
3944 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3946 ecc_mode
= of_get_nand_ecc_mode(dn
);
3947 ecc_algo
= of_get_nand_ecc_algo(dn
);
3948 ecc_strength
= of_get_nand_ecc_strength(dn
);
3949 ecc_step
= of_get_nand_ecc_step_size(dn
);
3951 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3952 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3953 pr_err("must set both strength and step size in DT\n");
3958 chip
->ecc
.mode
= ecc_mode
;
3961 chip
->ecc
.algo
= ecc_algo
;
3963 if (ecc_strength
>= 0)
3964 chip
->ecc
.strength
= ecc_strength
;
3967 chip
->ecc
.size
= ecc_step
;
3973 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3974 * @mtd: MTD device structure
3975 * @maxchips: number of chips to scan for
3976 * @table: alternative NAND ID table
3978 * This is the first phase of the normal nand_scan() function. It reads the
3979 * flash ID and sets up MTD fields accordingly.
3981 * The mtd->owner field must be set to the module of the caller.
3983 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3984 struct nand_flash_dev
*table
)
3986 int i
, nand_maf_id
, nand_dev_id
;
3987 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3988 struct nand_flash_dev
*type
;
3991 ret
= nand_dt_init(chip
);
3995 if (!mtd
->name
&& mtd
->dev
.parent
)
3996 mtd
->name
= dev_name(mtd
->dev
.parent
);
3998 /* Set the default functions */
3999 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4001 /* Read the flash type */
4002 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4003 &nand_dev_id
, table
);
4006 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4007 pr_warn("No NAND device found\n");
4008 chip
->select_chip(mtd
, -1);
4009 return PTR_ERR(type
);
4012 chip
->select_chip(mtd
, -1);
4014 /* Check for a chip array */
4015 for (i
= 1; i
< maxchips
; i
++) {
4016 chip
->select_chip(mtd
, i
);
4017 /* See comment in nand_get_flash_type for reset */
4018 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
4019 /* Send the command for reading device ID */
4020 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4021 /* Read manufacturer and device IDs */
4022 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4023 nand_dev_id
!= chip
->read_byte(mtd
)) {
4024 chip
->select_chip(mtd
, -1);
4027 chip
->select_chip(mtd
, -1);
4030 pr_info("%d chips detected\n", i
);
4032 /* Store the number of chips and calc total size for mtd */
4034 mtd
->size
= i
* chip
->chipsize
;
4038 EXPORT_SYMBOL(nand_scan_ident
);
4041 * Check if the chip configuration meet the datasheet requirements.
4043 * If our configuration corrects A bits per B bytes and the minimum
4044 * required correction level is X bits per Y bytes, then we must ensure
4045 * both of the following are true:
4047 * (1) A / B >= X / Y
4050 * Requirement (1) ensures we can correct for the required bitflip density.
4051 * Requirement (2) ensures we can correct even when all bitflips are clumped
4052 * in the same sector.
4054 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4056 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4057 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4060 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4061 /* Not enough information */
4065 * We get the number of corrected bits per page to compare
4066 * the correction density.
4068 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4069 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4071 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4075 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4076 * @mtd: MTD device structure
4078 * This is the second phase of the normal nand_scan() function. It fills out
4079 * all the uninitialized function pointers with the defaults and scans for a
4080 * bad block table if appropriate.
4082 int nand_scan_tail(struct mtd_info
*mtd
)
4084 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4085 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4086 struct nand_buffers
*nbuf
;
4089 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4090 if (WARN_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4091 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
)))
4094 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4095 nbuf
= kzalloc(sizeof(*nbuf
) + mtd
->writesize
4096 + mtd
->oobsize
* 3, GFP_KERNEL
);
4099 nbuf
->ecccalc
= (uint8_t *)(nbuf
+ 1);
4100 nbuf
->ecccode
= nbuf
->ecccalc
+ mtd
->oobsize
;
4101 nbuf
->databuf
= nbuf
->ecccode
+ mtd
->oobsize
;
4103 chip
->buffers
= nbuf
;
4109 /* Set the internal oob buffer location, just after the page data */
4110 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4113 * If no default placement scheme is given, select an appropriate one.
4115 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4116 switch (mtd
->oobsize
) {
4118 ecc
->layout
= &nand_oob_8
;
4121 ecc
->layout
= &nand_oob_16
;
4124 ecc
->layout
= &nand_oob_64
;
4127 ecc
->layout
= &nand_oob_128
;
4130 WARN(1, "No oob scheme defined for oobsize %d\n",
4137 if (!chip
->write_page
)
4138 chip
->write_page
= nand_write_page
;
4141 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4142 * selected and we have 256 byte pagesize fallback to software ECC
4145 switch (ecc
->mode
) {
4146 case NAND_ECC_HW_OOB_FIRST
:
4147 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4148 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4149 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4153 if (!ecc
->read_page
)
4154 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4157 /* Use standard hwecc read page function? */
4158 if (!ecc
->read_page
)
4159 ecc
->read_page
= nand_read_page_hwecc
;
4160 if (!ecc
->write_page
)
4161 ecc
->write_page
= nand_write_page_hwecc
;
4162 if (!ecc
->read_page_raw
)
4163 ecc
->read_page_raw
= nand_read_page_raw
;
4164 if (!ecc
->write_page_raw
)
4165 ecc
->write_page_raw
= nand_write_page_raw
;
4167 ecc
->read_oob
= nand_read_oob_std
;
4168 if (!ecc
->write_oob
)
4169 ecc
->write_oob
= nand_write_oob_std
;
4170 if (!ecc
->read_subpage
)
4171 ecc
->read_subpage
= nand_read_subpage
;
4172 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4173 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4175 case NAND_ECC_HW_SYNDROME
:
4176 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4178 ecc
->read_page
== nand_read_page_hwecc
||
4180 ecc
->write_page
== nand_write_page_hwecc
)) {
4181 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4185 /* Use standard syndrome read/write page function? */
4186 if (!ecc
->read_page
)
4187 ecc
->read_page
= nand_read_page_syndrome
;
4188 if (!ecc
->write_page
)
4189 ecc
->write_page
= nand_write_page_syndrome
;
4190 if (!ecc
->read_page_raw
)
4191 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4192 if (!ecc
->write_page_raw
)
4193 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4195 ecc
->read_oob
= nand_read_oob_syndrome
;
4196 if (!ecc
->write_oob
)
4197 ecc
->write_oob
= nand_write_oob_syndrome
;
4199 if (mtd
->writesize
>= ecc
->size
) {
4200 if (!ecc
->strength
) {
4201 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4207 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4208 ecc
->size
, mtd
->writesize
);
4209 ecc
->mode
= NAND_ECC_SOFT
;
4212 ecc
->calculate
= nand_calculate_ecc
;
4213 ecc
->correct
= nand_correct_data
;
4214 ecc
->read_page
= nand_read_page_swecc
;
4215 ecc
->read_subpage
= nand_read_subpage
;
4216 ecc
->write_page
= nand_write_page_swecc
;
4217 ecc
->read_page_raw
= nand_read_page_raw
;
4218 ecc
->write_page_raw
= nand_write_page_raw
;
4219 ecc
->read_oob
= nand_read_oob_std
;
4220 ecc
->write_oob
= nand_write_oob_std
;
4227 case NAND_ECC_SOFT_BCH
:
4228 if (!mtd_nand_has_bch()) {
4229 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4233 ecc
->calculate
= nand_bch_calculate_ecc
;
4234 ecc
->correct
= nand_bch_correct_data
;
4235 ecc
->read_page
= nand_read_page_swecc
;
4236 ecc
->read_subpage
= nand_read_subpage
;
4237 ecc
->write_page
= nand_write_page_swecc
;
4238 ecc
->read_page_raw
= nand_read_page_raw
;
4239 ecc
->write_page_raw
= nand_write_page_raw
;
4240 ecc
->read_oob
= nand_read_oob_std
;
4241 ecc
->write_oob
= nand_write_oob_std
;
4243 * Board driver should supply ecc.size and ecc.strength values
4244 * to select how many bits are correctable. Otherwise, default
4245 * to 4 bits for large page devices.
4247 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4252 /* See nand_bch_init() for details. */
4254 ecc
->priv
= nand_bch_init(mtd
);
4256 WARN(1, "BCH ECC initialization failed!\n");
4263 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4264 ecc
->read_page
= nand_read_page_raw
;
4265 ecc
->write_page
= nand_write_page_raw
;
4266 ecc
->read_oob
= nand_read_oob_std
;
4267 ecc
->read_page_raw
= nand_read_page_raw
;
4268 ecc
->write_page_raw
= nand_write_page_raw
;
4269 ecc
->write_oob
= nand_write_oob_std
;
4270 ecc
->size
= mtd
->writesize
;
4276 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4281 /* For many systems, the standard OOB write also works for raw */
4282 if (!ecc
->read_oob_raw
)
4283 ecc
->read_oob_raw
= ecc
->read_oob
;
4284 if (!ecc
->write_oob_raw
)
4285 ecc
->write_oob_raw
= ecc
->write_oob
;
4287 /* propagate ecc info to mtd_info */
4288 mtd
->ecclayout
= ecc
->layout
;
4289 mtd
->ecc_strength
= ecc
->strength
;
4290 mtd
->ecc_step_size
= ecc
->size
;
4293 * Set the number of read / write steps for one page depending on ECC
4296 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4297 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4298 WARN(1, "Invalid ECC parameters\n");
4302 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4305 * The number of bytes available for a client to place data into
4306 * the out of band area.
4308 ret
= mtd_ooblayout_count_freebytes(mtd
);
4312 mtd
->oobavail
= ret
;
4314 /* ECC sanity check: warn if it's too weak */
4315 if (!nand_ecc_strength_good(mtd
))
4316 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4319 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4320 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4321 switch (ecc
->steps
) {
4323 mtd
->subpage_sft
= 1;
4328 mtd
->subpage_sft
= 2;
4332 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4334 /* Initialize state */
4335 chip
->state
= FL_READY
;
4337 /* Invalidate the pagebuffer reference */
4340 /* Large page NAND with SOFT_ECC should support subpage reads */
4341 switch (ecc
->mode
) {
4343 case NAND_ECC_SOFT_BCH
:
4344 if (chip
->page_shift
> 9)
4345 chip
->options
|= NAND_SUBPAGE_READ
;
4352 /* Fill in remaining MTD driver data */
4353 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4354 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4356 mtd
->_erase
= nand_erase
;
4358 mtd
->_unpoint
= NULL
;
4359 mtd
->_read
= nand_read
;
4360 mtd
->_write
= nand_write
;
4361 mtd
->_panic_write
= panic_nand_write
;
4362 mtd
->_read_oob
= nand_read_oob
;
4363 mtd
->_write_oob
= nand_write_oob
;
4364 mtd
->_sync
= nand_sync
;
4366 mtd
->_unlock
= NULL
;
4367 mtd
->_suspend
= nand_suspend
;
4368 mtd
->_resume
= nand_resume
;
4369 mtd
->_reboot
= nand_shutdown
;
4370 mtd
->_block_isreserved
= nand_block_isreserved
;
4371 mtd
->_block_isbad
= nand_block_isbad
;
4372 mtd
->_block_markbad
= nand_block_markbad
;
4373 mtd
->writebufsize
= mtd
->writesize
;
4376 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4377 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4380 if (!mtd
->bitflip_threshold
)
4381 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4383 /* Check, if we should skip the bad block table scan */
4384 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4387 /* Build bad block table */
4388 return chip
->scan_bbt(mtd
);
4390 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4391 kfree(chip
->buffers
);
4394 EXPORT_SYMBOL(nand_scan_tail
);
4397 * is_module_text_address() isn't exported, and it's mostly a pointless
4398 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4399 * to call us from in-kernel code if the core NAND support is modular.
4402 #define caller_is_module() (1)
4404 #define caller_is_module() \
4405 is_module_text_address((unsigned long)__builtin_return_address(0))
4409 * nand_scan - [NAND Interface] Scan for the NAND device
4410 * @mtd: MTD device structure
4411 * @maxchips: number of chips to scan for
4413 * This fills out all the uninitialized function pointers with the defaults.
4414 * The flash ID is read and the mtd/chip structures are filled with the
4415 * appropriate values. The mtd->owner field must be set to the module of the
4418 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4422 /* Many callers got this wrong, so check for it for a while... */
4423 if (!mtd
->owner
&& caller_is_module()) {
4424 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
4428 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4430 ret
= nand_scan_tail(mtd
);
4433 EXPORT_SYMBOL(nand_scan
);
4436 * nand_release - [NAND Interface] Free resources held by the NAND device
4437 * @mtd: MTD device structure
4439 void nand_release(struct mtd_info
*mtd
)
4441 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4443 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
4444 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
4446 mtd_device_unregister(mtd
);
4448 /* Free bad block table memory */
4450 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4451 kfree(chip
->buffers
);
4453 /* Free bad block descriptor memory */
4454 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
4455 & NAND_BBT_DYNAMICSTRUCT
)
4456 kfree(chip
->badblock_pattern
);
4458 EXPORT_SYMBOL_GPL(nand_release
);
4460 MODULE_LICENSE("GPL");
4461 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4462 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4463 MODULE_DESCRIPTION("Generic NAND flash driver code");