3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
46 #include <linux/leds.h>
48 #include <linux/mtd/partitions.h>
49 #include <linux/of_mtd.h>
51 /* Define default oob placement schemes for large and small page devices */
52 static struct nand_ecclayout nand_oob_8
= {
62 static struct nand_ecclayout nand_oob_16
= {
64 .eccpos
= {0, 1, 2, 3, 6, 7},
70 static struct nand_ecclayout nand_oob_64
= {
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
81 static struct nand_ecclayout nand_oob_128
= {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
95 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
97 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
98 struct mtd_oob_ops
*ops
);
101 * For devices which display every fart in the system on a separate LED. Is
102 * compiled away when LED support is disabled.
104 DEFINE_LED_TRIGGER(nand_led_trigger
);
106 static int check_offs_len(struct mtd_info
*mtd
,
107 loff_t ofs
, uint64_t len
)
109 struct nand_chip
*chip
= mtd_to_nand(mtd
);
112 /* Start address must align on block boundary */
113 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
114 pr_debug("%s: unaligned address\n", __func__
);
118 /* Length must align on block boundary */
119 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
120 pr_debug("%s: length not block aligned\n", __func__
);
128 * nand_release_device - [GENERIC] release chip
129 * @mtd: MTD device structure
131 * Release chip lock and wake up anyone waiting on the device.
133 static void nand_release_device(struct mtd_info
*mtd
)
135 struct nand_chip
*chip
= mtd_to_nand(mtd
);
137 /* Release the controller and the chip */
138 spin_lock(&chip
->controller
->lock
);
139 chip
->controller
->active
= NULL
;
140 chip
->state
= FL_READY
;
141 wake_up(&chip
->controller
->wq
);
142 spin_unlock(&chip
->controller
->lock
);
146 * nand_read_byte - [DEFAULT] read one byte from the chip
147 * @mtd: MTD device structure
149 * Default read function for 8bit buswidth
151 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
153 struct nand_chip
*chip
= mtd_to_nand(mtd
);
154 return readb(chip
->IO_ADDR_R
);
158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
159 * @mtd: MTD device structure
161 * Default read function for 16bit buswidth with endianness conversion.
164 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
166 struct nand_chip
*chip
= mtd_to_nand(mtd
);
167 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
171 * nand_read_word - [DEFAULT] read one word from the chip
172 * @mtd: MTD device structure
174 * Default read function for 16bit buswidth without endianness conversion.
176 static u16
nand_read_word(struct mtd_info
*mtd
)
178 struct nand_chip
*chip
= mtd_to_nand(mtd
);
179 return readw(chip
->IO_ADDR_R
);
183 * nand_select_chip - [DEFAULT] control CE line
184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
187 * Default select function for 1 chip devices.
189 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
191 struct nand_chip
*chip
= mtd_to_nand(mtd
);
195 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
210 * Default function to write a byte to I/O[7:0]
212 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
214 struct nand_chip
*chip
= mtd_to_nand(mtd
);
216 chip
->write_buf(mtd
, &byte
, 1);
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
228 struct nand_chip
*chip
= mtd_to_nand(mtd
);
229 uint16_t word
= byte
;
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
247 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
251 * nand_write_buf - [DEFAULT] write buffer to chip
252 * @mtd: MTD device structure
254 * @len: number of bytes to write
256 * Default write function for 8bit buswidth.
258 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
260 struct nand_chip
*chip
= mtd_to_nand(mtd
);
262 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
266 * nand_read_buf - [DEFAULT] read chip data into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
271 * Default read function for 8bit buswidth.
273 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
275 struct nand_chip
*chip
= mtd_to_nand(mtd
);
277 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 * Default write function for 16bit buswidth.
288 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
290 struct nand_chip
*chip
= mtd_to_nand(mtd
);
291 u16
*p
= (u16
*) buf
;
293 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
302 * Default read function for 16bit buswidth.
304 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
306 struct nand_chip
*chip
= mtd_to_nand(mtd
);
307 u16
*p
= (u16
*) buf
;
309 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
318 * Check, if the block is bad.
320 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
322 int page
, chipnr
, res
= 0, i
= 0;
323 struct nand_chip
*chip
= mtd_to_nand(mtd
);
326 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
327 ofs
+= mtd
->erasesize
- mtd
->writesize
;
329 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
332 chipnr
= (int)(ofs
>> chip
->chip_shift
);
334 nand_get_device(mtd
, FL_READING
);
336 /* Select the NAND device */
337 chip
->select_chip(mtd
, chipnr
);
341 if (chip
->options
& NAND_BUSWIDTH_16
) {
342 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
343 chip
->badblockpos
& 0xFE, page
);
344 bad
= cpu_to_le16(chip
->read_word(mtd
));
345 if (chip
->badblockpos
& 0x1)
350 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
352 bad
= chip
->read_byte(mtd
);
355 if (likely(chip
->badblockbits
== 8))
358 res
= hweight8(bad
) < chip
->badblockbits
;
359 ofs
+= mtd
->writesize
;
360 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
362 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
365 chip
->select_chip(mtd
, -1);
366 nand_release_device(mtd
);
373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
374 * @mtd: MTD device structure
375 * @ofs: offset from device start
377 * This is the default implementation, which can be overridden by a hardware
378 * specific driver. It provides the details for writing a bad block marker to a
381 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
383 struct nand_chip
*chip
= mtd_to_nand(mtd
);
384 struct mtd_oob_ops ops
;
385 uint8_t buf
[2] = { 0, 0 };
386 int ret
= 0, res
, i
= 0;
388 memset(&ops
, 0, sizeof(ops
));
390 ops
.ooboffs
= chip
->badblockpos
;
391 if (chip
->options
& NAND_BUSWIDTH_16
) {
392 ops
.ooboffs
&= ~0x01;
393 ops
.len
= ops
.ooblen
= 2;
395 ops
.len
= ops
.ooblen
= 1;
397 ops
.mode
= MTD_OPS_PLACE_OOB
;
399 /* Write to first/last page(s) if necessary */
400 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
401 ofs
+= mtd
->erasesize
- mtd
->writesize
;
403 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
408 ofs
+= mtd
->writesize
;
409 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
423 * We try operations in the following order:
424 * (1) erase the affected block, to allow OOB marker to be written cleanly
425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
428 * Note that we retain the first error encountered in (2) or (3), finish the
429 * procedures, and dump the error in the end.
431 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
433 struct nand_chip
*chip
= mtd_to_nand(mtd
);
436 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
437 struct erase_info einfo
;
439 /* Attempt erase before marking OOB */
440 memset(&einfo
, 0, sizeof(einfo
));
443 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
444 nand_erase_nand(mtd
, &einfo
, 0);
446 /* Write bad block marker to OOB */
447 nand_get_device(mtd
, FL_WRITING
);
448 ret
= chip
->block_markbad(mtd
, ofs
);
449 nand_release_device(mtd
);
452 /* Mark block bad in BBT */
454 res
= nand_markbad_bbt(mtd
, ofs
);
460 mtd
->ecc_stats
.badblocks
++;
466 * nand_check_wp - [GENERIC] check if the chip is write protected
467 * @mtd: MTD device structure
469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
472 static int nand_check_wp(struct mtd_info
*mtd
)
474 struct nand_chip
*chip
= mtd_to_nand(mtd
);
476 /* Broken xD cards report WP despite being writable */
477 if (chip
->options
& NAND_BROKEN_XD
)
480 /* Check the WP bit */
481 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
482 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
487 * @mtd: MTD device structure
488 * @ofs: offset from device start
490 * Check if the block is marked as reserved.
492 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
494 struct nand_chip
*chip
= mtd_to_nand(mtd
);
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd
, ofs
);
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
512 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
515 struct nand_chip
*chip
= mtd_to_nand(mtd
);
518 return chip
->block_bad(mtd
, ofs
, getchip
);
520 /* Return info from the table */
521 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
526 * @mtd: MTD device structure
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
532 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
534 struct nand_chip
*chip
= mtd_to_nand(mtd
);
537 /* Wait for the device to get ready */
538 for (i
= 0; i
< timeo
; i
++) {
539 if (chip
->dev_ready(mtd
))
541 touch_softlockup_watchdog();
547 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
548 * @mtd: MTD device structure
550 * Wait for the ready pin after a command, and warn if a timeout occurs.
552 void nand_wait_ready(struct mtd_info
*mtd
)
554 struct nand_chip
*chip
= mtd_to_nand(mtd
);
555 unsigned long timeo
= 400;
557 if (in_interrupt() || oops_in_progress
)
558 return panic_nand_wait_ready(mtd
, timeo
);
560 led_trigger_event(nand_led_trigger
, LED_FULL
);
561 /* Wait until command is processed or timeout occurs */
562 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
564 if (chip
->dev_ready(mtd
))
567 } while (time_before(jiffies
, timeo
));
570 "timeout while waiting for chip to become ready\n");
572 led_trigger_event(nand_led_trigger
, LED_OFF
);
574 EXPORT_SYMBOL_GPL(nand_wait_ready
);
577 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
578 * @mtd: MTD device structure
579 * @timeo: Timeout in ms
581 * Wait for status ready (i.e. command done) or timeout.
583 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
585 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
587 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
589 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
591 touch_softlockup_watchdog();
592 } while (time_before(jiffies
, timeo
));
596 * nand_command - [DEFAULT] Send command to NAND device
597 * @mtd: MTD device structure
598 * @command: the command to be sent
599 * @column: the column address for this command, -1 if none
600 * @page_addr: the page address for this command, -1 if none
602 * Send command to NAND device. This function is used for small page devices
603 * (512 Bytes per page).
605 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
606 int column
, int page_addr
)
608 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
609 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
611 /* Write out the command to the device */
612 if (command
== NAND_CMD_SEQIN
) {
615 if (column
>= mtd
->writesize
) {
617 column
-= mtd
->writesize
;
618 readcmd
= NAND_CMD_READOOB
;
619 } else if (column
< 256) {
620 /* First 256 bytes --> READ0 */
621 readcmd
= NAND_CMD_READ0
;
624 readcmd
= NAND_CMD_READ1
;
626 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
627 ctrl
&= ~NAND_CTRL_CHANGE
;
629 chip
->cmd_ctrl(mtd
, command
, ctrl
);
631 /* Address cycle, when necessary */
632 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
633 /* Serially input address */
635 /* Adjust columns for 16 bit buswidth */
636 if (chip
->options
& NAND_BUSWIDTH_16
&&
637 !nand_opcode_8bits(command
))
639 chip
->cmd_ctrl(mtd
, column
, ctrl
);
640 ctrl
&= ~NAND_CTRL_CHANGE
;
642 if (page_addr
!= -1) {
643 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
644 ctrl
&= ~NAND_CTRL_CHANGE
;
645 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
646 /* One more address cycle for devices > 32MiB */
647 if (chip
->chipsize
> (32 << 20))
648 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
650 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
653 * Program and erase have their own busy handlers status and sequential
658 case NAND_CMD_PAGEPROG
:
659 case NAND_CMD_ERASE1
:
660 case NAND_CMD_ERASE2
:
662 case NAND_CMD_STATUS
:
668 udelay(chip
->chip_delay
);
669 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
670 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
672 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
673 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
674 nand_wait_status_ready(mtd
, 250);
677 /* This applies to read commands */
680 * If we don't have access to the busy pin, we apply the given
683 if (!chip
->dev_ready
) {
684 udelay(chip
->chip_delay
);
689 * Apply this short delay always to ensure that we do wait tWB in
690 * any case on any machine.
694 nand_wait_ready(mtd
);
698 * nand_command_lp - [DEFAULT] Send command to NAND large page device
699 * @mtd: MTD device structure
700 * @command: the command to be sent
701 * @column: the column address for this command, -1 if none
702 * @page_addr: the page address for this command, -1 if none
704 * Send command to NAND device. This is the version for the new large page
705 * devices. We don't have the separate regions as we have in the small page
706 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
708 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
709 int column
, int page_addr
)
711 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
713 /* Emulate NAND_CMD_READOOB */
714 if (command
== NAND_CMD_READOOB
) {
715 column
+= mtd
->writesize
;
716 command
= NAND_CMD_READ0
;
719 /* Command latch cycle */
720 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
722 if (column
!= -1 || page_addr
!= -1) {
723 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
725 /* Serially input address */
727 /* Adjust columns for 16 bit buswidth */
728 if (chip
->options
& NAND_BUSWIDTH_16
&&
729 !nand_opcode_8bits(command
))
731 chip
->cmd_ctrl(mtd
, column
, ctrl
);
732 ctrl
&= ~NAND_CTRL_CHANGE
;
733 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
735 if (page_addr
!= -1) {
736 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
737 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
738 NAND_NCE
| NAND_ALE
);
739 /* One more address cycle for devices > 128MiB */
740 if (chip
->chipsize
> (128 << 20))
741 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
742 NAND_NCE
| NAND_ALE
);
745 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
748 * Program and erase have their own busy handlers status, sequential
749 * in and status need no delay.
753 case NAND_CMD_CACHEDPROG
:
754 case NAND_CMD_PAGEPROG
:
755 case NAND_CMD_ERASE1
:
756 case NAND_CMD_ERASE2
:
759 case NAND_CMD_STATUS
:
765 udelay(chip
->chip_delay
);
766 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
767 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
768 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
769 NAND_NCE
| NAND_CTRL_CHANGE
);
770 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
771 nand_wait_status_ready(mtd
, 250);
774 case NAND_CMD_RNDOUT
:
775 /* No ready / busy check necessary */
776 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
777 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
778 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
779 NAND_NCE
| NAND_CTRL_CHANGE
);
783 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
784 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
785 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
786 NAND_NCE
| NAND_CTRL_CHANGE
);
788 /* This applies to read commands */
791 * If we don't have access to the busy pin, we apply the given
794 if (!chip
->dev_ready
) {
795 udelay(chip
->chip_delay
);
801 * Apply this short delay always to ensure that we do wait tWB in
802 * any case on any machine.
806 nand_wait_ready(mtd
);
810 * panic_nand_get_device - [GENERIC] Get chip for selected access
811 * @chip: the nand chip descriptor
812 * @mtd: MTD device structure
813 * @new_state: the state which is requested
815 * Used when in panic, no locks are taken.
817 static void panic_nand_get_device(struct nand_chip
*chip
,
818 struct mtd_info
*mtd
, int new_state
)
820 /* Hardware controller shared among independent devices */
821 chip
->controller
->active
= chip
;
822 chip
->state
= new_state
;
826 * nand_get_device - [GENERIC] Get chip for selected access
827 * @mtd: MTD device structure
828 * @new_state: the state which is requested
830 * Get the device and lock it for exclusive access
833 nand_get_device(struct mtd_info
*mtd
, int new_state
)
835 struct nand_chip
*chip
= mtd_to_nand(mtd
);
836 spinlock_t
*lock
= &chip
->controller
->lock
;
837 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
838 DECLARE_WAITQUEUE(wait
, current
);
842 /* Hardware controller shared among independent devices */
843 if (!chip
->controller
->active
)
844 chip
->controller
->active
= chip
;
846 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
847 chip
->state
= new_state
;
851 if (new_state
== FL_PM_SUSPENDED
) {
852 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
853 chip
->state
= FL_PM_SUSPENDED
;
858 set_current_state(TASK_UNINTERRUPTIBLE
);
859 add_wait_queue(wq
, &wait
);
862 remove_wait_queue(wq
, &wait
);
867 * panic_nand_wait - [GENERIC] wait until the command is done
868 * @mtd: MTD device structure
869 * @chip: NAND chip structure
872 * Wait for command done. This is a helper function for nand_wait used when
873 * we are in interrupt context. May happen when in panic and trying to write
874 * an oops through mtdoops.
876 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
880 for (i
= 0; i
< timeo
; i
++) {
881 if (chip
->dev_ready
) {
882 if (chip
->dev_ready(mtd
))
885 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
893 * nand_wait - [DEFAULT] wait until the command is done
894 * @mtd: MTD device structure
895 * @chip: NAND chip structure
897 * Wait for command done. This applies to erase and program only.
899 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
903 unsigned long timeo
= 400;
905 led_trigger_event(nand_led_trigger
, LED_FULL
);
908 * Apply this short delay always to ensure that we do wait tWB in any
909 * case on any machine.
913 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
915 if (in_interrupt() || oops_in_progress
)
916 panic_nand_wait(mtd
, chip
, timeo
);
918 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
920 if (chip
->dev_ready
) {
921 if (chip
->dev_ready(mtd
))
924 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
928 } while (time_before(jiffies
, timeo
));
930 led_trigger_event(nand_led_trigger
, LED_OFF
);
932 status
= (int)chip
->read_byte(mtd
);
933 /* This can happen if in case of timeout or buggy dev_ready */
934 WARN_ON(!(status
& NAND_STATUS_READY
));
939 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
941 * @ofs: offset to start unlock from
942 * @len: length to unlock
943 * @invert: when = 0, unlock the range of blocks within the lower and
944 * upper boundary address
945 * when = 1, unlock the range of blocks outside the boundaries
946 * of the lower and upper boundary address
948 * Returs unlock status.
950 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
951 uint64_t len
, int invert
)
955 struct nand_chip
*chip
= mtd_to_nand(mtd
);
957 /* Submit address of first page to unlock */
958 page
= ofs
>> chip
->page_shift
;
959 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
961 /* Submit address of last page to unlock */
962 page
= (ofs
+ len
) >> chip
->page_shift
;
963 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
964 (page
| invert
) & chip
->pagemask
);
966 /* Call wait ready function */
967 status
= chip
->waitfunc(mtd
, chip
);
968 /* See if device thinks it succeeded */
969 if (status
& NAND_STATUS_FAIL
) {
970 pr_debug("%s: error status = 0x%08x\n",
979 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
981 * @ofs: offset to start unlock from
982 * @len: length to unlock
984 * Returns unlock status.
986 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
990 struct nand_chip
*chip
= mtd_to_nand(mtd
);
992 pr_debug("%s: start = 0x%012llx, len = %llu\n",
993 __func__
, (unsigned long long)ofs
, len
);
995 if (check_offs_len(mtd
, ofs
, len
))
998 /* Align to last block address if size addresses end of the device */
999 if (ofs
+ len
== mtd
->size
)
1000 len
-= mtd
->erasesize
;
1002 nand_get_device(mtd
, FL_UNLOCKING
);
1004 /* Shift to get chip number */
1005 chipnr
= ofs
>> chip
->chip_shift
;
1007 chip
->select_chip(mtd
, chipnr
);
1011 * If we want to check the WP through READ STATUS and check the bit 7
1012 * we must reset the chip
1013 * some operation can also clear the bit 7 of status register
1014 * eg. erase/program a locked block
1016 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1018 /* Check, if it is write protected */
1019 if (nand_check_wp(mtd
)) {
1020 pr_debug("%s: device is write protected!\n",
1026 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
1029 chip
->select_chip(mtd
, -1);
1030 nand_release_device(mtd
);
1034 EXPORT_SYMBOL(nand_unlock
);
1037 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1039 * @ofs: offset to start unlock from
1040 * @len: length to unlock
1042 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1043 * have this feature, but it allows only to lock all blocks, not for specified
1044 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1047 * Returns lock status.
1049 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1052 int chipnr
, status
, page
;
1053 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1055 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1056 __func__
, (unsigned long long)ofs
, len
);
1058 if (check_offs_len(mtd
, ofs
, len
))
1061 nand_get_device(mtd
, FL_LOCKING
);
1063 /* Shift to get chip number */
1064 chipnr
= ofs
>> chip
->chip_shift
;
1066 chip
->select_chip(mtd
, chipnr
);
1070 * If we want to check the WP through READ STATUS and check the bit 7
1071 * we must reset the chip
1072 * some operation can also clear the bit 7 of status register
1073 * eg. erase/program a locked block
1075 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1077 /* Check, if it is write protected */
1078 if (nand_check_wp(mtd
)) {
1079 pr_debug("%s: device is write protected!\n",
1081 status
= MTD_ERASE_FAILED
;
1086 /* Submit address of first page to lock */
1087 page
= ofs
>> chip
->page_shift
;
1088 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1090 /* Call wait ready function */
1091 status
= chip
->waitfunc(mtd
, chip
);
1092 /* See if device thinks it succeeded */
1093 if (status
& NAND_STATUS_FAIL
) {
1094 pr_debug("%s: error status = 0x%08x\n",
1100 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1103 chip
->select_chip(mtd
, -1);
1104 nand_release_device(mtd
);
1108 EXPORT_SYMBOL(nand_lock
);
1111 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1112 * @buf: buffer to test
1113 * @len: buffer length
1114 * @bitflips_threshold: maximum number of bitflips
1116 * Check if a buffer contains only 0xff, which means the underlying region
1117 * has been erased and is ready to be programmed.
1118 * The bitflips_threshold specify the maximum number of bitflips before
1119 * considering the region is not erased.
1120 * Note: The logic of this function has been extracted from the memweight
1121 * implementation, except that nand_check_erased_buf function exit before
1122 * testing the whole buffer if the number of bitflips exceed the
1123 * bitflips_threshold value.
1125 * Returns a positive number of bitflips less than or equal to
1126 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1129 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1131 const unsigned char *bitmap
= buf
;
1135 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1137 weight
= hweight8(*bitmap
);
1138 bitflips
+= BITS_PER_BYTE
- weight
;
1139 if (unlikely(bitflips
> bitflips_threshold
))
1143 for (; len
>= sizeof(long);
1144 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1145 weight
= hweight_long(*((unsigned long *)bitmap
));
1146 bitflips
+= BITS_PER_LONG
- weight
;
1147 if (unlikely(bitflips
> bitflips_threshold
))
1151 for (; len
> 0; len
--, bitmap
++) {
1152 weight
= hweight8(*bitmap
);
1153 bitflips
+= BITS_PER_BYTE
- weight
;
1154 if (unlikely(bitflips
> bitflips_threshold
))
1162 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1164 * @data: data buffer to test
1165 * @datalen: data length
1167 * @ecclen: ECC length
1168 * @extraoob: extra OOB buffer
1169 * @extraooblen: extra OOB length
1170 * @bitflips_threshold: maximum number of bitflips
1172 * Check if a data buffer and its associated ECC and OOB data contains only
1173 * 0xff pattern, which means the underlying region has been erased and is
1174 * ready to be programmed.
1175 * The bitflips_threshold specify the maximum number of bitflips before
1176 * considering the region as not erased.
1179 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1180 * different from the NAND page size. When fixing bitflips, ECC engines will
1181 * report the number of errors per chunk, and the NAND core infrastructure
1182 * expect you to return the maximum number of bitflips for the whole page.
1183 * This is why you should always use this function on a single chunk and
1184 * not on the whole page. After checking each chunk you should update your
1185 * max_bitflips value accordingly.
1186 * 2/ When checking for bitflips in erased pages you should not only check
1187 * the payload data but also their associated ECC data, because a user might
1188 * have programmed almost all bits to 1 but a few. In this case, we
1189 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1191 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1192 * data are protected by the ECC engine.
1193 * It could also be used if you support subpages and want to attach some
1194 * extra OOB data to an ECC chunk.
1196 * Returns a positive number of bitflips less than or equal to
1197 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1198 * threshold. In case of success, the passed buffers are filled with 0xff.
1200 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1201 void *ecc
, int ecclen
,
1202 void *extraoob
, int extraooblen
,
1203 int bitflips_threshold
)
1205 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1207 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1208 bitflips_threshold
);
1209 if (data_bitflips
< 0)
1210 return data_bitflips
;
1212 bitflips_threshold
-= data_bitflips
;
1214 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1215 if (ecc_bitflips
< 0)
1216 return ecc_bitflips
;
1218 bitflips_threshold
-= ecc_bitflips
;
1220 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1221 bitflips_threshold
);
1222 if (extraoob_bitflips
< 0)
1223 return extraoob_bitflips
;
1226 memset(data
, 0xff, datalen
);
1229 memset(ecc
, 0xff, ecclen
);
1231 if (extraoob_bitflips
)
1232 memset(extraoob
, 0xff, extraooblen
);
1234 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1236 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1239 * nand_read_page_raw - [INTERN] read raw page data without ecc
1240 * @mtd: mtd info structure
1241 * @chip: nand chip info structure
1242 * @buf: buffer to store read data
1243 * @oob_required: caller requires OOB data read to chip->oob_poi
1244 * @page: page number to read
1246 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1248 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1249 uint8_t *buf
, int oob_required
, int page
)
1251 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1253 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1258 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1259 * @mtd: mtd info structure
1260 * @chip: nand chip info structure
1261 * @buf: buffer to store read data
1262 * @oob_required: caller requires OOB data read to chip->oob_poi
1263 * @page: page number to read
1265 * We need a special oob layout and handling even when OOB isn't used.
1267 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1268 struct nand_chip
*chip
, uint8_t *buf
,
1269 int oob_required
, int page
)
1271 int eccsize
= chip
->ecc
.size
;
1272 int eccbytes
= chip
->ecc
.bytes
;
1273 uint8_t *oob
= chip
->oob_poi
;
1276 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1277 chip
->read_buf(mtd
, buf
, eccsize
);
1280 if (chip
->ecc
.prepad
) {
1281 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1282 oob
+= chip
->ecc
.prepad
;
1285 chip
->read_buf(mtd
, oob
, eccbytes
);
1288 if (chip
->ecc
.postpad
) {
1289 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1290 oob
+= chip
->ecc
.postpad
;
1294 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1296 chip
->read_buf(mtd
, oob
, size
);
1302 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1303 * @mtd: mtd info structure
1304 * @chip: nand chip info structure
1305 * @buf: buffer to store read data
1306 * @oob_required: caller requires OOB data read to chip->oob_poi
1307 * @page: page number to read
1309 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1310 uint8_t *buf
, int oob_required
, int page
)
1312 int i
, eccsize
= chip
->ecc
.size
;
1313 int eccbytes
= chip
->ecc
.bytes
;
1314 int eccsteps
= chip
->ecc
.steps
;
1316 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1317 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1318 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1319 unsigned int max_bitflips
= 0;
1321 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1323 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1324 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1326 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1327 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1329 eccsteps
= chip
->ecc
.steps
;
1332 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1335 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1337 mtd
->ecc_stats
.failed
++;
1339 mtd
->ecc_stats
.corrected
+= stat
;
1340 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1343 return max_bitflips
;
1347 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1348 * @mtd: mtd info structure
1349 * @chip: nand chip info structure
1350 * @data_offs: offset of requested data within the page
1351 * @readlen: data length
1352 * @bufpoi: buffer to store read data
1353 * @page: page number to read
1355 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1356 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1359 int start_step
, end_step
, num_steps
;
1360 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1362 int data_col_addr
, i
, gaps
= 0;
1363 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1364 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1366 unsigned int max_bitflips
= 0;
1368 /* Column address within the page aligned to ECC size (256bytes) */
1369 start_step
= data_offs
/ chip
->ecc
.size
;
1370 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1371 num_steps
= end_step
- start_step
+ 1;
1372 index
= start_step
* chip
->ecc
.bytes
;
1374 /* Data size aligned to ECC ecc.size */
1375 datafrag_len
= num_steps
* chip
->ecc
.size
;
1376 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1378 data_col_addr
= start_step
* chip
->ecc
.size
;
1379 /* If we read not a page aligned data */
1380 if (data_col_addr
!= 0)
1381 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1383 p
= bufpoi
+ data_col_addr
;
1384 chip
->read_buf(mtd
, p
, datafrag_len
);
1387 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1388 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1391 * The performance is faster if we position offsets according to
1392 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1394 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1395 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1401 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1402 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1405 * Send the command to read the particular ECC bytes take care
1406 * about buswidth alignment in read_buf.
1408 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1409 aligned_len
= eccfrag_len
;
1410 if (eccpos
[index
] & (busw
- 1))
1412 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1415 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1416 mtd
->writesize
+ aligned_pos
, -1);
1417 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1420 for (i
= 0; i
< eccfrag_len
; i
++)
1421 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1423 p
= bufpoi
+ data_col_addr
;
1424 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1427 stat
= chip
->ecc
.correct(mtd
, p
,
1428 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1429 if (stat
== -EBADMSG
&&
1430 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1431 /* check for empty pages with bitflips */
1432 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1433 &chip
->buffers
->ecccode
[i
],
1436 chip
->ecc
.strength
);
1440 mtd
->ecc_stats
.failed
++;
1442 mtd
->ecc_stats
.corrected
+= stat
;
1443 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1446 return max_bitflips
;
1450 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1451 * @mtd: mtd info structure
1452 * @chip: nand chip info structure
1453 * @buf: buffer to store read data
1454 * @oob_required: caller requires OOB data read to chip->oob_poi
1455 * @page: page number to read
1457 * Not for syndrome calculating ECC controllers which need a special oob layout.
1459 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1460 uint8_t *buf
, int oob_required
, int page
)
1462 int i
, eccsize
= chip
->ecc
.size
;
1463 int eccbytes
= chip
->ecc
.bytes
;
1464 int eccsteps
= chip
->ecc
.steps
;
1466 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1467 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1468 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1469 unsigned int max_bitflips
= 0;
1471 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1472 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1473 chip
->read_buf(mtd
, p
, eccsize
);
1474 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1476 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1478 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1479 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1481 eccsteps
= chip
->ecc
.steps
;
1484 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1487 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1488 if (stat
== -EBADMSG
&&
1489 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1490 /* check for empty pages with bitflips */
1491 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1492 &ecc_code
[i
], eccbytes
,
1494 chip
->ecc
.strength
);
1498 mtd
->ecc_stats
.failed
++;
1500 mtd
->ecc_stats
.corrected
+= stat
;
1501 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1504 return max_bitflips
;
1508 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1509 * @mtd: mtd info structure
1510 * @chip: nand chip info structure
1511 * @buf: buffer to store read data
1512 * @oob_required: caller requires OOB data read to chip->oob_poi
1513 * @page: page number to read
1515 * Hardware ECC for large page chips, require OOB to be read first. For this
1516 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1517 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1518 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1519 * the data area, by overwriting the NAND manufacturer bad block markings.
1521 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1522 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1524 int i
, eccsize
= chip
->ecc
.size
;
1525 int eccbytes
= chip
->ecc
.bytes
;
1526 int eccsteps
= chip
->ecc
.steps
;
1528 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1529 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1530 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1531 unsigned int max_bitflips
= 0;
1533 /* Read the OOB area first */
1534 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1535 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1536 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1538 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1539 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1541 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1544 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1545 chip
->read_buf(mtd
, p
, eccsize
);
1546 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1548 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1549 if (stat
== -EBADMSG
&&
1550 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1551 /* check for empty pages with bitflips */
1552 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1553 &ecc_code
[i
], eccbytes
,
1555 chip
->ecc
.strength
);
1559 mtd
->ecc_stats
.failed
++;
1561 mtd
->ecc_stats
.corrected
+= stat
;
1562 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1565 return max_bitflips
;
1569 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1570 * @mtd: mtd info structure
1571 * @chip: nand chip info structure
1572 * @buf: buffer to store read data
1573 * @oob_required: caller requires OOB data read to chip->oob_poi
1574 * @page: page number to read
1576 * The hw generator calculates the error syndrome automatically. Therefore we
1577 * need a special oob layout and handling.
1579 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1580 uint8_t *buf
, int oob_required
, int page
)
1582 int i
, eccsize
= chip
->ecc
.size
;
1583 int eccbytes
= chip
->ecc
.bytes
;
1584 int eccsteps
= chip
->ecc
.steps
;
1585 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1587 uint8_t *oob
= chip
->oob_poi
;
1588 unsigned int max_bitflips
= 0;
1590 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1593 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1594 chip
->read_buf(mtd
, p
, eccsize
);
1596 if (chip
->ecc
.prepad
) {
1597 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1598 oob
+= chip
->ecc
.prepad
;
1601 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1602 chip
->read_buf(mtd
, oob
, eccbytes
);
1603 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1607 if (chip
->ecc
.postpad
) {
1608 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1609 oob
+= chip
->ecc
.postpad
;
1612 if (stat
== -EBADMSG
&&
1613 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1614 /* check for empty pages with bitflips */
1615 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1619 chip
->ecc
.strength
);
1623 mtd
->ecc_stats
.failed
++;
1625 mtd
->ecc_stats
.corrected
+= stat
;
1626 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1630 /* Calculate remaining oob bytes */
1631 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1633 chip
->read_buf(mtd
, oob
, i
);
1635 return max_bitflips
;
1639 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1640 * @chip: nand chip structure
1641 * @oob: oob destination address
1642 * @ops: oob ops structure
1643 * @len: size of oob to transfer
1645 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1646 struct mtd_oob_ops
*ops
, size_t len
)
1648 switch (ops
->mode
) {
1650 case MTD_OPS_PLACE_OOB
:
1652 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1655 case MTD_OPS_AUTO_OOB
: {
1656 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1657 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1660 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1661 /* Read request not from offset 0? */
1662 if (unlikely(roffs
)) {
1663 if (roffs
>= free
->length
) {
1664 roffs
-= free
->length
;
1667 boffs
= free
->offset
+ roffs
;
1668 bytes
= min_t(size_t, len
,
1669 (free
->length
- roffs
));
1672 bytes
= min_t(size_t, len
, free
->length
);
1673 boffs
= free
->offset
;
1675 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1687 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1688 * @mtd: MTD device structure
1689 * @retry_mode: the retry mode to use
1691 * Some vendors supply a special command to shift the Vt threshold, to be used
1692 * when there are too many bitflips in a page (i.e., ECC error). After setting
1693 * a new threshold, the host should retry reading the page.
1695 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1697 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1699 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1701 if (retry_mode
>= chip
->read_retries
)
1704 if (!chip
->setup_read_retry
)
1707 return chip
->setup_read_retry(mtd
, retry_mode
);
1711 * nand_do_read_ops - [INTERN] Read data with ECC
1712 * @mtd: MTD device structure
1713 * @from: offset to read from
1714 * @ops: oob ops structure
1716 * Internal function. Called with chip held.
1718 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1719 struct mtd_oob_ops
*ops
)
1721 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1722 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1724 uint32_t readlen
= ops
->len
;
1725 uint32_t oobreadlen
= ops
->ooblen
;
1726 uint32_t max_oobsize
= ops
->mode
== MTD_OPS_AUTO_OOB
?
1727 mtd
->oobavail
: mtd
->oobsize
;
1729 uint8_t *bufpoi
, *oob
, *buf
;
1731 unsigned int max_bitflips
= 0;
1733 bool ecc_fail
= false;
1735 chipnr
= (int)(from
>> chip
->chip_shift
);
1736 chip
->select_chip(mtd
, chipnr
);
1738 realpage
= (int)(from
>> chip
->page_shift
);
1739 page
= realpage
& chip
->pagemask
;
1741 col
= (int)(from
& (mtd
->writesize
- 1));
1745 oob_required
= oob
? 1 : 0;
1748 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1750 bytes
= min(mtd
->writesize
- col
, readlen
);
1751 aligned
= (bytes
== mtd
->writesize
);
1755 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1756 use_bufpoi
= !virt_addr_valid(buf
);
1760 /* Is the current page in the buffer? */
1761 if (realpage
!= chip
->pagebuf
|| oob
) {
1762 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1764 if (use_bufpoi
&& aligned
)
1765 pr_debug("%s: using read bounce buffer for buf@%p\n",
1769 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1772 * Now read the page into the buffer. Absent an error,
1773 * the read methods return max bitflips per ecc step.
1775 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1776 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1779 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1781 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1785 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1786 oob_required
, page
);
1789 /* Invalidate page cache */
1794 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1796 /* Transfer not aligned data */
1798 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1799 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1800 (ops
->mode
!= MTD_OPS_RAW
)) {
1801 chip
->pagebuf
= realpage
;
1802 chip
->pagebuf_bitflips
= ret
;
1804 /* Invalidate page cache */
1807 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1810 if (unlikely(oob
)) {
1811 int toread
= min(oobreadlen
, max_oobsize
);
1814 oob
= nand_transfer_oob(chip
,
1816 oobreadlen
-= toread
;
1820 if (chip
->options
& NAND_NEED_READRDY
) {
1821 /* Apply delay or wait for ready/busy pin */
1822 if (!chip
->dev_ready
)
1823 udelay(chip
->chip_delay
);
1825 nand_wait_ready(mtd
);
1828 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1829 if (retry_mode
+ 1 < chip
->read_retries
) {
1831 ret
= nand_setup_read_retry(mtd
,
1836 /* Reset failures; retry */
1837 mtd
->ecc_stats
.failed
= ecc_failures
;
1840 /* No more retry modes; real failure */
1847 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1849 max_bitflips
= max_t(unsigned int, max_bitflips
,
1850 chip
->pagebuf_bitflips
);
1855 /* Reset to retry mode 0 */
1857 ret
= nand_setup_read_retry(mtd
, 0);
1866 /* For subsequent reads align to page boundary */
1868 /* Increment page address */
1871 page
= realpage
& chip
->pagemask
;
1872 /* Check, if we cross a chip boundary */
1875 chip
->select_chip(mtd
, -1);
1876 chip
->select_chip(mtd
, chipnr
);
1879 chip
->select_chip(mtd
, -1);
1881 ops
->retlen
= ops
->len
- (size_t) readlen
;
1883 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1891 return max_bitflips
;
1895 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1896 * @mtd: MTD device structure
1897 * @from: offset to read from
1898 * @len: number of bytes to read
1899 * @retlen: pointer to variable to store the number of read bytes
1900 * @buf: the databuffer to put data
1902 * Get hold of the chip and call nand_do_read.
1904 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1905 size_t *retlen
, uint8_t *buf
)
1907 struct mtd_oob_ops ops
;
1910 nand_get_device(mtd
, FL_READING
);
1911 memset(&ops
, 0, sizeof(ops
));
1914 ops
.mode
= MTD_OPS_PLACE_OOB
;
1915 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1916 *retlen
= ops
.retlen
;
1917 nand_release_device(mtd
);
1922 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1923 * @mtd: mtd info structure
1924 * @chip: nand chip info structure
1925 * @page: page number to read
1927 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1930 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1931 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1936 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1938 * @mtd: mtd info structure
1939 * @chip: nand chip info structure
1940 * @page: page number to read
1942 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1945 int length
= mtd
->oobsize
;
1946 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1947 int eccsize
= chip
->ecc
.size
;
1948 uint8_t *bufpoi
= chip
->oob_poi
;
1949 int i
, toread
, sndrnd
= 0, pos
;
1951 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1952 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1954 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1955 if (mtd
->writesize
> 512)
1956 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1958 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1961 toread
= min_t(int, length
, chunk
);
1962 chip
->read_buf(mtd
, bufpoi
, toread
);
1967 chip
->read_buf(mtd
, bufpoi
, length
);
1973 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1974 * @mtd: mtd info structure
1975 * @chip: nand chip info structure
1976 * @page: page number to write
1978 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1982 const uint8_t *buf
= chip
->oob_poi
;
1983 int length
= mtd
->oobsize
;
1985 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1986 chip
->write_buf(mtd
, buf
, length
);
1987 /* Send command to program the OOB data */
1988 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1990 status
= chip
->waitfunc(mtd
, chip
);
1992 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1996 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1997 * with syndrome - only for large page flash
1998 * @mtd: mtd info structure
1999 * @chip: nand chip info structure
2000 * @page: page number to write
2002 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
2003 struct nand_chip
*chip
, int page
)
2005 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2006 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
2007 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
2008 const uint8_t *bufpoi
= chip
->oob_poi
;
2011 * data-ecc-data-ecc ... ecc-oob
2013 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2015 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
2016 pos
= steps
* (eccsize
+ chunk
);
2021 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
2022 for (i
= 0; i
< steps
; i
++) {
2024 if (mtd
->writesize
<= 512) {
2025 uint32_t fill
= 0xFFFFFFFF;
2029 int num
= min_t(int, len
, 4);
2030 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2035 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2036 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2040 len
= min_t(int, length
, chunk
);
2041 chip
->write_buf(mtd
, bufpoi
, len
);
2046 chip
->write_buf(mtd
, bufpoi
, length
);
2048 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2049 status
= chip
->waitfunc(mtd
, chip
);
2051 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2055 * nand_do_read_oob - [INTERN] NAND read out-of-band
2056 * @mtd: MTD device structure
2057 * @from: offset to read from
2058 * @ops: oob operations description structure
2060 * NAND read out-of-band data from the spare area.
2062 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2063 struct mtd_oob_ops
*ops
)
2065 int page
, realpage
, chipnr
;
2066 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2067 struct mtd_ecc_stats stats
;
2068 int readlen
= ops
->ooblen
;
2070 uint8_t *buf
= ops
->oobbuf
;
2073 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2074 __func__
, (unsigned long long)from
, readlen
);
2076 stats
= mtd
->ecc_stats
;
2078 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2079 len
= chip
->ecc
.layout
->oobavail
;
2083 if (unlikely(ops
->ooboffs
>= len
)) {
2084 pr_debug("%s: attempt to start read outside oob\n",
2089 /* Do not allow reads past end of device */
2090 if (unlikely(from
>= mtd
->size
||
2091 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2092 (from
>> chip
->page_shift
)) * len
)) {
2093 pr_debug("%s: attempt to read beyond end of device\n",
2098 chipnr
= (int)(from
>> chip
->chip_shift
);
2099 chip
->select_chip(mtd
, chipnr
);
2101 /* Shift to get page */
2102 realpage
= (int)(from
>> chip
->page_shift
);
2103 page
= realpage
& chip
->pagemask
;
2106 if (ops
->mode
== MTD_OPS_RAW
)
2107 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2109 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2114 len
= min(len
, readlen
);
2115 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
2117 if (chip
->options
& NAND_NEED_READRDY
) {
2118 /* Apply delay or wait for ready/busy pin */
2119 if (!chip
->dev_ready
)
2120 udelay(chip
->chip_delay
);
2122 nand_wait_ready(mtd
);
2129 /* Increment page address */
2132 page
= realpage
& chip
->pagemask
;
2133 /* Check, if we cross a chip boundary */
2136 chip
->select_chip(mtd
, -1);
2137 chip
->select_chip(mtd
, chipnr
);
2140 chip
->select_chip(mtd
, -1);
2142 ops
->oobretlen
= ops
->ooblen
- readlen
;
2147 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2150 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2154 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2155 * @mtd: MTD device structure
2156 * @from: offset to read from
2157 * @ops: oob operation description structure
2159 * NAND read data and/or out-of-band data.
2161 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2162 struct mtd_oob_ops
*ops
)
2164 int ret
= -ENOTSUPP
;
2168 /* Do not allow reads past end of device */
2169 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2170 pr_debug("%s: attempt to read beyond end of device\n",
2175 nand_get_device(mtd
, FL_READING
);
2177 switch (ops
->mode
) {
2178 case MTD_OPS_PLACE_OOB
:
2179 case MTD_OPS_AUTO_OOB
:
2188 ret
= nand_do_read_oob(mtd
, from
, ops
);
2190 ret
= nand_do_read_ops(mtd
, from
, ops
);
2193 nand_release_device(mtd
);
2199 * nand_write_page_raw - [INTERN] raw page write function
2200 * @mtd: mtd info structure
2201 * @chip: nand chip info structure
2203 * @oob_required: must write chip->oob_poi to OOB
2204 * @page: page number to write
2206 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2208 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2209 const uint8_t *buf
, int oob_required
, int page
)
2211 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2213 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2219 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2220 * @mtd: mtd info structure
2221 * @chip: nand chip info structure
2223 * @oob_required: must write chip->oob_poi to OOB
2224 * @page: page number to write
2226 * We need a special oob layout and handling even when ECC isn't checked.
2228 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2229 struct nand_chip
*chip
,
2230 const uint8_t *buf
, int oob_required
,
2233 int eccsize
= chip
->ecc
.size
;
2234 int eccbytes
= chip
->ecc
.bytes
;
2235 uint8_t *oob
= chip
->oob_poi
;
2238 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2239 chip
->write_buf(mtd
, buf
, eccsize
);
2242 if (chip
->ecc
.prepad
) {
2243 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2244 oob
+= chip
->ecc
.prepad
;
2247 chip
->write_buf(mtd
, oob
, eccbytes
);
2250 if (chip
->ecc
.postpad
) {
2251 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2252 oob
+= chip
->ecc
.postpad
;
2256 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2258 chip
->write_buf(mtd
, oob
, size
);
2263 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2264 * @mtd: mtd info structure
2265 * @chip: nand chip info structure
2267 * @oob_required: must write chip->oob_poi to OOB
2268 * @page: page number to write
2270 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2271 const uint8_t *buf
, int oob_required
,
2274 int i
, eccsize
= chip
->ecc
.size
;
2275 int eccbytes
= chip
->ecc
.bytes
;
2276 int eccsteps
= chip
->ecc
.steps
;
2277 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2278 const uint8_t *p
= buf
;
2279 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2281 /* Software ECC calculation */
2282 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2283 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2285 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2286 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2288 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2292 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2293 * @mtd: mtd info structure
2294 * @chip: nand chip info structure
2296 * @oob_required: must write chip->oob_poi to OOB
2297 * @page: page number to write
2299 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2300 const uint8_t *buf
, int oob_required
,
2303 int i
, eccsize
= chip
->ecc
.size
;
2304 int eccbytes
= chip
->ecc
.bytes
;
2305 int eccsteps
= chip
->ecc
.steps
;
2306 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2307 const uint8_t *p
= buf
;
2308 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2310 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2311 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2312 chip
->write_buf(mtd
, p
, eccsize
);
2313 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2316 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2317 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2319 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2326 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2327 * @mtd: mtd info structure
2328 * @chip: nand chip info structure
2329 * @offset: column address of subpage within the page
2330 * @data_len: data length
2332 * @oob_required: must write chip->oob_poi to OOB
2333 * @page: page number to write
2335 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2336 struct nand_chip
*chip
, uint32_t offset
,
2337 uint32_t data_len
, const uint8_t *buf
,
2338 int oob_required
, int page
)
2340 uint8_t *oob_buf
= chip
->oob_poi
;
2341 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2342 int ecc_size
= chip
->ecc
.size
;
2343 int ecc_bytes
= chip
->ecc
.bytes
;
2344 int ecc_steps
= chip
->ecc
.steps
;
2345 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2346 uint32_t start_step
= offset
/ ecc_size
;
2347 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2348 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2351 for (step
= 0; step
< ecc_steps
; step
++) {
2352 /* configure controller for WRITE access */
2353 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2355 /* write data (untouched subpages already masked by 0xFF) */
2356 chip
->write_buf(mtd
, buf
, ecc_size
);
2358 /* mask ECC of un-touched subpages by padding 0xFF */
2359 if ((step
< start_step
) || (step
> end_step
))
2360 memset(ecc_calc
, 0xff, ecc_bytes
);
2362 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2364 /* mask OOB of un-touched subpages by padding 0xFF */
2365 /* if oob_required, preserve OOB metadata of written subpage */
2366 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2367 memset(oob_buf
, 0xff, oob_bytes
);
2370 ecc_calc
+= ecc_bytes
;
2371 oob_buf
+= oob_bytes
;
2374 /* copy calculated ECC for whole page to chip->buffer->oob */
2375 /* this include masked-value(0xFF) for unwritten subpages */
2376 ecc_calc
= chip
->buffers
->ecccalc
;
2377 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2378 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2380 /* write OOB buffer to NAND device */
2381 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2388 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2389 * @mtd: mtd info structure
2390 * @chip: nand chip info structure
2392 * @oob_required: must write chip->oob_poi to OOB
2393 * @page: page number to write
2395 * The hw generator calculates the error syndrome automatically. Therefore we
2396 * need a special oob layout and handling.
2398 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2399 struct nand_chip
*chip
,
2400 const uint8_t *buf
, int oob_required
,
2403 int i
, eccsize
= chip
->ecc
.size
;
2404 int eccbytes
= chip
->ecc
.bytes
;
2405 int eccsteps
= chip
->ecc
.steps
;
2406 const uint8_t *p
= buf
;
2407 uint8_t *oob
= chip
->oob_poi
;
2409 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2411 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2412 chip
->write_buf(mtd
, p
, eccsize
);
2414 if (chip
->ecc
.prepad
) {
2415 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2416 oob
+= chip
->ecc
.prepad
;
2419 chip
->ecc
.calculate(mtd
, p
, oob
);
2420 chip
->write_buf(mtd
, oob
, eccbytes
);
2423 if (chip
->ecc
.postpad
) {
2424 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2425 oob
+= chip
->ecc
.postpad
;
2429 /* Calculate remaining oob bytes */
2430 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2432 chip
->write_buf(mtd
, oob
, i
);
2438 * nand_write_page - [REPLACEABLE] write one page
2439 * @mtd: MTD device structure
2440 * @chip: NAND chip descriptor
2441 * @offset: address offset within the page
2442 * @data_len: length of actual data to be written
2443 * @buf: the data to write
2444 * @oob_required: must write chip->oob_poi to OOB
2445 * @page: page number to write
2446 * @cached: cached programming
2447 * @raw: use _raw version of write_page
2449 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2450 uint32_t offset
, int data_len
, const uint8_t *buf
,
2451 int oob_required
, int page
, int cached
, int raw
)
2453 int status
, subpage
;
2455 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2456 chip
->ecc
.write_subpage
)
2457 subpage
= offset
|| (data_len
< mtd
->writesize
);
2461 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2464 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2465 oob_required
, page
);
2467 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2468 buf
, oob_required
, page
);
2470 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2477 * Cached progamming disabled for now. Not sure if it's worth the
2478 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2482 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2484 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2485 status
= chip
->waitfunc(mtd
, chip
);
2487 * See if operation failed and additional status checks are
2490 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2491 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2494 if (status
& NAND_STATUS_FAIL
)
2497 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2498 status
= chip
->waitfunc(mtd
, chip
);
2505 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2506 * @mtd: MTD device structure
2507 * @oob: oob data buffer
2508 * @len: oob data write length
2509 * @ops: oob ops structure
2511 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2512 struct mtd_oob_ops
*ops
)
2514 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2517 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2518 * data from a previous OOB read.
2520 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2522 switch (ops
->mode
) {
2524 case MTD_OPS_PLACE_OOB
:
2526 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2529 case MTD_OPS_AUTO_OOB
: {
2530 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2531 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2534 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2535 /* Write request not from offset 0? */
2536 if (unlikely(woffs
)) {
2537 if (woffs
>= free
->length
) {
2538 woffs
-= free
->length
;
2541 boffs
= free
->offset
+ woffs
;
2542 bytes
= min_t(size_t, len
,
2543 (free
->length
- woffs
));
2546 bytes
= min_t(size_t, len
, free
->length
);
2547 boffs
= free
->offset
;
2549 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2560 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2563 * nand_do_write_ops - [INTERN] NAND write with ECC
2564 * @mtd: MTD device structure
2565 * @to: offset to write to
2566 * @ops: oob operations description structure
2568 * NAND write with ECC.
2570 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2571 struct mtd_oob_ops
*ops
)
2573 int chipnr
, realpage
, page
, blockmask
, column
;
2574 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2575 uint32_t writelen
= ops
->len
;
2577 uint32_t oobwritelen
= ops
->ooblen
;
2578 uint32_t oobmaxlen
= ops
->mode
== MTD_OPS_AUTO_OOB
?
2579 mtd
->oobavail
: mtd
->oobsize
;
2581 uint8_t *oob
= ops
->oobbuf
;
2582 uint8_t *buf
= ops
->datbuf
;
2584 int oob_required
= oob
? 1 : 0;
2590 /* Reject writes, which are not page aligned */
2591 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2592 pr_notice("%s: attempt to write non page aligned data\n",
2597 column
= to
& (mtd
->writesize
- 1);
2599 chipnr
= (int)(to
>> chip
->chip_shift
);
2600 chip
->select_chip(mtd
, chipnr
);
2602 /* Check, if it is write protected */
2603 if (nand_check_wp(mtd
)) {
2608 realpage
= (int)(to
>> chip
->page_shift
);
2609 page
= realpage
& chip
->pagemask
;
2610 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2612 /* Invalidate the page cache, when we write to the cached page */
2613 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2614 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2617 /* Don't allow multipage oob writes with offset */
2618 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2624 int bytes
= mtd
->writesize
;
2625 int cached
= writelen
> bytes
&& page
!= blockmask
;
2626 uint8_t *wbuf
= buf
;
2628 int part_pagewr
= (column
|| writelen
< (mtd
->writesize
- 1));
2632 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2633 use_bufpoi
= !virt_addr_valid(buf
);
2637 /* Partial page write?, or need to use bounce buffer */
2639 pr_debug("%s: using write bounce buffer for buf@%p\n",
2643 bytes
= min_t(int, bytes
- column
, writelen
);
2645 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2646 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2647 wbuf
= chip
->buffers
->databuf
;
2650 if (unlikely(oob
)) {
2651 size_t len
= min(oobwritelen
, oobmaxlen
);
2652 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2655 /* We still need to erase leftover OOB data */
2656 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2658 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2659 oob_required
, page
, cached
,
2660 (ops
->mode
== MTD_OPS_RAW
));
2672 page
= realpage
& chip
->pagemask
;
2673 /* Check, if we cross a chip boundary */
2676 chip
->select_chip(mtd
, -1);
2677 chip
->select_chip(mtd
, chipnr
);
2681 ops
->retlen
= ops
->len
- writelen
;
2683 ops
->oobretlen
= ops
->ooblen
;
2686 chip
->select_chip(mtd
, -1);
2691 * panic_nand_write - [MTD Interface] NAND write with ECC
2692 * @mtd: MTD device structure
2693 * @to: offset to write to
2694 * @len: number of bytes to write
2695 * @retlen: pointer to variable to store the number of written bytes
2696 * @buf: the data to write
2698 * NAND write with ECC. Used when performing writes in interrupt context, this
2699 * may for example be called by mtdoops when writing an oops while in panic.
2701 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2702 size_t *retlen
, const uint8_t *buf
)
2704 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2705 struct mtd_oob_ops ops
;
2708 /* Wait for the device to get ready */
2709 panic_nand_wait(mtd
, chip
, 400);
2711 /* Grab the device */
2712 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2714 memset(&ops
, 0, sizeof(ops
));
2716 ops
.datbuf
= (uint8_t *)buf
;
2717 ops
.mode
= MTD_OPS_PLACE_OOB
;
2719 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2721 *retlen
= ops
.retlen
;
2726 * nand_write - [MTD Interface] NAND write with ECC
2727 * @mtd: MTD device structure
2728 * @to: offset to write to
2729 * @len: number of bytes to write
2730 * @retlen: pointer to variable to store the number of written bytes
2731 * @buf: the data to write
2733 * NAND write with ECC.
2735 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2736 size_t *retlen
, const uint8_t *buf
)
2738 struct mtd_oob_ops ops
;
2741 nand_get_device(mtd
, FL_WRITING
);
2742 memset(&ops
, 0, sizeof(ops
));
2744 ops
.datbuf
= (uint8_t *)buf
;
2745 ops
.mode
= MTD_OPS_PLACE_OOB
;
2746 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2747 *retlen
= ops
.retlen
;
2748 nand_release_device(mtd
);
2753 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2754 * @mtd: MTD device structure
2755 * @to: offset to write to
2756 * @ops: oob operation description structure
2758 * NAND write out-of-band.
2760 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2761 struct mtd_oob_ops
*ops
)
2763 int chipnr
, page
, status
, len
;
2764 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2766 pr_debug("%s: to = 0x%08x, len = %i\n",
2767 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2769 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2770 len
= chip
->ecc
.layout
->oobavail
;
2774 /* Do not allow write past end of page */
2775 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2776 pr_debug("%s: attempt to write past end of page\n",
2781 if (unlikely(ops
->ooboffs
>= len
)) {
2782 pr_debug("%s: attempt to start write outside oob\n",
2787 /* Do not allow write past end of device */
2788 if (unlikely(to
>= mtd
->size
||
2789 ops
->ooboffs
+ ops
->ooblen
>
2790 ((mtd
->size
>> chip
->page_shift
) -
2791 (to
>> chip
->page_shift
)) * len
)) {
2792 pr_debug("%s: attempt to write beyond end of device\n",
2797 chipnr
= (int)(to
>> chip
->chip_shift
);
2798 chip
->select_chip(mtd
, chipnr
);
2800 /* Shift to get page */
2801 page
= (int)(to
>> chip
->page_shift
);
2804 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2805 * of my DiskOnChip 2000 test units) will clear the whole data page too
2806 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2807 * it in the doc2000 driver in August 1999. dwmw2.
2809 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2811 /* Check, if it is write protected */
2812 if (nand_check_wp(mtd
)) {
2813 chip
->select_chip(mtd
, -1);
2817 /* Invalidate the page cache, if we write to the cached page */
2818 if (page
== chip
->pagebuf
)
2821 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2823 if (ops
->mode
== MTD_OPS_RAW
)
2824 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2826 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2828 chip
->select_chip(mtd
, -1);
2833 ops
->oobretlen
= ops
->ooblen
;
2839 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2840 * @mtd: MTD device structure
2841 * @to: offset to write to
2842 * @ops: oob operation description structure
2844 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2845 struct mtd_oob_ops
*ops
)
2847 int ret
= -ENOTSUPP
;
2851 /* Do not allow writes past end of device */
2852 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2853 pr_debug("%s: attempt to write beyond end of device\n",
2858 nand_get_device(mtd
, FL_WRITING
);
2860 switch (ops
->mode
) {
2861 case MTD_OPS_PLACE_OOB
:
2862 case MTD_OPS_AUTO_OOB
:
2871 ret
= nand_do_write_oob(mtd
, to
, ops
);
2873 ret
= nand_do_write_ops(mtd
, to
, ops
);
2876 nand_release_device(mtd
);
2881 * single_erase - [GENERIC] NAND standard block erase command function
2882 * @mtd: MTD device structure
2883 * @page: the page address of the block which will be erased
2885 * Standard erase command for NAND chips. Returns NAND status.
2887 static int single_erase(struct mtd_info
*mtd
, int page
)
2889 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2890 /* Send commands to erase a block */
2891 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2892 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2894 return chip
->waitfunc(mtd
, chip
);
2898 * nand_erase - [MTD Interface] erase block(s)
2899 * @mtd: MTD device structure
2900 * @instr: erase instruction
2902 * Erase one ore more blocks.
2904 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2906 return nand_erase_nand(mtd
, instr
, 0);
2910 * nand_erase_nand - [INTERN] erase block(s)
2911 * @mtd: MTD device structure
2912 * @instr: erase instruction
2913 * @allowbbt: allow erasing the bbt area
2915 * Erase one ore more blocks.
2917 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2920 int page
, status
, pages_per_block
, ret
, chipnr
;
2921 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2924 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2925 __func__
, (unsigned long long)instr
->addr
,
2926 (unsigned long long)instr
->len
);
2928 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2931 /* Grab the lock and see if the device is available */
2932 nand_get_device(mtd
, FL_ERASING
);
2934 /* Shift to get first page */
2935 page
= (int)(instr
->addr
>> chip
->page_shift
);
2936 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2938 /* Calculate pages in each block */
2939 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2941 /* Select the NAND device */
2942 chip
->select_chip(mtd
, chipnr
);
2944 /* Check, if it is write protected */
2945 if (nand_check_wp(mtd
)) {
2946 pr_debug("%s: device is write protected!\n",
2948 instr
->state
= MTD_ERASE_FAILED
;
2952 /* Loop through the pages */
2955 instr
->state
= MTD_ERASING
;
2958 /* Check if we have a bad block, we do not erase bad blocks! */
2959 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2960 chip
->page_shift
, 0, allowbbt
)) {
2961 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2963 instr
->state
= MTD_ERASE_FAILED
;
2968 * Invalidate the page cache, if we erase the block which
2969 * contains the current cached page.
2971 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2972 (page
+ pages_per_block
))
2975 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2978 * See if operation failed and additional status checks are
2981 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2982 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2985 /* See if block erase succeeded */
2986 if (status
& NAND_STATUS_FAIL
) {
2987 pr_debug("%s: failed erase, page 0x%08x\n",
2989 instr
->state
= MTD_ERASE_FAILED
;
2991 ((loff_t
)page
<< chip
->page_shift
);
2995 /* Increment page address and decrement length */
2996 len
-= (1ULL << chip
->phys_erase_shift
);
2997 page
+= pages_per_block
;
2999 /* Check, if we cross a chip boundary */
3000 if (len
&& !(page
& chip
->pagemask
)) {
3002 chip
->select_chip(mtd
, -1);
3003 chip
->select_chip(mtd
, chipnr
);
3006 instr
->state
= MTD_ERASE_DONE
;
3010 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
3012 /* Deselect and wake up anyone waiting on the device */
3013 chip
->select_chip(mtd
, -1);
3014 nand_release_device(mtd
);
3016 /* Do call back function */
3018 mtd_erase_callback(instr
);
3020 /* Return more or less happy */
3025 * nand_sync - [MTD Interface] sync
3026 * @mtd: MTD device structure
3028 * Sync is actually a wait for chip ready function.
3030 static void nand_sync(struct mtd_info
*mtd
)
3032 pr_debug("%s: called\n", __func__
);
3034 /* Grab the lock and see if the device is available */
3035 nand_get_device(mtd
, FL_SYNCING
);
3036 /* Release it and go back */
3037 nand_release_device(mtd
);
3041 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3042 * @mtd: MTD device structure
3043 * @offs: offset relative to mtd start
3045 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3047 return nand_block_checkbad(mtd
, offs
, 1, 0);
3051 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3052 * @mtd: MTD device structure
3053 * @ofs: offset relative to mtd start
3055 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3059 ret
= nand_block_isbad(mtd
, ofs
);
3061 /* If it was bad already, return success and do nothing */
3067 return nand_block_markbad_lowlevel(mtd
, ofs
);
3071 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3072 * @mtd: MTD device structure
3073 * @chip: nand chip info structure
3074 * @addr: feature address.
3075 * @subfeature_param: the subfeature parameters, a four bytes array.
3077 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3078 int addr
, uint8_t *subfeature_param
)
3083 if (!chip
->onfi_version
||
3084 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3085 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3088 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3089 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3090 chip
->write_byte(mtd
, subfeature_param
[i
]);
3092 status
= chip
->waitfunc(mtd
, chip
);
3093 if (status
& NAND_STATUS_FAIL
)
3099 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3100 * @mtd: MTD device structure
3101 * @chip: nand chip info structure
3102 * @addr: feature address.
3103 * @subfeature_param: the subfeature parameters, a four bytes array.
3105 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3106 int addr
, uint8_t *subfeature_param
)
3110 if (!chip
->onfi_version
||
3111 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3112 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3115 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3116 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3117 *subfeature_param
++ = chip
->read_byte(mtd
);
3122 * nand_suspend - [MTD Interface] Suspend the NAND flash
3123 * @mtd: MTD device structure
3125 static int nand_suspend(struct mtd_info
*mtd
)
3127 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3131 * nand_resume - [MTD Interface] Resume the NAND flash
3132 * @mtd: MTD device structure
3134 static void nand_resume(struct mtd_info
*mtd
)
3136 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3138 if (chip
->state
== FL_PM_SUSPENDED
)
3139 nand_release_device(mtd
);
3141 pr_err("%s called for a chip which is not in suspended state\n",
3146 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3147 * prevent further operations
3148 * @mtd: MTD device structure
3150 static void nand_shutdown(struct mtd_info
*mtd
)
3152 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3155 /* Set default functions */
3156 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3158 /* check for proper chip_delay setup, set 20us if not */
3159 if (!chip
->chip_delay
)
3160 chip
->chip_delay
= 20;
3162 /* check, if a user supplied command function given */
3163 if (chip
->cmdfunc
== NULL
)
3164 chip
->cmdfunc
= nand_command
;
3166 /* check, if a user supplied wait function given */
3167 if (chip
->waitfunc
== NULL
)
3168 chip
->waitfunc
= nand_wait
;
3170 if (!chip
->select_chip
)
3171 chip
->select_chip
= nand_select_chip
;
3173 /* set for ONFI nand */
3174 if (!chip
->onfi_set_features
)
3175 chip
->onfi_set_features
= nand_onfi_set_features
;
3176 if (!chip
->onfi_get_features
)
3177 chip
->onfi_get_features
= nand_onfi_get_features
;
3179 /* If called twice, pointers that depend on busw may need to be reset */
3180 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3181 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3182 if (!chip
->read_word
)
3183 chip
->read_word
= nand_read_word
;
3184 if (!chip
->block_bad
)
3185 chip
->block_bad
= nand_block_bad
;
3186 if (!chip
->block_markbad
)
3187 chip
->block_markbad
= nand_default_block_markbad
;
3188 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3189 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3190 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3191 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3192 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3193 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3194 if (!chip
->scan_bbt
)
3195 chip
->scan_bbt
= nand_default_bbt
;
3197 if (!chip
->controller
) {
3198 chip
->controller
= &chip
->hwcontrol
;
3199 spin_lock_init(&chip
->controller
->lock
);
3200 init_waitqueue_head(&chip
->controller
->wq
);
3205 /* Sanitize ONFI strings so we can safely print them */
3206 static void sanitize_string(uint8_t *s
, size_t len
)
3210 /* Null terminate */
3213 /* Remove non printable chars */
3214 for (i
= 0; i
< len
- 1; i
++) {
3215 if (s
[i
] < ' ' || s
[i
] > 127)
3219 /* Remove trailing spaces */
3223 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3228 for (i
= 0; i
< 8; i
++)
3229 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3235 /* Parse the Extended Parameter Page. */
3236 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3237 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3239 struct onfi_ext_param_page
*ep
;
3240 struct onfi_ext_section
*s
;
3241 struct onfi_ext_ecc_info
*ecc
;
3247 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3248 ep
= kmalloc(len
, GFP_KERNEL
);
3252 /* Send our own NAND_CMD_PARAM. */
3253 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3255 /* Use the Change Read Column command to skip the ONFI param pages. */
3256 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3257 sizeof(*p
) * p
->num_of_param_pages
, -1);
3259 /* Read out the Extended Parameter Page. */
3260 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3261 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3262 != le16_to_cpu(ep
->crc
))) {
3263 pr_debug("fail in the CRC.\n");
3268 * Check the signature.
3269 * Do not strictly follow the ONFI spec, maybe changed in future.
3271 if (strncmp(ep
->sig
, "EPPS", 4)) {
3272 pr_debug("The signature is invalid.\n");
3276 /* find the ECC section. */
3277 cursor
= (uint8_t *)(ep
+ 1);
3278 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3279 s
= ep
->sections
+ i
;
3280 if (s
->type
== ONFI_SECTION_TYPE_2
)
3282 cursor
+= s
->length
* 16;
3284 if (i
== ONFI_EXT_SECTION_MAX
) {
3285 pr_debug("We can not find the ECC section.\n");
3289 /* get the info we want. */
3290 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3292 if (!ecc
->codeword_size
) {
3293 pr_debug("Invalid codeword size\n");
3297 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3298 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3306 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3308 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3309 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3311 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3316 * Configure chip properties from Micron vendor-specific ONFI table
3318 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3319 struct nand_onfi_params
*p
)
3321 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3323 if (le16_to_cpu(p
->vendor_revision
) < 1)
3326 chip
->read_retries
= micron
->read_retry_options
;
3327 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3331 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3333 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3336 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3340 /* Try ONFI for unknown chip or LP */
3341 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3342 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3343 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3346 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3347 for (i
= 0; i
< 3; i
++) {
3348 for (j
= 0; j
< sizeof(*p
); j
++)
3349 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3350 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3351 le16_to_cpu(p
->crc
)) {
3357 pr_err("Could not find valid ONFI parameter page; aborting\n");
3362 val
= le16_to_cpu(p
->revision
);
3364 chip
->onfi_version
= 23;
3365 else if (val
& (1 << 4))
3366 chip
->onfi_version
= 22;
3367 else if (val
& (1 << 3))
3368 chip
->onfi_version
= 21;
3369 else if (val
& (1 << 2))
3370 chip
->onfi_version
= 20;
3371 else if (val
& (1 << 1))
3372 chip
->onfi_version
= 10;
3374 if (!chip
->onfi_version
) {
3375 pr_info("unsupported ONFI version: %d\n", val
);
3379 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3380 sanitize_string(p
->model
, sizeof(p
->model
));
3382 mtd
->name
= p
->model
;
3384 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3387 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3388 * (don't ask me who thought of this...). MTD assumes that these
3389 * dimensions will be power-of-2, so just truncate the remaining area.
3391 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3392 mtd
->erasesize
*= mtd
->writesize
;
3394 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3396 /* See erasesize comment */
3397 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3398 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3399 chip
->bits_per_cell
= p
->bits_per_cell
;
3401 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3402 *busw
= NAND_BUSWIDTH_16
;
3406 if (p
->ecc_bits
!= 0xff) {
3407 chip
->ecc_strength_ds
= p
->ecc_bits
;
3408 chip
->ecc_step_ds
= 512;
3409 } else if (chip
->onfi_version
>= 21 &&
3410 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3413 * The nand_flash_detect_ext_param_page() uses the
3414 * Change Read Column command which maybe not supported
3415 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3416 * now. We do not replace user supplied command function.
3418 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3419 chip
->cmdfunc
= nand_command_lp
;
3421 /* The Extended Parameter Page is supported since ONFI 2.1. */
3422 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3423 pr_warn("Failed to detect ONFI extended param page\n");
3425 pr_warn("Could not retrieve ONFI ECC requirements\n");
3428 if (p
->jedec_id
== NAND_MFR_MICRON
)
3429 nand_onfi_detect_micron(chip
, p
);
3435 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3437 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3440 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3441 struct jedec_ecc_info
*ecc
;
3445 /* Try JEDEC for unknown chip or LP */
3446 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3447 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3448 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3449 chip
->read_byte(mtd
) != 'C')
3452 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3453 for (i
= 0; i
< 3; i
++) {
3454 for (j
= 0; j
< sizeof(*p
); j
++)
3455 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3457 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3458 le16_to_cpu(p
->crc
))
3463 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3468 val
= le16_to_cpu(p
->revision
);
3470 chip
->jedec_version
= 10;
3471 else if (val
& (1 << 1))
3472 chip
->jedec_version
= 1; /* vendor specific version */
3474 if (!chip
->jedec_version
) {
3475 pr_info("unsupported JEDEC version: %d\n", val
);
3479 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3480 sanitize_string(p
->model
, sizeof(p
->model
));
3482 mtd
->name
= p
->model
;
3484 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3486 /* Please reference to the comment for nand_flash_detect_onfi. */
3487 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3488 mtd
->erasesize
*= mtd
->writesize
;
3490 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3492 /* Please reference to the comment for nand_flash_detect_onfi. */
3493 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3494 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3495 chip
->bits_per_cell
= p
->bits_per_cell
;
3497 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3498 *busw
= NAND_BUSWIDTH_16
;
3503 ecc
= &p
->ecc_info
[0];
3505 if (ecc
->codeword_size
>= 9) {
3506 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3507 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3509 pr_warn("Invalid codeword size\n");
3516 * nand_id_has_period - Check if an ID string has a given wraparound period
3517 * @id_data: the ID string
3518 * @arrlen: the length of the @id_data array
3519 * @period: the period of repitition
3521 * Check if an ID string is repeated within a given sequence of bytes at
3522 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3523 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3524 * if the repetition has a period of @period; otherwise, returns zero.
3526 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3529 for (i
= 0; i
< period
; i
++)
3530 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3531 if (id_data
[i
] != id_data
[j
])
3537 * nand_id_len - Get the length of an ID string returned by CMD_READID
3538 * @id_data: the ID string
3539 * @arrlen: the length of the @id_data array
3541 * Returns the length of the ID string, according to known wraparound/trailing
3542 * zero patterns. If no pattern exists, returns the length of the array.
3544 static int nand_id_len(u8
*id_data
, int arrlen
)
3546 int last_nonzero
, period
;
3548 /* Find last non-zero byte */
3549 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3550 if (id_data
[last_nonzero
])
3554 if (last_nonzero
< 0)
3557 /* Calculate wraparound period */
3558 for (period
= 1; period
< arrlen
; period
++)
3559 if (nand_id_has_period(id_data
, arrlen
, period
))
3562 /* There's a repeated pattern */
3563 if (period
< arrlen
)
3566 /* There are trailing zeros */
3567 if (last_nonzero
< arrlen
- 1)
3568 return last_nonzero
+ 1;
3570 /* No pattern detected */
3574 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3575 static int nand_get_bits_per_cell(u8 cellinfo
)
3579 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3580 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3585 * Many new NAND share similar device ID codes, which represent the size of the
3586 * chip. The rest of the parameters must be decoded according to generic or
3587 * manufacturer-specific "extended ID" decoding patterns.
3589 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3590 u8 id_data
[8], int *busw
)
3593 /* The 3rd id byte holds MLC / multichip data */
3594 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3595 /* The 4th id byte is the important one */
3598 id_len
= nand_id_len(id_data
, 8);
3601 * Field definitions are in the following datasheets:
3602 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3603 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3604 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3606 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3607 * ID to decide what to do.
3609 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3610 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3612 mtd
->writesize
= 2048 << (extid
& 0x03);
3615 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3635 default: /* Other cases are "reserved" (unknown) */
3636 mtd
->oobsize
= 1024;
3640 /* Calc blocksize */
3641 mtd
->erasesize
= (128 * 1024) <<
3642 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3644 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3645 !nand_is_slc(chip
)) {
3649 mtd
->writesize
= 2048 << (extid
& 0x03);
3652 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3676 /* Calc blocksize */
3677 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3679 mtd
->erasesize
= (128 * 1024) << tmp
;
3680 else if (tmp
== 0x03)
3681 mtd
->erasesize
= 768 * 1024;
3683 mtd
->erasesize
= (64 * 1024) << tmp
;
3687 mtd
->writesize
= 1024 << (extid
& 0x03);
3690 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3691 (mtd
->writesize
>> 9);
3693 /* Calc blocksize. Blocksize is multiples of 64KiB */
3694 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3696 /* Get buswidth information */
3697 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3700 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3701 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3703 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3705 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3707 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3708 nand_is_slc(chip
) &&
3709 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3710 !(id_data
[4] & 0x80) /* !BENAND */) {
3711 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3718 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3719 * decodes a matching ID table entry and assigns the MTD size parameters for
3722 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3723 struct nand_flash_dev
*type
, u8 id_data
[8],
3726 int maf_id
= id_data
[0];
3728 mtd
->erasesize
= type
->erasesize
;
3729 mtd
->writesize
= type
->pagesize
;
3730 mtd
->oobsize
= mtd
->writesize
/ 32;
3731 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3733 /* All legacy ID NAND are small-page, SLC */
3734 chip
->bits_per_cell
= 1;
3737 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3738 * some Spansion chips have erasesize that conflicts with size
3739 * listed in nand_ids table.
3740 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3742 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3743 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3744 && mtd
->writesize
== 512) {
3745 mtd
->erasesize
= 128 * 1024;
3746 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3751 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3752 * heuristic patterns using various detected parameters (e.g., manufacturer,
3753 * page size, cell-type information).
3755 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3756 struct nand_chip
*chip
, u8 id_data
[8])
3758 int maf_id
= id_data
[0];
3760 /* Set the bad block position */
3761 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3762 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3764 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3767 * Bad block marker is stored in the last page of each block on Samsung
3768 * and Hynix MLC devices; stored in first two pages of each block on
3769 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3770 * AMD/Spansion, and Macronix. All others scan only the first page.
3772 if (!nand_is_slc(chip
) &&
3773 (maf_id
== NAND_MFR_SAMSUNG
||
3774 maf_id
== NAND_MFR_HYNIX
))
3775 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3776 else if ((nand_is_slc(chip
) &&
3777 (maf_id
== NAND_MFR_SAMSUNG
||
3778 maf_id
== NAND_MFR_HYNIX
||
3779 maf_id
== NAND_MFR_TOSHIBA
||
3780 maf_id
== NAND_MFR_AMD
||
3781 maf_id
== NAND_MFR_MACRONIX
)) ||
3782 (mtd
->writesize
== 2048 &&
3783 maf_id
== NAND_MFR_MICRON
))
3784 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3787 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3789 return type
->id_len
;
3792 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3793 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3795 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3796 mtd
->writesize
= type
->pagesize
;
3797 mtd
->erasesize
= type
->erasesize
;
3798 mtd
->oobsize
= type
->oobsize
;
3800 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3801 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3802 chip
->options
|= type
->options
;
3803 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3804 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3805 chip
->onfi_timing_mode_default
=
3806 type
->onfi_timing_mode_default
;
3808 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3811 mtd
->name
= type
->name
;
3819 * Get the flash and manufacturer id and lookup if the type is supported.
3821 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3822 struct nand_chip
*chip
,
3823 int *maf_id
, int *dev_id
,
3824 struct nand_flash_dev
*type
)
3830 /* Select the device */
3831 chip
->select_chip(mtd
, 0);
3834 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3837 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3839 /* Send the command for reading device ID */
3840 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3842 /* Read manufacturer and device IDs */
3843 *maf_id
= chip
->read_byte(mtd
);
3844 *dev_id
= chip
->read_byte(mtd
);
3847 * Try again to make sure, as some systems the bus-hold or other
3848 * interface concerns can cause random data which looks like a
3849 * possibly credible NAND flash to appear. If the two results do
3850 * not match, ignore the device completely.
3853 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3855 /* Read entire ID string */
3856 for (i
= 0; i
< 8; i
++)
3857 id_data
[i
] = chip
->read_byte(mtd
);
3859 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3860 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3861 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3862 return ERR_PTR(-ENODEV
);
3866 type
= nand_flash_ids
;
3868 for (; type
->name
!= NULL
; type
++) {
3869 if (is_full_id_nand(type
)) {
3870 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3872 } else if (*dev_id
== type
->dev_id
) {
3877 chip
->onfi_version
= 0;
3878 if (!type
->name
|| !type
->pagesize
) {
3879 /* Check if the chip is ONFI compliant */
3880 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3883 /* Check if the chip is JEDEC compliant */
3884 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3889 return ERR_PTR(-ENODEV
);
3892 mtd
->name
= type
->name
;
3894 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3896 if (!type
->pagesize
) {
3897 /* Decode parameters from extended ID */
3898 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3900 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3902 /* Get chip options */
3903 chip
->options
|= type
->options
;
3906 * Check if chip is not a Samsung device. Do not clear the
3907 * options for chips which do not have an extended id.
3909 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3910 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3913 /* Try to identify manufacturer */
3914 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3915 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3919 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3920 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3921 chip
->options
|= busw
;
3922 nand_set_defaults(chip
, busw
);
3923 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3925 * Check, if buswidth is correct. Hardware drivers should set
3928 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3930 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3931 pr_warn("bus width %d instead %d bit\n",
3932 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3934 return ERR_PTR(-EINVAL
);
3937 nand_decode_bbm_options(mtd
, chip
, id_data
);
3939 /* Calculate the address shift from the page size */
3940 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3941 /* Convert chipsize to number of pages per chip -1 */
3942 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3944 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3945 ffs(mtd
->erasesize
) - 1;
3946 if (chip
->chipsize
& 0xffffffff)
3947 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3949 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3950 chip
->chip_shift
+= 32 - 1;
3953 chip
->badblockbits
= 8;
3954 chip
->erase
= single_erase
;
3956 /* Do not replace user supplied command function! */
3957 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3958 chip
->cmdfunc
= nand_command_lp
;
3960 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3963 if (chip
->onfi_version
)
3964 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3965 chip
->onfi_params
.model
);
3966 else if (chip
->jedec_version
)
3967 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3968 chip
->jedec_params
.model
);
3970 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3973 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3974 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3975 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3979 static int nand_dt_init(struct nand_chip
*chip
)
3981 struct device_node
*dn
= nand_get_flash_node(chip
);
3982 int ecc_mode
, ecc_strength
, ecc_step
;
3987 if (of_get_nand_bus_width(dn
) == 16)
3988 chip
->options
|= NAND_BUSWIDTH_16
;
3990 if (of_get_nand_on_flash_bbt(dn
))
3991 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3993 ecc_mode
= of_get_nand_ecc_mode(dn
);
3994 ecc_strength
= of_get_nand_ecc_strength(dn
);
3995 ecc_step
= of_get_nand_ecc_step_size(dn
);
3997 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3998 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3999 pr_err("must set both strength and step size in DT\n");
4004 chip
->ecc
.mode
= ecc_mode
;
4006 if (ecc_strength
>= 0)
4007 chip
->ecc
.strength
= ecc_strength
;
4010 chip
->ecc
.size
= ecc_step
;
4016 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4017 * @mtd: MTD device structure
4018 * @maxchips: number of chips to scan for
4019 * @table: alternative NAND ID table
4021 * This is the first phase of the normal nand_scan() function. It reads the
4022 * flash ID and sets up MTD fields accordingly.
4024 * The mtd->owner field must be set to the module of the caller.
4026 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4027 struct nand_flash_dev
*table
)
4029 int i
, nand_maf_id
, nand_dev_id
;
4030 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4031 struct nand_flash_dev
*type
;
4034 ret
= nand_dt_init(chip
);
4038 if (!mtd
->name
&& mtd
->dev
.parent
)
4039 mtd
->name
= dev_name(mtd
->dev
.parent
);
4041 /* Set the default functions */
4042 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4044 /* Read the flash type */
4045 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4046 &nand_dev_id
, table
);
4049 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4050 pr_warn("No NAND device found\n");
4051 chip
->select_chip(mtd
, -1);
4052 return PTR_ERR(type
);
4055 chip
->select_chip(mtd
, -1);
4057 /* Check for a chip array */
4058 for (i
= 1; i
< maxchips
; i
++) {
4059 chip
->select_chip(mtd
, i
);
4060 /* See comment in nand_get_flash_type for reset */
4061 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
4062 /* Send the command for reading device ID */
4063 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4064 /* Read manufacturer and device IDs */
4065 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4066 nand_dev_id
!= chip
->read_byte(mtd
)) {
4067 chip
->select_chip(mtd
, -1);
4070 chip
->select_chip(mtd
, -1);
4073 pr_info("%d chips detected\n", i
);
4075 /* Store the number of chips and calc total size for mtd */
4077 mtd
->size
= i
* chip
->chipsize
;
4081 EXPORT_SYMBOL(nand_scan_ident
);
4084 * Check if the chip configuration meet the datasheet requirements.
4086 * If our configuration corrects A bits per B bytes and the minimum
4087 * required correction level is X bits per Y bytes, then we must ensure
4088 * both of the following are true:
4090 * (1) A / B >= X / Y
4093 * Requirement (1) ensures we can correct for the required bitflip density.
4094 * Requirement (2) ensures we can correct even when all bitflips are clumped
4095 * in the same sector.
4097 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4099 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4100 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4103 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4104 /* Not enough information */
4108 * We get the number of corrected bits per page to compare
4109 * the correction density.
4111 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4112 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4114 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4118 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4119 * @mtd: MTD device structure
4121 * This is the second phase of the normal nand_scan() function. It fills out
4122 * all the uninitialized function pointers with the defaults and scans for a
4123 * bad block table if appropriate.
4125 int nand_scan_tail(struct mtd_info
*mtd
)
4128 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4129 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4130 struct nand_buffers
*nbuf
;
4132 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4133 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4134 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
4136 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4137 nbuf
= kzalloc(sizeof(*nbuf
) + mtd
->writesize
4138 + mtd
->oobsize
* 3, GFP_KERNEL
);
4141 nbuf
->ecccalc
= (uint8_t *)(nbuf
+ 1);
4142 nbuf
->ecccode
= nbuf
->ecccalc
+ mtd
->oobsize
;
4143 nbuf
->databuf
= nbuf
->ecccode
+ mtd
->oobsize
;
4145 chip
->buffers
= nbuf
;
4151 /* Set the internal oob buffer location, just after the page data */
4152 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4155 * If no default placement scheme is given, select an appropriate one.
4157 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4158 switch (mtd
->oobsize
) {
4160 ecc
->layout
= &nand_oob_8
;
4163 ecc
->layout
= &nand_oob_16
;
4166 ecc
->layout
= &nand_oob_64
;
4169 ecc
->layout
= &nand_oob_128
;
4172 pr_warn("No oob scheme defined for oobsize %d\n",
4178 if (!chip
->write_page
)
4179 chip
->write_page
= nand_write_page
;
4182 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4183 * selected and we have 256 byte pagesize fallback to software ECC
4186 switch (ecc
->mode
) {
4187 case NAND_ECC_HW_OOB_FIRST
:
4188 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4189 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4190 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4193 if (!ecc
->read_page
)
4194 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4197 /* Use standard hwecc read page function? */
4198 if (!ecc
->read_page
)
4199 ecc
->read_page
= nand_read_page_hwecc
;
4200 if (!ecc
->write_page
)
4201 ecc
->write_page
= nand_write_page_hwecc
;
4202 if (!ecc
->read_page_raw
)
4203 ecc
->read_page_raw
= nand_read_page_raw
;
4204 if (!ecc
->write_page_raw
)
4205 ecc
->write_page_raw
= nand_write_page_raw
;
4207 ecc
->read_oob
= nand_read_oob_std
;
4208 if (!ecc
->write_oob
)
4209 ecc
->write_oob
= nand_write_oob_std
;
4210 if (!ecc
->read_subpage
)
4211 ecc
->read_subpage
= nand_read_subpage
;
4212 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4213 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4215 case NAND_ECC_HW_SYNDROME
:
4216 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4218 ecc
->read_page
== nand_read_page_hwecc
||
4220 ecc
->write_page
== nand_write_page_hwecc
)) {
4221 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4224 /* Use standard syndrome read/write page function? */
4225 if (!ecc
->read_page
)
4226 ecc
->read_page
= nand_read_page_syndrome
;
4227 if (!ecc
->write_page
)
4228 ecc
->write_page
= nand_write_page_syndrome
;
4229 if (!ecc
->read_page_raw
)
4230 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4231 if (!ecc
->write_page_raw
)
4232 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4234 ecc
->read_oob
= nand_read_oob_syndrome
;
4235 if (!ecc
->write_oob
)
4236 ecc
->write_oob
= nand_write_oob_syndrome
;
4238 if (mtd
->writesize
>= ecc
->size
) {
4239 if (!ecc
->strength
) {
4240 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4245 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4246 ecc
->size
, mtd
->writesize
);
4247 ecc
->mode
= NAND_ECC_SOFT
;
4250 ecc
->calculate
= nand_calculate_ecc
;
4251 ecc
->correct
= nand_correct_data
;
4252 ecc
->read_page
= nand_read_page_swecc
;
4253 ecc
->read_subpage
= nand_read_subpage
;
4254 ecc
->write_page
= nand_write_page_swecc
;
4255 ecc
->read_page_raw
= nand_read_page_raw
;
4256 ecc
->write_page_raw
= nand_write_page_raw
;
4257 ecc
->read_oob
= nand_read_oob_std
;
4258 ecc
->write_oob
= nand_write_oob_std
;
4265 case NAND_ECC_SOFT_BCH
:
4266 if (!mtd_nand_has_bch()) {
4267 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4270 ecc
->calculate
= nand_bch_calculate_ecc
;
4271 ecc
->correct
= nand_bch_correct_data
;
4272 ecc
->read_page
= nand_read_page_swecc
;
4273 ecc
->read_subpage
= nand_read_subpage
;
4274 ecc
->write_page
= nand_write_page_swecc
;
4275 ecc
->read_page_raw
= nand_read_page_raw
;
4276 ecc
->write_page_raw
= nand_write_page_raw
;
4277 ecc
->read_oob
= nand_read_oob_std
;
4278 ecc
->write_oob
= nand_write_oob_std
;
4280 * Board driver should supply ecc.size and ecc.strength values
4281 * to select how many bits are correctable. Otherwise, default
4282 * to 4 bits for large page devices.
4284 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4289 /* See nand_bch_init() for details. */
4290 ecc
->bytes
= DIV_ROUND_UP(
4291 ecc
->strength
* fls(8 * ecc
->size
), 8);
4292 ecc
->priv
= nand_bch_init(mtd
, ecc
->size
, ecc
->bytes
,
4295 pr_warn("BCH ECC initialization failed!\n");
4301 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4302 ecc
->read_page
= nand_read_page_raw
;
4303 ecc
->write_page
= nand_write_page_raw
;
4304 ecc
->read_oob
= nand_read_oob_std
;
4305 ecc
->read_page_raw
= nand_read_page_raw
;
4306 ecc
->write_page_raw
= nand_write_page_raw
;
4307 ecc
->write_oob
= nand_write_oob_std
;
4308 ecc
->size
= mtd
->writesize
;
4314 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4318 /* For many systems, the standard OOB write also works for raw */
4319 if (!ecc
->read_oob_raw
)
4320 ecc
->read_oob_raw
= ecc
->read_oob
;
4321 if (!ecc
->write_oob_raw
)
4322 ecc
->write_oob_raw
= ecc
->write_oob
;
4325 * The number of bytes available for a client to place data into
4326 * the out of band area.
4328 ecc
->layout
->oobavail
= 0;
4329 for (i
= 0; ecc
->layout
->oobfree
[i
].length
4330 && i
< ARRAY_SIZE(ecc
->layout
->oobfree
); i
++)
4331 ecc
->layout
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4332 mtd
->oobavail
= ecc
->layout
->oobavail
;
4334 /* ECC sanity check: warn if it's too weak */
4335 if (!nand_ecc_strength_good(mtd
))
4336 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4340 * Set the number of read / write steps for one page depending on ECC
4343 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4344 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4345 pr_warn("Invalid ECC parameters\n");
4348 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4350 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4351 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4352 switch (ecc
->steps
) {
4354 mtd
->subpage_sft
= 1;
4359 mtd
->subpage_sft
= 2;
4363 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4365 /* Initialize state */
4366 chip
->state
= FL_READY
;
4368 /* Invalidate the pagebuffer reference */
4371 /* Large page NAND with SOFT_ECC should support subpage reads */
4372 switch (ecc
->mode
) {
4374 case NAND_ECC_SOFT_BCH
:
4375 if (chip
->page_shift
> 9)
4376 chip
->options
|= NAND_SUBPAGE_READ
;
4383 /* Fill in remaining MTD driver data */
4384 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4385 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4387 mtd
->_erase
= nand_erase
;
4389 mtd
->_unpoint
= NULL
;
4390 mtd
->_read
= nand_read
;
4391 mtd
->_write
= nand_write
;
4392 mtd
->_panic_write
= panic_nand_write
;
4393 mtd
->_read_oob
= nand_read_oob
;
4394 mtd
->_write_oob
= nand_write_oob
;
4395 mtd
->_sync
= nand_sync
;
4397 mtd
->_unlock
= NULL
;
4398 mtd
->_suspend
= nand_suspend
;
4399 mtd
->_resume
= nand_resume
;
4400 mtd
->_reboot
= nand_shutdown
;
4401 mtd
->_block_isreserved
= nand_block_isreserved
;
4402 mtd
->_block_isbad
= nand_block_isbad
;
4403 mtd
->_block_markbad
= nand_block_markbad
;
4404 mtd
->writebufsize
= mtd
->writesize
;
4406 /* propagate ecc info to mtd_info */
4407 mtd
->ecclayout
= ecc
->layout
;
4408 mtd
->ecc_strength
= ecc
->strength
;
4409 mtd
->ecc_step_size
= ecc
->size
;
4411 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4412 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4415 if (!mtd
->bitflip_threshold
)
4416 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4418 /* Check, if we should skip the bad block table scan */
4419 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4422 /* Build bad block table */
4423 return chip
->scan_bbt(mtd
);
4425 EXPORT_SYMBOL(nand_scan_tail
);
4428 * is_module_text_address() isn't exported, and it's mostly a pointless
4429 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4430 * to call us from in-kernel code if the core NAND support is modular.
4433 #define caller_is_module() (1)
4435 #define caller_is_module() \
4436 is_module_text_address((unsigned long)__builtin_return_address(0))
4440 * nand_scan - [NAND Interface] Scan for the NAND device
4441 * @mtd: MTD device structure
4442 * @maxchips: number of chips to scan for
4444 * This fills out all the uninitialized function pointers with the defaults.
4445 * The flash ID is read and the mtd/chip structures are filled with the
4446 * appropriate values. The mtd->owner field must be set to the module of the
4449 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4453 /* Many callers got this wrong, so check for it for a while... */
4454 if (!mtd
->owner
&& caller_is_module()) {
4455 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
4459 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4461 ret
= nand_scan_tail(mtd
);
4464 EXPORT_SYMBOL(nand_scan
);
4467 * nand_release - [NAND Interface] Free resources held by the NAND device
4468 * @mtd: MTD device structure
4470 void nand_release(struct mtd_info
*mtd
)
4472 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4474 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
4475 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
4477 mtd_device_unregister(mtd
);
4479 /* Free bad block table memory */
4481 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4482 kfree(chip
->buffers
);
4484 /* Free bad block descriptor memory */
4485 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
4486 & NAND_BBT_DYNAMICSTRUCT
)
4487 kfree(chip
->badblock_pattern
);
4489 EXPORT_SYMBOL_GPL(nand_release
);
4491 static int __init
nand_base_init(void)
4493 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
4497 static void __exit
nand_base_exit(void)
4499 led_trigger_unregister_simple(nand_led_trigger
);
4502 module_init(nand_base_init
);
4503 module_exit(nand_base_exit
);
4505 MODULE_LICENSE("GPL");
4506 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4507 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4508 MODULE_DESCRIPTION("Generic NAND flash driver code");