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mtd: replace the hardcode with the onfi_feature()
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 *
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
10 *
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 *
14 * Credits:
15 * David Woodhouse for adding multichip support
16 *
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
20 * TODO:
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #include <linux/interrupt.h>
44 #include <linux/bitops.h>
45 #include <linux/leds.h>
46 #include <linux/io.h>
47 #include <linux/mtd/partitions.h>
48
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
57 .length = 2} }
58 };
59
60 static struct nand_ecclayout nand_oob_16 = {
61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
63 .oobfree = {
64 {.offset = 8,
65 . length = 8} }
66 };
67
68 static struct nand_ecclayout nand_oob_64 = {
69 .eccbytes = 24,
70 .eccpos = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
74 .oobfree = {
75 {.offset = 2,
76 .length = 38} }
77 };
78
79 static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
90 .length = 78} }
91 };
92
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
94
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
98 /*
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
101 */
102 DEFINE_LED_TRIGGER(nand_led_trigger);
103
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106 {
107 struct nand_chip *chip = mtd->priv;
108 int ret = 0;
109
110 /* Start address must align on block boundary */
111 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
117 if (len & ((1 << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
119 ret = -EINVAL;
120 }
121
122 return ret;
123 }
124
125 /**
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
128 *
129 * Release chip lock and wake up anyone waiting on the device.
130 */
131 static void nand_release_device(struct mtd_info *mtd)
132 {
133 struct nand_chip *chip = mtd->priv;
134
135 /* Release the controller and the chip */
136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
141 }
142
143 /**
144 * nand_read_byte - [DEFAULT] read one byte from the chip
145 * @mtd: MTD device structure
146 *
147 * Default read function for 8bit buswidth
148 */
149 static uint8_t nand_read_byte(struct mtd_info *mtd)
150 {
151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
153 }
154
155 /**
156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
158 * @mtd: MTD device structure
159 *
160 * Default read function for 16bit buswidth with endianness conversion.
161 *
162 */
163 static uint8_t nand_read_byte16(struct mtd_info *mtd)
164 {
165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
167 }
168
169 /**
170 * nand_read_word - [DEFAULT] read one word from the chip
171 * @mtd: MTD device structure
172 *
173 * Default read function for 16bit buswidth without endianness conversion.
174 */
175 static u16 nand_read_word(struct mtd_info *mtd)
176 {
177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
179 }
180
181 /**
182 * nand_select_chip - [DEFAULT] control CE line
183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
185 *
186 * Default select function for 1 chip devices.
187 */
188 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
189 {
190 struct nand_chip *chip = mtd->priv;
191
192 switch (chipnr) {
193 case -1:
194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
195 break;
196 case 0:
197 break;
198
199 default:
200 BUG();
201 }
202 }
203
204 /**
205 * nand_write_buf - [DEFAULT] write buffer to chip
206 * @mtd: MTD device structure
207 * @buf: data buffer
208 * @len: number of bytes to write
209 *
210 * Default write function for 8bit buswidth.
211 */
212 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
213 {
214 struct nand_chip *chip = mtd->priv;
215
216 iowrite8_rep(chip->IO_ADDR_W, buf, len);
217 }
218
219 /**
220 * nand_read_buf - [DEFAULT] read chip data into buffer
221 * @mtd: MTD device structure
222 * @buf: buffer to store date
223 * @len: number of bytes to read
224 *
225 * Default read function for 8bit buswidth.
226 */
227 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
228 {
229 struct nand_chip *chip = mtd->priv;
230
231 ioread8_rep(chip->IO_ADDR_R, buf, len);
232 }
233
234 /**
235 * nand_write_buf16 - [DEFAULT] write buffer to chip
236 * @mtd: MTD device structure
237 * @buf: data buffer
238 * @len: number of bytes to write
239 *
240 * Default write function for 16bit buswidth.
241 */
242 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
243 {
244 struct nand_chip *chip = mtd->priv;
245 u16 *p = (u16 *) buf;
246
247 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
248 }
249
250 /**
251 * nand_read_buf16 - [DEFAULT] read chip data into buffer
252 * @mtd: MTD device structure
253 * @buf: buffer to store date
254 * @len: number of bytes to read
255 *
256 * Default read function for 16bit buswidth.
257 */
258 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
259 {
260 struct nand_chip *chip = mtd->priv;
261 u16 *p = (u16 *) buf;
262
263 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
264 }
265
266 /**
267 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
268 * @mtd: MTD device structure
269 * @ofs: offset from device start
270 * @getchip: 0, if the chip is already selected
271 *
272 * Check, if the block is bad.
273 */
274 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
275 {
276 int page, chipnr, res = 0, i = 0;
277 struct nand_chip *chip = mtd->priv;
278 u16 bad;
279
280 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
281 ofs += mtd->erasesize - mtd->writesize;
282
283 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
284
285 if (getchip) {
286 chipnr = (int)(ofs >> chip->chip_shift);
287
288 nand_get_device(mtd, FL_READING);
289
290 /* Select the NAND device */
291 chip->select_chip(mtd, chipnr);
292 }
293
294 do {
295 if (chip->options & NAND_BUSWIDTH_16) {
296 chip->cmdfunc(mtd, NAND_CMD_READOOB,
297 chip->badblockpos & 0xFE, page);
298 bad = cpu_to_le16(chip->read_word(mtd));
299 if (chip->badblockpos & 0x1)
300 bad >>= 8;
301 else
302 bad &= 0xFF;
303 } else {
304 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
305 page);
306 bad = chip->read_byte(mtd);
307 }
308
309 if (likely(chip->badblockbits == 8))
310 res = bad != 0xFF;
311 else
312 res = hweight8(bad) < chip->badblockbits;
313 ofs += mtd->writesize;
314 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
315 i++;
316 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
317
318 if (getchip) {
319 chip->select_chip(mtd, -1);
320 nand_release_device(mtd);
321 }
322
323 return res;
324 }
325
326 /**
327 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
328 * @mtd: MTD device structure
329 * @ofs: offset from device start
330 *
331 * This is the default implementation, which can be overridden by a hardware
332 * specific driver. It provides the details for writing a bad block marker to a
333 * block.
334 */
335 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
336 {
337 struct nand_chip *chip = mtd->priv;
338 struct mtd_oob_ops ops;
339 uint8_t buf[2] = { 0, 0 };
340 int ret = 0, res, i = 0;
341
342 ops.datbuf = NULL;
343 ops.oobbuf = buf;
344 ops.ooboffs = chip->badblockpos;
345 if (chip->options & NAND_BUSWIDTH_16) {
346 ops.ooboffs &= ~0x01;
347 ops.len = ops.ooblen = 2;
348 } else {
349 ops.len = ops.ooblen = 1;
350 }
351 ops.mode = MTD_OPS_PLACE_OOB;
352
353 /* Write to first/last page(s) if necessary */
354 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
355 ofs += mtd->erasesize - mtd->writesize;
356 do {
357 res = nand_do_write_oob(mtd, ofs, &ops);
358 if (!ret)
359 ret = res;
360
361 i++;
362 ofs += mtd->writesize;
363 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
364
365 return ret;
366 }
367
368 /**
369 * nand_block_markbad_lowlevel - mark a block bad
370 * @mtd: MTD device structure
371 * @ofs: offset from device start
372 *
373 * This function performs the generic NAND bad block marking steps (i.e., bad
374 * block table(s) and/or marker(s)). We only allow the hardware driver to
375 * specify how to write bad block markers to OOB (chip->block_markbad).
376 *
377 * We try operations in the following order:
378 * (1) erase the affected block, to allow OOB marker to be written cleanly
379 * (2) write bad block marker to OOB area of affected block (unless flag
380 * NAND_BBT_NO_OOB_BBM is present)
381 * (3) update the BBT
382 * Note that we retain the first error encountered in (2) or (3), finish the
383 * procedures, and dump the error in the end.
384 */
385 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
386 {
387 struct nand_chip *chip = mtd->priv;
388 int res, ret = 0;
389
390 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
391 struct erase_info einfo;
392
393 /* Attempt erase before marking OOB */
394 memset(&einfo, 0, sizeof(einfo));
395 einfo.mtd = mtd;
396 einfo.addr = ofs;
397 einfo.len = 1 << chip->phys_erase_shift;
398 nand_erase_nand(mtd, &einfo, 0);
399
400 /* Write bad block marker to OOB */
401 nand_get_device(mtd, FL_WRITING);
402 ret = chip->block_markbad(mtd, ofs);
403 nand_release_device(mtd);
404 }
405
406 /* Mark block bad in BBT */
407 if (chip->bbt) {
408 res = nand_markbad_bbt(mtd, ofs);
409 if (!ret)
410 ret = res;
411 }
412
413 if (!ret)
414 mtd->ecc_stats.badblocks++;
415
416 return ret;
417 }
418
419 /**
420 * nand_check_wp - [GENERIC] check if the chip is write protected
421 * @mtd: MTD device structure
422 *
423 * Check, if the device is write protected. The function expects, that the
424 * device is already selected.
425 */
426 static int nand_check_wp(struct mtd_info *mtd)
427 {
428 struct nand_chip *chip = mtd->priv;
429
430 /* Broken xD cards report WP despite being writable */
431 if (chip->options & NAND_BROKEN_XD)
432 return 0;
433
434 /* Check the WP bit */
435 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
436 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
437 }
438
439 /**
440 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
441 * @mtd: MTD device structure
442 * @ofs: offset from device start
443 * @getchip: 0, if the chip is already selected
444 * @allowbbt: 1, if its allowed to access the bbt area
445 *
446 * Check, if the block is bad. Either by reading the bad block table or
447 * calling of the scan function.
448 */
449 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
450 int allowbbt)
451 {
452 struct nand_chip *chip = mtd->priv;
453
454 if (!chip->bbt)
455 return chip->block_bad(mtd, ofs, getchip);
456
457 /* Return info from the table */
458 return nand_isbad_bbt(mtd, ofs, allowbbt);
459 }
460
461 /**
462 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
463 * @mtd: MTD device structure
464 * @timeo: Timeout
465 *
466 * Helper function for nand_wait_ready used when needing to wait in interrupt
467 * context.
468 */
469 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
470 {
471 struct nand_chip *chip = mtd->priv;
472 int i;
473
474 /* Wait for the device to get ready */
475 for (i = 0; i < timeo; i++) {
476 if (chip->dev_ready(mtd))
477 break;
478 touch_softlockup_watchdog();
479 mdelay(1);
480 }
481 }
482
483 /* Wait for the ready pin, after a command. The timeout is caught later. */
484 void nand_wait_ready(struct mtd_info *mtd)
485 {
486 struct nand_chip *chip = mtd->priv;
487 unsigned long timeo = jiffies + msecs_to_jiffies(20);
488
489 /* 400ms timeout */
490 if (in_interrupt() || oops_in_progress)
491 return panic_nand_wait_ready(mtd, 400);
492
493 led_trigger_event(nand_led_trigger, LED_FULL);
494 /* Wait until command is processed or timeout occurs */
495 do {
496 if (chip->dev_ready(mtd))
497 break;
498 touch_softlockup_watchdog();
499 } while (time_before(jiffies, timeo));
500 led_trigger_event(nand_led_trigger, LED_OFF);
501 }
502 EXPORT_SYMBOL_GPL(nand_wait_ready);
503
504 /**
505 * nand_command - [DEFAULT] Send command to NAND device
506 * @mtd: MTD device structure
507 * @command: the command to be sent
508 * @column: the column address for this command, -1 if none
509 * @page_addr: the page address for this command, -1 if none
510 *
511 * Send command to NAND device. This function is used for small page devices
512 * (512 Bytes per page).
513 */
514 static void nand_command(struct mtd_info *mtd, unsigned int command,
515 int column, int page_addr)
516 {
517 register struct nand_chip *chip = mtd->priv;
518 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
519
520 /* Write out the command to the device */
521 if (command == NAND_CMD_SEQIN) {
522 int readcmd;
523
524 if (column >= mtd->writesize) {
525 /* OOB area */
526 column -= mtd->writesize;
527 readcmd = NAND_CMD_READOOB;
528 } else if (column < 256) {
529 /* First 256 bytes --> READ0 */
530 readcmd = NAND_CMD_READ0;
531 } else {
532 column -= 256;
533 readcmd = NAND_CMD_READ1;
534 }
535 chip->cmd_ctrl(mtd, readcmd, ctrl);
536 ctrl &= ~NAND_CTRL_CHANGE;
537 }
538 chip->cmd_ctrl(mtd, command, ctrl);
539
540 /* Address cycle, when necessary */
541 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
542 /* Serially input address */
543 if (column != -1) {
544 /* Adjust columns for 16 bit buswidth */
545 if (chip->options & NAND_BUSWIDTH_16)
546 column >>= 1;
547 chip->cmd_ctrl(mtd, column, ctrl);
548 ctrl &= ~NAND_CTRL_CHANGE;
549 }
550 if (page_addr != -1) {
551 chip->cmd_ctrl(mtd, page_addr, ctrl);
552 ctrl &= ~NAND_CTRL_CHANGE;
553 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
554 /* One more address cycle for devices > 32MiB */
555 if (chip->chipsize > (32 << 20))
556 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
557 }
558 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
559
560 /*
561 * Program and erase have their own busy handlers status and sequential
562 * in needs no delay
563 */
564 switch (command) {
565
566 case NAND_CMD_PAGEPROG:
567 case NAND_CMD_ERASE1:
568 case NAND_CMD_ERASE2:
569 case NAND_CMD_SEQIN:
570 case NAND_CMD_STATUS:
571 return;
572
573 case NAND_CMD_RESET:
574 if (chip->dev_ready)
575 break;
576 udelay(chip->chip_delay);
577 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
578 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
579 chip->cmd_ctrl(mtd,
580 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
581 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
582 ;
583 return;
584
585 /* This applies to read commands */
586 default:
587 /*
588 * If we don't have access to the busy pin, we apply the given
589 * command delay
590 */
591 if (!chip->dev_ready) {
592 udelay(chip->chip_delay);
593 return;
594 }
595 }
596 /*
597 * Apply this short delay always to ensure that we do wait tWB in
598 * any case on any machine.
599 */
600 ndelay(100);
601
602 nand_wait_ready(mtd);
603 }
604
605 /**
606 * nand_command_lp - [DEFAULT] Send command to NAND large page device
607 * @mtd: MTD device structure
608 * @command: the command to be sent
609 * @column: the column address for this command, -1 if none
610 * @page_addr: the page address for this command, -1 if none
611 *
612 * Send command to NAND device. This is the version for the new large page
613 * devices. We don't have the separate regions as we have in the small page
614 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
615 */
616 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
617 int column, int page_addr)
618 {
619 register struct nand_chip *chip = mtd->priv;
620
621 /* Emulate NAND_CMD_READOOB */
622 if (command == NAND_CMD_READOOB) {
623 column += mtd->writesize;
624 command = NAND_CMD_READ0;
625 }
626
627 /* Command latch cycle */
628 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
629
630 if (column != -1 || page_addr != -1) {
631 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
632
633 /* Serially input address */
634 if (column != -1) {
635 /* Adjust columns for 16 bit buswidth */
636 if (chip->options & NAND_BUSWIDTH_16)
637 column >>= 1;
638 chip->cmd_ctrl(mtd, column, ctrl);
639 ctrl &= ~NAND_CTRL_CHANGE;
640 chip->cmd_ctrl(mtd, column >> 8, ctrl);
641 }
642 if (page_addr != -1) {
643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 chip->cmd_ctrl(mtd, page_addr >> 8,
645 NAND_NCE | NAND_ALE);
646 /* One more address cycle for devices > 128MiB */
647 if (chip->chipsize > (128 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16,
649 NAND_NCE | NAND_ALE);
650 }
651 }
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
653
654 /*
655 * Program and erase have their own busy handlers status, sequential
656 * in, and deplete1 need no delay.
657 */
658 switch (command) {
659
660 case NAND_CMD_CACHEDPROG:
661 case NAND_CMD_PAGEPROG:
662 case NAND_CMD_ERASE1:
663 case NAND_CMD_ERASE2:
664 case NAND_CMD_SEQIN:
665 case NAND_CMD_RNDIN:
666 case NAND_CMD_STATUS:
667 return;
668
669 case NAND_CMD_RESET:
670 if (chip->dev_ready)
671 break;
672 udelay(chip->chip_delay);
673 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
674 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
675 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
676 NAND_NCE | NAND_CTRL_CHANGE);
677 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
678 ;
679 return;
680
681 case NAND_CMD_RNDOUT:
682 /* No ready / busy check necessary */
683 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
684 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
685 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
686 NAND_NCE | NAND_CTRL_CHANGE);
687 return;
688
689 case NAND_CMD_READ0:
690 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
691 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
692 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
693 NAND_NCE | NAND_CTRL_CHANGE);
694
695 /* This applies to read commands */
696 default:
697 /*
698 * If we don't have access to the busy pin, we apply the given
699 * command delay.
700 */
701 if (!chip->dev_ready) {
702 udelay(chip->chip_delay);
703 return;
704 }
705 }
706
707 /*
708 * Apply this short delay always to ensure that we do wait tWB in
709 * any case on any machine.
710 */
711 ndelay(100);
712
713 nand_wait_ready(mtd);
714 }
715
716 /**
717 * panic_nand_get_device - [GENERIC] Get chip for selected access
718 * @chip: the nand chip descriptor
719 * @mtd: MTD device structure
720 * @new_state: the state which is requested
721 *
722 * Used when in panic, no locks are taken.
723 */
724 static void panic_nand_get_device(struct nand_chip *chip,
725 struct mtd_info *mtd, int new_state)
726 {
727 /* Hardware controller shared among independent devices */
728 chip->controller->active = chip;
729 chip->state = new_state;
730 }
731
732 /**
733 * nand_get_device - [GENERIC] Get chip for selected access
734 * @mtd: MTD device structure
735 * @new_state: the state which is requested
736 *
737 * Get the device and lock it for exclusive access
738 */
739 static int
740 nand_get_device(struct mtd_info *mtd, int new_state)
741 {
742 struct nand_chip *chip = mtd->priv;
743 spinlock_t *lock = &chip->controller->lock;
744 wait_queue_head_t *wq = &chip->controller->wq;
745 DECLARE_WAITQUEUE(wait, current);
746 retry:
747 spin_lock(lock);
748
749 /* Hardware controller shared among independent devices */
750 if (!chip->controller->active)
751 chip->controller->active = chip;
752
753 if (chip->controller->active == chip && chip->state == FL_READY) {
754 chip->state = new_state;
755 spin_unlock(lock);
756 return 0;
757 }
758 if (new_state == FL_PM_SUSPENDED) {
759 if (chip->controller->active->state == FL_PM_SUSPENDED) {
760 chip->state = FL_PM_SUSPENDED;
761 spin_unlock(lock);
762 return 0;
763 }
764 }
765 set_current_state(TASK_UNINTERRUPTIBLE);
766 add_wait_queue(wq, &wait);
767 spin_unlock(lock);
768 schedule();
769 remove_wait_queue(wq, &wait);
770 goto retry;
771 }
772
773 /**
774 * panic_nand_wait - [GENERIC] wait until the command is done
775 * @mtd: MTD device structure
776 * @chip: NAND chip structure
777 * @timeo: timeout
778 *
779 * Wait for command done. This is a helper function for nand_wait used when
780 * we are in interrupt context. May happen when in panic and trying to write
781 * an oops through mtdoops.
782 */
783 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
784 unsigned long timeo)
785 {
786 int i;
787 for (i = 0; i < timeo; i++) {
788 if (chip->dev_ready) {
789 if (chip->dev_ready(mtd))
790 break;
791 } else {
792 if (chip->read_byte(mtd) & NAND_STATUS_READY)
793 break;
794 }
795 mdelay(1);
796 }
797 }
798
799 /**
800 * nand_wait - [DEFAULT] wait until the command is done
801 * @mtd: MTD device structure
802 * @chip: NAND chip structure
803 *
804 * Wait for command done. This applies to erase and program only. Erase can
805 * take up to 400ms and program up to 20ms according to general NAND and
806 * SmartMedia specs.
807 */
808 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
809 {
810
811 int status, state = chip->state;
812 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
813
814 led_trigger_event(nand_led_trigger, LED_FULL);
815
816 /*
817 * Apply this short delay always to ensure that we do wait tWB in any
818 * case on any machine.
819 */
820 ndelay(100);
821
822 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
823
824 if (in_interrupt() || oops_in_progress)
825 panic_nand_wait(mtd, chip, timeo);
826 else {
827 timeo = jiffies + msecs_to_jiffies(timeo);
828 while (time_before(jiffies, timeo)) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
831 break;
832 } else {
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
834 break;
835 }
836 cond_resched();
837 }
838 }
839 led_trigger_event(nand_led_trigger, LED_OFF);
840
841 status = (int)chip->read_byte(mtd);
842 /* This can happen if in case of timeout or buggy dev_ready */
843 WARN_ON(!(status & NAND_STATUS_READY));
844 return status;
845 }
846
847 /**
848 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
849 * @mtd: mtd info
850 * @ofs: offset to start unlock from
851 * @len: length to unlock
852 * @invert: when = 0, unlock the range of blocks within the lower and
853 * upper boundary address
854 * when = 1, unlock the range of blocks outside the boundaries
855 * of the lower and upper boundary address
856 *
857 * Returs unlock status.
858 */
859 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
860 uint64_t len, int invert)
861 {
862 int ret = 0;
863 int status, page;
864 struct nand_chip *chip = mtd->priv;
865
866 /* Submit address of first page to unlock */
867 page = ofs >> chip->page_shift;
868 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
869
870 /* Submit address of last page to unlock */
871 page = (ofs + len) >> chip->page_shift;
872 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
873 (page | invert) & chip->pagemask);
874
875 /* Call wait ready function */
876 status = chip->waitfunc(mtd, chip);
877 /* See if device thinks it succeeded */
878 if (status & NAND_STATUS_FAIL) {
879 pr_debug("%s: error status = 0x%08x\n",
880 __func__, status);
881 ret = -EIO;
882 }
883
884 return ret;
885 }
886
887 /**
888 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
889 * @mtd: mtd info
890 * @ofs: offset to start unlock from
891 * @len: length to unlock
892 *
893 * Returns unlock status.
894 */
895 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
896 {
897 int ret = 0;
898 int chipnr;
899 struct nand_chip *chip = mtd->priv;
900
901 pr_debug("%s: start = 0x%012llx, len = %llu\n",
902 __func__, (unsigned long long)ofs, len);
903
904 if (check_offs_len(mtd, ofs, len))
905 ret = -EINVAL;
906
907 /* Align to last block address if size addresses end of the device */
908 if (ofs + len == mtd->size)
909 len -= mtd->erasesize;
910
911 nand_get_device(mtd, FL_UNLOCKING);
912
913 /* Shift to get chip number */
914 chipnr = ofs >> chip->chip_shift;
915
916 chip->select_chip(mtd, chipnr);
917
918 /* Check, if it is write protected */
919 if (nand_check_wp(mtd)) {
920 pr_debug("%s: device is write protected!\n",
921 __func__);
922 ret = -EIO;
923 goto out;
924 }
925
926 ret = __nand_unlock(mtd, ofs, len, 0);
927
928 out:
929 chip->select_chip(mtd, -1);
930 nand_release_device(mtd);
931
932 return ret;
933 }
934 EXPORT_SYMBOL(nand_unlock);
935
936 /**
937 * nand_lock - [REPLACEABLE] locks all blocks present in the device
938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
941 *
942 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
943 * have this feature, but it allows only to lock all blocks, not for specified
944 * range for block. Implementing 'lock' feature by making use of 'unlock', for
945 * now.
946 *
947 * Returns lock status.
948 */
949 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
950 {
951 int ret = 0;
952 int chipnr, status, page;
953 struct nand_chip *chip = mtd->priv;
954
955 pr_debug("%s: start = 0x%012llx, len = %llu\n",
956 __func__, (unsigned long long)ofs, len);
957
958 if (check_offs_len(mtd, ofs, len))
959 ret = -EINVAL;
960
961 nand_get_device(mtd, FL_LOCKING);
962
963 /* Shift to get chip number */
964 chipnr = ofs >> chip->chip_shift;
965
966 chip->select_chip(mtd, chipnr);
967
968 /* Check, if it is write protected */
969 if (nand_check_wp(mtd)) {
970 pr_debug("%s: device is write protected!\n",
971 __func__);
972 status = MTD_ERASE_FAILED;
973 ret = -EIO;
974 goto out;
975 }
976
977 /* Submit address of first page to lock */
978 page = ofs >> chip->page_shift;
979 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
980
981 /* Call wait ready function */
982 status = chip->waitfunc(mtd, chip);
983 /* See if device thinks it succeeded */
984 if (status & NAND_STATUS_FAIL) {
985 pr_debug("%s: error status = 0x%08x\n",
986 __func__, status);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0x1);
992
993 out:
994 chip->select_chip(mtd, -1);
995 nand_release_device(mtd);
996
997 return ret;
998 }
999 EXPORT_SYMBOL(nand_lock);
1000
1001 /**
1002 * nand_read_page_raw - [INTERN] read raw page data without ecc
1003 * @mtd: mtd info structure
1004 * @chip: nand chip info structure
1005 * @buf: buffer to store read data
1006 * @oob_required: caller requires OOB data read to chip->oob_poi
1007 * @page: page number to read
1008 *
1009 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1010 */
1011 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1012 uint8_t *buf, int oob_required, int page)
1013 {
1014 chip->read_buf(mtd, buf, mtd->writesize);
1015 if (oob_required)
1016 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1017 return 0;
1018 }
1019
1020 /**
1021 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1025 * @oob_required: caller requires OOB data read to chip->oob_poi
1026 * @page: page number to read
1027 *
1028 * We need a special oob layout and handling even when OOB isn't used.
1029 */
1030 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1031 struct nand_chip *chip, uint8_t *buf,
1032 int oob_required, int page)
1033 {
1034 int eccsize = chip->ecc.size;
1035 int eccbytes = chip->ecc.bytes;
1036 uint8_t *oob = chip->oob_poi;
1037 int steps, size;
1038
1039 for (steps = chip->ecc.steps; steps > 0; steps--) {
1040 chip->read_buf(mtd, buf, eccsize);
1041 buf += eccsize;
1042
1043 if (chip->ecc.prepad) {
1044 chip->read_buf(mtd, oob, chip->ecc.prepad);
1045 oob += chip->ecc.prepad;
1046 }
1047
1048 chip->read_buf(mtd, oob, eccbytes);
1049 oob += eccbytes;
1050
1051 if (chip->ecc.postpad) {
1052 chip->read_buf(mtd, oob, chip->ecc.postpad);
1053 oob += chip->ecc.postpad;
1054 }
1055 }
1056
1057 size = mtd->oobsize - (oob - chip->oob_poi);
1058 if (size)
1059 chip->read_buf(mtd, oob, size);
1060
1061 return 0;
1062 }
1063
1064 /**
1065 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @oob_required: caller requires OOB data read to chip->oob_poi
1070 * @page: page number to read
1071 */
1072 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1073 uint8_t *buf, int oob_required, int page)
1074 {
1075 int i, eccsize = chip->ecc.size;
1076 int eccbytes = chip->ecc.bytes;
1077 int eccsteps = chip->ecc.steps;
1078 uint8_t *p = buf;
1079 uint8_t *ecc_calc = chip->buffers->ecccalc;
1080 uint8_t *ecc_code = chip->buffers->ecccode;
1081 uint32_t *eccpos = chip->ecc.layout->eccpos;
1082 unsigned int max_bitflips = 0;
1083
1084 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1085
1086 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1087 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1088
1089 for (i = 0; i < chip->ecc.total; i++)
1090 ecc_code[i] = chip->oob_poi[eccpos[i]];
1091
1092 eccsteps = chip->ecc.steps;
1093 p = buf;
1094
1095 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1096 int stat;
1097
1098 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1099 if (stat < 0) {
1100 mtd->ecc_stats.failed++;
1101 } else {
1102 mtd->ecc_stats.corrected += stat;
1103 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1104 }
1105 }
1106 return max_bitflips;
1107 }
1108
1109 /**
1110 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1111 * @mtd: mtd info structure
1112 * @chip: nand chip info structure
1113 * @data_offs: offset of requested data within the page
1114 * @readlen: data length
1115 * @bufpoi: buffer to store read data
1116 */
1117 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1118 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1119 {
1120 int start_step, end_step, num_steps;
1121 uint32_t *eccpos = chip->ecc.layout->eccpos;
1122 uint8_t *p;
1123 int data_col_addr, i, gaps = 0;
1124 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1125 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1126 int index = 0;
1127 unsigned int max_bitflips = 0;
1128
1129 /* Column address within the page aligned to ECC size (256bytes) */
1130 start_step = data_offs / chip->ecc.size;
1131 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1132 num_steps = end_step - start_step + 1;
1133
1134 /* Data size aligned to ECC ecc.size */
1135 datafrag_len = num_steps * chip->ecc.size;
1136 eccfrag_len = num_steps * chip->ecc.bytes;
1137
1138 data_col_addr = start_step * chip->ecc.size;
1139 /* If we read not a page aligned data */
1140 if (data_col_addr != 0)
1141 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1142
1143 p = bufpoi + data_col_addr;
1144 chip->read_buf(mtd, p, datafrag_len);
1145
1146 /* Calculate ECC */
1147 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1148 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1149
1150 /*
1151 * The performance is faster if we position offsets according to
1152 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1153 */
1154 for (i = 0; i < eccfrag_len - 1; i++) {
1155 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1156 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1157 gaps = 1;
1158 break;
1159 }
1160 }
1161 if (gaps) {
1162 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1163 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1164 } else {
1165 /*
1166 * Send the command to read the particular ECC bytes take care
1167 * about buswidth alignment in read_buf.
1168 */
1169 index = start_step * chip->ecc.bytes;
1170
1171 aligned_pos = eccpos[index] & ~(busw - 1);
1172 aligned_len = eccfrag_len;
1173 if (eccpos[index] & (busw - 1))
1174 aligned_len++;
1175 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1176 aligned_len++;
1177
1178 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1179 mtd->writesize + aligned_pos, -1);
1180 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1181 }
1182
1183 for (i = 0; i < eccfrag_len; i++)
1184 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1185
1186 p = bufpoi + data_col_addr;
1187 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1188 int stat;
1189
1190 stat = chip->ecc.correct(mtd, p,
1191 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1192 if (stat < 0) {
1193 mtd->ecc_stats.failed++;
1194 } else {
1195 mtd->ecc_stats.corrected += stat;
1196 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1197 }
1198 }
1199 return max_bitflips;
1200 }
1201
1202 /**
1203 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1204 * @mtd: mtd info structure
1205 * @chip: nand chip info structure
1206 * @buf: buffer to store read data
1207 * @oob_required: caller requires OOB data read to chip->oob_poi
1208 * @page: page number to read
1209 *
1210 * Not for syndrome calculating ECC controllers which need a special oob layout.
1211 */
1212 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1213 uint8_t *buf, int oob_required, int page)
1214 {
1215 int i, eccsize = chip->ecc.size;
1216 int eccbytes = chip->ecc.bytes;
1217 int eccsteps = chip->ecc.steps;
1218 uint8_t *p = buf;
1219 uint8_t *ecc_calc = chip->buffers->ecccalc;
1220 uint8_t *ecc_code = chip->buffers->ecccode;
1221 uint32_t *eccpos = chip->ecc.layout->eccpos;
1222 unsigned int max_bitflips = 0;
1223
1224 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1225 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1226 chip->read_buf(mtd, p, eccsize);
1227 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1228 }
1229 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1230
1231 for (i = 0; i < chip->ecc.total; i++)
1232 ecc_code[i] = chip->oob_poi[eccpos[i]];
1233
1234 eccsteps = chip->ecc.steps;
1235 p = buf;
1236
1237 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1238 int stat;
1239
1240 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1241 if (stat < 0) {
1242 mtd->ecc_stats.failed++;
1243 } else {
1244 mtd->ecc_stats.corrected += stat;
1245 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1246 }
1247 }
1248 return max_bitflips;
1249 }
1250
1251 /**
1252 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1256 * @oob_required: caller requires OOB data read to chip->oob_poi
1257 * @page: page number to read
1258 *
1259 * Hardware ECC for large page chips, require OOB to be read first. For this
1260 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1261 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1262 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1263 * the data area, by overwriting the NAND manufacturer bad block markings.
1264 */
1265 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1266 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1267 {
1268 int i, eccsize = chip->ecc.size;
1269 int eccbytes = chip->ecc.bytes;
1270 int eccsteps = chip->ecc.steps;
1271 uint8_t *p = buf;
1272 uint8_t *ecc_code = chip->buffers->ecccode;
1273 uint32_t *eccpos = chip->ecc.layout->eccpos;
1274 uint8_t *ecc_calc = chip->buffers->ecccalc;
1275 unsigned int max_bitflips = 0;
1276
1277 /* Read the OOB area first */
1278 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1279 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1280 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1281
1282 for (i = 0; i < chip->ecc.total; i++)
1283 ecc_code[i] = chip->oob_poi[eccpos[i]];
1284
1285 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1286 int stat;
1287
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1291
1292 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1293 if (stat < 0) {
1294 mtd->ecc_stats.failed++;
1295 } else {
1296 mtd->ecc_stats.corrected += stat;
1297 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1298 }
1299 }
1300 return max_bitflips;
1301 }
1302
1303 /**
1304 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1305 * @mtd: mtd info structure
1306 * @chip: nand chip info structure
1307 * @buf: buffer to store read data
1308 * @oob_required: caller requires OOB data read to chip->oob_poi
1309 * @page: page number to read
1310 *
1311 * The hw generator calculates the error syndrome automatically. Therefore we
1312 * need a special oob layout and handling.
1313 */
1314 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1315 uint8_t *buf, int oob_required, int page)
1316 {
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1320 uint8_t *p = buf;
1321 uint8_t *oob = chip->oob_poi;
1322 unsigned int max_bitflips = 0;
1323
1324 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1325 int stat;
1326
1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1329
1330 if (chip->ecc.prepad) {
1331 chip->read_buf(mtd, oob, chip->ecc.prepad);
1332 oob += chip->ecc.prepad;
1333 }
1334
1335 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1336 chip->read_buf(mtd, oob, eccbytes);
1337 stat = chip->ecc.correct(mtd, p, oob, NULL);
1338
1339 if (stat < 0) {
1340 mtd->ecc_stats.failed++;
1341 } else {
1342 mtd->ecc_stats.corrected += stat;
1343 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1344 }
1345
1346 oob += eccbytes;
1347
1348 if (chip->ecc.postpad) {
1349 chip->read_buf(mtd, oob, chip->ecc.postpad);
1350 oob += chip->ecc.postpad;
1351 }
1352 }
1353
1354 /* Calculate remaining oob bytes */
1355 i = mtd->oobsize - (oob - chip->oob_poi);
1356 if (i)
1357 chip->read_buf(mtd, oob, i);
1358
1359 return max_bitflips;
1360 }
1361
1362 /**
1363 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1364 * @chip: nand chip structure
1365 * @oob: oob destination address
1366 * @ops: oob ops structure
1367 * @len: size of oob to transfer
1368 */
1369 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1370 struct mtd_oob_ops *ops, size_t len)
1371 {
1372 switch (ops->mode) {
1373
1374 case MTD_OPS_PLACE_OOB:
1375 case MTD_OPS_RAW:
1376 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1377 return oob + len;
1378
1379 case MTD_OPS_AUTO_OOB: {
1380 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1381 uint32_t boffs = 0, roffs = ops->ooboffs;
1382 size_t bytes = 0;
1383
1384 for (; free->length && len; free++, len -= bytes) {
1385 /* Read request not from offset 0? */
1386 if (unlikely(roffs)) {
1387 if (roffs >= free->length) {
1388 roffs -= free->length;
1389 continue;
1390 }
1391 boffs = free->offset + roffs;
1392 bytes = min_t(size_t, len,
1393 (free->length - roffs));
1394 roffs = 0;
1395 } else {
1396 bytes = min_t(size_t, len, free->length);
1397 boffs = free->offset;
1398 }
1399 memcpy(oob, chip->oob_poi + boffs, bytes);
1400 oob += bytes;
1401 }
1402 return oob;
1403 }
1404 default:
1405 BUG();
1406 }
1407 return NULL;
1408 }
1409
1410 /**
1411 * nand_do_read_ops - [INTERN] Read data with ECC
1412 * @mtd: MTD device structure
1413 * @from: offset to read from
1414 * @ops: oob ops structure
1415 *
1416 * Internal function. Called with chip held.
1417 */
1418 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1419 struct mtd_oob_ops *ops)
1420 {
1421 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1422 struct nand_chip *chip = mtd->priv;
1423 struct mtd_ecc_stats stats;
1424 int ret = 0;
1425 uint32_t readlen = ops->len;
1426 uint32_t oobreadlen = ops->ooblen;
1427 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1428 mtd->oobavail : mtd->oobsize;
1429
1430 uint8_t *bufpoi, *oob, *buf;
1431 unsigned int max_bitflips = 0;
1432
1433 stats = mtd->ecc_stats;
1434
1435 chipnr = (int)(from >> chip->chip_shift);
1436 chip->select_chip(mtd, chipnr);
1437
1438 realpage = (int)(from >> chip->page_shift);
1439 page = realpage & chip->pagemask;
1440
1441 col = (int)(from & (mtd->writesize - 1));
1442
1443 buf = ops->datbuf;
1444 oob = ops->oobbuf;
1445 oob_required = oob ? 1 : 0;
1446
1447 while (1) {
1448 bytes = min(mtd->writesize - col, readlen);
1449 aligned = (bytes == mtd->writesize);
1450
1451 /* Is the current page in the buffer? */
1452 if (realpage != chip->pagebuf || oob) {
1453 bufpoi = aligned ? buf : chip->buffers->databuf;
1454
1455 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1456
1457 /*
1458 * Now read the page into the buffer. Absent an error,
1459 * the read methods return max bitflips per ecc step.
1460 */
1461 if (unlikely(ops->mode == MTD_OPS_RAW))
1462 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1463 oob_required,
1464 page);
1465 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1466 !oob)
1467 ret = chip->ecc.read_subpage(mtd, chip,
1468 col, bytes, bufpoi);
1469 else
1470 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1471 oob_required, page);
1472 if (ret < 0) {
1473 if (!aligned)
1474 /* Invalidate page cache */
1475 chip->pagebuf = -1;
1476 break;
1477 }
1478
1479 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1480
1481 /* Transfer not aligned data */
1482 if (!aligned) {
1483 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1484 !(mtd->ecc_stats.failed - stats.failed) &&
1485 (ops->mode != MTD_OPS_RAW)) {
1486 chip->pagebuf = realpage;
1487 chip->pagebuf_bitflips = ret;
1488 } else {
1489 /* Invalidate page cache */
1490 chip->pagebuf = -1;
1491 }
1492 memcpy(buf, chip->buffers->databuf + col, bytes);
1493 }
1494
1495 buf += bytes;
1496
1497 if (unlikely(oob)) {
1498 int toread = min(oobreadlen, max_oobsize);
1499
1500 if (toread) {
1501 oob = nand_transfer_oob(chip,
1502 oob, ops, toread);
1503 oobreadlen -= toread;
1504 }
1505 }
1506
1507 if (chip->options & NAND_NEED_READRDY) {
1508 /* Apply delay or wait for ready/busy pin */
1509 if (!chip->dev_ready)
1510 udelay(chip->chip_delay);
1511 else
1512 nand_wait_ready(mtd);
1513 }
1514 } else {
1515 memcpy(buf, chip->buffers->databuf + col, bytes);
1516 buf += bytes;
1517 max_bitflips = max_t(unsigned int, max_bitflips,
1518 chip->pagebuf_bitflips);
1519 }
1520
1521 readlen -= bytes;
1522
1523 if (!readlen)
1524 break;
1525
1526 /* For subsequent reads align to page boundary */
1527 col = 0;
1528 /* Increment page address */
1529 realpage++;
1530
1531 page = realpage & chip->pagemask;
1532 /* Check, if we cross a chip boundary */
1533 if (!page) {
1534 chipnr++;
1535 chip->select_chip(mtd, -1);
1536 chip->select_chip(mtd, chipnr);
1537 }
1538 }
1539 chip->select_chip(mtd, -1);
1540
1541 ops->retlen = ops->len - (size_t) readlen;
1542 if (oob)
1543 ops->oobretlen = ops->ooblen - oobreadlen;
1544
1545 if (ret < 0)
1546 return ret;
1547
1548 if (mtd->ecc_stats.failed - stats.failed)
1549 return -EBADMSG;
1550
1551 return max_bitflips;
1552 }
1553
1554 /**
1555 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1556 * @mtd: MTD device structure
1557 * @from: offset to read from
1558 * @len: number of bytes to read
1559 * @retlen: pointer to variable to store the number of read bytes
1560 * @buf: the databuffer to put data
1561 *
1562 * Get hold of the chip and call nand_do_read.
1563 */
1564 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1565 size_t *retlen, uint8_t *buf)
1566 {
1567 struct mtd_oob_ops ops;
1568 int ret;
1569
1570 nand_get_device(mtd, FL_READING);
1571 ops.len = len;
1572 ops.datbuf = buf;
1573 ops.oobbuf = NULL;
1574 ops.mode = MTD_OPS_PLACE_OOB;
1575 ret = nand_do_read_ops(mtd, from, &ops);
1576 *retlen = ops.retlen;
1577 nand_release_device(mtd);
1578 return ret;
1579 }
1580
1581 /**
1582 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1585 * @page: page number to read
1586 */
1587 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1588 int page)
1589 {
1590 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1591 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1592 return 0;
1593 }
1594
1595 /**
1596 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1597 * with syndromes
1598 * @mtd: mtd info structure
1599 * @chip: nand chip info structure
1600 * @page: page number to read
1601 */
1602 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1603 int page)
1604 {
1605 uint8_t *buf = chip->oob_poi;
1606 int length = mtd->oobsize;
1607 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1608 int eccsize = chip->ecc.size;
1609 uint8_t *bufpoi = buf;
1610 int i, toread, sndrnd = 0, pos;
1611
1612 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1613 for (i = 0; i < chip->ecc.steps; i++) {
1614 if (sndrnd) {
1615 pos = eccsize + i * (eccsize + chunk);
1616 if (mtd->writesize > 512)
1617 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1618 else
1619 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1620 } else
1621 sndrnd = 1;
1622 toread = min_t(int, length, chunk);
1623 chip->read_buf(mtd, bufpoi, toread);
1624 bufpoi += toread;
1625 length -= toread;
1626 }
1627 if (length > 0)
1628 chip->read_buf(mtd, bufpoi, length);
1629
1630 return 0;
1631 }
1632
1633 /**
1634 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to write
1638 */
1639 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1640 int page)
1641 {
1642 int status = 0;
1643 const uint8_t *buf = chip->oob_poi;
1644 int length = mtd->oobsize;
1645
1646 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1647 chip->write_buf(mtd, buf, length);
1648 /* Send command to program the OOB data */
1649 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1650
1651 status = chip->waitfunc(mtd, chip);
1652
1653 return status & NAND_STATUS_FAIL ? -EIO : 0;
1654 }
1655
1656 /**
1657 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1658 * with syndrome - only for large page flash
1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1661 * @page: page number to write
1662 */
1663 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1664 struct nand_chip *chip, int page)
1665 {
1666 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1667 int eccsize = chip->ecc.size, length = mtd->oobsize;
1668 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1669 const uint8_t *bufpoi = chip->oob_poi;
1670
1671 /*
1672 * data-ecc-data-ecc ... ecc-oob
1673 * or
1674 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1675 */
1676 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1677 pos = steps * (eccsize + chunk);
1678 steps = 0;
1679 } else
1680 pos = eccsize;
1681
1682 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1683 for (i = 0; i < steps; i++) {
1684 if (sndcmd) {
1685 if (mtd->writesize <= 512) {
1686 uint32_t fill = 0xFFFFFFFF;
1687
1688 len = eccsize;
1689 while (len > 0) {
1690 int num = min_t(int, len, 4);
1691 chip->write_buf(mtd, (uint8_t *)&fill,
1692 num);
1693 len -= num;
1694 }
1695 } else {
1696 pos = eccsize + i * (eccsize + chunk);
1697 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1698 }
1699 } else
1700 sndcmd = 1;
1701 len = min_t(int, length, chunk);
1702 chip->write_buf(mtd, bufpoi, len);
1703 bufpoi += len;
1704 length -= len;
1705 }
1706 if (length > 0)
1707 chip->write_buf(mtd, bufpoi, length);
1708
1709 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1710 status = chip->waitfunc(mtd, chip);
1711
1712 return status & NAND_STATUS_FAIL ? -EIO : 0;
1713 }
1714
1715 /**
1716 * nand_do_read_oob - [INTERN] NAND read out-of-band
1717 * @mtd: MTD device structure
1718 * @from: offset to read from
1719 * @ops: oob operations description structure
1720 *
1721 * NAND read out-of-band data from the spare area.
1722 */
1723 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1724 struct mtd_oob_ops *ops)
1725 {
1726 int page, realpage, chipnr;
1727 struct nand_chip *chip = mtd->priv;
1728 struct mtd_ecc_stats stats;
1729 int readlen = ops->ooblen;
1730 int len;
1731 uint8_t *buf = ops->oobbuf;
1732 int ret = 0;
1733
1734 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1735 __func__, (unsigned long long)from, readlen);
1736
1737 stats = mtd->ecc_stats;
1738
1739 if (ops->mode == MTD_OPS_AUTO_OOB)
1740 len = chip->ecc.layout->oobavail;
1741 else
1742 len = mtd->oobsize;
1743
1744 if (unlikely(ops->ooboffs >= len)) {
1745 pr_debug("%s: attempt to start read outside oob\n",
1746 __func__);
1747 return -EINVAL;
1748 }
1749
1750 /* Do not allow reads past end of device */
1751 if (unlikely(from >= mtd->size ||
1752 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1753 (from >> chip->page_shift)) * len)) {
1754 pr_debug("%s: attempt to read beyond end of device\n",
1755 __func__);
1756 return -EINVAL;
1757 }
1758
1759 chipnr = (int)(from >> chip->chip_shift);
1760 chip->select_chip(mtd, chipnr);
1761
1762 /* Shift to get page */
1763 realpage = (int)(from >> chip->page_shift);
1764 page = realpage & chip->pagemask;
1765
1766 while (1) {
1767 if (ops->mode == MTD_OPS_RAW)
1768 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1769 else
1770 ret = chip->ecc.read_oob(mtd, chip, page);
1771
1772 if (ret < 0)
1773 break;
1774
1775 len = min(len, readlen);
1776 buf = nand_transfer_oob(chip, buf, ops, len);
1777
1778 if (chip->options & NAND_NEED_READRDY) {
1779 /* Apply delay or wait for ready/busy pin */
1780 if (!chip->dev_ready)
1781 udelay(chip->chip_delay);
1782 else
1783 nand_wait_ready(mtd);
1784 }
1785
1786 readlen -= len;
1787 if (!readlen)
1788 break;
1789
1790 /* Increment page address */
1791 realpage++;
1792
1793 page = realpage & chip->pagemask;
1794 /* Check, if we cross a chip boundary */
1795 if (!page) {
1796 chipnr++;
1797 chip->select_chip(mtd, -1);
1798 chip->select_chip(mtd, chipnr);
1799 }
1800 }
1801 chip->select_chip(mtd, -1);
1802
1803 ops->oobretlen = ops->ooblen - readlen;
1804
1805 if (ret < 0)
1806 return ret;
1807
1808 if (mtd->ecc_stats.failed - stats.failed)
1809 return -EBADMSG;
1810
1811 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1812 }
1813
1814 /**
1815 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1816 * @mtd: MTD device structure
1817 * @from: offset to read from
1818 * @ops: oob operation description structure
1819 *
1820 * NAND read data and/or out-of-band data.
1821 */
1822 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1823 struct mtd_oob_ops *ops)
1824 {
1825 int ret = -ENOTSUPP;
1826
1827 ops->retlen = 0;
1828
1829 /* Do not allow reads past end of device */
1830 if (ops->datbuf && (from + ops->len) > mtd->size) {
1831 pr_debug("%s: attempt to read beyond end of device\n",
1832 __func__);
1833 return -EINVAL;
1834 }
1835
1836 nand_get_device(mtd, FL_READING);
1837
1838 switch (ops->mode) {
1839 case MTD_OPS_PLACE_OOB:
1840 case MTD_OPS_AUTO_OOB:
1841 case MTD_OPS_RAW:
1842 break;
1843
1844 default:
1845 goto out;
1846 }
1847
1848 if (!ops->datbuf)
1849 ret = nand_do_read_oob(mtd, from, ops);
1850 else
1851 ret = nand_do_read_ops(mtd, from, ops);
1852
1853 out:
1854 nand_release_device(mtd);
1855 return ret;
1856 }
1857
1858
1859 /**
1860 * nand_write_page_raw - [INTERN] raw page write function
1861 * @mtd: mtd info structure
1862 * @chip: nand chip info structure
1863 * @buf: data buffer
1864 * @oob_required: must write chip->oob_poi to OOB
1865 *
1866 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1867 */
1868 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1869 const uint8_t *buf, int oob_required)
1870 {
1871 chip->write_buf(mtd, buf, mtd->writesize);
1872 if (oob_required)
1873 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1874
1875 return 0;
1876 }
1877
1878 /**
1879 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1880 * @mtd: mtd info structure
1881 * @chip: nand chip info structure
1882 * @buf: data buffer
1883 * @oob_required: must write chip->oob_poi to OOB
1884 *
1885 * We need a special oob layout and handling even when ECC isn't checked.
1886 */
1887 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1888 struct nand_chip *chip,
1889 const uint8_t *buf, int oob_required)
1890 {
1891 int eccsize = chip->ecc.size;
1892 int eccbytes = chip->ecc.bytes;
1893 uint8_t *oob = chip->oob_poi;
1894 int steps, size;
1895
1896 for (steps = chip->ecc.steps; steps > 0; steps--) {
1897 chip->write_buf(mtd, buf, eccsize);
1898 buf += eccsize;
1899
1900 if (chip->ecc.prepad) {
1901 chip->write_buf(mtd, oob, chip->ecc.prepad);
1902 oob += chip->ecc.prepad;
1903 }
1904
1905 chip->read_buf(mtd, oob, eccbytes);
1906 oob += eccbytes;
1907
1908 if (chip->ecc.postpad) {
1909 chip->write_buf(mtd, oob, chip->ecc.postpad);
1910 oob += chip->ecc.postpad;
1911 }
1912 }
1913
1914 size = mtd->oobsize - (oob - chip->oob_poi);
1915 if (size)
1916 chip->write_buf(mtd, oob, size);
1917
1918 return 0;
1919 }
1920 /**
1921 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1922 * @mtd: mtd info structure
1923 * @chip: nand chip info structure
1924 * @buf: data buffer
1925 * @oob_required: must write chip->oob_poi to OOB
1926 */
1927 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1928 const uint8_t *buf, int oob_required)
1929 {
1930 int i, eccsize = chip->ecc.size;
1931 int eccbytes = chip->ecc.bytes;
1932 int eccsteps = chip->ecc.steps;
1933 uint8_t *ecc_calc = chip->buffers->ecccalc;
1934 const uint8_t *p = buf;
1935 uint32_t *eccpos = chip->ecc.layout->eccpos;
1936
1937 /* Software ECC calculation */
1938 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1939 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1940
1941 for (i = 0; i < chip->ecc.total; i++)
1942 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1943
1944 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1945 }
1946
1947 /**
1948 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1949 * @mtd: mtd info structure
1950 * @chip: nand chip info structure
1951 * @buf: data buffer
1952 * @oob_required: must write chip->oob_poi to OOB
1953 */
1954 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1955 const uint8_t *buf, int oob_required)
1956 {
1957 int i, eccsize = chip->ecc.size;
1958 int eccbytes = chip->ecc.bytes;
1959 int eccsteps = chip->ecc.steps;
1960 uint8_t *ecc_calc = chip->buffers->ecccalc;
1961 const uint8_t *p = buf;
1962 uint32_t *eccpos = chip->ecc.layout->eccpos;
1963
1964 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1965 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1966 chip->write_buf(mtd, p, eccsize);
1967 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1968 }
1969
1970 for (i = 0; i < chip->ecc.total; i++)
1971 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1972
1973 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1974
1975 return 0;
1976 }
1977
1978
1979 /**
1980 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
1983 * @column: column address of subpage within the page
1984 * @data_len: data length
1985 * @oob_required: must write chip->oob_poi to OOB
1986 */
1987 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1988 struct nand_chip *chip, uint32_t offset,
1989 uint32_t data_len, const uint8_t *data_buf,
1990 int oob_required)
1991 {
1992 uint8_t *oob_buf = chip->oob_poi;
1993 uint8_t *ecc_calc = chip->buffers->ecccalc;
1994 int ecc_size = chip->ecc.size;
1995 int ecc_bytes = chip->ecc.bytes;
1996 int ecc_steps = chip->ecc.steps;
1997 uint32_t *eccpos = chip->ecc.layout->eccpos;
1998 uint32_t start_step = offset / ecc_size;
1999 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2000 int oob_bytes = mtd->oobsize / ecc_steps;
2001 int step, i;
2002
2003 for (step = 0; step < ecc_steps; step++) {
2004 /* configure controller for WRITE access */
2005 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2006
2007 /* write data (untouched subpages already masked by 0xFF) */
2008 chip->write_buf(mtd, data_buf, ecc_size);
2009
2010 /* mask ECC of un-touched subpages by padding 0xFF */
2011 if ((step < start_step) || (step > end_step))
2012 memset(ecc_calc, 0xff, ecc_bytes);
2013 else
2014 chip->ecc.calculate(mtd, data_buf, ecc_calc);
2015
2016 /* mask OOB of un-touched subpages by padding 0xFF */
2017 /* if oob_required, preserve OOB metadata of written subpage */
2018 if (!oob_required || (step < start_step) || (step > end_step))
2019 memset(oob_buf, 0xff, oob_bytes);
2020
2021 data_buf += ecc_size;
2022 ecc_calc += ecc_bytes;
2023 oob_buf += oob_bytes;
2024 }
2025
2026 /* copy calculated ECC for whole page to chip->buffer->oob */
2027 /* this include masked-value(0xFF) for unwritten subpages */
2028 ecc_calc = chip->buffers->ecccalc;
2029 for (i = 0; i < chip->ecc.total; i++)
2030 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2031
2032 /* write OOB buffer to NAND device */
2033 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2034
2035 return 0;
2036 }
2037
2038
2039 /**
2040 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2041 * @mtd: mtd info structure
2042 * @chip: nand chip info structure
2043 * @buf: data buffer
2044 * @oob_required: must write chip->oob_poi to OOB
2045 *
2046 * The hw generator calculates the error syndrome automatically. Therefore we
2047 * need a special oob layout and handling.
2048 */
2049 static int nand_write_page_syndrome(struct mtd_info *mtd,
2050 struct nand_chip *chip,
2051 const uint8_t *buf, int oob_required)
2052 {
2053 int i, eccsize = chip->ecc.size;
2054 int eccbytes = chip->ecc.bytes;
2055 int eccsteps = chip->ecc.steps;
2056 const uint8_t *p = buf;
2057 uint8_t *oob = chip->oob_poi;
2058
2059 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2060
2061 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2062 chip->write_buf(mtd, p, eccsize);
2063
2064 if (chip->ecc.prepad) {
2065 chip->write_buf(mtd, oob, chip->ecc.prepad);
2066 oob += chip->ecc.prepad;
2067 }
2068
2069 chip->ecc.calculate(mtd, p, oob);
2070 chip->write_buf(mtd, oob, eccbytes);
2071 oob += eccbytes;
2072
2073 if (chip->ecc.postpad) {
2074 chip->write_buf(mtd, oob, chip->ecc.postpad);
2075 oob += chip->ecc.postpad;
2076 }
2077 }
2078
2079 /* Calculate remaining oob bytes */
2080 i = mtd->oobsize - (oob - chip->oob_poi);
2081 if (i)
2082 chip->write_buf(mtd, oob, i);
2083
2084 return 0;
2085 }
2086
2087 /**
2088 * nand_write_page - [REPLACEABLE] write one page
2089 * @mtd: MTD device structure
2090 * @chip: NAND chip descriptor
2091 * @offset: address offset within the page
2092 * @data_len: length of actual data to be written
2093 * @buf: the data to write
2094 * @oob_required: must write chip->oob_poi to OOB
2095 * @page: page number to write
2096 * @cached: cached programming
2097 * @raw: use _raw version of write_page
2098 */
2099 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2100 uint32_t offset, int data_len, const uint8_t *buf,
2101 int oob_required, int page, int cached, int raw)
2102 {
2103 int status, subpage;
2104
2105 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2106 chip->ecc.write_subpage)
2107 subpage = offset || (data_len < mtd->writesize);
2108 else
2109 subpage = 0;
2110
2111 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2112
2113 if (unlikely(raw))
2114 status = chip->ecc.write_page_raw(mtd, chip, buf,
2115 oob_required);
2116 else if (subpage)
2117 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2118 buf, oob_required);
2119 else
2120 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2121
2122 if (status < 0)
2123 return status;
2124
2125 /*
2126 * Cached progamming disabled for now. Not sure if it's worth the
2127 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2128 */
2129 cached = 0;
2130
2131 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2132
2133 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2134 status = chip->waitfunc(mtd, chip);
2135 /*
2136 * See if operation failed and additional status checks are
2137 * available.
2138 */
2139 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2140 status = chip->errstat(mtd, chip, FL_WRITING, status,
2141 page);
2142
2143 if (status & NAND_STATUS_FAIL)
2144 return -EIO;
2145 } else {
2146 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2147 status = chip->waitfunc(mtd, chip);
2148 }
2149
2150 return 0;
2151 }
2152
2153 /**
2154 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2155 * @mtd: MTD device structure
2156 * @oob: oob data buffer
2157 * @len: oob data write length
2158 * @ops: oob ops structure
2159 */
2160 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2161 struct mtd_oob_ops *ops)
2162 {
2163 struct nand_chip *chip = mtd->priv;
2164
2165 /*
2166 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2167 * data from a previous OOB read.
2168 */
2169 memset(chip->oob_poi, 0xff, mtd->oobsize);
2170
2171 switch (ops->mode) {
2172
2173 case MTD_OPS_PLACE_OOB:
2174 case MTD_OPS_RAW:
2175 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2176 return oob + len;
2177
2178 case MTD_OPS_AUTO_OOB: {
2179 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2180 uint32_t boffs = 0, woffs = ops->ooboffs;
2181 size_t bytes = 0;
2182
2183 for (; free->length && len; free++, len -= bytes) {
2184 /* Write request not from offset 0? */
2185 if (unlikely(woffs)) {
2186 if (woffs >= free->length) {
2187 woffs -= free->length;
2188 continue;
2189 }
2190 boffs = free->offset + woffs;
2191 bytes = min_t(size_t, len,
2192 (free->length - woffs));
2193 woffs = 0;
2194 } else {
2195 bytes = min_t(size_t, len, free->length);
2196 boffs = free->offset;
2197 }
2198 memcpy(chip->oob_poi + boffs, oob, bytes);
2199 oob += bytes;
2200 }
2201 return oob;
2202 }
2203 default:
2204 BUG();
2205 }
2206 return NULL;
2207 }
2208
2209 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2210
2211 /**
2212 * nand_do_write_ops - [INTERN] NAND write with ECC
2213 * @mtd: MTD device structure
2214 * @to: offset to write to
2215 * @ops: oob operations description structure
2216 *
2217 * NAND write with ECC.
2218 */
2219 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2220 struct mtd_oob_ops *ops)
2221 {
2222 int chipnr, realpage, page, blockmask, column;
2223 struct nand_chip *chip = mtd->priv;
2224 uint32_t writelen = ops->len;
2225
2226 uint32_t oobwritelen = ops->ooblen;
2227 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2228 mtd->oobavail : mtd->oobsize;
2229
2230 uint8_t *oob = ops->oobbuf;
2231 uint8_t *buf = ops->datbuf;
2232 int ret;
2233 int oob_required = oob ? 1 : 0;
2234
2235 ops->retlen = 0;
2236 if (!writelen)
2237 return 0;
2238
2239 /* Reject writes, which are not page aligned */
2240 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2241 pr_notice("%s: attempt to write non page aligned data\n",
2242 __func__);
2243 return -EINVAL;
2244 }
2245
2246 column = to & (mtd->writesize - 1);
2247
2248 chipnr = (int)(to >> chip->chip_shift);
2249 chip->select_chip(mtd, chipnr);
2250
2251 /* Check, if it is write protected */
2252 if (nand_check_wp(mtd)) {
2253 ret = -EIO;
2254 goto err_out;
2255 }
2256
2257 realpage = (int)(to >> chip->page_shift);
2258 page = realpage & chip->pagemask;
2259 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2260
2261 /* Invalidate the page cache, when we write to the cached page */
2262 if (to <= (chip->pagebuf << chip->page_shift) &&
2263 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2264 chip->pagebuf = -1;
2265
2266 /* Don't allow multipage oob writes with offset */
2267 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2268 ret = -EINVAL;
2269 goto err_out;
2270 }
2271
2272 while (1) {
2273 int bytes = mtd->writesize;
2274 int cached = writelen > bytes && page != blockmask;
2275 uint8_t *wbuf = buf;
2276
2277 /* Partial page write? */
2278 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2279 cached = 0;
2280 bytes = min_t(int, bytes - column, (int) writelen);
2281 chip->pagebuf = -1;
2282 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2283 memcpy(&chip->buffers->databuf[column], buf, bytes);
2284 wbuf = chip->buffers->databuf;
2285 }
2286
2287 if (unlikely(oob)) {
2288 size_t len = min(oobwritelen, oobmaxlen);
2289 oob = nand_fill_oob(mtd, oob, len, ops);
2290 oobwritelen -= len;
2291 } else {
2292 /* We still need to erase leftover OOB data */
2293 memset(chip->oob_poi, 0xff, mtd->oobsize);
2294 }
2295 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2296 oob_required, page, cached,
2297 (ops->mode == MTD_OPS_RAW));
2298 if (ret)
2299 break;
2300
2301 writelen -= bytes;
2302 if (!writelen)
2303 break;
2304
2305 column = 0;
2306 buf += bytes;
2307 realpage++;
2308
2309 page = realpage & chip->pagemask;
2310 /* Check, if we cross a chip boundary */
2311 if (!page) {
2312 chipnr++;
2313 chip->select_chip(mtd, -1);
2314 chip->select_chip(mtd, chipnr);
2315 }
2316 }
2317
2318 ops->retlen = ops->len - writelen;
2319 if (unlikely(oob))
2320 ops->oobretlen = ops->ooblen;
2321
2322 err_out:
2323 chip->select_chip(mtd, -1);
2324 return ret;
2325 }
2326
2327 /**
2328 * panic_nand_write - [MTD Interface] NAND write with ECC
2329 * @mtd: MTD device structure
2330 * @to: offset to write to
2331 * @len: number of bytes to write
2332 * @retlen: pointer to variable to store the number of written bytes
2333 * @buf: the data to write
2334 *
2335 * NAND write with ECC. Used when performing writes in interrupt context, this
2336 * may for example be called by mtdoops when writing an oops while in panic.
2337 */
2338 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2339 size_t *retlen, const uint8_t *buf)
2340 {
2341 struct nand_chip *chip = mtd->priv;
2342 struct mtd_oob_ops ops;
2343 int ret;
2344
2345 /* Wait for the device to get ready */
2346 panic_nand_wait(mtd, chip, 400);
2347
2348 /* Grab the device */
2349 panic_nand_get_device(chip, mtd, FL_WRITING);
2350
2351 ops.len = len;
2352 ops.datbuf = (uint8_t *)buf;
2353 ops.oobbuf = NULL;
2354 ops.mode = MTD_OPS_PLACE_OOB;
2355
2356 ret = nand_do_write_ops(mtd, to, &ops);
2357
2358 *retlen = ops.retlen;
2359 return ret;
2360 }
2361
2362 /**
2363 * nand_write - [MTD Interface] NAND write with ECC
2364 * @mtd: MTD device structure
2365 * @to: offset to write to
2366 * @len: number of bytes to write
2367 * @retlen: pointer to variable to store the number of written bytes
2368 * @buf: the data to write
2369 *
2370 * NAND write with ECC.
2371 */
2372 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2373 size_t *retlen, const uint8_t *buf)
2374 {
2375 struct mtd_oob_ops ops;
2376 int ret;
2377
2378 nand_get_device(mtd, FL_WRITING);
2379 ops.len = len;
2380 ops.datbuf = (uint8_t *)buf;
2381 ops.oobbuf = NULL;
2382 ops.mode = MTD_OPS_PLACE_OOB;
2383 ret = nand_do_write_ops(mtd, to, &ops);
2384 *retlen = ops.retlen;
2385 nand_release_device(mtd);
2386 return ret;
2387 }
2388
2389 /**
2390 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2391 * @mtd: MTD device structure
2392 * @to: offset to write to
2393 * @ops: oob operation description structure
2394 *
2395 * NAND write out-of-band.
2396 */
2397 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2398 struct mtd_oob_ops *ops)
2399 {
2400 int chipnr, page, status, len;
2401 struct nand_chip *chip = mtd->priv;
2402
2403 pr_debug("%s: to = 0x%08x, len = %i\n",
2404 __func__, (unsigned int)to, (int)ops->ooblen);
2405
2406 if (ops->mode == MTD_OPS_AUTO_OOB)
2407 len = chip->ecc.layout->oobavail;
2408 else
2409 len = mtd->oobsize;
2410
2411 /* Do not allow write past end of page */
2412 if ((ops->ooboffs + ops->ooblen) > len) {
2413 pr_debug("%s: attempt to write past end of page\n",
2414 __func__);
2415 return -EINVAL;
2416 }
2417
2418 if (unlikely(ops->ooboffs >= len)) {
2419 pr_debug("%s: attempt to start write outside oob\n",
2420 __func__);
2421 return -EINVAL;
2422 }
2423
2424 /* Do not allow write past end of device */
2425 if (unlikely(to >= mtd->size ||
2426 ops->ooboffs + ops->ooblen >
2427 ((mtd->size >> chip->page_shift) -
2428 (to >> chip->page_shift)) * len)) {
2429 pr_debug("%s: attempt to write beyond end of device\n",
2430 __func__);
2431 return -EINVAL;
2432 }
2433
2434 chipnr = (int)(to >> chip->chip_shift);
2435 chip->select_chip(mtd, chipnr);
2436
2437 /* Shift to get page */
2438 page = (int)(to >> chip->page_shift);
2439
2440 /*
2441 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2442 * of my DiskOnChip 2000 test units) will clear the whole data page too
2443 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2444 * it in the doc2000 driver in August 1999. dwmw2.
2445 */
2446 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2447
2448 /* Check, if it is write protected */
2449 if (nand_check_wp(mtd)) {
2450 chip->select_chip(mtd, -1);
2451 return -EROFS;
2452 }
2453
2454 /* Invalidate the page cache, if we write to the cached page */
2455 if (page == chip->pagebuf)
2456 chip->pagebuf = -1;
2457
2458 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2459
2460 if (ops->mode == MTD_OPS_RAW)
2461 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2462 else
2463 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2464
2465 chip->select_chip(mtd, -1);
2466
2467 if (status)
2468 return status;
2469
2470 ops->oobretlen = ops->ooblen;
2471
2472 return 0;
2473 }
2474
2475 /**
2476 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2477 * @mtd: MTD device structure
2478 * @to: offset to write to
2479 * @ops: oob operation description structure
2480 */
2481 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2482 struct mtd_oob_ops *ops)
2483 {
2484 int ret = -ENOTSUPP;
2485
2486 ops->retlen = 0;
2487
2488 /* Do not allow writes past end of device */
2489 if (ops->datbuf && (to + ops->len) > mtd->size) {
2490 pr_debug("%s: attempt to write beyond end of device\n",
2491 __func__);
2492 return -EINVAL;
2493 }
2494
2495 nand_get_device(mtd, FL_WRITING);
2496
2497 switch (ops->mode) {
2498 case MTD_OPS_PLACE_OOB:
2499 case MTD_OPS_AUTO_OOB:
2500 case MTD_OPS_RAW:
2501 break;
2502
2503 default:
2504 goto out;
2505 }
2506
2507 if (!ops->datbuf)
2508 ret = nand_do_write_oob(mtd, to, ops);
2509 else
2510 ret = nand_do_write_ops(mtd, to, ops);
2511
2512 out:
2513 nand_release_device(mtd);
2514 return ret;
2515 }
2516
2517 /**
2518 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2519 * @mtd: MTD device structure
2520 * @page: the page address of the block which will be erased
2521 *
2522 * Standard erase command for NAND chips.
2523 */
2524 static void single_erase_cmd(struct mtd_info *mtd, int page)
2525 {
2526 struct nand_chip *chip = mtd->priv;
2527 /* Send commands to erase a block */
2528 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2529 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2530 }
2531
2532 /**
2533 * nand_erase - [MTD Interface] erase block(s)
2534 * @mtd: MTD device structure
2535 * @instr: erase instruction
2536 *
2537 * Erase one ore more blocks.
2538 */
2539 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2540 {
2541 return nand_erase_nand(mtd, instr, 0);
2542 }
2543
2544 /**
2545 * nand_erase_nand - [INTERN] erase block(s)
2546 * @mtd: MTD device structure
2547 * @instr: erase instruction
2548 * @allowbbt: allow erasing the bbt area
2549 *
2550 * Erase one ore more blocks.
2551 */
2552 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2553 int allowbbt)
2554 {
2555 int page, status, pages_per_block, ret, chipnr;
2556 struct nand_chip *chip = mtd->priv;
2557 loff_t len;
2558
2559 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2560 __func__, (unsigned long long)instr->addr,
2561 (unsigned long long)instr->len);
2562
2563 if (check_offs_len(mtd, instr->addr, instr->len))
2564 return -EINVAL;
2565
2566 /* Grab the lock and see if the device is available */
2567 nand_get_device(mtd, FL_ERASING);
2568
2569 /* Shift to get first page */
2570 page = (int)(instr->addr >> chip->page_shift);
2571 chipnr = (int)(instr->addr >> chip->chip_shift);
2572
2573 /* Calculate pages in each block */
2574 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2575
2576 /* Select the NAND device */
2577 chip->select_chip(mtd, chipnr);
2578
2579 /* Check, if it is write protected */
2580 if (nand_check_wp(mtd)) {
2581 pr_debug("%s: device is write protected!\n",
2582 __func__);
2583 instr->state = MTD_ERASE_FAILED;
2584 goto erase_exit;
2585 }
2586
2587 /* Loop through the pages */
2588 len = instr->len;
2589
2590 instr->state = MTD_ERASING;
2591
2592 while (len) {
2593 /* Check if we have a bad block, we do not erase bad blocks! */
2594 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2595 chip->page_shift, 0, allowbbt)) {
2596 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2597 __func__, page);
2598 instr->state = MTD_ERASE_FAILED;
2599 goto erase_exit;
2600 }
2601
2602 /*
2603 * Invalidate the page cache, if we erase the block which
2604 * contains the current cached page.
2605 */
2606 if (page <= chip->pagebuf && chip->pagebuf <
2607 (page + pages_per_block))
2608 chip->pagebuf = -1;
2609
2610 chip->erase_cmd(mtd, page & chip->pagemask);
2611
2612 status = chip->waitfunc(mtd, chip);
2613
2614 /*
2615 * See if operation failed and additional status checks are
2616 * available
2617 */
2618 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2619 status = chip->errstat(mtd, chip, FL_ERASING,
2620 status, page);
2621
2622 /* See if block erase succeeded */
2623 if (status & NAND_STATUS_FAIL) {
2624 pr_debug("%s: failed erase, page 0x%08x\n",
2625 __func__, page);
2626 instr->state = MTD_ERASE_FAILED;
2627 instr->fail_addr =
2628 ((loff_t)page << chip->page_shift);
2629 goto erase_exit;
2630 }
2631
2632 /* Increment page address and decrement length */
2633 len -= (1 << chip->phys_erase_shift);
2634 page += pages_per_block;
2635
2636 /* Check, if we cross a chip boundary */
2637 if (len && !(page & chip->pagemask)) {
2638 chipnr++;
2639 chip->select_chip(mtd, -1);
2640 chip->select_chip(mtd, chipnr);
2641 }
2642 }
2643 instr->state = MTD_ERASE_DONE;
2644
2645 erase_exit:
2646
2647 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2648
2649 /* Deselect and wake up anyone waiting on the device */
2650 chip->select_chip(mtd, -1);
2651 nand_release_device(mtd);
2652
2653 /* Do call back function */
2654 if (!ret)
2655 mtd_erase_callback(instr);
2656
2657 /* Return more or less happy */
2658 return ret;
2659 }
2660
2661 /**
2662 * nand_sync - [MTD Interface] sync
2663 * @mtd: MTD device structure
2664 *
2665 * Sync is actually a wait for chip ready function.
2666 */
2667 static void nand_sync(struct mtd_info *mtd)
2668 {
2669 pr_debug("%s: called\n", __func__);
2670
2671 /* Grab the lock and see if the device is available */
2672 nand_get_device(mtd, FL_SYNCING);
2673 /* Release it and go back */
2674 nand_release_device(mtd);
2675 }
2676
2677 /**
2678 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2679 * @mtd: MTD device structure
2680 * @offs: offset relative to mtd start
2681 */
2682 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2683 {
2684 return nand_block_checkbad(mtd, offs, 1, 0);
2685 }
2686
2687 /**
2688 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2689 * @mtd: MTD device structure
2690 * @ofs: offset relative to mtd start
2691 */
2692 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2693 {
2694 int ret;
2695
2696 ret = nand_block_isbad(mtd, ofs);
2697 if (ret) {
2698 /* If it was bad already, return success and do nothing */
2699 if (ret > 0)
2700 return 0;
2701 return ret;
2702 }
2703
2704 return nand_block_markbad_lowlevel(mtd, ofs);
2705 }
2706
2707 /**
2708 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2709 * @mtd: MTD device structure
2710 * @chip: nand chip info structure
2711 * @addr: feature address.
2712 * @subfeature_param: the subfeature parameters, a four bytes array.
2713 */
2714 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2715 int addr, uint8_t *subfeature_param)
2716 {
2717 int status;
2718
2719 if (!chip->onfi_version ||
2720 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2721 & ONFI_OPT_CMD_SET_GET_FEATURES))
2722 return -EINVAL;
2723
2724 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2725 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2726 status = chip->waitfunc(mtd, chip);
2727 if (status & NAND_STATUS_FAIL)
2728 return -EIO;
2729 return 0;
2730 }
2731
2732 /**
2733 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2734 * @mtd: MTD device structure
2735 * @chip: nand chip info structure
2736 * @addr: feature address.
2737 * @subfeature_param: the subfeature parameters, a four bytes array.
2738 */
2739 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2740 int addr, uint8_t *subfeature_param)
2741 {
2742 if (!chip->onfi_version ||
2743 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2744 & ONFI_OPT_CMD_SET_GET_FEATURES))
2745 return -EINVAL;
2746
2747 /* clear the sub feature parameters */
2748 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2749
2750 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2751 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2752 return 0;
2753 }
2754
2755 /**
2756 * nand_suspend - [MTD Interface] Suspend the NAND flash
2757 * @mtd: MTD device structure
2758 */
2759 static int nand_suspend(struct mtd_info *mtd)
2760 {
2761 return nand_get_device(mtd, FL_PM_SUSPENDED);
2762 }
2763
2764 /**
2765 * nand_resume - [MTD Interface] Resume the NAND flash
2766 * @mtd: MTD device structure
2767 */
2768 static void nand_resume(struct mtd_info *mtd)
2769 {
2770 struct nand_chip *chip = mtd->priv;
2771
2772 if (chip->state == FL_PM_SUSPENDED)
2773 nand_release_device(mtd);
2774 else
2775 pr_err("%s called for a chip which is not in suspended state\n",
2776 __func__);
2777 }
2778
2779 /* Set default functions */
2780 static void nand_set_defaults(struct nand_chip *chip, int busw)
2781 {
2782 /* check for proper chip_delay setup, set 20us if not */
2783 if (!chip->chip_delay)
2784 chip->chip_delay = 20;
2785
2786 /* check, if a user supplied command function given */
2787 if (chip->cmdfunc == NULL)
2788 chip->cmdfunc = nand_command;
2789
2790 /* check, if a user supplied wait function given */
2791 if (chip->waitfunc == NULL)
2792 chip->waitfunc = nand_wait;
2793
2794 if (!chip->select_chip)
2795 chip->select_chip = nand_select_chip;
2796
2797 /* If called twice, pointers that depend on busw may need to be reset */
2798 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2799 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2800 if (!chip->read_word)
2801 chip->read_word = nand_read_word;
2802 if (!chip->block_bad)
2803 chip->block_bad = nand_block_bad;
2804 if (!chip->block_markbad)
2805 chip->block_markbad = nand_default_block_markbad;
2806 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2807 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2808 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2809 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2810 if (!chip->scan_bbt)
2811 chip->scan_bbt = nand_default_bbt;
2812
2813 if (!chip->controller) {
2814 chip->controller = &chip->hwcontrol;
2815 spin_lock_init(&chip->controller->lock);
2816 init_waitqueue_head(&chip->controller->wq);
2817 }
2818
2819 }
2820
2821 /* Sanitize ONFI strings so we can safely print them */
2822 static void sanitize_string(uint8_t *s, size_t len)
2823 {
2824 ssize_t i;
2825
2826 /* Null terminate */
2827 s[len - 1] = 0;
2828
2829 /* Remove non printable chars */
2830 for (i = 0; i < len - 1; i++) {
2831 if (s[i] < ' ' || s[i] > 127)
2832 s[i] = '?';
2833 }
2834
2835 /* Remove trailing spaces */
2836 strim(s);
2837 }
2838
2839 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2840 {
2841 int i;
2842 while (len--) {
2843 crc ^= *p++ << 8;
2844 for (i = 0; i < 8; i++)
2845 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2846 }
2847
2848 return crc;
2849 }
2850
2851 /* Parse the Extended Parameter Page. */
2852 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2853 struct nand_chip *chip, struct nand_onfi_params *p)
2854 {
2855 struct onfi_ext_param_page *ep;
2856 struct onfi_ext_section *s;
2857 struct onfi_ext_ecc_info *ecc;
2858 uint8_t *cursor;
2859 int ret = -EINVAL;
2860 int len;
2861 int i;
2862
2863 len = le16_to_cpu(p->ext_param_page_length) * 16;
2864 ep = kmalloc(len, GFP_KERNEL);
2865 if (!ep) {
2866 ret = -ENOMEM;
2867 goto ext_out;
2868 }
2869
2870 /* Send our own NAND_CMD_PARAM. */
2871 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2872
2873 /* Use the Change Read Column command to skip the ONFI param pages. */
2874 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2875 sizeof(*p) * p->num_of_param_pages , -1);
2876
2877 /* Read out the Extended Parameter Page. */
2878 chip->read_buf(mtd, (uint8_t *)ep, len);
2879 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2880 != le16_to_cpu(ep->crc))) {
2881 pr_debug("fail in the CRC.\n");
2882 goto ext_out;
2883 }
2884
2885 /*
2886 * Check the signature.
2887 * Do not strictly follow the ONFI spec, maybe changed in future.
2888 */
2889 if (strncmp(ep->sig, "EPPS", 4)) {
2890 pr_debug("The signature is invalid.\n");
2891 goto ext_out;
2892 }
2893
2894 /* find the ECC section. */
2895 cursor = (uint8_t *)(ep + 1);
2896 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
2897 s = ep->sections + i;
2898 if (s->type == ONFI_SECTION_TYPE_2)
2899 break;
2900 cursor += s->length * 16;
2901 }
2902 if (i == ONFI_EXT_SECTION_MAX) {
2903 pr_debug("We can not find the ECC section.\n");
2904 goto ext_out;
2905 }
2906
2907 /* get the info we want. */
2908 ecc = (struct onfi_ext_ecc_info *)cursor;
2909
2910 if (ecc->codeword_size) {
2911 chip->ecc_strength_ds = ecc->ecc_bits;
2912 chip->ecc_step_ds = 1 << ecc->codeword_size;
2913 }
2914
2915 pr_info("ONFI extended param page detected.\n");
2916 return 0;
2917
2918 ext_out:
2919 kfree(ep);
2920 return ret;
2921 }
2922
2923 /*
2924 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2925 */
2926 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2927 int *busw)
2928 {
2929 struct nand_onfi_params *p = &chip->onfi_params;
2930 int i;
2931 int val;
2932
2933 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2934 if (chip->options & NAND_BUSWIDTH_16) {
2935 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2936 return 0;
2937 }
2938 /* Try ONFI for unknown chip or LP */
2939 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2940 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2941 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2942 return 0;
2943
2944 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2945 for (i = 0; i < 3; i++) {
2946 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2947 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2948 le16_to_cpu(p->crc)) {
2949 pr_info("ONFI param page %d valid\n", i);
2950 break;
2951 }
2952 }
2953
2954 if (i == 3)
2955 return 0;
2956
2957 /* Check version */
2958 val = le16_to_cpu(p->revision);
2959 if (val & (1 << 5))
2960 chip->onfi_version = 23;
2961 else if (val & (1 << 4))
2962 chip->onfi_version = 22;
2963 else if (val & (1 << 3))
2964 chip->onfi_version = 21;
2965 else if (val & (1 << 2))
2966 chip->onfi_version = 20;
2967 else if (val & (1 << 1))
2968 chip->onfi_version = 10;
2969
2970 if (!chip->onfi_version) {
2971 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2972 return 0;
2973 }
2974
2975 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2976 sanitize_string(p->model, sizeof(p->model));
2977 if (!mtd->name)
2978 mtd->name = p->model;
2979 mtd->writesize = le32_to_cpu(p->byte_per_page);
2980 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2981 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2982 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2983 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2984
2985 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
2986 *busw = NAND_BUSWIDTH_16;
2987 else
2988 *busw = 0;
2989
2990 if (p->ecc_bits != 0xff) {
2991 chip->ecc_strength_ds = p->ecc_bits;
2992 chip->ecc_step_ds = 512;
2993 } else if (chip->onfi_version >= 21 &&
2994 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
2995
2996 /*
2997 * The nand_flash_detect_ext_param_page() uses the
2998 * Change Read Column command which maybe not supported
2999 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3000 * now. We do not replace user supplied command function.
3001 */
3002 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3003 chip->cmdfunc = nand_command_lp;
3004
3005 /* The Extended Parameter Page is supported since ONFI 2.1. */
3006 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3007 pr_info("Failed to detect the extended param page.\n");
3008 }
3009
3010 pr_info("ONFI flash detected\n");
3011 return 1;
3012 }
3013
3014 /*
3015 * nand_id_has_period - Check if an ID string has a given wraparound period
3016 * @id_data: the ID string
3017 * @arrlen: the length of the @id_data array
3018 * @period: the period of repitition
3019 *
3020 * Check if an ID string is repeated within a given sequence of bytes at
3021 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3022 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3023 * if the repetition has a period of @period; otherwise, returns zero.
3024 */
3025 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3026 {
3027 int i, j;
3028 for (i = 0; i < period; i++)
3029 for (j = i + period; j < arrlen; j += period)
3030 if (id_data[i] != id_data[j])
3031 return 0;
3032 return 1;
3033 }
3034
3035 /*
3036 * nand_id_len - Get the length of an ID string returned by CMD_READID
3037 * @id_data: the ID string
3038 * @arrlen: the length of the @id_data array
3039
3040 * Returns the length of the ID string, according to known wraparound/trailing
3041 * zero patterns. If no pattern exists, returns the length of the array.
3042 */
3043 static int nand_id_len(u8 *id_data, int arrlen)
3044 {
3045 int last_nonzero, period;
3046
3047 /* Find last non-zero byte */
3048 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3049 if (id_data[last_nonzero])
3050 break;
3051
3052 /* All zeros */
3053 if (last_nonzero < 0)
3054 return 0;
3055
3056 /* Calculate wraparound period */
3057 for (period = 1; period < arrlen; period++)
3058 if (nand_id_has_period(id_data, arrlen, period))
3059 break;
3060
3061 /* There's a repeated pattern */
3062 if (period < arrlen)
3063 return period;
3064
3065 /* There are trailing zeros */
3066 if (last_nonzero < arrlen - 1)
3067 return last_nonzero + 1;
3068
3069 /* No pattern detected */
3070 return arrlen;
3071 }
3072
3073 /*
3074 * Many new NAND share similar device ID codes, which represent the size of the
3075 * chip. The rest of the parameters must be decoded according to generic or
3076 * manufacturer-specific "extended ID" decoding patterns.
3077 */
3078 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3079 u8 id_data[8], int *busw)
3080 {
3081 int extid, id_len;
3082 /* The 3rd id byte holds MLC / multichip data */
3083 chip->cellinfo = id_data[2];
3084 /* The 4th id byte is the important one */
3085 extid = id_data[3];
3086
3087 id_len = nand_id_len(id_data, 8);
3088
3089 /*
3090 * Field definitions are in the following datasheets:
3091 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3092 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3093 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3094 *
3095 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3096 * ID to decide what to do.
3097 */
3098 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3099 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3100 id_data[5] != 0x00) {
3101 /* Calc pagesize */
3102 mtd->writesize = 2048 << (extid & 0x03);
3103 extid >>= 2;
3104 /* Calc oobsize */
3105 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3106 case 1:
3107 mtd->oobsize = 128;
3108 break;
3109 case 2:
3110 mtd->oobsize = 218;
3111 break;
3112 case 3:
3113 mtd->oobsize = 400;
3114 break;
3115 case 4:
3116 mtd->oobsize = 436;
3117 break;
3118 case 5:
3119 mtd->oobsize = 512;
3120 break;
3121 case 6:
3122 default: /* Other cases are "reserved" (unknown) */
3123 mtd->oobsize = 640;
3124 break;
3125 }
3126 extid >>= 2;
3127 /* Calc blocksize */
3128 mtd->erasesize = (128 * 1024) <<
3129 (((extid >> 1) & 0x04) | (extid & 0x03));
3130 *busw = 0;
3131 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3132 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3133 unsigned int tmp;
3134
3135 /* Calc pagesize */
3136 mtd->writesize = 2048 << (extid & 0x03);
3137 extid >>= 2;
3138 /* Calc oobsize */
3139 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3140 case 0:
3141 mtd->oobsize = 128;
3142 break;
3143 case 1:
3144 mtd->oobsize = 224;
3145 break;
3146 case 2:
3147 mtd->oobsize = 448;
3148 break;
3149 case 3:
3150 mtd->oobsize = 64;
3151 break;
3152 case 4:
3153 mtd->oobsize = 32;
3154 break;
3155 case 5:
3156 mtd->oobsize = 16;
3157 break;
3158 default:
3159 mtd->oobsize = 640;
3160 break;
3161 }
3162 extid >>= 2;
3163 /* Calc blocksize */
3164 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3165 if (tmp < 0x03)
3166 mtd->erasesize = (128 * 1024) << tmp;
3167 else if (tmp == 0x03)
3168 mtd->erasesize = 768 * 1024;
3169 else
3170 mtd->erasesize = (64 * 1024) << tmp;
3171 *busw = 0;
3172 } else {
3173 /* Calc pagesize */
3174 mtd->writesize = 1024 << (extid & 0x03);
3175 extid >>= 2;
3176 /* Calc oobsize */
3177 mtd->oobsize = (8 << (extid & 0x01)) *
3178 (mtd->writesize >> 9);
3179 extid >>= 2;
3180 /* Calc blocksize. Blocksize is multiples of 64KiB */
3181 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3182 extid >>= 2;
3183 /* Get buswidth information */
3184 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3185
3186 /*
3187 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3188 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3189 * follows:
3190 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3191 * 110b -> 24nm
3192 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3193 */
3194 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3195 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3196 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3197 !(id_data[4] & 0x80) /* !BENAND */) {
3198 mtd->oobsize = 32 * mtd->writesize >> 9;
3199 }
3200
3201 }
3202 }
3203
3204 /*
3205 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3206 * decodes a matching ID table entry and assigns the MTD size parameters for
3207 * the chip.
3208 */
3209 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3210 struct nand_flash_dev *type, u8 id_data[8],
3211 int *busw)
3212 {
3213 int maf_id = id_data[0];
3214
3215 mtd->erasesize = type->erasesize;
3216 mtd->writesize = type->pagesize;
3217 mtd->oobsize = mtd->writesize / 32;
3218 *busw = type->options & NAND_BUSWIDTH_16;
3219
3220 /*
3221 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3222 * some Spansion chips have erasesize that conflicts with size
3223 * listed in nand_ids table.
3224 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3225 */
3226 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3227 && id_data[6] == 0x00 && id_data[7] == 0x00
3228 && mtd->writesize == 512) {
3229 mtd->erasesize = 128 * 1024;
3230 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3231 }
3232 }
3233
3234 /*
3235 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3236 * heuristic patterns using various detected parameters (e.g., manufacturer,
3237 * page size, cell-type information).
3238 */
3239 static void nand_decode_bbm_options(struct mtd_info *mtd,
3240 struct nand_chip *chip, u8 id_data[8])
3241 {
3242 int maf_id = id_data[0];
3243
3244 /* Set the bad block position */
3245 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3246 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3247 else
3248 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3249
3250 /*
3251 * Bad block marker is stored in the last page of each block on Samsung
3252 * and Hynix MLC devices; stored in first two pages of each block on
3253 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3254 * AMD/Spansion, and Macronix. All others scan only the first page.
3255 */
3256 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3257 (maf_id == NAND_MFR_SAMSUNG ||
3258 maf_id == NAND_MFR_HYNIX))
3259 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3260 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3261 (maf_id == NAND_MFR_SAMSUNG ||
3262 maf_id == NAND_MFR_HYNIX ||
3263 maf_id == NAND_MFR_TOSHIBA ||
3264 maf_id == NAND_MFR_AMD ||
3265 maf_id == NAND_MFR_MACRONIX)) ||
3266 (mtd->writesize == 2048 &&
3267 maf_id == NAND_MFR_MICRON))
3268 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3269 }
3270
3271 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3272 {
3273 return type->id_len;
3274 }
3275
3276 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3277 struct nand_flash_dev *type, u8 *id_data, int *busw)
3278 {
3279 if (!strncmp(type->id, id_data, type->id_len)) {
3280 mtd->writesize = type->pagesize;
3281 mtd->erasesize = type->erasesize;
3282 mtd->oobsize = type->oobsize;
3283
3284 chip->cellinfo = id_data[2];
3285 chip->chipsize = (uint64_t)type->chipsize << 20;
3286 chip->options |= type->options;
3287
3288 *busw = type->options & NAND_BUSWIDTH_16;
3289
3290 return true;
3291 }
3292 return false;
3293 }
3294
3295 /*
3296 * Get the flash and manufacturer id and lookup if the type is supported.
3297 */
3298 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3299 struct nand_chip *chip,
3300 int busw,
3301 int *maf_id, int *dev_id,
3302 struct nand_flash_dev *type)
3303 {
3304 int i, maf_idx;
3305 u8 id_data[8];
3306
3307 /* Select the device */
3308 chip->select_chip(mtd, 0);
3309
3310 /*
3311 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3312 * after power-up.
3313 */
3314 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3315
3316 /* Send the command for reading device ID */
3317 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3318
3319 /* Read manufacturer and device IDs */
3320 *maf_id = chip->read_byte(mtd);
3321 *dev_id = chip->read_byte(mtd);
3322
3323 /*
3324 * Try again to make sure, as some systems the bus-hold or other
3325 * interface concerns can cause random data which looks like a
3326 * possibly credible NAND flash to appear. If the two results do
3327 * not match, ignore the device completely.
3328 */
3329
3330 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3331
3332 /* Read entire ID string */
3333 for (i = 0; i < 8; i++)
3334 id_data[i] = chip->read_byte(mtd);
3335
3336 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3337 pr_info("%s: second ID read did not match "
3338 "%02x,%02x against %02x,%02x\n", __func__,
3339 *maf_id, *dev_id, id_data[0], id_data[1]);
3340 return ERR_PTR(-ENODEV);
3341 }
3342
3343 if (!type)
3344 type = nand_flash_ids;
3345
3346 for (; type->name != NULL; type++) {
3347 if (is_full_id_nand(type)) {
3348 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3349 goto ident_done;
3350 } else if (*dev_id == type->dev_id) {
3351 break;
3352 }
3353 }
3354
3355 chip->onfi_version = 0;
3356 if (!type->name || !type->pagesize) {
3357 /* Check is chip is ONFI compliant */
3358 if (nand_flash_detect_onfi(mtd, chip, &busw))
3359 goto ident_done;
3360 }
3361
3362 if (!type->name)
3363 return ERR_PTR(-ENODEV);
3364
3365 if (!mtd->name)
3366 mtd->name = type->name;
3367
3368 chip->chipsize = (uint64_t)type->chipsize << 20;
3369
3370 if (!type->pagesize && chip->init_size) {
3371 /* Set the pagesize, oobsize, erasesize by the driver */
3372 busw = chip->init_size(mtd, chip, id_data);
3373 } else if (!type->pagesize) {
3374 /* Decode parameters from extended ID */
3375 nand_decode_ext_id(mtd, chip, id_data, &busw);
3376 } else {
3377 nand_decode_id(mtd, chip, type, id_data, &busw);
3378 }
3379 /* Get chip options */
3380 chip->options |= type->options;
3381
3382 /*
3383 * Check if chip is not a Samsung device. Do not clear the
3384 * options for chips which do not have an extended id.
3385 */
3386 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3387 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3388 ident_done:
3389
3390 /* Try to identify manufacturer */
3391 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3392 if (nand_manuf_ids[maf_idx].id == *maf_id)
3393 break;
3394 }
3395
3396 if (chip->options & NAND_BUSWIDTH_AUTO) {
3397 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3398 chip->options |= busw;
3399 nand_set_defaults(chip, busw);
3400 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3401 /*
3402 * Check, if buswidth is correct. Hardware drivers should set
3403 * chip correct!
3404 */
3405 pr_info("NAND device: Manufacturer ID:"
3406 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3407 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3408 pr_warn("NAND bus width %d instead %d bit\n",
3409 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3410 busw ? 16 : 8);
3411 return ERR_PTR(-EINVAL);
3412 }
3413
3414 nand_decode_bbm_options(mtd, chip, id_data);
3415
3416 /* Calculate the address shift from the page size */
3417 chip->page_shift = ffs(mtd->writesize) - 1;
3418 /* Convert chipsize to number of pages per chip -1 */
3419 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3420
3421 chip->bbt_erase_shift = chip->phys_erase_shift =
3422 ffs(mtd->erasesize) - 1;
3423 if (chip->chipsize & 0xffffffff)
3424 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3425 else {
3426 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3427 chip->chip_shift += 32 - 1;
3428 }
3429
3430 chip->badblockbits = 8;
3431 chip->erase_cmd = single_erase_cmd;
3432
3433 /* Do not replace user supplied command function! */
3434 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3435 chip->cmdfunc = nand_command_lp;
3436
3437 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3438 " %dMiB, page size: %d, OOB size: %d\n",
3439 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3440 chip->onfi_version ? chip->onfi_params.model : type->name,
3441 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3442
3443 return type;
3444 }
3445
3446 /**
3447 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3448 * @mtd: MTD device structure
3449 * @maxchips: number of chips to scan for
3450 * @table: alternative NAND ID table
3451 *
3452 * This is the first phase of the normal nand_scan() function. It reads the
3453 * flash ID and sets up MTD fields accordingly.
3454 *
3455 * The mtd->owner field must be set to the module of the caller.
3456 */
3457 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3458 struct nand_flash_dev *table)
3459 {
3460 int i, busw, nand_maf_id, nand_dev_id;
3461 struct nand_chip *chip = mtd->priv;
3462 struct nand_flash_dev *type;
3463
3464 /* Get buswidth to select the correct functions */
3465 busw = chip->options & NAND_BUSWIDTH_16;
3466 /* Set the default functions */
3467 nand_set_defaults(chip, busw);
3468
3469 /* Read the flash type */
3470 type = nand_get_flash_type(mtd, chip, busw,
3471 &nand_maf_id, &nand_dev_id, table);
3472
3473 if (IS_ERR(type)) {
3474 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3475 pr_warn("No NAND device found\n");
3476 chip->select_chip(mtd, -1);
3477 return PTR_ERR(type);
3478 }
3479
3480 chip->select_chip(mtd, -1);
3481
3482 /* Check for a chip array */
3483 for (i = 1; i < maxchips; i++) {
3484 chip->select_chip(mtd, i);
3485 /* See comment in nand_get_flash_type for reset */
3486 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3487 /* Send the command for reading device ID */
3488 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3489 /* Read manufacturer and device IDs */
3490 if (nand_maf_id != chip->read_byte(mtd) ||
3491 nand_dev_id != chip->read_byte(mtd)) {
3492 chip->select_chip(mtd, -1);
3493 break;
3494 }
3495 chip->select_chip(mtd, -1);
3496 }
3497 if (i > 1)
3498 pr_info("%d NAND chips detected\n", i);
3499
3500 /* Store the number of chips and calc total size for mtd */
3501 chip->numchips = i;
3502 mtd->size = i * chip->chipsize;
3503
3504 return 0;
3505 }
3506 EXPORT_SYMBOL(nand_scan_ident);
3507
3508
3509 /**
3510 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3511 * @mtd: MTD device structure
3512 *
3513 * This is the second phase of the normal nand_scan() function. It fills out
3514 * all the uninitialized function pointers with the defaults and scans for a
3515 * bad block table if appropriate.
3516 */
3517 int nand_scan_tail(struct mtd_info *mtd)
3518 {
3519 int i;
3520 struct nand_chip *chip = mtd->priv;
3521
3522 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3523 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3524 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3525
3526 if (!(chip->options & NAND_OWN_BUFFERS))
3527 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3528 if (!chip->buffers)
3529 return -ENOMEM;
3530
3531 /* Set the internal oob buffer location, just after the page data */
3532 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3533
3534 /*
3535 * If no default placement scheme is given, select an appropriate one.
3536 */
3537 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3538 switch (mtd->oobsize) {
3539 case 8:
3540 chip->ecc.layout = &nand_oob_8;
3541 break;
3542 case 16:
3543 chip->ecc.layout = &nand_oob_16;
3544 break;
3545 case 64:
3546 chip->ecc.layout = &nand_oob_64;
3547 break;
3548 case 128:
3549 chip->ecc.layout = &nand_oob_128;
3550 break;
3551 default:
3552 pr_warn("No oob scheme defined for oobsize %d\n",
3553 mtd->oobsize);
3554 BUG();
3555 }
3556 }
3557
3558 if (!chip->write_page)
3559 chip->write_page = nand_write_page;
3560
3561 /* set for ONFI nand */
3562 if (!chip->onfi_set_features)
3563 chip->onfi_set_features = nand_onfi_set_features;
3564 if (!chip->onfi_get_features)
3565 chip->onfi_get_features = nand_onfi_get_features;
3566
3567 /*
3568 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3569 * selected and we have 256 byte pagesize fallback to software ECC
3570 */
3571
3572 switch (chip->ecc.mode) {
3573 case NAND_ECC_HW_OOB_FIRST:
3574 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3575 if (!chip->ecc.calculate || !chip->ecc.correct ||
3576 !chip->ecc.hwctl) {
3577 pr_warn("No ECC functions supplied; "
3578 "hardware ECC not possible\n");
3579 BUG();
3580 }
3581 if (!chip->ecc.read_page)
3582 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3583
3584 case NAND_ECC_HW:
3585 /* Use standard hwecc read page function? */
3586 if (!chip->ecc.read_page)
3587 chip->ecc.read_page = nand_read_page_hwecc;
3588 if (!chip->ecc.write_page)
3589 chip->ecc.write_page = nand_write_page_hwecc;
3590 if (!chip->ecc.read_page_raw)
3591 chip->ecc.read_page_raw = nand_read_page_raw;
3592 if (!chip->ecc.write_page_raw)
3593 chip->ecc.write_page_raw = nand_write_page_raw;
3594 if (!chip->ecc.read_oob)
3595 chip->ecc.read_oob = nand_read_oob_std;
3596 if (!chip->ecc.write_oob)
3597 chip->ecc.write_oob = nand_write_oob_std;
3598 if (!chip->ecc.read_subpage)
3599 chip->ecc.read_subpage = nand_read_subpage;
3600 if (!chip->ecc.write_subpage)
3601 chip->ecc.write_subpage = nand_write_subpage_hwecc;
3602
3603 case NAND_ECC_HW_SYNDROME:
3604 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3605 !chip->ecc.hwctl) &&
3606 (!chip->ecc.read_page ||
3607 chip->ecc.read_page == nand_read_page_hwecc ||
3608 !chip->ecc.write_page ||
3609 chip->ecc.write_page == nand_write_page_hwecc)) {
3610 pr_warn("No ECC functions supplied; "
3611 "hardware ECC not possible\n");
3612 BUG();
3613 }
3614 /* Use standard syndrome read/write page function? */
3615 if (!chip->ecc.read_page)
3616 chip->ecc.read_page = nand_read_page_syndrome;
3617 if (!chip->ecc.write_page)
3618 chip->ecc.write_page = nand_write_page_syndrome;
3619 if (!chip->ecc.read_page_raw)
3620 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3621 if (!chip->ecc.write_page_raw)
3622 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3623 if (!chip->ecc.read_oob)
3624 chip->ecc.read_oob = nand_read_oob_syndrome;
3625 if (!chip->ecc.write_oob)
3626 chip->ecc.write_oob = nand_write_oob_syndrome;
3627
3628 if (mtd->writesize >= chip->ecc.size) {
3629 if (!chip->ecc.strength) {
3630 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3631 BUG();
3632 }
3633 break;
3634 }
3635 pr_warn("%d byte HW ECC not possible on "
3636 "%d byte page size, fallback to SW ECC\n",
3637 chip->ecc.size, mtd->writesize);
3638 chip->ecc.mode = NAND_ECC_SOFT;
3639
3640 case NAND_ECC_SOFT:
3641 chip->ecc.calculate = nand_calculate_ecc;
3642 chip->ecc.correct = nand_correct_data;
3643 chip->ecc.read_page = nand_read_page_swecc;
3644 chip->ecc.read_subpage = nand_read_subpage;
3645 chip->ecc.write_page = nand_write_page_swecc;
3646 chip->ecc.read_page_raw = nand_read_page_raw;
3647 chip->ecc.write_page_raw = nand_write_page_raw;
3648 chip->ecc.read_oob = nand_read_oob_std;
3649 chip->ecc.write_oob = nand_write_oob_std;
3650 if (!chip->ecc.size)
3651 chip->ecc.size = 256;
3652 chip->ecc.bytes = 3;
3653 chip->ecc.strength = 1;
3654 break;
3655
3656 case NAND_ECC_SOFT_BCH:
3657 if (!mtd_nand_has_bch()) {
3658 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3659 BUG();
3660 }
3661 chip->ecc.calculate = nand_bch_calculate_ecc;
3662 chip->ecc.correct = nand_bch_correct_data;
3663 chip->ecc.read_page = nand_read_page_swecc;
3664 chip->ecc.read_subpage = nand_read_subpage;
3665 chip->ecc.write_page = nand_write_page_swecc;
3666 chip->ecc.read_page_raw = nand_read_page_raw;
3667 chip->ecc.write_page_raw = nand_write_page_raw;
3668 chip->ecc.read_oob = nand_read_oob_std;
3669 chip->ecc.write_oob = nand_write_oob_std;
3670 /*
3671 * Board driver should supply ecc.size and ecc.bytes values to
3672 * select how many bits are correctable; see nand_bch_init()
3673 * for details. Otherwise, default to 4 bits for large page
3674 * devices.
3675 */
3676 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3677 chip->ecc.size = 512;
3678 chip->ecc.bytes = 7;
3679 }
3680 chip->ecc.priv = nand_bch_init(mtd,
3681 chip->ecc.size,
3682 chip->ecc.bytes,
3683 &chip->ecc.layout);
3684 if (!chip->ecc.priv) {
3685 pr_warn("BCH ECC initialization failed!\n");
3686 BUG();
3687 }
3688 chip->ecc.strength =
3689 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3690 break;
3691
3692 case NAND_ECC_NONE:
3693 pr_warn("NAND_ECC_NONE selected by board driver. "
3694 "This is not recommended!\n");
3695 chip->ecc.read_page = nand_read_page_raw;
3696 chip->ecc.write_page = nand_write_page_raw;
3697 chip->ecc.read_oob = nand_read_oob_std;
3698 chip->ecc.read_page_raw = nand_read_page_raw;
3699 chip->ecc.write_page_raw = nand_write_page_raw;
3700 chip->ecc.write_oob = nand_write_oob_std;
3701 chip->ecc.size = mtd->writesize;
3702 chip->ecc.bytes = 0;
3703 chip->ecc.strength = 0;
3704 break;
3705
3706 default:
3707 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3708 BUG();
3709 }
3710
3711 /* For many systems, the standard OOB write also works for raw */
3712 if (!chip->ecc.read_oob_raw)
3713 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3714 if (!chip->ecc.write_oob_raw)
3715 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3716
3717 /*
3718 * The number of bytes available for a client to place data into
3719 * the out of band area.
3720 */
3721 chip->ecc.layout->oobavail = 0;
3722 for (i = 0; chip->ecc.layout->oobfree[i].length
3723 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3724 chip->ecc.layout->oobavail +=
3725 chip->ecc.layout->oobfree[i].length;
3726 mtd->oobavail = chip->ecc.layout->oobavail;
3727
3728 /*
3729 * Set the number of read / write steps for one page depending on ECC
3730 * mode.
3731 */
3732 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3733 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3734 pr_warn("Invalid ECC parameters\n");
3735 BUG();
3736 }
3737 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3738
3739 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3740 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3741 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3742 switch (chip->ecc.steps) {
3743 case 2:
3744 mtd->subpage_sft = 1;
3745 break;
3746 case 4:
3747 case 8:
3748 case 16:
3749 mtd->subpage_sft = 2;
3750 break;
3751 }
3752 }
3753 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3754
3755 /* Initialize state */
3756 chip->state = FL_READY;
3757
3758 /* Invalidate the pagebuffer reference */
3759 chip->pagebuf = -1;
3760
3761 /* Large page NAND with SOFT_ECC should support subpage reads */
3762 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3763 chip->options |= NAND_SUBPAGE_READ;
3764
3765 /* Fill in remaining MTD driver data */
3766 mtd->type = MTD_NANDFLASH;
3767 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3768 MTD_CAP_NANDFLASH;
3769 mtd->_erase = nand_erase;
3770 mtd->_point = NULL;
3771 mtd->_unpoint = NULL;
3772 mtd->_read = nand_read;
3773 mtd->_write = nand_write;
3774 mtd->_panic_write = panic_nand_write;
3775 mtd->_read_oob = nand_read_oob;
3776 mtd->_write_oob = nand_write_oob;
3777 mtd->_sync = nand_sync;
3778 mtd->_lock = NULL;
3779 mtd->_unlock = NULL;
3780 mtd->_suspend = nand_suspend;
3781 mtd->_resume = nand_resume;
3782 mtd->_block_isbad = nand_block_isbad;
3783 mtd->_block_markbad = nand_block_markbad;
3784 mtd->writebufsize = mtd->writesize;
3785
3786 /* propagate ecc info to mtd_info */
3787 mtd->ecclayout = chip->ecc.layout;
3788 mtd->ecc_strength = chip->ecc.strength;
3789 /*
3790 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3791 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3792 * properly set.
3793 */
3794 if (!mtd->bitflip_threshold)
3795 mtd->bitflip_threshold = mtd->ecc_strength;
3796
3797 /* Check, if we should skip the bad block table scan */
3798 if (chip->options & NAND_SKIP_BBTSCAN)
3799 return 0;
3800
3801 /* Build bad block table */
3802 return chip->scan_bbt(mtd);
3803 }
3804 EXPORT_SYMBOL(nand_scan_tail);
3805
3806 /*
3807 * is_module_text_address() isn't exported, and it's mostly a pointless
3808 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3809 * to call us from in-kernel code if the core NAND support is modular.
3810 */
3811 #ifdef MODULE
3812 #define caller_is_module() (1)
3813 #else
3814 #define caller_is_module() \
3815 is_module_text_address((unsigned long)__builtin_return_address(0))
3816 #endif
3817
3818 /**
3819 * nand_scan - [NAND Interface] Scan for the NAND device
3820 * @mtd: MTD device structure
3821 * @maxchips: number of chips to scan for
3822 *
3823 * This fills out all the uninitialized function pointers with the defaults.
3824 * The flash ID is read and the mtd/chip structures are filled with the
3825 * appropriate values. The mtd->owner field must be set to the module of the
3826 * caller.
3827 */
3828 int nand_scan(struct mtd_info *mtd, int maxchips)
3829 {
3830 int ret;
3831
3832 /* Many callers got this wrong, so check for it for a while... */
3833 if (!mtd->owner && caller_is_module()) {
3834 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3835 BUG();
3836 }
3837
3838 ret = nand_scan_ident(mtd, maxchips, NULL);
3839 if (!ret)
3840 ret = nand_scan_tail(mtd);
3841 return ret;
3842 }
3843 EXPORT_SYMBOL(nand_scan);
3844
3845 /**
3846 * nand_release - [NAND Interface] Free resources held by the NAND device
3847 * @mtd: MTD device structure
3848 */
3849 void nand_release(struct mtd_info *mtd)
3850 {
3851 struct nand_chip *chip = mtd->priv;
3852
3853 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3854 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3855
3856 mtd_device_unregister(mtd);
3857
3858 /* Free bad block table memory */
3859 kfree(chip->bbt);
3860 if (!(chip->options & NAND_OWN_BUFFERS))
3861 kfree(chip->buffers);
3862
3863 /* Free bad block descriptor memory */
3864 if (chip->badblock_pattern && chip->badblock_pattern->options
3865 & NAND_BBT_DYNAMICSTRUCT)
3866 kfree(chip->badblock_pattern);
3867 }
3868 EXPORT_SYMBOL_GPL(nand_release);
3869
3870 static int __init nand_base_init(void)
3871 {
3872 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3873 return 0;
3874 }
3875
3876 static void __exit nand_base_exit(void)
3877 {
3878 led_trigger_unregister_simple(nand_led_trigger);
3879 }
3880
3881 module_init(nand_base_init);
3882 module_exit(nand_base_exit);
3883
3884 MODULE_LICENSE("GPL");
3885 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3886 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3887 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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