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mtd: nand: omap: ecc.calculate: refactor omap_calculate_ecc_bch for BCHx_HW ecc-scheme
[deliverable/linux.git] / drivers / mtd / nand / omap2.c
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/platform_data/mtd-nand-omap2.h>
32
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
35
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
48
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
61
62 #define TF(value) (value ? 1 : 0)
63
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
105 #define CS_MASK 0x7
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
112 #define ECC1 0x1
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
118
119 #define OMAP24XX_DMA_GPMC 4
120
121 #define SECTOR_BYTES 512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD 4
124
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
131
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136
137 #define BADBLOCK_MARKER_LENGTH 2
138
139 #ifdef CONFIG_MTD_NAND_OMAP_BCH
140 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
141 0xac, 0x6b, 0xff, 0x99, 0x7b};
142 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
143 #endif
144
145 /* oob info generated runtime depending on ecc algorithm and layout selected */
146 static struct nand_ecclayout omap_oobinfo;
147
148 struct omap_nand_info {
149 struct nand_hw_control controller;
150 struct omap_nand_platform_data *pdata;
151 struct mtd_info mtd;
152 struct nand_chip nand;
153 struct platform_device *pdev;
154
155 int gpmc_cs;
156 unsigned long phys_base;
157 unsigned long mem_size;
158 enum omap_ecc ecc_opt;
159 struct completion comp;
160 struct dma_chan *dma;
161 int gpmc_irq_fifo;
162 int gpmc_irq_count;
163 enum {
164 OMAP_NAND_IO_READ = 0, /* read */
165 OMAP_NAND_IO_WRITE, /* write */
166 } iomode;
167 u_char *buf;
168 int buf_len;
169 struct gpmc_nand_regs reg;
170 /* fields specific for BCHx_HW ECC scheme */
171 bool is_elm_used;
172 struct device *elm_dev;
173 struct device_node *of_node;
174 };
175
176 /**
177 * omap_prefetch_enable - configures and starts prefetch transfer
178 * @cs: cs (chip select) number
179 * @fifo_th: fifo threshold to be used for read/ write
180 * @dma_mode: dma mode enable (1) or disable (0)
181 * @u32_count: number of bytes to be transferred
182 * @is_write: prefetch read(0) or write post(1) mode
183 */
184 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
185 unsigned int u32_count, int is_write, struct omap_nand_info *info)
186 {
187 u32 val;
188
189 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
190 return -1;
191
192 if (readl(info->reg.gpmc_prefetch_control))
193 return -EBUSY;
194
195 /* Set the amount of bytes to be prefetched */
196 writel(u32_count, info->reg.gpmc_prefetch_config2);
197
198 /* Set dma/mpu mode, the prefetch read / post write and
199 * enable the engine. Set which cs is has requested for.
200 */
201 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
202 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
203 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
204 writel(val, info->reg.gpmc_prefetch_config1);
205
206 /* Start the prefetch engine */
207 writel(0x1, info->reg.gpmc_prefetch_control);
208
209 return 0;
210 }
211
212 /**
213 * omap_prefetch_reset - disables and stops the prefetch engine
214 */
215 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
216 {
217 u32 config1;
218
219 /* check if the same module/cs is trying to reset */
220 config1 = readl(info->reg.gpmc_prefetch_config1);
221 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
222 return -EINVAL;
223
224 /* Stop the PFPW engine */
225 writel(0x0, info->reg.gpmc_prefetch_control);
226
227 /* Reset/disable the PFPW engine */
228 writel(0x0, info->reg.gpmc_prefetch_config1);
229
230 return 0;
231 }
232
233 /**
234 * omap_hwcontrol - hardware specific access to control-lines
235 * @mtd: MTD device structure
236 * @cmd: command to device
237 * @ctrl:
238 * NAND_NCE: bit 0 -> don't care
239 * NAND_CLE: bit 1 -> Command Latch
240 * NAND_ALE: bit 2 -> Address Latch
241 *
242 * NOTE: boards may use different bits for these!!
243 */
244 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
245 {
246 struct omap_nand_info *info = container_of(mtd,
247 struct omap_nand_info, mtd);
248
249 if (cmd != NAND_CMD_NONE) {
250 if (ctrl & NAND_CLE)
251 writeb(cmd, info->reg.gpmc_nand_command);
252
253 else if (ctrl & NAND_ALE)
254 writeb(cmd, info->reg.gpmc_nand_address);
255
256 else /* NAND_NCE */
257 writeb(cmd, info->reg.gpmc_nand_data);
258 }
259 }
260
261 /**
262 * omap_read_buf8 - read data from NAND controller into buffer
263 * @mtd: MTD device structure
264 * @buf: buffer to store date
265 * @len: number of bytes to read
266 */
267 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
268 {
269 struct nand_chip *nand = mtd->priv;
270
271 ioread8_rep(nand->IO_ADDR_R, buf, len);
272 }
273
274 /**
275 * omap_write_buf8 - write buffer to NAND controller
276 * @mtd: MTD device structure
277 * @buf: data buffer
278 * @len: number of bytes to write
279 */
280 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
281 {
282 struct omap_nand_info *info = container_of(mtd,
283 struct omap_nand_info, mtd);
284 u_char *p = (u_char *)buf;
285 u32 status = 0;
286
287 while (len--) {
288 iowrite8(*p++, info->nand.IO_ADDR_W);
289 /* wait until buffer is available for write */
290 do {
291 status = readl(info->reg.gpmc_status) &
292 STATUS_BUFF_EMPTY;
293 } while (!status);
294 }
295 }
296
297 /**
298 * omap_read_buf16 - read data from NAND controller into buffer
299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
302 */
303 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
304 {
305 struct nand_chip *nand = mtd->priv;
306
307 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
308 }
309
310 /**
311 * omap_write_buf16 - write buffer to NAND controller
312 * @mtd: MTD device structure
313 * @buf: data buffer
314 * @len: number of bytes to write
315 */
316 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
317 {
318 struct omap_nand_info *info = container_of(mtd,
319 struct omap_nand_info, mtd);
320 u16 *p = (u16 *) buf;
321 u32 status = 0;
322 /* FIXME try bursts of writesw() or DMA ... */
323 len >>= 1;
324
325 while (len--) {
326 iowrite16(*p++, info->nand.IO_ADDR_W);
327 /* wait until buffer is available for write */
328 do {
329 status = readl(info->reg.gpmc_status) &
330 STATUS_BUFF_EMPTY;
331 } while (!status);
332 }
333 }
334
335 /**
336 * omap_read_buf_pref - read data from NAND controller into buffer
337 * @mtd: MTD device structure
338 * @buf: buffer to store date
339 * @len: number of bytes to read
340 */
341 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
342 {
343 struct omap_nand_info *info = container_of(mtd,
344 struct omap_nand_info, mtd);
345 uint32_t r_count = 0;
346 int ret = 0;
347 u32 *p = (u32 *)buf;
348
349 /* take care of subpage reads */
350 if (len % 4) {
351 if (info->nand.options & NAND_BUSWIDTH_16)
352 omap_read_buf16(mtd, buf, len % 4);
353 else
354 omap_read_buf8(mtd, buf, len % 4);
355 p = (u32 *) (buf + len % 4);
356 len -= len % 4;
357 }
358
359 /* configure and start prefetch transfer */
360 ret = omap_prefetch_enable(info->gpmc_cs,
361 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
362 if (ret) {
363 /* PFPW engine is busy, use cpu copy method */
364 if (info->nand.options & NAND_BUSWIDTH_16)
365 omap_read_buf16(mtd, (u_char *)p, len);
366 else
367 omap_read_buf8(mtd, (u_char *)p, len);
368 } else {
369 do {
370 r_count = readl(info->reg.gpmc_prefetch_status);
371 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
372 r_count = r_count >> 2;
373 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
374 p += r_count;
375 len -= r_count << 2;
376 } while (len);
377 /* disable and stop the PFPW engine */
378 omap_prefetch_reset(info->gpmc_cs, info);
379 }
380 }
381
382 /**
383 * omap_write_buf_pref - write buffer to NAND controller
384 * @mtd: MTD device structure
385 * @buf: data buffer
386 * @len: number of bytes to write
387 */
388 static void omap_write_buf_pref(struct mtd_info *mtd,
389 const u_char *buf, int len)
390 {
391 struct omap_nand_info *info = container_of(mtd,
392 struct omap_nand_info, mtd);
393 uint32_t w_count = 0;
394 int i = 0, ret = 0;
395 u16 *p = (u16 *)buf;
396 unsigned long tim, limit;
397 u32 val;
398
399 /* take care of subpage writes */
400 if (len % 2 != 0) {
401 writeb(*buf, info->nand.IO_ADDR_W);
402 p = (u16 *)(buf + 1);
403 len--;
404 }
405
406 /* configure and start prefetch transfer */
407 ret = omap_prefetch_enable(info->gpmc_cs,
408 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
409 if (ret) {
410 /* PFPW engine is busy, use cpu copy method */
411 if (info->nand.options & NAND_BUSWIDTH_16)
412 omap_write_buf16(mtd, (u_char *)p, len);
413 else
414 omap_write_buf8(mtd, (u_char *)p, len);
415 } else {
416 while (len) {
417 w_count = readl(info->reg.gpmc_prefetch_status);
418 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
419 w_count = w_count >> 1;
420 for (i = 0; (i < w_count) && len; i++, len -= 2)
421 iowrite16(*p++, info->nand.IO_ADDR_W);
422 }
423 /* wait for data to flushed-out before reset the prefetch */
424 tim = 0;
425 limit = (loops_per_jiffy *
426 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
427 do {
428 cpu_relax();
429 val = readl(info->reg.gpmc_prefetch_status);
430 val = PREFETCH_STATUS_COUNT(val);
431 } while (val && (tim++ < limit));
432
433 /* disable and stop the PFPW engine */
434 omap_prefetch_reset(info->gpmc_cs, info);
435 }
436 }
437
438 /*
439 * omap_nand_dma_callback: callback on the completion of dma transfer
440 * @data: pointer to completion data structure
441 */
442 static void omap_nand_dma_callback(void *data)
443 {
444 complete((struct completion *) data);
445 }
446
447 /*
448 * omap_nand_dma_transfer: configure and start dma transfer
449 * @mtd: MTD device structure
450 * @addr: virtual address in RAM of source/destination
451 * @len: number of data bytes to be transferred
452 * @is_write: flag for read/write operation
453 */
454 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
455 unsigned int len, int is_write)
456 {
457 struct omap_nand_info *info = container_of(mtd,
458 struct omap_nand_info, mtd);
459 struct dma_async_tx_descriptor *tx;
460 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
461 DMA_FROM_DEVICE;
462 struct scatterlist sg;
463 unsigned long tim, limit;
464 unsigned n;
465 int ret;
466 u32 val;
467
468 if (addr >= high_memory) {
469 struct page *p1;
470
471 if (((size_t)addr & PAGE_MASK) !=
472 ((size_t)(addr + len - 1) & PAGE_MASK))
473 goto out_copy;
474 p1 = vmalloc_to_page(addr);
475 if (!p1)
476 goto out_copy;
477 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
478 }
479
480 sg_init_one(&sg, addr, len);
481 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
482 if (n == 0) {
483 dev_err(&info->pdev->dev,
484 "Couldn't DMA map a %d byte buffer\n", len);
485 goto out_copy;
486 }
487
488 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
489 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
490 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
491 if (!tx)
492 goto out_copy_unmap;
493
494 tx->callback = omap_nand_dma_callback;
495 tx->callback_param = &info->comp;
496 dmaengine_submit(tx);
497
498 /* configure and start prefetch transfer */
499 ret = omap_prefetch_enable(info->gpmc_cs,
500 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
501 if (ret)
502 /* PFPW engine is busy, use cpu copy method */
503 goto out_copy_unmap;
504
505 init_completion(&info->comp);
506 dma_async_issue_pending(info->dma);
507
508 /* setup and start DMA using dma_addr */
509 wait_for_completion(&info->comp);
510 tim = 0;
511 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
512
513 do {
514 cpu_relax();
515 val = readl(info->reg.gpmc_prefetch_status);
516 val = PREFETCH_STATUS_COUNT(val);
517 } while (val && (tim++ < limit));
518
519 /* disable and stop the PFPW engine */
520 omap_prefetch_reset(info->gpmc_cs, info);
521
522 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
523 return 0;
524
525 out_copy_unmap:
526 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
527 out_copy:
528 if (info->nand.options & NAND_BUSWIDTH_16)
529 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
530 : omap_write_buf16(mtd, (u_char *) addr, len);
531 else
532 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
533 : omap_write_buf8(mtd, (u_char *) addr, len);
534 return 0;
535 }
536
537 /**
538 * omap_read_buf_dma_pref - read data from NAND controller into buffer
539 * @mtd: MTD device structure
540 * @buf: buffer to store date
541 * @len: number of bytes to read
542 */
543 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
544 {
545 if (len <= mtd->oobsize)
546 omap_read_buf_pref(mtd, buf, len);
547 else
548 /* start transfer in DMA mode */
549 omap_nand_dma_transfer(mtd, buf, len, 0x0);
550 }
551
552 /**
553 * omap_write_buf_dma_pref - write buffer to NAND controller
554 * @mtd: MTD device structure
555 * @buf: data buffer
556 * @len: number of bytes to write
557 */
558 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
559 const u_char *buf, int len)
560 {
561 if (len <= mtd->oobsize)
562 omap_write_buf_pref(mtd, buf, len);
563 else
564 /* start transfer in DMA mode */
565 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
566 }
567
568 /*
569 * omap_nand_irq - GPMC irq handler
570 * @this_irq: gpmc irq number
571 * @dev: omap_nand_info structure pointer is passed here
572 */
573 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
574 {
575 struct omap_nand_info *info = (struct omap_nand_info *) dev;
576 u32 bytes;
577
578 bytes = readl(info->reg.gpmc_prefetch_status);
579 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
580 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
581 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
582 if (this_irq == info->gpmc_irq_count)
583 goto done;
584
585 if (info->buf_len && (info->buf_len < bytes))
586 bytes = info->buf_len;
587 else if (!info->buf_len)
588 bytes = 0;
589 iowrite32_rep(info->nand.IO_ADDR_W,
590 (u32 *)info->buf, bytes >> 2);
591 info->buf = info->buf + bytes;
592 info->buf_len -= bytes;
593
594 } else {
595 ioread32_rep(info->nand.IO_ADDR_R,
596 (u32 *)info->buf, bytes >> 2);
597 info->buf = info->buf + bytes;
598
599 if (this_irq == info->gpmc_irq_count)
600 goto done;
601 }
602
603 return IRQ_HANDLED;
604
605 done:
606 complete(&info->comp);
607
608 disable_irq_nosync(info->gpmc_irq_fifo);
609 disable_irq_nosync(info->gpmc_irq_count);
610
611 return IRQ_HANDLED;
612 }
613
614 /*
615 * omap_read_buf_irq_pref - read data from NAND controller into buffer
616 * @mtd: MTD device structure
617 * @buf: buffer to store date
618 * @len: number of bytes to read
619 */
620 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
621 {
622 struct omap_nand_info *info = container_of(mtd,
623 struct omap_nand_info, mtd);
624 int ret = 0;
625
626 if (len <= mtd->oobsize) {
627 omap_read_buf_pref(mtd, buf, len);
628 return;
629 }
630
631 info->iomode = OMAP_NAND_IO_READ;
632 info->buf = buf;
633 init_completion(&info->comp);
634
635 /* configure and start prefetch transfer */
636 ret = omap_prefetch_enable(info->gpmc_cs,
637 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
638 if (ret)
639 /* PFPW engine is busy, use cpu copy method */
640 goto out_copy;
641
642 info->buf_len = len;
643
644 enable_irq(info->gpmc_irq_count);
645 enable_irq(info->gpmc_irq_fifo);
646
647 /* waiting for read to complete */
648 wait_for_completion(&info->comp);
649
650 /* disable and stop the PFPW engine */
651 omap_prefetch_reset(info->gpmc_cs, info);
652 return;
653
654 out_copy:
655 if (info->nand.options & NAND_BUSWIDTH_16)
656 omap_read_buf16(mtd, buf, len);
657 else
658 omap_read_buf8(mtd, buf, len);
659 }
660
661 /*
662 * omap_write_buf_irq_pref - write buffer to NAND controller
663 * @mtd: MTD device structure
664 * @buf: data buffer
665 * @len: number of bytes to write
666 */
667 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
668 const u_char *buf, int len)
669 {
670 struct omap_nand_info *info = container_of(mtd,
671 struct omap_nand_info, mtd);
672 int ret = 0;
673 unsigned long tim, limit;
674 u32 val;
675
676 if (len <= mtd->oobsize) {
677 omap_write_buf_pref(mtd, buf, len);
678 return;
679 }
680
681 info->iomode = OMAP_NAND_IO_WRITE;
682 info->buf = (u_char *) buf;
683 init_completion(&info->comp);
684
685 /* configure and start prefetch transfer : size=24 */
686 ret = omap_prefetch_enable(info->gpmc_cs,
687 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
688 if (ret)
689 /* PFPW engine is busy, use cpu copy method */
690 goto out_copy;
691
692 info->buf_len = len;
693
694 enable_irq(info->gpmc_irq_count);
695 enable_irq(info->gpmc_irq_fifo);
696
697 /* waiting for write to complete */
698 wait_for_completion(&info->comp);
699
700 /* wait for data to flushed-out before reset the prefetch */
701 tim = 0;
702 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
703 do {
704 val = readl(info->reg.gpmc_prefetch_status);
705 val = PREFETCH_STATUS_COUNT(val);
706 cpu_relax();
707 } while (val && (tim++ < limit));
708
709 /* disable and stop the PFPW engine */
710 omap_prefetch_reset(info->gpmc_cs, info);
711 return;
712
713 out_copy:
714 if (info->nand.options & NAND_BUSWIDTH_16)
715 omap_write_buf16(mtd, buf, len);
716 else
717 omap_write_buf8(mtd, buf, len);
718 }
719
720 /**
721 * gen_true_ecc - This function will generate true ECC value
722 * @ecc_buf: buffer to store ecc code
723 *
724 * This generated true ECC value can be used when correcting
725 * data read from NAND flash memory core
726 */
727 static void gen_true_ecc(u8 *ecc_buf)
728 {
729 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
730 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
731
732 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
733 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
734 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
735 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
736 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
737 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
738 }
739
740 /**
741 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
742 * @ecc_data1: ecc code from nand spare area
743 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
744 * @page_data: page data
745 *
746 * This function compares two ECC's and indicates if there is an error.
747 * If the error can be corrected it will be corrected to the buffer.
748 * If there is no error, %0 is returned. If there is an error but it
749 * was corrected, %1 is returned. Otherwise, %-1 is returned.
750 */
751 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
752 u8 *ecc_data2, /* read from register */
753 u8 *page_data)
754 {
755 uint i;
756 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
757 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
758 u8 ecc_bit[24];
759 u8 ecc_sum = 0;
760 u8 find_bit = 0;
761 uint find_byte = 0;
762 int isEccFF;
763
764 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
765
766 gen_true_ecc(ecc_data1);
767 gen_true_ecc(ecc_data2);
768
769 for (i = 0; i <= 2; i++) {
770 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
771 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
772 }
773
774 for (i = 0; i < 8; i++) {
775 tmp0_bit[i] = *ecc_data1 % 2;
776 *ecc_data1 = *ecc_data1 / 2;
777 }
778
779 for (i = 0; i < 8; i++) {
780 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
781 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
782 }
783
784 for (i = 0; i < 8; i++) {
785 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
786 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
787 }
788
789 for (i = 0; i < 8; i++) {
790 comp0_bit[i] = *ecc_data2 % 2;
791 *ecc_data2 = *ecc_data2 / 2;
792 }
793
794 for (i = 0; i < 8; i++) {
795 comp1_bit[i] = *(ecc_data2 + 1) % 2;
796 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
797 }
798
799 for (i = 0; i < 8; i++) {
800 comp2_bit[i] = *(ecc_data2 + 2) % 2;
801 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
802 }
803
804 for (i = 0; i < 6; i++)
805 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
806
807 for (i = 0; i < 8; i++)
808 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
809
810 for (i = 0; i < 8; i++)
811 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
812
813 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
814 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
815
816 for (i = 0; i < 24; i++)
817 ecc_sum += ecc_bit[i];
818
819 switch (ecc_sum) {
820 case 0:
821 /* Not reached because this function is not called if
822 * ECC values are equal
823 */
824 return 0;
825
826 case 1:
827 /* Uncorrectable error */
828 pr_debug("ECC UNCORRECTED_ERROR 1\n");
829 return -1;
830
831 case 11:
832 /* UN-Correctable error */
833 pr_debug("ECC UNCORRECTED_ERROR B\n");
834 return -1;
835
836 case 12:
837 /* Correctable error */
838 find_byte = (ecc_bit[23] << 8) +
839 (ecc_bit[21] << 7) +
840 (ecc_bit[19] << 6) +
841 (ecc_bit[17] << 5) +
842 (ecc_bit[15] << 4) +
843 (ecc_bit[13] << 3) +
844 (ecc_bit[11] << 2) +
845 (ecc_bit[9] << 1) +
846 ecc_bit[7];
847
848 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
849
850 pr_debug("Correcting single bit ECC error at offset: "
851 "%d, bit: %d\n", find_byte, find_bit);
852
853 page_data[find_byte] ^= (1 << find_bit);
854
855 return 1;
856 default:
857 if (isEccFF) {
858 if (ecc_data2[0] == 0 &&
859 ecc_data2[1] == 0 &&
860 ecc_data2[2] == 0)
861 return 0;
862 }
863 pr_debug("UNCORRECTED_ERROR default\n");
864 return -1;
865 }
866 }
867
868 /**
869 * omap_correct_data - Compares the ECC read with HW generated ECC
870 * @mtd: MTD device structure
871 * @dat: page data
872 * @read_ecc: ecc read from nand flash
873 * @calc_ecc: ecc read from HW ECC registers
874 *
875 * Compares the ecc read from nand spare area with ECC registers values
876 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
877 * detection and correction. If there are no errors, %0 is returned. If
878 * there were errors and all of the errors were corrected, the number of
879 * corrected errors is returned. If uncorrectable errors exist, %-1 is
880 * returned.
881 */
882 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
883 u_char *read_ecc, u_char *calc_ecc)
884 {
885 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
886 mtd);
887 int blockCnt = 0, i = 0, ret = 0;
888 int stat = 0;
889
890 /* Ex NAND_ECC_HW12_2048 */
891 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
892 (info->nand.ecc.size == 2048))
893 blockCnt = 4;
894 else
895 blockCnt = 1;
896
897 for (i = 0; i < blockCnt; i++) {
898 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
899 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
900 if (ret < 0)
901 return ret;
902 /* keep track of the number of corrected errors */
903 stat += ret;
904 }
905 read_ecc += 3;
906 calc_ecc += 3;
907 dat += 512;
908 }
909 return stat;
910 }
911
912 /**
913 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
914 * @mtd: MTD device structure
915 * @dat: The pointer to data on which ecc is computed
916 * @ecc_code: The ecc_code buffer
917 *
918 * Using noninverted ECC can be considered ugly since writing a blank
919 * page ie. padding will clear the ECC bytes. This is no problem as long
920 * nobody is trying to write data on the seemingly unused page. Reading
921 * an erased page will produce an ECC mismatch between generated and read
922 * ECC bytes that has to be dealt with separately.
923 */
924 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
925 u_char *ecc_code)
926 {
927 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
928 mtd);
929 u32 val;
930
931 val = readl(info->reg.gpmc_ecc_config);
932 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
933 return -EINVAL;
934
935 /* read ecc result */
936 val = readl(info->reg.gpmc_ecc1_result);
937 *ecc_code++ = val; /* P128e, ..., P1e */
938 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
939 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
940 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
941
942 return 0;
943 }
944
945 /**
946 * omap_enable_hwecc - This function enables the hardware ecc functionality
947 * @mtd: MTD device structure
948 * @mode: Read/Write mode
949 */
950 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
951 {
952 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
953 mtd);
954 struct nand_chip *chip = mtd->priv;
955 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
956 u32 val;
957
958 /* clear ecc and enable bits */
959 val = ECCCLEAR | ECC1;
960 writel(val, info->reg.gpmc_ecc_control);
961
962 /* program ecc and result sizes */
963 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
964 ECC1RESULTSIZE);
965 writel(val, info->reg.gpmc_ecc_size_config);
966
967 switch (mode) {
968 case NAND_ECC_READ:
969 case NAND_ECC_WRITE:
970 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
971 break;
972 case NAND_ECC_READSYN:
973 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
974 break;
975 default:
976 dev_info(&info->pdev->dev,
977 "error: unrecognized Mode[%d]!\n", mode);
978 break;
979 }
980
981 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
982 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
983 writel(val, info->reg.gpmc_ecc_config);
984 }
985
986 /**
987 * omap_wait - wait until the command is done
988 * @mtd: MTD device structure
989 * @chip: NAND Chip structure
990 *
991 * Wait function is called during Program and erase operations and
992 * the way it is called from MTD layer, we should wait till the NAND
993 * chip is ready after the programming/erase operation has completed.
994 *
995 * Erase can take up to 400ms and program up to 20ms according to
996 * general NAND and SmartMedia specs
997 */
998 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
999 {
1000 struct nand_chip *this = mtd->priv;
1001 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1002 mtd);
1003 unsigned long timeo = jiffies;
1004 int status, state = this->state;
1005
1006 if (state == FL_ERASING)
1007 timeo += msecs_to_jiffies(400);
1008 else
1009 timeo += msecs_to_jiffies(20);
1010
1011 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1012 while (time_before(jiffies, timeo)) {
1013 status = readb(info->reg.gpmc_nand_data);
1014 if (status & NAND_STATUS_READY)
1015 break;
1016 cond_resched();
1017 }
1018
1019 status = readb(info->reg.gpmc_nand_data);
1020 return status;
1021 }
1022
1023 /**
1024 * omap_dev_ready - calls the platform specific dev_ready function
1025 * @mtd: MTD device structure
1026 */
1027 static int omap_dev_ready(struct mtd_info *mtd)
1028 {
1029 unsigned int val = 0;
1030 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1031 mtd);
1032
1033 val = readl(info->reg.gpmc_status);
1034
1035 if ((val & 0x100) == 0x100) {
1036 return 1;
1037 } else {
1038 return 0;
1039 }
1040 }
1041
1042 #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
1043 /**
1044 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1045 * @mtd: MTD device structure
1046 * @mode: Read/Write mode
1047 *
1048 * When using BCH, sector size is hardcoded to 512 bytes.
1049 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1050 * for error correction.
1051 * On writing,
1052 * eccsize0 = 0 (no additional protected byte in spare area)
1053 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1054 */
1055 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1056 {
1057 int nerrors;
1058 unsigned int dev_width, nsectors;
1059 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1060 mtd);
1061 struct nand_chip *chip = mtd->priv;
1062 u32 val, wr_mode;
1063 unsigned int ecc_size1, ecc_size0;
1064
1065 /* Using wrapping mode 6 for writing */
1066 wr_mode = BCH_WRAPMODE_6;
1067
1068 /*
1069 * ECC engine enabled for valid ecc_size0 nibbles
1070 * and disabled for ecc_size1 nibbles.
1071 */
1072 ecc_size0 = BCH_ECC_SIZE0;
1073 ecc_size1 = BCH_ECC_SIZE1;
1074
1075 /* Perform ecc calculation on 512-byte sector */
1076 nsectors = 1;
1077
1078 /* Update number of error correction */
1079 nerrors = info->nand.ecc.strength;
1080
1081 /* Multi sector reading/writing for NAND flash with page size < 4096 */
1082 if (info->is_elm_used && (mtd->writesize <= 4096)) {
1083 if (mode == NAND_ECC_READ) {
1084 /* Using wrapping mode 1 for reading */
1085 wr_mode = BCH_WRAPMODE_1;
1086
1087 /*
1088 * ECC engine enabled for ecc_size0 nibbles
1089 * and disabled for ecc_size1 nibbles.
1090 */
1091 ecc_size0 = (nerrors == 8) ?
1092 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1093 ecc_size1 = (nerrors == 8) ?
1094 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1095 }
1096
1097 /* Perform ecc calculation for one page (< 4096) */
1098 nsectors = info->nand.ecc.steps;
1099 }
1100
1101 writel(ECC1, info->reg.gpmc_ecc_control);
1102
1103 /* Configure ecc size for BCH */
1104 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1105 writel(val, info->reg.gpmc_ecc_size_config);
1106
1107 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1108
1109 /* BCH configuration */
1110 val = ((1 << 16) | /* enable BCH */
1111 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1112 (wr_mode << 8) | /* wrap mode */
1113 (dev_width << 7) | /* bus width */
1114 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1115 (info->gpmc_cs << 1) | /* ECC CS */
1116 (0x1)); /* enable ECC */
1117
1118 writel(val, info->reg.gpmc_ecc_config);
1119
1120 /* Clear ecc and enable bits */
1121 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1122 }
1123 #endif
1124
1125 #ifdef CONFIG_MTD_NAND_ECC_BCH
1126 /**
1127 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1128 * @mtd: MTD device structure
1129 * @dat: The pointer to data on which ecc is computed
1130 * @ecc_code: The ecc_code buffer
1131 */
1132 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1133 u_char *ecc_code)
1134 {
1135 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1136 mtd);
1137 unsigned long nsectors, val1, val2;
1138 int i;
1139
1140 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1141
1142 for (i = 0; i < nsectors; i++) {
1143
1144 /* Read hw-computed remainder */
1145 val1 = readl(info->reg.gpmc_bch_result0[i]);
1146 val2 = readl(info->reg.gpmc_bch_result1[i]);
1147
1148 /*
1149 * Add constant polynomial to remainder, in order to get an ecc
1150 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1151 * left-justify the resulting polynomial.
1152 */
1153 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1154 *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1155 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1156 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1157 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1158 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1159 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1160 }
1161
1162 return 0;
1163 }
1164
1165 /**
1166 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1167 * @mtd: MTD device structure
1168 * @dat: The pointer to data on which ecc is computed
1169 * @ecc_code: The ecc_code buffer
1170 */
1171 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1172 u_char *ecc_code)
1173 {
1174 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1175 mtd);
1176 unsigned long nsectors, val1, val2, val3, val4;
1177 int i;
1178
1179 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1180
1181 for (i = 0; i < nsectors; i++) {
1182
1183 /* Read hw-computed remainder */
1184 val1 = readl(info->reg.gpmc_bch_result0[i]);
1185 val2 = readl(info->reg.gpmc_bch_result1[i]);
1186 val3 = readl(info->reg.gpmc_bch_result2[i]);
1187 val4 = readl(info->reg.gpmc_bch_result3[i]);
1188
1189 /*
1190 * Add constant polynomial to remainder, in order to get an ecc
1191 * sequence of 0xFFs for a buffer filled with 0xFFs.
1192 */
1193 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1194 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1195 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1196 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1197 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1198 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1199 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1200 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1201 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1202 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1203 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1204 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1205 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1206 }
1207
1208 return 0;
1209 }
1210 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1211
1212 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1213 /**
1214 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1215 * @mtd: MTD device structure
1216 * @dat: The pointer to data on which ecc is computed
1217 * @ecc_code: The ecc_code buffer
1218 *
1219 * Support calculating of BCH4/8 ecc vectors for the page
1220 */
1221 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1222 const u_char *dat, u_char *ecc_calc)
1223 {
1224 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1225 mtd);
1226 int eccbytes = info->nand.ecc.bytes;
1227 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1228 u8 *ecc_code;
1229 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1230 int i;
1231
1232 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1233 for (i = 0; i < nsectors; i++) {
1234 ecc_code = ecc_calc;
1235 switch (info->ecc_opt) {
1236 case OMAP_ECC_BCH8_CODE_HW:
1237 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1238 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1239 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1240 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1241 *ecc_code++ = (bch_val4 & 0xFF);
1242 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1243 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1244 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1245 *ecc_code++ = (bch_val3 & 0xFF);
1246 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1247 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1248 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1249 *ecc_code++ = (bch_val2 & 0xFF);
1250 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1251 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1252 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1253 *ecc_code++ = (bch_val1 & 0xFF);
1254 break;
1255 case OMAP_ECC_BCH4_CODE_HW:
1256 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1257 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1258 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1259 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1260 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1261 ((bch_val1 >> 28) & 0xF);
1262 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1263 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1264 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1265 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 /* ECC scheme specific syndrome customizations */
1272 switch (info->ecc_opt) {
1273 case OMAP_ECC_BCH4_CODE_HW:
1274 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1275 ecc_calc[eccbytes - 1] = 0x0;
1276 break;
1277 case OMAP_ECC_BCH8_CODE_HW:
1278 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1279 ecc_calc[eccbytes - 1] = 0x0;
1280 break;
1281 default:
1282 return -EINVAL;
1283 }
1284
1285 ecc_calc += eccbytes;
1286 }
1287
1288 return 0;
1289 }
1290
1291 /**
1292 * erased_sector_bitflips - count bit flips
1293 * @data: data sector buffer
1294 * @oob: oob buffer
1295 * @info: omap_nand_info
1296 *
1297 * Check the bit flips in erased page falls below correctable level.
1298 * If falls below, report the page as erased with correctable bit
1299 * flip, else report as uncorrectable page.
1300 */
1301 static int erased_sector_bitflips(u_char *data, u_char *oob,
1302 struct omap_nand_info *info)
1303 {
1304 int flip_bits = 0, i;
1305
1306 for (i = 0; i < info->nand.ecc.size; i++) {
1307 flip_bits += hweight8(~data[i]);
1308 if (flip_bits > info->nand.ecc.strength)
1309 return 0;
1310 }
1311
1312 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1313 flip_bits += hweight8(~oob[i]);
1314 if (flip_bits > info->nand.ecc.strength)
1315 return 0;
1316 }
1317
1318 /*
1319 * Bit flips falls in correctable level.
1320 * Fill data area with 0xFF
1321 */
1322 if (flip_bits) {
1323 memset(data, 0xFF, info->nand.ecc.size);
1324 memset(oob, 0xFF, info->nand.ecc.bytes);
1325 }
1326
1327 return flip_bits;
1328 }
1329
1330 /**
1331 * omap_elm_correct_data - corrects page data area in case error reported
1332 * @mtd: MTD device structure
1333 * @data: page data
1334 * @read_ecc: ecc read from nand flash
1335 * @calc_ecc: ecc read from HW ECC registers
1336 *
1337 * Calculated ecc vector reported as zero in case of non-error pages.
1338 * In case of non-zero ecc vector, first filter out erased-pages, and
1339 * then process data via ELM to detect bit-flips.
1340 */
1341 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1342 u_char *read_ecc, u_char *calc_ecc)
1343 {
1344 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1345 mtd);
1346 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1347 int eccsteps = info->nand.ecc.steps;
1348 int i , j, stat = 0;
1349 int eccflag, actual_eccbytes;
1350 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1351 u_char *ecc_vec = calc_ecc;
1352 u_char *spare_ecc = read_ecc;
1353 u_char *erased_ecc_vec;
1354 u_char *buf;
1355 int bitflip_count;
1356 bool is_error_reported = false;
1357 u32 bit_pos, byte_pos, error_max, pos;
1358 int err;
1359
1360 switch (info->ecc_opt) {
1361 case OMAP_ECC_BCH4_CODE_HW:
1362 /* omit 7th ECC byte reserved for ROM code compatibility */
1363 actual_eccbytes = ecc->bytes - 1;
1364 erased_ecc_vec = bch4_vector;
1365 break;
1366 case OMAP_ECC_BCH8_CODE_HW:
1367 /* omit 14th ECC byte reserved for ROM code compatibility */
1368 actual_eccbytes = ecc->bytes - 1;
1369 erased_ecc_vec = bch8_vector;
1370 break;
1371 default:
1372 pr_err("invalid driver configuration\n");
1373 return -EINVAL;
1374 }
1375
1376 /* Initialize elm error vector to zero */
1377 memset(err_vec, 0, sizeof(err_vec));
1378
1379 for (i = 0; i < eccsteps ; i++) {
1380 eccflag = 0; /* initialize eccflag */
1381
1382 /*
1383 * Check any error reported,
1384 * In case of error, non zero ecc reported.
1385 */
1386 for (j = 0; j < actual_eccbytes; j++) {
1387 if (calc_ecc[j] != 0) {
1388 eccflag = 1; /* non zero ecc, error present */
1389 break;
1390 }
1391 }
1392
1393 if (eccflag == 1) {
1394 if (memcmp(calc_ecc, erased_ecc_vec,
1395 actual_eccbytes) == 0) {
1396 /*
1397 * calc_ecc[] matches pattern for ECC(all 0xff)
1398 * so this is definitely an erased-page
1399 */
1400 } else {
1401 buf = &data[info->nand.ecc.size * i];
1402 /*
1403 * count number of 0-bits in read_buf.
1404 * This check can be removed once a similar
1405 * check is introduced in generic NAND driver
1406 */
1407 bitflip_count = erased_sector_bitflips(
1408 buf, read_ecc, info);
1409 if (bitflip_count) {
1410 /*
1411 * number of 0-bits within ECC limits
1412 * So this may be an erased-page
1413 */
1414 stat += bitflip_count;
1415 } else {
1416 /*
1417 * Too many 0-bits. It may be a
1418 * - programmed-page, OR
1419 * - erased-page with many bit-flips
1420 * So this page requires check by ELM
1421 */
1422 err_vec[i].error_reported = true;
1423 is_error_reported = true;
1424 }
1425 }
1426 }
1427
1428 /* Update the ecc vector */
1429 calc_ecc += ecc->bytes;
1430 read_ecc += ecc->bytes;
1431 }
1432
1433 /* Check if any error reported */
1434 if (!is_error_reported)
1435 return 0;
1436
1437 /* Decode BCH error using ELM module */
1438 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1439
1440 err = 0;
1441 for (i = 0; i < eccsteps; i++) {
1442 if (err_vec[i].error_uncorrectable) {
1443 pr_err("nand: uncorrectable bit-flips found\n");
1444 err = -EBADMSG;
1445 } else if (err_vec[i].error_reported) {
1446 for (j = 0; j < err_vec[i].error_count; j++) {
1447 switch (info->ecc_opt) {
1448 case OMAP_ECC_BCH4_CODE_HW:
1449 /* Add 4 bits to take care of padding */
1450 pos = err_vec[i].error_loc[j] +
1451 BCH4_BIT_PAD;
1452 break;
1453 case OMAP_ECC_BCH8_CODE_HW:
1454 pos = err_vec[i].error_loc[j];
1455 break;
1456 default:
1457 return -EINVAL;
1458 }
1459 error_max = (ecc->size + actual_eccbytes) * 8;
1460 /* Calculate bit position of error */
1461 bit_pos = pos % 8;
1462
1463 /* Calculate byte position of error */
1464 byte_pos = (error_max - pos - 1) / 8;
1465
1466 if (pos < error_max) {
1467 if (byte_pos < 512) {
1468 pr_debug("bitflip@dat[%d]=%x\n",
1469 byte_pos, data[byte_pos]);
1470 data[byte_pos] ^= 1 << bit_pos;
1471 } else {
1472 pr_debug("bitflip@oob[%d]=%x\n",
1473 (byte_pos - 512),
1474 spare_ecc[byte_pos - 512]);
1475 spare_ecc[byte_pos - 512] ^=
1476 1 << bit_pos;
1477 }
1478 } else {
1479 pr_err("invalid bit-flip @ %d:%d\n",
1480 byte_pos, bit_pos);
1481 err = -EBADMSG;
1482 }
1483 }
1484 }
1485
1486 /* Update number of correctable errors */
1487 stat += err_vec[i].error_count;
1488
1489 /* Update page data with sector size */
1490 data += ecc->size;
1491 spare_ecc += ecc->bytes;
1492 }
1493
1494 return (err) ? err : stat;
1495 }
1496
1497 /**
1498 * omap_write_page_bch - BCH ecc based write page function for entire page
1499 * @mtd: mtd info structure
1500 * @chip: nand chip info structure
1501 * @buf: data buffer
1502 * @oob_required: must write chip->oob_poi to OOB
1503 *
1504 * Custom write page method evolved to support multi sector writing in one shot
1505 */
1506 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1507 const uint8_t *buf, int oob_required)
1508 {
1509 int i;
1510 uint8_t *ecc_calc = chip->buffers->ecccalc;
1511 uint32_t *eccpos = chip->ecc.layout->eccpos;
1512
1513 /* Enable GPMC ecc engine */
1514 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1515
1516 /* Write data */
1517 chip->write_buf(mtd, buf, mtd->writesize);
1518
1519 /* Update ecc vector from GPMC result registers */
1520 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1521
1522 for (i = 0; i < chip->ecc.total; i++)
1523 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1524
1525 /* Write ecc vector to OOB area */
1526 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1527 return 0;
1528 }
1529
1530 /**
1531 * omap_read_page_bch - BCH ecc based page read function for entire page
1532 * @mtd: mtd info structure
1533 * @chip: nand chip info structure
1534 * @buf: buffer to store read data
1535 * @oob_required: caller requires OOB data read to chip->oob_poi
1536 * @page: page number to read
1537 *
1538 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1539 * used for error correction.
1540 * Custom method evolved to support ELM error correction & multi sector
1541 * reading. On reading page data area is read along with OOB data with
1542 * ecc engine enabled. ecc vector updated after read of OOB data.
1543 * For non error pages ecc vector reported as zero.
1544 */
1545 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1546 uint8_t *buf, int oob_required, int page)
1547 {
1548 uint8_t *ecc_calc = chip->buffers->ecccalc;
1549 uint8_t *ecc_code = chip->buffers->ecccode;
1550 uint32_t *eccpos = chip->ecc.layout->eccpos;
1551 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1552 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1553 int stat;
1554 unsigned int max_bitflips = 0;
1555
1556 /* Enable GPMC ecc engine */
1557 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1558
1559 /* Read data */
1560 chip->read_buf(mtd, buf, mtd->writesize);
1561
1562 /* Read oob bytes */
1563 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1564 chip->read_buf(mtd, oob, chip->ecc.total);
1565
1566 /* Calculate ecc bytes */
1567 chip->ecc.calculate(mtd, buf, ecc_calc);
1568
1569 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1570
1571 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1572
1573 if (stat < 0) {
1574 mtd->ecc_stats.failed++;
1575 } else {
1576 mtd->ecc_stats.corrected += stat;
1577 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1578 }
1579
1580 return max_bitflips;
1581 }
1582
1583 /**
1584 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1585 * @omap_nand_info: NAND device structure containing platform data
1586 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1587 */
1588 static int is_elm_present(struct omap_nand_info *info,
1589 struct device_node *elm_node, enum bch_ecc bch_type)
1590 {
1591 struct platform_device *pdev;
1592 info->is_elm_used = false;
1593 /* check whether elm-id is passed via DT */
1594 if (!elm_node) {
1595 pr_err("nand: error: ELM DT node not found\n");
1596 return -ENODEV;
1597 }
1598 pdev = of_find_device_by_node(elm_node);
1599 /* check whether ELM device is registered */
1600 if (!pdev) {
1601 pr_err("nand: error: ELM device not found\n");
1602 return -ENODEV;
1603 }
1604 /* ELM module available, now configure it */
1605 info->elm_dev = &pdev->dev;
1606 if (elm_config(info->elm_dev, bch_type))
1607 return -ENODEV;
1608 info->is_elm_used = true;
1609 return 0;
1610 }
1611 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1612
1613 static int omap_nand_probe(struct platform_device *pdev)
1614 {
1615 struct omap_nand_info *info;
1616 struct omap_nand_platform_data *pdata;
1617 struct mtd_info *mtd;
1618 struct nand_chip *nand_chip;
1619 struct nand_ecclayout *ecclayout;
1620 int err;
1621 int i;
1622 dma_cap_mask_t mask;
1623 unsigned sig;
1624 unsigned oob_index;
1625 struct resource *res;
1626 struct mtd_part_parser_data ppdata = {};
1627
1628 pdata = dev_get_platdata(&pdev->dev);
1629 if (pdata == NULL) {
1630 dev_err(&pdev->dev, "platform data missing\n");
1631 return -ENODEV;
1632 }
1633
1634 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1635 GFP_KERNEL);
1636 if (!info)
1637 return -ENOMEM;
1638
1639 platform_set_drvdata(pdev, info);
1640
1641 spin_lock_init(&info->controller.lock);
1642 init_waitqueue_head(&info->controller.wq);
1643
1644 info->pdev = pdev;
1645 info->gpmc_cs = pdata->cs;
1646 info->reg = pdata->reg;
1647 info->of_node = pdata->of_node;
1648 info->ecc_opt = pdata->ecc_opt;
1649 mtd = &info->mtd;
1650 mtd->priv = &info->nand;
1651 mtd->name = dev_name(&pdev->dev);
1652 mtd->owner = THIS_MODULE;
1653 nand_chip = &info->nand;
1654 nand_chip->ecc.priv = NULL;
1655 nand_chip->options |= NAND_SKIP_BBTSCAN;
1656
1657 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1658 if (res == NULL) {
1659 err = -EINVAL;
1660 dev_err(&pdev->dev, "error getting memory resource\n");
1661 goto return_error;
1662 }
1663
1664 info->phys_base = res->start;
1665 info->mem_size = resource_size(res);
1666
1667 if (!devm_request_mem_region(&pdev->dev, info->phys_base,
1668 info->mem_size, pdev->dev.driver->name)) {
1669 err = -EBUSY;
1670 goto return_error;
1671 }
1672
1673 nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base,
1674 info->mem_size);
1675 if (!nand_chip->IO_ADDR_R) {
1676 err = -ENOMEM;
1677 goto return_error;
1678 }
1679
1680 nand_chip->controller = &info->controller;
1681
1682 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1683 nand_chip->cmd_ctrl = omap_hwcontrol;
1684
1685 /*
1686 * If RDY/BSY line is connected to OMAP then use the omap ready
1687 * function and the generic nand_wait function which reads the status
1688 * register after monitoring the RDY/BSY line. Otherwise use a standard
1689 * chip delay which is slightly more than tR (AC Timing) of the NAND
1690 * device and read status register until you get a failure or success
1691 */
1692 if (pdata->dev_ready) {
1693 nand_chip->dev_ready = omap_dev_ready;
1694 nand_chip->chip_delay = 0;
1695 } else {
1696 nand_chip->waitfunc = omap_wait;
1697 nand_chip->chip_delay = 50;
1698 }
1699
1700 /* scan NAND device connected to chip controller */
1701 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1702 if (nand_scan_ident(mtd, 1, NULL)) {
1703 pr_err("nand device scan failed, may be bus-width mismatch\n");
1704 err = -ENXIO;
1705 goto return_error;
1706 }
1707
1708 /* check for small page devices */
1709 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1710 pr_err("small page devices are not supported\n");
1711 err = -EINVAL;
1712 goto return_error;
1713 }
1714
1715 /* re-populate low-level callbacks based on xfer modes */
1716 switch (pdata->xfer_type) {
1717 case NAND_OMAP_PREFETCH_POLLED:
1718 nand_chip->read_buf = omap_read_buf_pref;
1719 nand_chip->write_buf = omap_write_buf_pref;
1720 break;
1721
1722 case NAND_OMAP_POLLED:
1723 /* Use nand_base defaults for {read,write}_buf */
1724 break;
1725
1726 case NAND_OMAP_PREFETCH_DMA:
1727 dma_cap_zero(mask);
1728 dma_cap_set(DMA_SLAVE, mask);
1729 sig = OMAP24XX_DMA_GPMC;
1730 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1731 if (!info->dma) {
1732 dev_err(&pdev->dev, "DMA engine request failed\n");
1733 err = -ENXIO;
1734 goto return_error;
1735 } else {
1736 struct dma_slave_config cfg;
1737
1738 memset(&cfg, 0, sizeof(cfg));
1739 cfg.src_addr = info->phys_base;
1740 cfg.dst_addr = info->phys_base;
1741 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1742 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1743 cfg.src_maxburst = 16;
1744 cfg.dst_maxburst = 16;
1745 err = dmaengine_slave_config(info->dma, &cfg);
1746 if (err) {
1747 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1748 err);
1749 goto return_error;
1750 }
1751 nand_chip->read_buf = omap_read_buf_dma_pref;
1752 nand_chip->write_buf = omap_write_buf_dma_pref;
1753 }
1754 break;
1755
1756 case NAND_OMAP_PREFETCH_IRQ:
1757 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1758 if (info->gpmc_irq_fifo <= 0) {
1759 dev_err(&pdev->dev, "error getting fifo irq\n");
1760 err = -ENODEV;
1761 goto return_error;
1762 }
1763 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1764 omap_nand_irq, IRQF_SHARED,
1765 "gpmc-nand-fifo", info);
1766 if (err) {
1767 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1768 info->gpmc_irq_fifo, err);
1769 info->gpmc_irq_fifo = 0;
1770 goto return_error;
1771 }
1772
1773 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1774 if (info->gpmc_irq_count <= 0) {
1775 dev_err(&pdev->dev, "error getting count irq\n");
1776 err = -ENODEV;
1777 goto return_error;
1778 }
1779 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1780 omap_nand_irq, IRQF_SHARED,
1781 "gpmc-nand-count", info);
1782 if (err) {
1783 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1784 info->gpmc_irq_count, err);
1785 info->gpmc_irq_count = 0;
1786 goto return_error;
1787 }
1788
1789 nand_chip->read_buf = omap_read_buf_irq_pref;
1790 nand_chip->write_buf = omap_write_buf_irq_pref;
1791
1792 break;
1793
1794 default:
1795 dev_err(&pdev->dev,
1796 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1797 err = -EINVAL;
1798 goto return_error;
1799 }
1800
1801 /* populate MTD interface based on ECC scheme */
1802 nand_chip->ecc.layout = &omap_oobinfo;
1803 ecclayout = &omap_oobinfo;
1804 switch (info->ecc_opt) {
1805 case OMAP_ECC_HAM1_CODE_HW:
1806 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1807 nand_chip->ecc.mode = NAND_ECC_HW;
1808 nand_chip->ecc.bytes = 3;
1809 nand_chip->ecc.size = 512;
1810 nand_chip->ecc.strength = 1;
1811 nand_chip->ecc.calculate = omap_calculate_ecc;
1812 nand_chip->ecc.hwctl = omap_enable_hwecc;
1813 nand_chip->ecc.correct = omap_correct_data;
1814 /* define ECC layout */
1815 ecclayout->eccbytes = nand_chip->ecc.bytes *
1816 (mtd->writesize /
1817 nand_chip->ecc.size);
1818 if (nand_chip->options & NAND_BUSWIDTH_16)
1819 oob_index = BADBLOCK_MARKER_LENGTH;
1820 else
1821 oob_index = 1;
1822 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1823 ecclayout->eccpos[i] = oob_index;
1824 /* no reserved-marker in ecclayout for this ecc-scheme */
1825 ecclayout->oobfree->offset =
1826 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1827 break;
1828
1829 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1830 #ifdef CONFIG_MTD_NAND_ECC_BCH
1831 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1832 nand_chip->ecc.mode = NAND_ECC_HW;
1833 nand_chip->ecc.size = 512;
1834 nand_chip->ecc.bytes = 7;
1835 nand_chip->ecc.strength = 4;
1836 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1837 nand_chip->ecc.correct = nand_bch_correct_data;
1838 nand_chip->ecc.calculate = omap3_calculate_ecc_bch4;
1839 /* define ECC layout */
1840 ecclayout->eccbytes = nand_chip->ecc.bytes *
1841 (mtd->writesize /
1842 nand_chip->ecc.size);
1843 oob_index = BADBLOCK_MARKER_LENGTH;
1844 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1845 ecclayout->eccpos[i] = oob_index;
1846 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1847 oob_index++;
1848 }
1849 /* include reserved-marker in ecclayout->oobfree calculation */
1850 ecclayout->oobfree->offset = 1 +
1851 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1852 /* software bch library is used for locating errors */
1853 nand_chip->ecc.priv = nand_bch_init(mtd,
1854 nand_chip->ecc.size,
1855 nand_chip->ecc.bytes,
1856 &nand_chip->ecc.layout);
1857 if (!nand_chip->ecc.priv) {
1858 pr_err("nand: error: unable to use s/w BCH library\n");
1859 err = -EINVAL;
1860 }
1861 break;
1862 #else
1863 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1864 err = -EINVAL;
1865 goto return_error;
1866 #endif
1867
1868 case OMAP_ECC_BCH4_CODE_HW:
1869 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1870 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1871 nand_chip->ecc.mode = NAND_ECC_HW;
1872 nand_chip->ecc.size = 512;
1873 /* 14th bit is kept reserved for ROM-code compatibility */
1874 nand_chip->ecc.bytes = 7 + 1;
1875 nand_chip->ecc.strength = 4;
1876 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1877 nand_chip->ecc.correct = omap_elm_correct_data;
1878 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1879 nand_chip->ecc.read_page = omap_read_page_bch;
1880 nand_chip->ecc.write_page = omap_write_page_bch;
1881 /* define ECC layout */
1882 ecclayout->eccbytes = nand_chip->ecc.bytes *
1883 (mtd->writesize /
1884 nand_chip->ecc.size);
1885 oob_index = BADBLOCK_MARKER_LENGTH;
1886 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1887 ecclayout->eccpos[i] = oob_index;
1888 /* reserved marker already included in ecclayout->eccbytes */
1889 ecclayout->oobfree->offset =
1890 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1891 /* This ECC scheme requires ELM H/W block */
1892 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1893 pr_err("nand: error: could not initialize ELM\n");
1894 err = -ENODEV;
1895 goto return_error;
1896 }
1897 break;
1898 #else
1899 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1900 err = -EINVAL;
1901 goto return_error;
1902 #endif
1903
1904 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1905 #ifdef CONFIG_MTD_NAND_ECC_BCH
1906 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1907 nand_chip->ecc.mode = NAND_ECC_HW;
1908 nand_chip->ecc.size = 512;
1909 nand_chip->ecc.bytes = 13;
1910 nand_chip->ecc.strength = 8;
1911 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1912 nand_chip->ecc.correct = nand_bch_correct_data;
1913 nand_chip->ecc.calculate = omap3_calculate_ecc_bch8;
1914 /* define ECC layout */
1915 ecclayout->eccbytes = nand_chip->ecc.bytes *
1916 (mtd->writesize /
1917 nand_chip->ecc.size);
1918 oob_index = BADBLOCK_MARKER_LENGTH;
1919 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1920 ecclayout->eccpos[i] = oob_index;
1921 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1922 oob_index++;
1923 }
1924 /* include reserved-marker in ecclayout->oobfree calculation */
1925 ecclayout->oobfree->offset = 1 +
1926 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1927 /* software bch library is used for locating errors */
1928 nand_chip->ecc.priv = nand_bch_init(mtd,
1929 nand_chip->ecc.size,
1930 nand_chip->ecc.bytes,
1931 &nand_chip->ecc.layout);
1932 if (!nand_chip->ecc.priv) {
1933 pr_err("nand: error: unable to use s/w BCH library\n");
1934 err = -EINVAL;
1935 goto return_error;
1936 }
1937 break;
1938 #else
1939 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1940 err = -EINVAL;
1941 goto return_error;
1942 #endif
1943
1944 case OMAP_ECC_BCH8_CODE_HW:
1945 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1946 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1947 nand_chip->ecc.mode = NAND_ECC_HW;
1948 nand_chip->ecc.size = 512;
1949 /* 14th bit is kept reserved for ROM-code compatibility */
1950 nand_chip->ecc.bytes = 13 + 1;
1951 nand_chip->ecc.strength = 8;
1952 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1953 nand_chip->ecc.correct = omap_elm_correct_data;
1954 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1955 nand_chip->ecc.read_page = omap_read_page_bch;
1956 nand_chip->ecc.write_page = omap_write_page_bch;
1957 /* This ECC scheme requires ELM H/W block */
1958 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1959 if (err < 0) {
1960 pr_err("nand: error: could not initialize ELM\n");
1961 goto return_error;
1962 }
1963 /* define ECC layout */
1964 ecclayout->eccbytes = nand_chip->ecc.bytes *
1965 (mtd->writesize /
1966 nand_chip->ecc.size);
1967 oob_index = BADBLOCK_MARKER_LENGTH;
1968 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1969 ecclayout->eccpos[i] = oob_index;
1970 /* reserved marker already included in ecclayout->eccbytes */
1971 ecclayout->oobfree->offset =
1972 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1973 break;
1974 #else
1975 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1976 err = -EINVAL;
1977 goto return_error;
1978 #endif
1979
1980 default:
1981 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1982 err = -EINVAL;
1983 goto return_error;
1984 }
1985
1986 /* all OOB bytes from oobfree->offset till end off OOB are free */
1987 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1988 /* check if NAND device's OOB is enough to store ECC signatures */
1989 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1990 pr_err("not enough OOB bytes required = %d, available=%d\n",
1991 ecclayout->eccbytes, mtd->oobsize);
1992 err = -EINVAL;
1993 goto return_error;
1994 }
1995
1996 /* second phase scan */
1997 if (nand_scan_tail(mtd)) {
1998 err = -ENXIO;
1999 goto return_error;
2000 }
2001
2002 ppdata.of_node = pdata->of_node;
2003 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2004 pdata->nr_parts);
2005
2006 platform_set_drvdata(pdev, mtd);
2007
2008 return 0;
2009
2010 return_error:
2011 if (info->dma)
2012 dma_release_channel(info->dma);
2013 if (nand_chip->ecc.priv) {
2014 nand_bch_free(nand_chip->ecc.priv);
2015 nand_chip->ecc.priv = NULL;
2016 }
2017 return err;
2018 }
2019
2020 static int omap_nand_remove(struct platform_device *pdev)
2021 {
2022 struct mtd_info *mtd = platform_get_drvdata(pdev);
2023 struct nand_chip *nand_chip = mtd->priv;
2024 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2025 mtd);
2026 if (nand_chip->ecc.priv) {
2027 nand_bch_free(nand_chip->ecc.priv);
2028 nand_chip->ecc.priv = NULL;
2029 }
2030 if (info->dma)
2031 dma_release_channel(info->dma);
2032 nand_release(mtd);
2033 return 0;
2034 }
2035
2036 static struct platform_driver omap_nand_driver = {
2037 .probe = omap_nand_probe,
2038 .remove = omap_nand_remove,
2039 .driver = {
2040 .name = DRIVER_NAME,
2041 .owner = THIS_MODULE,
2042 },
2043 };
2044
2045 module_platform_driver(omap_nand_driver);
2046
2047 MODULE_ALIAS("platform:" DRIVER_NAME);
2048 MODULE_LICENSE("GPL");
2049 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux kernel - Deliverables
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