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mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix erased-page detection for...
[deliverable/linux.git] / drivers / mtd / nand / omap2.c
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/platform_data/mtd-nand-omap2.h>
32
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
35
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
48
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
61
62 #define TF(value) (value ? 1 : 0)
63
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
105 #define CS_MASK 0x7
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
112 #define ECC1 0x1
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
118
119 #define OMAP24XX_DMA_GPMC 4
120
121 #define BCH8_MAX_ERROR 8 /* upto 8 bit correctable */
122 #define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */
123
124 #define SECTOR_BYTES 512
125 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
126 #define BCH4_BIT_PAD 4
127 #define BCH8_ECC_MAX ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
128 #define BCH4_ECC_MAX ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
129
130 /* GPMC ecc engine settings for read */
131 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
132 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
133 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
134 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
135 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
136
137 /* GPMC ecc engine settings for write */
138 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
139 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
140 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
141
142 #define BADBLOCK_MARKER_LENGTH 2
143
144 #ifdef CONFIG_MTD_NAND_OMAP_BCH
145 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
146 0xac, 0x6b, 0xff, 0x99, 0x7b};
147 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
148 #endif
149
150 /* oob info generated runtime depending on ecc algorithm and layout selected */
151 static struct nand_ecclayout omap_oobinfo;
152
153 struct omap_nand_info {
154 struct nand_hw_control controller;
155 struct omap_nand_platform_data *pdata;
156 struct mtd_info mtd;
157 struct nand_chip nand;
158 struct platform_device *pdev;
159
160 int gpmc_cs;
161 unsigned long phys_base;
162 unsigned long mem_size;
163 enum omap_ecc ecc_opt;
164 struct completion comp;
165 struct dma_chan *dma;
166 int gpmc_irq_fifo;
167 int gpmc_irq_count;
168 enum {
169 OMAP_NAND_IO_READ = 0, /* read */
170 OMAP_NAND_IO_WRITE, /* write */
171 } iomode;
172 u_char *buf;
173 int buf_len;
174 struct gpmc_nand_regs reg;
175 /* fields specific for BCHx_HW ECC scheme */
176 bool is_elm_used;
177 struct device *elm_dev;
178 struct device_node *of_node;
179 };
180
181 /**
182 * omap_prefetch_enable - configures and starts prefetch transfer
183 * @cs: cs (chip select) number
184 * @fifo_th: fifo threshold to be used for read/ write
185 * @dma_mode: dma mode enable (1) or disable (0)
186 * @u32_count: number of bytes to be transferred
187 * @is_write: prefetch read(0) or write post(1) mode
188 */
189 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
190 unsigned int u32_count, int is_write, struct omap_nand_info *info)
191 {
192 u32 val;
193
194 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
195 return -1;
196
197 if (readl(info->reg.gpmc_prefetch_control))
198 return -EBUSY;
199
200 /* Set the amount of bytes to be prefetched */
201 writel(u32_count, info->reg.gpmc_prefetch_config2);
202
203 /* Set dma/mpu mode, the prefetch read / post write and
204 * enable the engine. Set which cs is has requested for.
205 */
206 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
207 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
208 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
209 writel(val, info->reg.gpmc_prefetch_config1);
210
211 /* Start the prefetch engine */
212 writel(0x1, info->reg.gpmc_prefetch_control);
213
214 return 0;
215 }
216
217 /**
218 * omap_prefetch_reset - disables and stops the prefetch engine
219 */
220 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
221 {
222 u32 config1;
223
224 /* check if the same module/cs is trying to reset */
225 config1 = readl(info->reg.gpmc_prefetch_config1);
226 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
227 return -EINVAL;
228
229 /* Stop the PFPW engine */
230 writel(0x0, info->reg.gpmc_prefetch_control);
231
232 /* Reset/disable the PFPW engine */
233 writel(0x0, info->reg.gpmc_prefetch_config1);
234
235 return 0;
236 }
237
238 /**
239 * omap_hwcontrol - hardware specific access to control-lines
240 * @mtd: MTD device structure
241 * @cmd: command to device
242 * @ctrl:
243 * NAND_NCE: bit 0 -> don't care
244 * NAND_CLE: bit 1 -> Command Latch
245 * NAND_ALE: bit 2 -> Address Latch
246 *
247 * NOTE: boards may use different bits for these!!
248 */
249 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
250 {
251 struct omap_nand_info *info = container_of(mtd,
252 struct omap_nand_info, mtd);
253
254 if (cmd != NAND_CMD_NONE) {
255 if (ctrl & NAND_CLE)
256 writeb(cmd, info->reg.gpmc_nand_command);
257
258 else if (ctrl & NAND_ALE)
259 writeb(cmd, info->reg.gpmc_nand_address);
260
261 else /* NAND_NCE */
262 writeb(cmd, info->reg.gpmc_nand_data);
263 }
264 }
265
266 /**
267 * omap_read_buf8 - read data from NAND controller into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
271 */
272 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
273 {
274 struct nand_chip *nand = mtd->priv;
275
276 ioread8_rep(nand->IO_ADDR_R, buf, len);
277 }
278
279 /**
280 * omap_write_buf8 - write buffer to NAND controller
281 * @mtd: MTD device structure
282 * @buf: data buffer
283 * @len: number of bytes to write
284 */
285 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
286 {
287 struct omap_nand_info *info = container_of(mtd,
288 struct omap_nand_info, mtd);
289 u_char *p = (u_char *)buf;
290 u32 status = 0;
291
292 while (len--) {
293 iowrite8(*p++, info->nand.IO_ADDR_W);
294 /* wait until buffer is available for write */
295 do {
296 status = readl(info->reg.gpmc_status) &
297 STATUS_BUFF_EMPTY;
298 } while (!status);
299 }
300 }
301
302 /**
303 * omap_read_buf16 - read data from NAND controller into buffer
304 * @mtd: MTD device structure
305 * @buf: buffer to store date
306 * @len: number of bytes to read
307 */
308 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
309 {
310 struct nand_chip *nand = mtd->priv;
311
312 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
313 }
314
315 /**
316 * omap_write_buf16 - write buffer to NAND controller
317 * @mtd: MTD device structure
318 * @buf: data buffer
319 * @len: number of bytes to write
320 */
321 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
322 {
323 struct omap_nand_info *info = container_of(mtd,
324 struct omap_nand_info, mtd);
325 u16 *p = (u16 *) buf;
326 u32 status = 0;
327 /* FIXME try bursts of writesw() or DMA ... */
328 len >>= 1;
329
330 while (len--) {
331 iowrite16(*p++, info->nand.IO_ADDR_W);
332 /* wait until buffer is available for write */
333 do {
334 status = readl(info->reg.gpmc_status) &
335 STATUS_BUFF_EMPTY;
336 } while (!status);
337 }
338 }
339
340 /**
341 * omap_read_buf_pref - read data from NAND controller into buffer
342 * @mtd: MTD device structure
343 * @buf: buffer to store date
344 * @len: number of bytes to read
345 */
346 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
347 {
348 struct omap_nand_info *info = container_of(mtd,
349 struct omap_nand_info, mtd);
350 uint32_t r_count = 0;
351 int ret = 0;
352 u32 *p = (u32 *)buf;
353
354 /* take care of subpage reads */
355 if (len % 4) {
356 if (info->nand.options & NAND_BUSWIDTH_16)
357 omap_read_buf16(mtd, buf, len % 4);
358 else
359 omap_read_buf8(mtd, buf, len % 4);
360 p = (u32 *) (buf + len % 4);
361 len -= len % 4;
362 }
363
364 /* configure and start prefetch transfer */
365 ret = omap_prefetch_enable(info->gpmc_cs,
366 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
367 if (ret) {
368 /* PFPW engine is busy, use cpu copy method */
369 if (info->nand.options & NAND_BUSWIDTH_16)
370 omap_read_buf16(mtd, (u_char *)p, len);
371 else
372 omap_read_buf8(mtd, (u_char *)p, len);
373 } else {
374 do {
375 r_count = readl(info->reg.gpmc_prefetch_status);
376 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
377 r_count = r_count >> 2;
378 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
379 p += r_count;
380 len -= r_count << 2;
381 } while (len);
382 /* disable and stop the PFPW engine */
383 omap_prefetch_reset(info->gpmc_cs, info);
384 }
385 }
386
387 /**
388 * omap_write_buf_pref - write buffer to NAND controller
389 * @mtd: MTD device structure
390 * @buf: data buffer
391 * @len: number of bytes to write
392 */
393 static void omap_write_buf_pref(struct mtd_info *mtd,
394 const u_char *buf, int len)
395 {
396 struct omap_nand_info *info = container_of(mtd,
397 struct omap_nand_info, mtd);
398 uint32_t w_count = 0;
399 int i = 0, ret = 0;
400 u16 *p = (u16 *)buf;
401 unsigned long tim, limit;
402 u32 val;
403
404 /* take care of subpage writes */
405 if (len % 2 != 0) {
406 writeb(*buf, info->nand.IO_ADDR_W);
407 p = (u16 *)(buf + 1);
408 len--;
409 }
410
411 /* configure and start prefetch transfer */
412 ret = omap_prefetch_enable(info->gpmc_cs,
413 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
414 if (ret) {
415 /* PFPW engine is busy, use cpu copy method */
416 if (info->nand.options & NAND_BUSWIDTH_16)
417 omap_write_buf16(mtd, (u_char *)p, len);
418 else
419 omap_write_buf8(mtd, (u_char *)p, len);
420 } else {
421 while (len) {
422 w_count = readl(info->reg.gpmc_prefetch_status);
423 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
424 w_count = w_count >> 1;
425 for (i = 0; (i < w_count) && len; i++, len -= 2)
426 iowrite16(*p++, info->nand.IO_ADDR_W);
427 }
428 /* wait for data to flushed-out before reset the prefetch */
429 tim = 0;
430 limit = (loops_per_jiffy *
431 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
432 do {
433 cpu_relax();
434 val = readl(info->reg.gpmc_prefetch_status);
435 val = PREFETCH_STATUS_COUNT(val);
436 } while (val && (tim++ < limit));
437
438 /* disable and stop the PFPW engine */
439 omap_prefetch_reset(info->gpmc_cs, info);
440 }
441 }
442
443 /*
444 * omap_nand_dma_callback: callback on the completion of dma transfer
445 * @data: pointer to completion data structure
446 */
447 static void omap_nand_dma_callback(void *data)
448 {
449 complete((struct completion *) data);
450 }
451
452 /*
453 * omap_nand_dma_transfer: configure and start dma transfer
454 * @mtd: MTD device structure
455 * @addr: virtual address in RAM of source/destination
456 * @len: number of data bytes to be transferred
457 * @is_write: flag for read/write operation
458 */
459 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
460 unsigned int len, int is_write)
461 {
462 struct omap_nand_info *info = container_of(mtd,
463 struct omap_nand_info, mtd);
464 struct dma_async_tx_descriptor *tx;
465 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
466 DMA_FROM_DEVICE;
467 struct scatterlist sg;
468 unsigned long tim, limit;
469 unsigned n;
470 int ret;
471 u32 val;
472
473 if (addr >= high_memory) {
474 struct page *p1;
475
476 if (((size_t)addr & PAGE_MASK) !=
477 ((size_t)(addr + len - 1) & PAGE_MASK))
478 goto out_copy;
479 p1 = vmalloc_to_page(addr);
480 if (!p1)
481 goto out_copy;
482 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
483 }
484
485 sg_init_one(&sg, addr, len);
486 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
487 if (n == 0) {
488 dev_err(&info->pdev->dev,
489 "Couldn't DMA map a %d byte buffer\n", len);
490 goto out_copy;
491 }
492
493 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
494 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
496 if (!tx)
497 goto out_copy_unmap;
498
499 tx->callback = omap_nand_dma_callback;
500 tx->callback_param = &info->comp;
501 dmaengine_submit(tx);
502
503 /* configure and start prefetch transfer */
504 ret = omap_prefetch_enable(info->gpmc_cs,
505 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
506 if (ret)
507 /* PFPW engine is busy, use cpu copy method */
508 goto out_copy_unmap;
509
510 init_completion(&info->comp);
511 dma_async_issue_pending(info->dma);
512
513 /* setup and start DMA using dma_addr */
514 wait_for_completion(&info->comp);
515 tim = 0;
516 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
517
518 do {
519 cpu_relax();
520 val = readl(info->reg.gpmc_prefetch_status);
521 val = PREFETCH_STATUS_COUNT(val);
522 } while (val && (tim++ < limit));
523
524 /* disable and stop the PFPW engine */
525 omap_prefetch_reset(info->gpmc_cs, info);
526
527 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
528 return 0;
529
530 out_copy_unmap:
531 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
532 out_copy:
533 if (info->nand.options & NAND_BUSWIDTH_16)
534 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
535 : omap_write_buf16(mtd, (u_char *) addr, len);
536 else
537 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
538 : omap_write_buf8(mtd, (u_char *) addr, len);
539 return 0;
540 }
541
542 /**
543 * omap_read_buf_dma_pref - read data from NAND controller into buffer
544 * @mtd: MTD device structure
545 * @buf: buffer to store date
546 * @len: number of bytes to read
547 */
548 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
549 {
550 if (len <= mtd->oobsize)
551 omap_read_buf_pref(mtd, buf, len);
552 else
553 /* start transfer in DMA mode */
554 omap_nand_dma_transfer(mtd, buf, len, 0x0);
555 }
556
557 /**
558 * omap_write_buf_dma_pref - write buffer to NAND controller
559 * @mtd: MTD device structure
560 * @buf: data buffer
561 * @len: number of bytes to write
562 */
563 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
564 const u_char *buf, int len)
565 {
566 if (len <= mtd->oobsize)
567 omap_write_buf_pref(mtd, buf, len);
568 else
569 /* start transfer in DMA mode */
570 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
571 }
572
573 /*
574 * omap_nand_irq - GPMC irq handler
575 * @this_irq: gpmc irq number
576 * @dev: omap_nand_info structure pointer is passed here
577 */
578 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
579 {
580 struct omap_nand_info *info = (struct omap_nand_info *) dev;
581 u32 bytes;
582
583 bytes = readl(info->reg.gpmc_prefetch_status);
584 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
585 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
586 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
587 if (this_irq == info->gpmc_irq_count)
588 goto done;
589
590 if (info->buf_len && (info->buf_len < bytes))
591 bytes = info->buf_len;
592 else if (!info->buf_len)
593 bytes = 0;
594 iowrite32_rep(info->nand.IO_ADDR_W,
595 (u32 *)info->buf, bytes >> 2);
596 info->buf = info->buf + bytes;
597 info->buf_len -= bytes;
598
599 } else {
600 ioread32_rep(info->nand.IO_ADDR_R,
601 (u32 *)info->buf, bytes >> 2);
602 info->buf = info->buf + bytes;
603
604 if (this_irq == info->gpmc_irq_count)
605 goto done;
606 }
607
608 return IRQ_HANDLED;
609
610 done:
611 complete(&info->comp);
612
613 disable_irq_nosync(info->gpmc_irq_fifo);
614 disable_irq_nosync(info->gpmc_irq_count);
615
616 return IRQ_HANDLED;
617 }
618
619 /*
620 * omap_read_buf_irq_pref - read data from NAND controller into buffer
621 * @mtd: MTD device structure
622 * @buf: buffer to store date
623 * @len: number of bytes to read
624 */
625 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
626 {
627 struct omap_nand_info *info = container_of(mtd,
628 struct omap_nand_info, mtd);
629 int ret = 0;
630
631 if (len <= mtd->oobsize) {
632 omap_read_buf_pref(mtd, buf, len);
633 return;
634 }
635
636 info->iomode = OMAP_NAND_IO_READ;
637 info->buf = buf;
638 init_completion(&info->comp);
639
640 /* configure and start prefetch transfer */
641 ret = omap_prefetch_enable(info->gpmc_cs,
642 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
643 if (ret)
644 /* PFPW engine is busy, use cpu copy method */
645 goto out_copy;
646
647 info->buf_len = len;
648
649 enable_irq(info->gpmc_irq_count);
650 enable_irq(info->gpmc_irq_fifo);
651
652 /* waiting for read to complete */
653 wait_for_completion(&info->comp);
654
655 /* disable and stop the PFPW engine */
656 omap_prefetch_reset(info->gpmc_cs, info);
657 return;
658
659 out_copy:
660 if (info->nand.options & NAND_BUSWIDTH_16)
661 omap_read_buf16(mtd, buf, len);
662 else
663 omap_read_buf8(mtd, buf, len);
664 }
665
666 /*
667 * omap_write_buf_irq_pref - write buffer to NAND controller
668 * @mtd: MTD device structure
669 * @buf: data buffer
670 * @len: number of bytes to write
671 */
672 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
673 const u_char *buf, int len)
674 {
675 struct omap_nand_info *info = container_of(mtd,
676 struct omap_nand_info, mtd);
677 int ret = 0;
678 unsigned long tim, limit;
679 u32 val;
680
681 if (len <= mtd->oobsize) {
682 omap_write_buf_pref(mtd, buf, len);
683 return;
684 }
685
686 info->iomode = OMAP_NAND_IO_WRITE;
687 info->buf = (u_char *) buf;
688 init_completion(&info->comp);
689
690 /* configure and start prefetch transfer : size=24 */
691 ret = omap_prefetch_enable(info->gpmc_cs,
692 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
693 if (ret)
694 /* PFPW engine is busy, use cpu copy method */
695 goto out_copy;
696
697 info->buf_len = len;
698
699 enable_irq(info->gpmc_irq_count);
700 enable_irq(info->gpmc_irq_fifo);
701
702 /* waiting for write to complete */
703 wait_for_completion(&info->comp);
704
705 /* wait for data to flushed-out before reset the prefetch */
706 tim = 0;
707 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
708 do {
709 val = readl(info->reg.gpmc_prefetch_status);
710 val = PREFETCH_STATUS_COUNT(val);
711 cpu_relax();
712 } while (val && (tim++ < limit));
713
714 /* disable and stop the PFPW engine */
715 omap_prefetch_reset(info->gpmc_cs, info);
716 return;
717
718 out_copy:
719 if (info->nand.options & NAND_BUSWIDTH_16)
720 omap_write_buf16(mtd, buf, len);
721 else
722 omap_write_buf8(mtd, buf, len);
723 }
724
725 /**
726 * gen_true_ecc - This function will generate true ECC value
727 * @ecc_buf: buffer to store ecc code
728 *
729 * This generated true ECC value can be used when correcting
730 * data read from NAND flash memory core
731 */
732 static void gen_true_ecc(u8 *ecc_buf)
733 {
734 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
735 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
736
737 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
738 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
739 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
740 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
741 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
742 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
743 }
744
745 /**
746 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
747 * @ecc_data1: ecc code from nand spare area
748 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
749 * @page_data: page data
750 *
751 * This function compares two ECC's and indicates if there is an error.
752 * If the error can be corrected it will be corrected to the buffer.
753 * If there is no error, %0 is returned. If there is an error but it
754 * was corrected, %1 is returned. Otherwise, %-1 is returned.
755 */
756 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
757 u8 *ecc_data2, /* read from register */
758 u8 *page_data)
759 {
760 uint i;
761 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
762 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
763 u8 ecc_bit[24];
764 u8 ecc_sum = 0;
765 u8 find_bit = 0;
766 uint find_byte = 0;
767 int isEccFF;
768
769 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
770
771 gen_true_ecc(ecc_data1);
772 gen_true_ecc(ecc_data2);
773
774 for (i = 0; i <= 2; i++) {
775 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
776 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
777 }
778
779 for (i = 0; i < 8; i++) {
780 tmp0_bit[i] = *ecc_data1 % 2;
781 *ecc_data1 = *ecc_data1 / 2;
782 }
783
784 for (i = 0; i < 8; i++) {
785 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
786 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
787 }
788
789 for (i = 0; i < 8; i++) {
790 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
791 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
792 }
793
794 for (i = 0; i < 8; i++) {
795 comp0_bit[i] = *ecc_data2 % 2;
796 *ecc_data2 = *ecc_data2 / 2;
797 }
798
799 for (i = 0; i < 8; i++) {
800 comp1_bit[i] = *(ecc_data2 + 1) % 2;
801 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
802 }
803
804 for (i = 0; i < 8; i++) {
805 comp2_bit[i] = *(ecc_data2 + 2) % 2;
806 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
807 }
808
809 for (i = 0; i < 6; i++)
810 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
811
812 for (i = 0; i < 8; i++)
813 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
814
815 for (i = 0; i < 8; i++)
816 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
817
818 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
819 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
820
821 for (i = 0; i < 24; i++)
822 ecc_sum += ecc_bit[i];
823
824 switch (ecc_sum) {
825 case 0:
826 /* Not reached because this function is not called if
827 * ECC values are equal
828 */
829 return 0;
830
831 case 1:
832 /* Uncorrectable error */
833 pr_debug("ECC UNCORRECTED_ERROR 1\n");
834 return -1;
835
836 case 11:
837 /* UN-Correctable error */
838 pr_debug("ECC UNCORRECTED_ERROR B\n");
839 return -1;
840
841 case 12:
842 /* Correctable error */
843 find_byte = (ecc_bit[23] << 8) +
844 (ecc_bit[21] << 7) +
845 (ecc_bit[19] << 6) +
846 (ecc_bit[17] << 5) +
847 (ecc_bit[15] << 4) +
848 (ecc_bit[13] << 3) +
849 (ecc_bit[11] << 2) +
850 (ecc_bit[9] << 1) +
851 ecc_bit[7];
852
853 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
854
855 pr_debug("Correcting single bit ECC error at offset: "
856 "%d, bit: %d\n", find_byte, find_bit);
857
858 page_data[find_byte] ^= (1 << find_bit);
859
860 return 1;
861 default:
862 if (isEccFF) {
863 if (ecc_data2[0] == 0 &&
864 ecc_data2[1] == 0 &&
865 ecc_data2[2] == 0)
866 return 0;
867 }
868 pr_debug("UNCORRECTED_ERROR default\n");
869 return -1;
870 }
871 }
872
873 /**
874 * omap_correct_data - Compares the ECC read with HW generated ECC
875 * @mtd: MTD device structure
876 * @dat: page data
877 * @read_ecc: ecc read from nand flash
878 * @calc_ecc: ecc read from HW ECC registers
879 *
880 * Compares the ecc read from nand spare area with ECC registers values
881 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
882 * detection and correction. If there are no errors, %0 is returned. If
883 * there were errors and all of the errors were corrected, the number of
884 * corrected errors is returned. If uncorrectable errors exist, %-1 is
885 * returned.
886 */
887 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
888 u_char *read_ecc, u_char *calc_ecc)
889 {
890 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
891 mtd);
892 int blockCnt = 0, i = 0, ret = 0;
893 int stat = 0;
894
895 /* Ex NAND_ECC_HW12_2048 */
896 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
897 (info->nand.ecc.size == 2048))
898 blockCnt = 4;
899 else
900 blockCnt = 1;
901
902 for (i = 0; i < blockCnt; i++) {
903 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
904 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
905 if (ret < 0)
906 return ret;
907 /* keep track of the number of corrected errors */
908 stat += ret;
909 }
910 read_ecc += 3;
911 calc_ecc += 3;
912 dat += 512;
913 }
914 return stat;
915 }
916
917 /**
918 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
919 * @mtd: MTD device structure
920 * @dat: The pointer to data on which ecc is computed
921 * @ecc_code: The ecc_code buffer
922 *
923 * Using noninverted ECC can be considered ugly since writing a blank
924 * page ie. padding will clear the ECC bytes. This is no problem as long
925 * nobody is trying to write data on the seemingly unused page. Reading
926 * an erased page will produce an ECC mismatch between generated and read
927 * ECC bytes that has to be dealt with separately.
928 */
929 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
930 u_char *ecc_code)
931 {
932 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
933 mtd);
934 u32 val;
935
936 val = readl(info->reg.gpmc_ecc_config);
937 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
938 return -EINVAL;
939
940 /* read ecc result */
941 val = readl(info->reg.gpmc_ecc1_result);
942 *ecc_code++ = val; /* P128e, ..., P1e */
943 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
944 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
945 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
946
947 return 0;
948 }
949
950 /**
951 * omap_enable_hwecc - This function enables the hardware ecc functionality
952 * @mtd: MTD device structure
953 * @mode: Read/Write mode
954 */
955 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
956 {
957 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
958 mtd);
959 struct nand_chip *chip = mtd->priv;
960 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
961 u32 val;
962
963 /* clear ecc and enable bits */
964 val = ECCCLEAR | ECC1;
965 writel(val, info->reg.gpmc_ecc_control);
966
967 /* program ecc and result sizes */
968 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
969 ECC1RESULTSIZE);
970 writel(val, info->reg.gpmc_ecc_size_config);
971
972 switch (mode) {
973 case NAND_ECC_READ:
974 case NAND_ECC_WRITE:
975 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
976 break;
977 case NAND_ECC_READSYN:
978 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
979 break;
980 default:
981 dev_info(&info->pdev->dev,
982 "error: unrecognized Mode[%d]!\n", mode);
983 break;
984 }
985
986 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
987 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
988 writel(val, info->reg.gpmc_ecc_config);
989 }
990
991 /**
992 * omap_wait - wait until the command is done
993 * @mtd: MTD device structure
994 * @chip: NAND Chip structure
995 *
996 * Wait function is called during Program and erase operations and
997 * the way it is called from MTD layer, we should wait till the NAND
998 * chip is ready after the programming/erase operation has completed.
999 *
1000 * Erase can take up to 400ms and program up to 20ms according to
1001 * general NAND and SmartMedia specs
1002 */
1003 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1004 {
1005 struct nand_chip *this = mtd->priv;
1006 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1007 mtd);
1008 unsigned long timeo = jiffies;
1009 int status, state = this->state;
1010
1011 if (state == FL_ERASING)
1012 timeo += msecs_to_jiffies(400);
1013 else
1014 timeo += msecs_to_jiffies(20);
1015
1016 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1017 while (time_before(jiffies, timeo)) {
1018 status = readb(info->reg.gpmc_nand_data);
1019 if (status & NAND_STATUS_READY)
1020 break;
1021 cond_resched();
1022 }
1023
1024 status = readb(info->reg.gpmc_nand_data);
1025 return status;
1026 }
1027
1028 /**
1029 * omap_dev_ready - calls the platform specific dev_ready function
1030 * @mtd: MTD device structure
1031 */
1032 static int omap_dev_ready(struct mtd_info *mtd)
1033 {
1034 unsigned int val = 0;
1035 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1036 mtd);
1037
1038 val = readl(info->reg.gpmc_status);
1039
1040 if ((val & 0x100) == 0x100) {
1041 return 1;
1042 } else {
1043 return 0;
1044 }
1045 }
1046
1047 #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
1048 /**
1049 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1050 * @mtd: MTD device structure
1051 * @mode: Read/Write mode
1052 *
1053 * When using BCH, sector size is hardcoded to 512 bytes.
1054 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1055 * for error correction.
1056 * On writing,
1057 * eccsize0 = 0 (no additional protected byte in spare area)
1058 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1059 */
1060 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1061 {
1062 int nerrors;
1063 unsigned int dev_width, nsectors;
1064 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1065 mtd);
1066 struct nand_chip *chip = mtd->priv;
1067 u32 val, wr_mode;
1068 unsigned int ecc_size1, ecc_size0;
1069
1070 /* Using wrapping mode 6 for writing */
1071 wr_mode = BCH_WRAPMODE_6;
1072
1073 /*
1074 * ECC engine enabled for valid ecc_size0 nibbles
1075 * and disabled for ecc_size1 nibbles.
1076 */
1077 ecc_size0 = BCH_ECC_SIZE0;
1078 ecc_size1 = BCH_ECC_SIZE1;
1079
1080 /* Perform ecc calculation on 512-byte sector */
1081 nsectors = 1;
1082
1083 /* Update number of error correction */
1084 nerrors = info->nand.ecc.strength;
1085
1086 /* Multi sector reading/writing for NAND flash with page size < 4096 */
1087 if (info->is_elm_used && (mtd->writesize <= 4096)) {
1088 if (mode == NAND_ECC_READ) {
1089 /* Using wrapping mode 1 for reading */
1090 wr_mode = BCH_WRAPMODE_1;
1091
1092 /*
1093 * ECC engine enabled for ecc_size0 nibbles
1094 * and disabled for ecc_size1 nibbles.
1095 */
1096 ecc_size0 = (nerrors == 8) ?
1097 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1098 ecc_size1 = (nerrors == 8) ?
1099 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1100 }
1101
1102 /* Perform ecc calculation for one page (< 4096) */
1103 nsectors = info->nand.ecc.steps;
1104 }
1105
1106 writel(ECC1, info->reg.gpmc_ecc_control);
1107
1108 /* Configure ecc size for BCH */
1109 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1110 writel(val, info->reg.gpmc_ecc_size_config);
1111
1112 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1113
1114 /* BCH configuration */
1115 val = ((1 << 16) | /* enable BCH */
1116 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1117 (wr_mode << 8) | /* wrap mode */
1118 (dev_width << 7) | /* bus width */
1119 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1120 (info->gpmc_cs << 1) | /* ECC CS */
1121 (0x1)); /* enable ECC */
1122
1123 writel(val, info->reg.gpmc_ecc_config);
1124
1125 /* Clear ecc and enable bits */
1126 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1127 }
1128 #endif
1129
1130 #ifdef CONFIG_MTD_NAND_ECC_BCH
1131 /**
1132 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1133 * @mtd: MTD device structure
1134 * @dat: The pointer to data on which ecc is computed
1135 * @ecc_code: The ecc_code buffer
1136 */
1137 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1138 u_char *ecc_code)
1139 {
1140 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1141 mtd);
1142 unsigned long nsectors, val1, val2;
1143 int i;
1144
1145 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1146
1147 for (i = 0; i < nsectors; i++) {
1148
1149 /* Read hw-computed remainder */
1150 val1 = readl(info->reg.gpmc_bch_result0[i]);
1151 val2 = readl(info->reg.gpmc_bch_result1[i]);
1152
1153 /*
1154 * Add constant polynomial to remainder, in order to get an ecc
1155 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1156 * left-justify the resulting polynomial.
1157 */
1158 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1159 *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1160 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1161 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1162 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1163 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1164 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1165 }
1166
1167 return 0;
1168 }
1169
1170 /**
1171 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1172 * @mtd: MTD device structure
1173 * @dat: The pointer to data on which ecc is computed
1174 * @ecc_code: The ecc_code buffer
1175 */
1176 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1177 u_char *ecc_code)
1178 {
1179 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1180 mtd);
1181 unsigned long nsectors, val1, val2, val3, val4;
1182 int i;
1183
1184 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1185
1186 for (i = 0; i < nsectors; i++) {
1187
1188 /* Read hw-computed remainder */
1189 val1 = readl(info->reg.gpmc_bch_result0[i]);
1190 val2 = readl(info->reg.gpmc_bch_result1[i]);
1191 val3 = readl(info->reg.gpmc_bch_result2[i]);
1192 val4 = readl(info->reg.gpmc_bch_result3[i]);
1193
1194 /*
1195 * Add constant polynomial to remainder, in order to get an ecc
1196 * sequence of 0xFFs for a buffer filled with 0xFFs.
1197 */
1198 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1199 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1200 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1201 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1202 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1203 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1204 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1205 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1206 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1207 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1208 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1209 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1210 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1211 }
1212
1213 return 0;
1214 }
1215 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1216
1217 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1218 /**
1219 * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
1220 * @mtd: MTD device structure
1221 * @dat: The pointer to data on which ecc is computed
1222 * @ecc_code: The ecc_code buffer
1223 *
1224 * Support calculating of BCH4/8 ecc vectors for the page
1225 */
1226 static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
1227 u_char *ecc_code)
1228 {
1229 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1230 mtd);
1231 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1232 int i, eccbchtsel;
1233
1234 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1235 /*
1236 * find BCH scheme used
1237 * 0 -> BCH4
1238 * 1 -> BCH8
1239 */
1240 eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
1241
1242 for (i = 0; i < nsectors; i++) {
1243
1244 /* Read hw-computed remainder */
1245 bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
1246 bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
1247 if (eccbchtsel) {
1248 bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
1249 bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
1250 }
1251
1252 if (eccbchtsel) {
1253 /* BCH8 ecc scheme */
1254 *ecc_code++ = (bch_val4 & 0xFF);
1255 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1256 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1257 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1258 *ecc_code++ = (bch_val3 & 0xFF);
1259 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1260 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1261 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1262 *ecc_code++ = (bch_val2 & 0xFF);
1263 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1264 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1265 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1266 *ecc_code++ = (bch_val1 & 0xFF);
1267 /*
1268 * Setting 14th byte to zero to handle
1269 * erased page & maintain compatibility
1270 * with RBL
1271 */
1272 *ecc_code++ = 0x0;
1273 } else {
1274 /* BCH4 ecc scheme */
1275 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1276 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1277 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1278 ((bch_val1 >> 28) & 0xF);
1279 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1280 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1281 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1282 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1283 /*
1284 * Setting 8th byte to zero to handle
1285 * erased page
1286 */
1287 *ecc_code++ = 0x0;
1288 }
1289 }
1290
1291 return 0;
1292 }
1293
1294 /**
1295 * erased_sector_bitflips - count bit flips
1296 * @data: data sector buffer
1297 * @oob: oob buffer
1298 * @info: omap_nand_info
1299 *
1300 * Check the bit flips in erased page falls below correctable level.
1301 * If falls below, report the page as erased with correctable bit
1302 * flip, else report as uncorrectable page.
1303 */
1304 static int erased_sector_bitflips(u_char *data, u_char *oob,
1305 struct omap_nand_info *info)
1306 {
1307 int flip_bits = 0, i;
1308
1309 for (i = 0; i < info->nand.ecc.size; i++) {
1310 flip_bits += hweight8(~data[i]);
1311 if (flip_bits > info->nand.ecc.strength)
1312 return 0;
1313 }
1314
1315 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1316 flip_bits += hweight8(~oob[i]);
1317 if (flip_bits > info->nand.ecc.strength)
1318 return 0;
1319 }
1320
1321 /*
1322 * Bit flips falls in correctable level.
1323 * Fill data area with 0xFF
1324 */
1325 if (flip_bits) {
1326 memset(data, 0xFF, info->nand.ecc.size);
1327 memset(oob, 0xFF, info->nand.ecc.bytes);
1328 }
1329
1330 return flip_bits;
1331 }
1332
1333 /**
1334 * omap_elm_correct_data - corrects page data area in case error reported
1335 * @mtd: MTD device structure
1336 * @data: page data
1337 * @read_ecc: ecc read from nand flash
1338 * @calc_ecc: ecc read from HW ECC registers
1339 *
1340 * Calculated ecc vector reported as zero in case of non-error pages.
1341 * In case of non-zero ecc vector, first filter out erased-pages, and
1342 * then process data via ELM to detect bit-flips.
1343 */
1344 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1345 u_char *read_ecc, u_char *calc_ecc)
1346 {
1347 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1348 mtd);
1349 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1350 int eccsteps = info->nand.ecc.steps;
1351 int i , j, stat = 0;
1352 int eccflag, actual_eccbytes;
1353 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1354 u_char *ecc_vec = calc_ecc;
1355 u_char *spare_ecc = read_ecc;
1356 u_char *erased_ecc_vec;
1357 u_char *buf;
1358 int bitflip_count;
1359 enum bch_ecc type;
1360 bool is_error_reported = false;
1361
1362 switch (info->ecc_opt) {
1363 case OMAP_ECC_BCH4_CODE_HW:
1364 /* omit 7th ECC byte reserved for ROM code compatibility */
1365 actual_eccbytes = ecc->bytes - 1;
1366 erased_ecc_vec = bch4_vector;
1367 break;
1368 case OMAP_ECC_BCH8_CODE_HW:
1369 /* omit 14th ECC byte reserved for ROM code compatibility */
1370 actual_eccbytes = ecc->bytes - 1;
1371 erased_ecc_vec = bch8_vector;
1372 break;
1373 default:
1374 pr_err("invalid driver configuration\n");
1375 return -EINVAL;
1376 }
1377
1378 /* Initialize elm error vector to zero */
1379 memset(err_vec, 0, sizeof(err_vec));
1380
1381 if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
1382 type = BCH8_ECC;
1383 } else {
1384 type = BCH4_ECC;
1385 }
1386
1387 for (i = 0; i < eccsteps ; i++) {
1388 eccflag = 0; /* initialize eccflag */
1389
1390 /*
1391 * Check any error reported,
1392 * In case of error, non zero ecc reported.
1393 */
1394 for (j = 0; j < actual_eccbytes; j++) {
1395 if (calc_ecc[j] != 0) {
1396 eccflag = 1; /* non zero ecc, error present */
1397 break;
1398 }
1399 }
1400
1401 if (eccflag == 1) {
1402 if (memcmp(calc_ecc, erased_ecc_vec,
1403 actual_eccbytes) == 0) {
1404 /*
1405 * calc_ecc[] matches pattern for ECC(all 0xff)
1406 * so this is definitely an erased-page
1407 */
1408 } else {
1409 buf = &data[info->nand.ecc.size * i];
1410 /*
1411 * count number of 0-bits in read_buf.
1412 * This check can be removed once a similar
1413 * check is introduced in generic NAND driver
1414 */
1415 bitflip_count = erased_sector_bitflips(
1416 buf, read_ecc, info);
1417 if (bitflip_count) {
1418 /*
1419 * number of 0-bits within ECC limits
1420 * So this may be an erased-page
1421 */
1422 stat += bitflip_count;
1423 } else {
1424 /*
1425 * Too many 0-bits. It may be a
1426 * - programmed-page, OR
1427 * - erased-page with many bit-flips
1428 * So this page requires check by ELM
1429 */
1430 err_vec[i].error_reported = true;
1431 is_error_reported = true;
1432 }
1433 }
1434 }
1435
1436 /* Update the ecc vector */
1437 calc_ecc += ecc->bytes;
1438 read_ecc += ecc->bytes;
1439 }
1440
1441 /* Check if any error reported */
1442 if (!is_error_reported)
1443 return 0;
1444
1445 /* Decode BCH error using ELM module */
1446 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1447
1448 for (i = 0; i < eccsteps; i++) {
1449 if (err_vec[i].error_reported) {
1450 for (j = 0; j < err_vec[i].error_count; j++) {
1451 u32 bit_pos, byte_pos, error_max, pos;
1452
1453 if (type == BCH8_ECC)
1454 error_max = BCH8_ECC_MAX;
1455 else
1456 error_max = BCH4_ECC_MAX;
1457
1458 if (info->nand.ecc.strength == BCH8_MAX_ERROR)
1459 pos = err_vec[i].error_loc[j];
1460 else
1461 /* Add 4 to take care 4 bit padding */
1462 pos = err_vec[i].error_loc[j] +
1463 BCH4_BIT_PAD;
1464
1465 /* Calculate bit position of error */
1466 bit_pos = pos % 8;
1467
1468 /* Calculate byte position of error */
1469 byte_pos = (error_max - pos - 1) / 8;
1470
1471 if (pos < error_max) {
1472 if (byte_pos < 512)
1473 data[byte_pos] ^= 1 << bit_pos;
1474 else
1475 spare_ecc[byte_pos - 512] ^=
1476 1 << bit_pos;
1477 }
1478 /* else, not interested to correct ecc */
1479 }
1480 }
1481
1482 /* Update number of correctable errors */
1483 stat += err_vec[i].error_count;
1484
1485 /* Update page data with sector size */
1486 data += info->nand.ecc.size;
1487 spare_ecc += ecc->bytes;
1488 }
1489
1490 for (i = 0; i < eccsteps; i++)
1491 /* Return error if uncorrectable error present */
1492 if (err_vec[i].error_uncorrectable)
1493 return -EINVAL;
1494
1495 return stat;
1496 }
1497
1498 /**
1499 * omap_write_page_bch - BCH ecc based write page function for entire page
1500 * @mtd: mtd info structure
1501 * @chip: nand chip info structure
1502 * @buf: data buffer
1503 * @oob_required: must write chip->oob_poi to OOB
1504 *
1505 * Custom write page method evolved to support multi sector writing in one shot
1506 */
1507 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1508 const uint8_t *buf, int oob_required)
1509 {
1510 int i;
1511 uint8_t *ecc_calc = chip->buffers->ecccalc;
1512 uint32_t *eccpos = chip->ecc.layout->eccpos;
1513
1514 /* Enable GPMC ecc engine */
1515 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1516
1517 /* Write data */
1518 chip->write_buf(mtd, buf, mtd->writesize);
1519
1520 /* Update ecc vector from GPMC result registers */
1521 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1522
1523 for (i = 0; i < chip->ecc.total; i++)
1524 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1525
1526 /* Write ecc vector to OOB area */
1527 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1528 return 0;
1529 }
1530
1531 /**
1532 * omap_read_page_bch - BCH ecc based page read function for entire page
1533 * @mtd: mtd info structure
1534 * @chip: nand chip info structure
1535 * @buf: buffer to store read data
1536 * @oob_required: caller requires OOB data read to chip->oob_poi
1537 * @page: page number to read
1538 *
1539 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1540 * used for error correction.
1541 * Custom method evolved to support ELM error correction & multi sector
1542 * reading. On reading page data area is read along with OOB data with
1543 * ecc engine enabled. ecc vector updated after read of OOB data.
1544 * For non error pages ecc vector reported as zero.
1545 */
1546 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1547 uint8_t *buf, int oob_required, int page)
1548 {
1549 uint8_t *ecc_calc = chip->buffers->ecccalc;
1550 uint8_t *ecc_code = chip->buffers->ecccode;
1551 uint32_t *eccpos = chip->ecc.layout->eccpos;
1552 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1553 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1554 int stat;
1555 unsigned int max_bitflips = 0;
1556
1557 /* Enable GPMC ecc engine */
1558 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1559
1560 /* Read data */
1561 chip->read_buf(mtd, buf, mtd->writesize);
1562
1563 /* Read oob bytes */
1564 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1565 chip->read_buf(mtd, oob, chip->ecc.total);
1566
1567 /* Calculate ecc bytes */
1568 chip->ecc.calculate(mtd, buf, ecc_calc);
1569
1570 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1571
1572 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1573
1574 if (stat < 0) {
1575 mtd->ecc_stats.failed++;
1576 } else {
1577 mtd->ecc_stats.corrected += stat;
1578 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1579 }
1580
1581 return max_bitflips;
1582 }
1583
1584 /**
1585 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1586 * @omap_nand_info: NAND device structure containing platform data
1587 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1588 */
1589 static int is_elm_present(struct omap_nand_info *info,
1590 struct device_node *elm_node, enum bch_ecc bch_type)
1591 {
1592 struct platform_device *pdev;
1593 info->is_elm_used = false;
1594 /* check whether elm-id is passed via DT */
1595 if (!elm_node) {
1596 pr_err("nand: error: ELM DT node not found\n");
1597 return -ENODEV;
1598 }
1599 pdev = of_find_device_by_node(elm_node);
1600 /* check whether ELM device is registered */
1601 if (!pdev) {
1602 pr_err("nand: error: ELM device not found\n");
1603 return -ENODEV;
1604 }
1605 /* ELM module available, now configure it */
1606 info->elm_dev = &pdev->dev;
1607 if (elm_config(info->elm_dev, bch_type))
1608 return -ENODEV;
1609 info->is_elm_used = true;
1610 return 0;
1611 }
1612 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1613
1614 static int omap_nand_probe(struct platform_device *pdev)
1615 {
1616 struct omap_nand_info *info;
1617 struct omap_nand_platform_data *pdata;
1618 struct mtd_info *mtd;
1619 struct nand_chip *nand_chip;
1620 struct nand_ecclayout *ecclayout;
1621 int err;
1622 int i;
1623 dma_cap_mask_t mask;
1624 unsigned sig;
1625 unsigned oob_index;
1626 struct resource *res;
1627 struct mtd_part_parser_data ppdata = {};
1628
1629 pdata = dev_get_platdata(&pdev->dev);
1630 if (pdata == NULL) {
1631 dev_err(&pdev->dev, "platform data missing\n");
1632 return -ENODEV;
1633 }
1634
1635 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1636 GFP_KERNEL);
1637 if (!info)
1638 return -ENOMEM;
1639
1640 platform_set_drvdata(pdev, info);
1641
1642 spin_lock_init(&info->controller.lock);
1643 init_waitqueue_head(&info->controller.wq);
1644
1645 info->pdev = pdev;
1646 info->gpmc_cs = pdata->cs;
1647 info->reg = pdata->reg;
1648 info->of_node = pdata->of_node;
1649 info->ecc_opt = pdata->ecc_opt;
1650 mtd = &info->mtd;
1651 mtd->priv = &info->nand;
1652 mtd->name = dev_name(&pdev->dev);
1653 mtd->owner = THIS_MODULE;
1654 nand_chip = &info->nand;
1655 nand_chip->ecc.priv = NULL;
1656 nand_chip->options |= NAND_SKIP_BBTSCAN;
1657
1658 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1659 if (res == NULL) {
1660 err = -EINVAL;
1661 dev_err(&pdev->dev, "error getting memory resource\n");
1662 goto return_error;
1663 }
1664
1665 info->phys_base = res->start;
1666 info->mem_size = resource_size(res);
1667
1668 if (!devm_request_mem_region(&pdev->dev, info->phys_base,
1669 info->mem_size, pdev->dev.driver->name)) {
1670 err = -EBUSY;
1671 goto return_error;
1672 }
1673
1674 nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base,
1675 info->mem_size);
1676 if (!nand_chip->IO_ADDR_R) {
1677 err = -ENOMEM;
1678 goto return_error;
1679 }
1680
1681 nand_chip->controller = &info->controller;
1682
1683 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1684 nand_chip->cmd_ctrl = omap_hwcontrol;
1685
1686 /*
1687 * If RDY/BSY line is connected to OMAP then use the omap ready
1688 * function and the generic nand_wait function which reads the status
1689 * register after monitoring the RDY/BSY line. Otherwise use a standard
1690 * chip delay which is slightly more than tR (AC Timing) of the NAND
1691 * device and read status register until you get a failure or success
1692 */
1693 if (pdata->dev_ready) {
1694 nand_chip->dev_ready = omap_dev_ready;
1695 nand_chip->chip_delay = 0;
1696 } else {
1697 nand_chip->waitfunc = omap_wait;
1698 nand_chip->chip_delay = 50;
1699 }
1700
1701 /* scan NAND device connected to chip controller */
1702 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1703 if (nand_scan_ident(mtd, 1, NULL)) {
1704 pr_err("nand device scan failed, may be bus-width mismatch\n");
1705 err = -ENXIO;
1706 goto return_error;
1707 }
1708
1709 /* check for small page devices */
1710 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1711 pr_err("small page devices are not supported\n");
1712 err = -EINVAL;
1713 goto return_error;
1714 }
1715
1716 /* re-populate low-level callbacks based on xfer modes */
1717 switch (pdata->xfer_type) {
1718 case NAND_OMAP_PREFETCH_POLLED:
1719 nand_chip->read_buf = omap_read_buf_pref;
1720 nand_chip->write_buf = omap_write_buf_pref;
1721 break;
1722
1723 case NAND_OMAP_POLLED:
1724 /* Use nand_base defaults for {read,write}_buf */
1725 break;
1726
1727 case NAND_OMAP_PREFETCH_DMA:
1728 dma_cap_zero(mask);
1729 dma_cap_set(DMA_SLAVE, mask);
1730 sig = OMAP24XX_DMA_GPMC;
1731 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1732 if (!info->dma) {
1733 dev_err(&pdev->dev, "DMA engine request failed\n");
1734 err = -ENXIO;
1735 goto return_error;
1736 } else {
1737 struct dma_slave_config cfg;
1738
1739 memset(&cfg, 0, sizeof(cfg));
1740 cfg.src_addr = info->phys_base;
1741 cfg.dst_addr = info->phys_base;
1742 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1743 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1744 cfg.src_maxburst = 16;
1745 cfg.dst_maxburst = 16;
1746 err = dmaengine_slave_config(info->dma, &cfg);
1747 if (err) {
1748 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1749 err);
1750 goto return_error;
1751 }
1752 nand_chip->read_buf = omap_read_buf_dma_pref;
1753 nand_chip->write_buf = omap_write_buf_dma_pref;
1754 }
1755 break;
1756
1757 case NAND_OMAP_PREFETCH_IRQ:
1758 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1759 if (info->gpmc_irq_fifo <= 0) {
1760 dev_err(&pdev->dev, "error getting fifo irq\n");
1761 err = -ENODEV;
1762 goto return_error;
1763 }
1764 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1765 omap_nand_irq, IRQF_SHARED,
1766 "gpmc-nand-fifo", info);
1767 if (err) {
1768 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1769 info->gpmc_irq_fifo, err);
1770 info->gpmc_irq_fifo = 0;
1771 goto return_error;
1772 }
1773
1774 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1775 if (info->gpmc_irq_count <= 0) {
1776 dev_err(&pdev->dev, "error getting count irq\n");
1777 err = -ENODEV;
1778 goto return_error;
1779 }
1780 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1781 omap_nand_irq, IRQF_SHARED,
1782 "gpmc-nand-count", info);
1783 if (err) {
1784 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1785 info->gpmc_irq_count, err);
1786 info->gpmc_irq_count = 0;
1787 goto return_error;
1788 }
1789
1790 nand_chip->read_buf = omap_read_buf_irq_pref;
1791 nand_chip->write_buf = omap_write_buf_irq_pref;
1792
1793 break;
1794
1795 default:
1796 dev_err(&pdev->dev,
1797 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1798 err = -EINVAL;
1799 goto return_error;
1800 }
1801
1802 /* populate MTD interface based on ECC scheme */
1803 nand_chip->ecc.layout = &omap_oobinfo;
1804 ecclayout = &omap_oobinfo;
1805 switch (info->ecc_opt) {
1806 case OMAP_ECC_HAM1_CODE_HW:
1807 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1808 nand_chip->ecc.mode = NAND_ECC_HW;
1809 nand_chip->ecc.bytes = 3;
1810 nand_chip->ecc.size = 512;
1811 nand_chip->ecc.strength = 1;
1812 nand_chip->ecc.calculate = omap_calculate_ecc;
1813 nand_chip->ecc.hwctl = omap_enable_hwecc;
1814 nand_chip->ecc.correct = omap_correct_data;
1815 /* define ECC layout */
1816 ecclayout->eccbytes = nand_chip->ecc.bytes *
1817 (mtd->writesize /
1818 nand_chip->ecc.size);
1819 if (nand_chip->options & NAND_BUSWIDTH_16)
1820 oob_index = BADBLOCK_MARKER_LENGTH;
1821 else
1822 oob_index = 1;
1823 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1824 ecclayout->eccpos[i] = oob_index;
1825 /* no reserved-marker in ecclayout for this ecc-scheme */
1826 ecclayout->oobfree->offset =
1827 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1828 break;
1829
1830 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1831 #ifdef CONFIG_MTD_NAND_ECC_BCH
1832 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1833 nand_chip->ecc.mode = NAND_ECC_HW;
1834 nand_chip->ecc.size = 512;
1835 nand_chip->ecc.bytes = 7;
1836 nand_chip->ecc.strength = 4;
1837 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1838 nand_chip->ecc.correct = nand_bch_correct_data;
1839 nand_chip->ecc.calculate = omap3_calculate_ecc_bch4;
1840 /* define ECC layout */
1841 ecclayout->eccbytes = nand_chip->ecc.bytes *
1842 (mtd->writesize /
1843 nand_chip->ecc.size);
1844 oob_index = BADBLOCK_MARKER_LENGTH;
1845 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1846 ecclayout->eccpos[i] = oob_index;
1847 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1848 oob_index++;
1849 }
1850 /* include reserved-marker in ecclayout->oobfree calculation */
1851 ecclayout->oobfree->offset = 1 +
1852 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1853 /* software bch library is used for locating errors */
1854 nand_chip->ecc.priv = nand_bch_init(mtd,
1855 nand_chip->ecc.size,
1856 nand_chip->ecc.bytes,
1857 &nand_chip->ecc.layout);
1858 if (!nand_chip->ecc.priv) {
1859 pr_err("nand: error: unable to use s/w BCH library\n");
1860 err = -EINVAL;
1861 }
1862 break;
1863 #else
1864 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1865 err = -EINVAL;
1866 goto return_error;
1867 #endif
1868
1869 case OMAP_ECC_BCH4_CODE_HW:
1870 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1871 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1872 nand_chip->ecc.mode = NAND_ECC_HW;
1873 nand_chip->ecc.size = 512;
1874 /* 14th bit is kept reserved for ROM-code compatibility */
1875 nand_chip->ecc.bytes = 7 + 1;
1876 nand_chip->ecc.strength = 4;
1877 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1878 nand_chip->ecc.correct = omap_elm_correct_data;
1879 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1880 nand_chip->ecc.read_page = omap_read_page_bch;
1881 nand_chip->ecc.write_page = omap_write_page_bch;
1882 /* define ECC layout */
1883 ecclayout->eccbytes = nand_chip->ecc.bytes *
1884 (mtd->writesize /
1885 nand_chip->ecc.size);
1886 oob_index = BADBLOCK_MARKER_LENGTH;
1887 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1888 ecclayout->eccpos[i] = oob_index;
1889 /* reserved marker already included in ecclayout->eccbytes */
1890 ecclayout->oobfree->offset =
1891 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1892 /* This ECC scheme requires ELM H/W block */
1893 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1894 pr_err("nand: error: could not initialize ELM\n");
1895 err = -ENODEV;
1896 goto return_error;
1897 }
1898 break;
1899 #else
1900 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1901 err = -EINVAL;
1902 goto return_error;
1903 #endif
1904
1905 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1906 #ifdef CONFIG_MTD_NAND_ECC_BCH
1907 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1908 nand_chip->ecc.mode = NAND_ECC_HW;
1909 nand_chip->ecc.size = 512;
1910 nand_chip->ecc.bytes = 13;
1911 nand_chip->ecc.strength = 8;
1912 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1913 nand_chip->ecc.correct = nand_bch_correct_data;
1914 nand_chip->ecc.calculate = omap3_calculate_ecc_bch8;
1915 /* define ECC layout */
1916 ecclayout->eccbytes = nand_chip->ecc.bytes *
1917 (mtd->writesize /
1918 nand_chip->ecc.size);
1919 oob_index = BADBLOCK_MARKER_LENGTH;
1920 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1921 ecclayout->eccpos[i] = oob_index;
1922 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1923 oob_index++;
1924 }
1925 /* include reserved-marker in ecclayout->oobfree calculation */
1926 ecclayout->oobfree->offset = 1 +
1927 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1928 /* software bch library is used for locating errors */
1929 nand_chip->ecc.priv = nand_bch_init(mtd,
1930 nand_chip->ecc.size,
1931 nand_chip->ecc.bytes,
1932 &nand_chip->ecc.layout);
1933 if (!nand_chip->ecc.priv) {
1934 pr_err("nand: error: unable to use s/w BCH library\n");
1935 err = -EINVAL;
1936 goto return_error;
1937 }
1938 break;
1939 #else
1940 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1941 err = -EINVAL;
1942 goto return_error;
1943 #endif
1944
1945 case OMAP_ECC_BCH8_CODE_HW:
1946 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1947 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1948 nand_chip->ecc.mode = NAND_ECC_HW;
1949 nand_chip->ecc.size = 512;
1950 /* 14th bit is kept reserved for ROM-code compatibility */
1951 nand_chip->ecc.bytes = 13 + 1;
1952 nand_chip->ecc.strength = 8;
1953 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1954 nand_chip->ecc.correct = omap_elm_correct_data;
1955 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1956 nand_chip->ecc.read_page = omap_read_page_bch;
1957 nand_chip->ecc.write_page = omap_write_page_bch;
1958 /* This ECC scheme requires ELM H/W block */
1959 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1960 if (err < 0) {
1961 pr_err("nand: error: could not initialize ELM\n");
1962 goto return_error;
1963 }
1964 /* define ECC layout */
1965 ecclayout->eccbytes = nand_chip->ecc.bytes *
1966 (mtd->writesize /
1967 nand_chip->ecc.size);
1968 oob_index = BADBLOCK_MARKER_LENGTH;
1969 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1970 ecclayout->eccpos[i] = oob_index;
1971 /* reserved marker already included in ecclayout->eccbytes */
1972 ecclayout->oobfree->offset =
1973 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1974 break;
1975 #else
1976 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1977 err = -EINVAL;
1978 goto return_error;
1979 #endif
1980
1981 default:
1982 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1983 err = -EINVAL;
1984 goto return_error;
1985 }
1986
1987 /* all OOB bytes from oobfree->offset till end off OOB are free */
1988 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1989 /* check if NAND device's OOB is enough to store ECC signatures */
1990 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1991 pr_err("not enough OOB bytes required = %d, available=%d\n",
1992 ecclayout->eccbytes, mtd->oobsize);
1993 err = -EINVAL;
1994 goto return_error;
1995 }
1996
1997 /* second phase scan */
1998 if (nand_scan_tail(mtd)) {
1999 err = -ENXIO;
2000 goto return_error;
2001 }
2002
2003 ppdata.of_node = pdata->of_node;
2004 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2005 pdata->nr_parts);
2006
2007 platform_set_drvdata(pdev, mtd);
2008
2009 return 0;
2010
2011 return_error:
2012 if (info->dma)
2013 dma_release_channel(info->dma);
2014 if (nand_chip->ecc.priv) {
2015 nand_bch_free(nand_chip->ecc.priv);
2016 nand_chip->ecc.priv = NULL;
2017 }
2018 return err;
2019 }
2020
2021 static int omap_nand_remove(struct platform_device *pdev)
2022 {
2023 struct mtd_info *mtd = platform_get_drvdata(pdev);
2024 struct nand_chip *nand_chip = mtd->priv;
2025 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2026 mtd);
2027 if (nand_chip->ecc.priv) {
2028 nand_bch_free(nand_chip->ecc.priv);
2029 nand_chip->ecc.priv = NULL;
2030 }
2031 if (info->dma)
2032 dma_release_channel(info->dma);
2033 nand_release(mtd);
2034 return 0;
2035 }
2036
2037 static struct platform_driver omap_nand_driver = {
2038 .probe = omap_nand_probe,
2039 .remove = omap_nand_remove,
2040 .driver = {
2041 .name = DRIVER_NAME,
2042 .owner = THIS_MODULE,
2043 },
2044 };
2045
2046 module_platform_driver(omap_nand_driver);
2047
2048 MODULE_ALIAS("platform:" DRIVER_NAME);
2049 MODULE_LICENSE("GPL");
2050 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux kernel - Deliverables
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