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mtd: nand: omap: Use gpmc_omap_get_nand_ops() to get NAND registers
[deliverable/linux.git] / drivers / mtd / nand / omap2.c
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/omap-gpmc.h>
32 #include <linux/platform_data/mtd-nand-omap2.h>
33
34 #define DRIVER_NAME "omap2-nand"
35 #define OMAP_NAND_TIMEOUT_MS 5000
36
37 #define NAND_Ecc_P1e (1 << 0)
38 #define NAND_Ecc_P2e (1 << 1)
39 #define NAND_Ecc_P4e (1 << 2)
40 #define NAND_Ecc_P8e (1 << 3)
41 #define NAND_Ecc_P16e (1 << 4)
42 #define NAND_Ecc_P32e (1 << 5)
43 #define NAND_Ecc_P64e (1 << 6)
44 #define NAND_Ecc_P128e (1 << 7)
45 #define NAND_Ecc_P256e (1 << 8)
46 #define NAND_Ecc_P512e (1 << 9)
47 #define NAND_Ecc_P1024e (1 << 10)
48 #define NAND_Ecc_P2048e (1 << 11)
49
50 #define NAND_Ecc_P1o (1 << 16)
51 #define NAND_Ecc_P2o (1 << 17)
52 #define NAND_Ecc_P4o (1 << 18)
53 #define NAND_Ecc_P8o (1 << 19)
54 #define NAND_Ecc_P16o (1 << 20)
55 #define NAND_Ecc_P32o (1 << 21)
56 #define NAND_Ecc_P64o (1 << 22)
57 #define NAND_Ecc_P128o (1 << 23)
58 #define NAND_Ecc_P256o (1 << 24)
59 #define NAND_Ecc_P512o (1 << 25)
60 #define NAND_Ecc_P1024o (1 << 26)
61 #define NAND_Ecc_P2048o (1 << 27)
62
63 #define TF(value) (value ? 1 : 0)
64
65 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
66 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
67 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
68 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
69 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
70 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
71 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
72 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
73
74 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
75 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
76 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
77 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
78 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
79 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
80 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
81 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
82
83 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
84 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
85 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
86 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
87 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
88 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
89 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
90 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
91
92 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
93 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
94 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
95 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
96 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
97 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
98 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
99 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
100
101 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
102 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
103
104 #define PREFETCH_CONFIG1_CS_SHIFT 24
105 #define ECC_CONFIG_CS_SHIFT 1
106 #define CS_MASK 0x7
107 #define ENABLE_PREFETCH (0x1 << 7)
108 #define DMA_MPU_MODE_SHIFT 2
109 #define ECCSIZE0_SHIFT 12
110 #define ECCSIZE1_SHIFT 22
111 #define ECC1RESULTSIZE 0x1
112 #define ECCCLEAR 0x100
113 #define ECC1 0x1
114 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
115 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
116 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
117 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
118 #define STATUS_BUFF_EMPTY 0x00000001
119
120 #define OMAP24XX_DMA_GPMC 4
121
122 #define SECTOR_BYTES 512
123 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
124 #define BCH4_BIT_PAD 4
125
126 /* GPMC ecc engine settings for read */
127 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
128 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
129 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
130 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
131 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
132
133 /* GPMC ecc engine settings for write */
134 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
135 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
136 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
137
138 #define BADBLOCK_MARKER_LENGTH 2
139
140 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
141 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
142 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
143 0x07, 0x0e};
144 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
145 0xac, 0x6b, 0xff, 0x99, 0x7b};
146 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
147
148 /* Shared among all NAND instances to synchronize access to the ECC Engine */
149 static struct nand_hw_control omap_gpmc_controller = {
150 .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
151 .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
152 };
153
154 struct omap_nand_info {
155 struct omap_nand_platform_data *pdata;
156 struct nand_chip nand;
157 struct platform_device *pdev;
158
159 int gpmc_cs;
160 unsigned long phys_base;
161 enum omap_ecc ecc_opt;
162 struct completion comp;
163 struct dma_chan *dma;
164 int gpmc_irq_fifo;
165 int gpmc_irq_count;
166 enum {
167 OMAP_NAND_IO_READ = 0, /* read */
168 OMAP_NAND_IO_WRITE, /* write */
169 } iomode;
170 u_char *buf;
171 int buf_len;
172 /* Interface to GPMC */
173 struct gpmc_nand_regs reg;
174 struct gpmc_nand_ops *ops;
175 /* generated at runtime depending on ECC algorithm and layout selected */
176 struct nand_ecclayout oobinfo;
177 /* fields specific for BCHx_HW ECC scheme */
178 struct device *elm_dev;
179 struct device_node *of_node;
180 };
181
182 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
183 {
184 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
185 }
186
187 /**
188 * omap_prefetch_enable - configures and starts prefetch transfer
189 * @cs: cs (chip select) number
190 * @fifo_th: fifo threshold to be used for read/ write
191 * @dma_mode: dma mode enable (1) or disable (0)
192 * @u32_count: number of bytes to be transferred
193 * @is_write: prefetch read(0) or write post(1) mode
194 */
195 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
196 unsigned int u32_count, int is_write, struct omap_nand_info *info)
197 {
198 u32 val;
199
200 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
201 return -1;
202
203 if (readl(info->reg.gpmc_prefetch_control))
204 return -EBUSY;
205
206 /* Set the amount of bytes to be prefetched */
207 writel(u32_count, info->reg.gpmc_prefetch_config2);
208
209 /* Set dma/mpu mode, the prefetch read / post write and
210 * enable the engine. Set which cs is has requested for.
211 */
212 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
213 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
214 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
215 writel(val, info->reg.gpmc_prefetch_config1);
216
217 /* Start the prefetch engine */
218 writel(0x1, info->reg.gpmc_prefetch_control);
219
220 return 0;
221 }
222
223 /**
224 * omap_prefetch_reset - disables and stops the prefetch engine
225 */
226 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
227 {
228 u32 config1;
229
230 /* check if the same module/cs is trying to reset */
231 config1 = readl(info->reg.gpmc_prefetch_config1);
232 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
233 return -EINVAL;
234
235 /* Stop the PFPW engine */
236 writel(0x0, info->reg.gpmc_prefetch_control);
237
238 /* Reset/disable the PFPW engine */
239 writel(0x0, info->reg.gpmc_prefetch_config1);
240
241 return 0;
242 }
243
244 /**
245 * omap_hwcontrol - hardware specific access to control-lines
246 * @mtd: MTD device structure
247 * @cmd: command to device
248 * @ctrl:
249 * NAND_NCE: bit 0 -> don't care
250 * NAND_CLE: bit 1 -> Command Latch
251 * NAND_ALE: bit 2 -> Address Latch
252 *
253 * NOTE: boards may use different bits for these!!
254 */
255 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
256 {
257 struct omap_nand_info *info = mtd_to_omap(mtd);
258
259 if (cmd != NAND_CMD_NONE) {
260 if (ctrl & NAND_CLE)
261 writeb(cmd, info->reg.gpmc_nand_command);
262
263 else if (ctrl & NAND_ALE)
264 writeb(cmd, info->reg.gpmc_nand_address);
265
266 else /* NAND_NCE */
267 writeb(cmd, info->reg.gpmc_nand_data);
268 }
269 }
270
271 /**
272 * omap_read_buf8 - read data from NAND controller into buffer
273 * @mtd: MTD device structure
274 * @buf: buffer to store date
275 * @len: number of bytes to read
276 */
277 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
278 {
279 struct nand_chip *nand = mtd_to_nand(mtd);
280
281 ioread8_rep(nand->IO_ADDR_R, buf, len);
282 }
283
284 /**
285 * omap_write_buf8 - write buffer to NAND controller
286 * @mtd: MTD device structure
287 * @buf: data buffer
288 * @len: number of bytes to write
289 */
290 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
291 {
292 struct omap_nand_info *info = mtd_to_omap(mtd);
293 u_char *p = (u_char *)buf;
294 u32 status = 0;
295
296 while (len--) {
297 iowrite8(*p++, info->nand.IO_ADDR_W);
298 /* wait until buffer is available for write */
299 do {
300 status = readl(info->reg.gpmc_status) &
301 STATUS_BUFF_EMPTY;
302 } while (!status);
303 }
304 }
305
306 /**
307 * omap_read_buf16 - read data from NAND controller into buffer
308 * @mtd: MTD device structure
309 * @buf: buffer to store date
310 * @len: number of bytes to read
311 */
312 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
313 {
314 struct nand_chip *nand = mtd_to_nand(mtd);
315
316 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
317 }
318
319 /**
320 * omap_write_buf16 - write buffer to NAND controller
321 * @mtd: MTD device structure
322 * @buf: data buffer
323 * @len: number of bytes to write
324 */
325 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
326 {
327 struct omap_nand_info *info = mtd_to_omap(mtd);
328 u16 *p = (u16 *) buf;
329 u32 status = 0;
330 /* FIXME try bursts of writesw() or DMA ... */
331 len >>= 1;
332
333 while (len--) {
334 iowrite16(*p++, info->nand.IO_ADDR_W);
335 /* wait until buffer is available for write */
336 do {
337 status = readl(info->reg.gpmc_status) &
338 STATUS_BUFF_EMPTY;
339 } while (!status);
340 }
341 }
342
343 /**
344 * omap_read_buf_pref - read data from NAND controller into buffer
345 * @mtd: MTD device structure
346 * @buf: buffer to store date
347 * @len: number of bytes to read
348 */
349 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
350 {
351 struct omap_nand_info *info = mtd_to_omap(mtd);
352 uint32_t r_count = 0;
353 int ret = 0;
354 u32 *p = (u32 *)buf;
355
356 /* take care of subpage reads */
357 if (len % 4) {
358 if (info->nand.options & NAND_BUSWIDTH_16)
359 omap_read_buf16(mtd, buf, len % 4);
360 else
361 omap_read_buf8(mtd, buf, len % 4);
362 p = (u32 *) (buf + len % 4);
363 len -= len % 4;
364 }
365
366 /* configure and start prefetch transfer */
367 ret = omap_prefetch_enable(info->gpmc_cs,
368 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
369 if (ret) {
370 /* PFPW engine is busy, use cpu copy method */
371 if (info->nand.options & NAND_BUSWIDTH_16)
372 omap_read_buf16(mtd, (u_char *)p, len);
373 else
374 omap_read_buf8(mtd, (u_char *)p, len);
375 } else {
376 do {
377 r_count = readl(info->reg.gpmc_prefetch_status);
378 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
379 r_count = r_count >> 2;
380 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
381 p += r_count;
382 len -= r_count << 2;
383 } while (len);
384 /* disable and stop the PFPW engine */
385 omap_prefetch_reset(info->gpmc_cs, info);
386 }
387 }
388
389 /**
390 * omap_write_buf_pref - write buffer to NAND controller
391 * @mtd: MTD device structure
392 * @buf: data buffer
393 * @len: number of bytes to write
394 */
395 static void omap_write_buf_pref(struct mtd_info *mtd,
396 const u_char *buf, int len)
397 {
398 struct omap_nand_info *info = mtd_to_omap(mtd);
399 uint32_t w_count = 0;
400 int i = 0, ret = 0;
401 u16 *p = (u16 *)buf;
402 unsigned long tim, limit;
403 u32 val;
404
405 /* take care of subpage writes */
406 if (len % 2 != 0) {
407 writeb(*buf, info->nand.IO_ADDR_W);
408 p = (u16 *)(buf + 1);
409 len--;
410 }
411
412 /* configure and start prefetch transfer */
413 ret = omap_prefetch_enable(info->gpmc_cs,
414 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
415 if (ret) {
416 /* PFPW engine is busy, use cpu copy method */
417 if (info->nand.options & NAND_BUSWIDTH_16)
418 omap_write_buf16(mtd, (u_char *)p, len);
419 else
420 omap_write_buf8(mtd, (u_char *)p, len);
421 } else {
422 while (len) {
423 w_count = readl(info->reg.gpmc_prefetch_status);
424 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
425 w_count = w_count >> 1;
426 for (i = 0; (i < w_count) && len; i++, len -= 2)
427 iowrite16(*p++, info->nand.IO_ADDR_W);
428 }
429 /* wait for data to flushed-out before reset the prefetch */
430 tim = 0;
431 limit = (loops_per_jiffy *
432 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
433 do {
434 cpu_relax();
435 val = readl(info->reg.gpmc_prefetch_status);
436 val = PREFETCH_STATUS_COUNT(val);
437 } while (val && (tim++ < limit));
438
439 /* disable and stop the PFPW engine */
440 omap_prefetch_reset(info->gpmc_cs, info);
441 }
442 }
443
444 /*
445 * omap_nand_dma_callback: callback on the completion of dma transfer
446 * @data: pointer to completion data structure
447 */
448 static void omap_nand_dma_callback(void *data)
449 {
450 complete((struct completion *) data);
451 }
452
453 /*
454 * omap_nand_dma_transfer: configure and start dma transfer
455 * @mtd: MTD device structure
456 * @addr: virtual address in RAM of source/destination
457 * @len: number of data bytes to be transferred
458 * @is_write: flag for read/write operation
459 */
460 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
461 unsigned int len, int is_write)
462 {
463 struct omap_nand_info *info = mtd_to_omap(mtd);
464 struct dma_async_tx_descriptor *tx;
465 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
466 DMA_FROM_DEVICE;
467 struct scatterlist sg;
468 unsigned long tim, limit;
469 unsigned n;
470 int ret;
471 u32 val;
472
473 if (addr >= high_memory) {
474 struct page *p1;
475
476 if (((size_t)addr & PAGE_MASK) !=
477 ((size_t)(addr + len - 1) & PAGE_MASK))
478 goto out_copy;
479 p1 = vmalloc_to_page(addr);
480 if (!p1)
481 goto out_copy;
482 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
483 }
484
485 sg_init_one(&sg, addr, len);
486 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
487 if (n == 0) {
488 dev_err(&info->pdev->dev,
489 "Couldn't DMA map a %d byte buffer\n", len);
490 goto out_copy;
491 }
492
493 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
494 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
496 if (!tx)
497 goto out_copy_unmap;
498
499 tx->callback = omap_nand_dma_callback;
500 tx->callback_param = &info->comp;
501 dmaengine_submit(tx);
502
503 /* configure and start prefetch transfer */
504 ret = omap_prefetch_enable(info->gpmc_cs,
505 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
506 if (ret)
507 /* PFPW engine is busy, use cpu copy method */
508 goto out_copy_unmap;
509
510 init_completion(&info->comp);
511 dma_async_issue_pending(info->dma);
512
513 /* setup and start DMA using dma_addr */
514 wait_for_completion(&info->comp);
515 tim = 0;
516 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
517
518 do {
519 cpu_relax();
520 val = readl(info->reg.gpmc_prefetch_status);
521 val = PREFETCH_STATUS_COUNT(val);
522 } while (val && (tim++ < limit));
523
524 /* disable and stop the PFPW engine */
525 omap_prefetch_reset(info->gpmc_cs, info);
526
527 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
528 return 0;
529
530 out_copy_unmap:
531 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
532 out_copy:
533 if (info->nand.options & NAND_BUSWIDTH_16)
534 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
535 : omap_write_buf16(mtd, (u_char *) addr, len);
536 else
537 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
538 : omap_write_buf8(mtd, (u_char *) addr, len);
539 return 0;
540 }
541
542 /**
543 * omap_read_buf_dma_pref - read data from NAND controller into buffer
544 * @mtd: MTD device structure
545 * @buf: buffer to store date
546 * @len: number of bytes to read
547 */
548 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
549 {
550 if (len <= mtd->oobsize)
551 omap_read_buf_pref(mtd, buf, len);
552 else
553 /* start transfer in DMA mode */
554 omap_nand_dma_transfer(mtd, buf, len, 0x0);
555 }
556
557 /**
558 * omap_write_buf_dma_pref - write buffer to NAND controller
559 * @mtd: MTD device structure
560 * @buf: data buffer
561 * @len: number of bytes to write
562 */
563 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
564 const u_char *buf, int len)
565 {
566 if (len <= mtd->oobsize)
567 omap_write_buf_pref(mtd, buf, len);
568 else
569 /* start transfer in DMA mode */
570 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
571 }
572
573 /*
574 * omap_nand_irq - GPMC irq handler
575 * @this_irq: gpmc irq number
576 * @dev: omap_nand_info structure pointer is passed here
577 */
578 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
579 {
580 struct omap_nand_info *info = (struct omap_nand_info *) dev;
581 u32 bytes;
582
583 bytes = readl(info->reg.gpmc_prefetch_status);
584 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
585 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
586 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
587 if (this_irq == info->gpmc_irq_count)
588 goto done;
589
590 if (info->buf_len && (info->buf_len < bytes))
591 bytes = info->buf_len;
592 else if (!info->buf_len)
593 bytes = 0;
594 iowrite32_rep(info->nand.IO_ADDR_W,
595 (u32 *)info->buf, bytes >> 2);
596 info->buf = info->buf + bytes;
597 info->buf_len -= bytes;
598
599 } else {
600 ioread32_rep(info->nand.IO_ADDR_R,
601 (u32 *)info->buf, bytes >> 2);
602 info->buf = info->buf + bytes;
603
604 if (this_irq == info->gpmc_irq_count)
605 goto done;
606 }
607
608 return IRQ_HANDLED;
609
610 done:
611 complete(&info->comp);
612
613 disable_irq_nosync(info->gpmc_irq_fifo);
614 disable_irq_nosync(info->gpmc_irq_count);
615
616 return IRQ_HANDLED;
617 }
618
619 /*
620 * omap_read_buf_irq_pref - read data from NAND controller into buffer
621 * @mtd: MTD device structure
622 * @buf: buffer to store date
623 * @len: number of bytes to read
624 */
625 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
626 {
627 struct omap_nand_info *info = mtd_to_omap(mtd);
628 int ret = 0;
629
630 if (len <= mtd->oobsize) {
631 omap_read_buf_pref(mtd, buf, len);
632 return;
633 }
634
635 info->iomode = OMAP_NAND_IO_READ;
636 info->buf = buf;
637 init_completion(&info->comp);
638
639 /* configure and start prefetch transfer */
640 ret = omap_prefetch_enable(info->gpmc_cs,
641 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
642 if (ret)
643 /* PFPW engine is busy, use cpu copy method */
644 goto out_copy;
645
646 info->buf_len = len;
647
648 enable_irq(info->gpmc_irq_count);
649 enable_irq(info->gpmc_irq_fifo);
650
651 /* waiting for read to complete */
652 wait_for_completion(&info->comp);
653
654 /* disable and stop the PFPW engine */
655 omap_prefetch_reset(info->gpmc_cs, info);
656 return;
657
658 out_copy:
659 if (info->nand.options & NAND_BUSWIDTH_16)
660 omap_read_buf16(mtd, buf, len);
661 else
662 omap_read_buf8(mtd, buf, len);
663 }
664
665 /*
666 * omap_write_buf_irq_pref - write buffer to NAND controller
667 * @mtd: MTD device structure
668 * @buf: data buffer
669 * @len: number of bytes to write
670 */
671 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
672 const u_char *buf, int len)
673 {
674 struct omap_nand_info *info = mtd_to_omap(mtd);
675 int ret = 0;
676 unsigned long tim, limit;
677 u32 val;
678
679 if (len <= mtd->oobsize) {
680 omap_write_buf_pref(mtd, buf, len);
681 return;
682 }
683
684 info->iomode = OMAP_NAND_IO_WRITE;
685 info->buf = (u_char *) buf;
686 init_completion(&info->comp);
687
688 /* configure and start prefetch transfer : size=24 */
689 ret = omap_prefetch_enable(info->gpmc_cs,
690 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
691 if (ret)
692 /* PFPW engine is busy, use cpu copy method */
693 goto out_copy;
694
695 info->buf_len = len;
696
697 enable_irq(info->gpmc_irq_count);
698 enable_irq(info->gpmc_irq_fifo);
699
700 /* waiting for write to complete */
701 wait_for_completion(&info->comp);
702
703 /* wait for data to flushed-out before reset the prefetch */
704 tim = 0;
705 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
706 do {
707 val = readl(info->reg.gpmc_prefetch_status);
708 val = PREFETCH_STATUS_COUNT(val);
709 cpu_relax();
710 } while (val && (tim++ < limit));
711
712 /* disable and stop the PFPW engine */
713 omap_prefetch_reset(info->gpmc_cs, info);
714 return;
715
716 out_copy:
717 if (info->nand.options & NAND_BUSWIDTH_16)
718 omap_write_buf16(mtd, buf, len);
719 else
720 omap_write_buf8(mtd, buf, len);
721 }
722
723 /**
724 * gen_true_ecc - This function will generate true ECC value
725 * @ecc_buf: buffer to store ecc code
726 *
727 * This generated true ECC value can be used when correcting
728 * data read from NAND flash memory core
729 */
730 static void gen_true_ecc(u8 *ecc_buf)
731 {
732 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
733 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
734
735 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
736 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
737 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
738 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
739 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
740 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
741 }
742
743 /**
744 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
745 * @ecc_data1: ecc code from nand spare area
746 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
747 * @page_data: page data
748 *
749 * This function compares two ECC's and indicates if there is an error.
750 * If the error can be corrected it will be corrected to the buffer.
751 * If there is no error, %0 is returned. If there is an error but it
752 * was corrected, %1 is returned. Otherwise, %-1 is returned.
753 */
754 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
755 u8 *ecc_data2, /* read from register */
756 u8 *page_data)
757 {
758 uint i;
759 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
760 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
761 u8 ecc_bit[24];
762 u8 ecc_sum = 0;
763 u8 find_bit = 0;
764 uint find_byte = 0;
765 int isEccFF;
766
767 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
768
769 gen_true_ecc(ecc_data1);
770 gen_true_ecc(ecc_data2);
771
772 for (i = 0; i <= 2; i++) {
773 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
774 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
775 }
776
777 for (i = 0; i < 8; i++) {
778 tmp0_bit[i] = *ecc_data1 % 2;
779 *ecc_data1 = *ecc_data1 / 2;
780 }
781
782 for (i = 0; i < 8; i++) {
783 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
784 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
785 }
786
787 for (i = 0; i < 8; i++) {
788 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
789 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
790 }
791
792 for (i = 0; i < 8; i++) {
793 comp0_bit[i] = *ecc_data2 % 2;
794 *ecc_data2 = *ecc_data2 / 2;
795 }
796
797 for (i = 0; i < 8; i++) {
798 comp1_bit[i] = *(ecc_data2 + 1) % 2;
799 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
800 }
801
802 for (i = 0; i < 8; i++) {
803 comp2_bit[i] = *(ecc_data2 + 2) % 2;
804 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
805 }
806
807 for (i = 0; i < 6; i++)
808 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
809
810 for (i = 0; i < 8; i++)
811 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
812
813 for (i = 0; i < 8; i++)
814 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
815
816 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
817 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
818
819 for (i = 0; i < 24; i++)
820 ecc_sum += ecc_bit[i];
821
822 switch (ecc_sum) {
823 case 0:
824 /* Not reached because this function is not called if
825 * ECC values are equal
826 */
827 return 0;
828
829 case 1:
830 /* Uncorrectable error */
831 pr_debug("ECC UNCORRECTED_ERROR 1\n");
832 return -EBADMSG;
833
834 case 11:
835 /* UN-Correctable error */
836 pr_debug("ECC UNCORRECTED_ERROR B\n");
837 return -EBADMSG;
838
839 case 12:
840 /* Correctable error */
841 find_byte = (ecc_bit[23] << 8) +
842 (ecc_bit[21] << 7) +
843 (ecc_bit[19] << 6) +
844 (ecc_bit[17] << 5) +
845 (ecc_bit[15] << 4) +
846 (ecc_bit[13] << 3) +
847 (ecc_bit[11] << 2) +
848 (ecc_bit[9] << 1) +
849 ecc_bit[7];
850
851 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
852
853 pr_debug("Correcting single bit ECC error at offset: "
854 "%d, bit: %d\n", find_byte, find_bit);
855
856 page_data[find_byte] ^= (1 << find_bit);
857
858 return 1;
859 default:
860 if (isEccFF) {
861 if (ecc_data2[0] == 0 &&
862 ecc_data2[1] == 0 &&
863 ecc_data2[2] == 0)
864 return 0;
865 }
866 pr_debug("UNCORRECTED_ERROR default\n");
867 return -EBADMSG;
868 }
869 }
870
871 /**
872 * omap_correct_data - Compares the ECC read with HW generated ECC
873 * @mtd: MTD device structure
874 * @dat: page data
875 * @read_ecc: ecc read from nand flash
876 * @calc_ecc: ecc read from HW ECC registers
877 *
878 * Compares the ecc read from nand spare area with ECC registers values
879 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
880 * detection and correction. If there are no errors, %0 is returned. If
881 * there were errors and all of the errors were corrected, the number of
882 * corrected errors is returned. If uncorrectable errors exist, %-1 is
883 * returned.
884 */
885 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
886 u_char *read_ecc, u_char *calc_ecc)
887 {
888 struct omap_nand_info *info = mtd_to_omap(mtd);
889 int blockCnt = 0, i = 0, ret = 0;
890 int stat = 0;
891
892 /* Ex NAND_ECC_HW12_2048 */
893 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
894 (info->nand.ecc.size == 2048))
895 blockCnt = 4;
896 else
897 blockCnt = 1;
898
899 for (i = 0; i < blockCnt; i++) {
900 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
901 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
902 if (ret < 0)
903 return ret;
904 /* keep track of the number of corrected errors */
905 stat += ret;
906 }
907 read_ecc += 3;
908 calc_ecc += 3;
909 dat += 512;
910 }
911 return stat;
912 }
913
914 /**
915 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
916 * @mtd: MTD device structure
917 * @dat: The pointer to data on which ecc is computed
918 * @ecc_code: The ecc_code buffer
919 *
920 * Using noninverted ECC can be considered ugly since writing a blank
921 * page ie. padding will clear the ECC bytes. This is no problem as long
922 * nobody is trying to write data on the seemingly unused page. Reading
923 * an erased page will produce an ECC mismatch between generated and read
924 * ECC bytes that has to be dealt with separately.
925 */
926 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
927 u_char *ecc_code)
928 {
929 struct omap_nand_info *info = mtd_to_omap(mtd);
930 u32 val;
931
932 val = readl(info->reg.gpmc_ecc_config);
933 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
934 return -EINVAL;
935
936 /* read ecc result */
937 val = readl(info->reg.gpmc_ecc1_result);
938 *ecc_code++ = val; /* P128e, ..., P1e */
939 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
940 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
941 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
942
943 return 0;
944 }
945
946 /**
947 * omap_enable_hwecc - This function enables the hardware ecc functionality
948 * @mtd: MTD device structure
949 * @mode: Read/Write mode
950 */
951 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
952 {
953 struct omap_nand_info *info = mtd_to_omap(mtd);
954 struct nand_chip *chip = mtd_to_nand(mtd);
955 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
956 u32 val;
957
958 /* clear ecc and enable bits */
959 val = ECCCLEAR | ECC1;
960 writel(val, info->reg.gpmc_ecc_control);
961
962 /* program ecc and result sizes */
963 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
964 ECC1RESULTSIZE);
965 writel(val, info->reg.gpmc_ecc_size_config);
966
967 switch (mode) {
968 case NAND_ECC_READ:
969 case NAND_ECC_WRITE:
970 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
971 break;
972 case NAND_ECC_READSYN:
973 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
974 break;
975 default:
976 dev_info(&info->pdev->dev,
977 "error: unrecognized Mode[%d]!\n", mode);
978 break;
979 }
980
981 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
982 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
983 writel(val, info->reg.gpmc_ecc_config);
984 }
985
986 /**
987 * omap_wait - wait until the command is done
988 * @mtd: MTD device structure
989 * @chip: NAND Chip structure
990 *
991 * Wait function is called during Program and erase operations and
992 * the way it is called from MTD layer, we should wait till the NAND
993 * chip is ready after the programming/erase operation has completed.
994 *
995 * Erase can take up to 400ms and program up to 20ms according to
996 * general NAND and SmartMedia specs
997 */
998 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
999 {
1000 struct nand_chip *this = mtd_to_nand(mtd);
1001 struct omap_nand_info *info = mtd_to_omap(mtd);
1002 unsigned long timeo = jiffies;
1003 int status, state = this->state;
1004
1005 if (state == FL_ERASING)
1006 timeo += msecs_to_jiffies(400);
1007 else
1008 timeo += msecs_to_jiffies(20);
1009
1010 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1011 while (time_before(jiffies, timeo)) {
1012 status = readb(info->reg.gpmc_nand_data);
1013 if (status & NAND_STATUS_READY)
1014 break;
1015 cond_resched();
1016 }
1017
1018 status = readb(info->reg.gpmc_nand_data);
1019 return status;
1020 }
1021
1022 /**
1023 * omap_dev_ready - calls the platform specific dev_ready function
1024 * @mtd: MTD device structure
1025 */
1026 static int omap_dev_ready(struct mtd_info *mtd)
1027 {
1028 unsigned int val = 0;
1029 struct omap_nand_info *info = mtd_to_omap(mtd);
1030
1031 val = readl(info->reg.gpmc_status);
1032
1033 if ((val & 0x100) == 0x100) {
1034 return 1;
1035 } else {
1036 return 0;
1037 }
1038 }
1039
1040 /**
1041 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1042 * @mtd: MTD device structure
1043 * @mode: Read/Write mode
1044 *
1045 * When using BCH with SW correction (i.e. no ELM), sector size is set
1046 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1047 * for both reading and writing with:
1048 * eccsize0 = 0 (no additional protected byte in spare area)
1049 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1050 */
1051 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1052 {
1053 unsigned int bch_type;
1054 unsigned int dev_width, nsectors;
1055 struct omap_nand_info *info = mtd_to_omap(mtd);
1056 enum omap_ecc ecc_opt = info->ecc_opt;
1057 struct nand_chip *chip = mtd_to_nand(mtd);
1058 u32 val, wr_mode;
1059 unsigned int ecc_size1, ecc_size0;
1060
1061 /* GPMC configurations for calculating ECC */
1062 switch (ecc_opt) {
1063 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1064 bch_type = 0;
1065 nsectors = 1;
1066 wr_mode = BCH_WRAPMODE_6;
1067 ecc_size0 = BCH_ECC_SIZE0;
1068 ecc_size1 = BCH_ECC_SIZE1;
1069 break;
1070 case OMAP_ECC_BCH4_CODE_HW:
1071 bch_type = 0;
1072 nsectors = chip->ecc.steps;
1073 if (mode == NAND_ECC_READ) {
1074 wr_mode = BCH_WRAPMODE_1;
1075 ecc_size0 = BCH4R_ECC_SIZE0;
1076 ecc_size1 = BCH4R_ECC_SIZE1;
1077 } else {
1078 wr_mode = BCH_WRAPMODE_6;
1079 ecc_size0 = BCH_ECC_SIZE0;
1080 ecc_size1 = BCH_ECC_SIZE1;
1081 }
1082 break;
1083 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1084 bch_type = 1;
1085 nsectors = 1;
1086 wr_mode = BCH_WRAPMODE_6;
1087 ecc_size0 = BCH_ECC_SIZE0;
1088 ecc_size1 = BCH_ECC_SIZE1;
1089 break;
1090 case OMAP_ECC_BCH8_CODE_HW:
1091 bch_type = 1;
1092 nsectors = chip->ecc.steps;
1093 if (mode == NAND_ECC_READ) {
1094 wr_mode = BCH_WRAPMODE_1;
1095 ecc_size0 = BCH8R_ECC_SIZE0;
1096 ecc_size1 = BCH8R_ECC_SIZE1;
1097 } else {
1098 wr_mode = BCH_WRAPMODE_6;
1099 ecc_size0 = BCH_ECC_SIZE0;
1100 ecc_size1 = BCH_ECC_SIZE1;
1101 }
1102 break;
1103 case OMAP_ECC_BCH16_CODE_HW:
1104 bch_type = 0x2;
1105 nsectors = chip->ecc.steps;
1106 if (mode == NAND_ECC_READ) {
1107 wr_mode = 0x01;
1108 ecc_size0 = 52; /* ECC bits in nibbles per sector */
1109 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
1110 } else {
1111 wr_mode = 0x01;
1112 ecc_size0 = 0; /* extra bits in nibbles per sector */
1113 ecc_size1 = 52; /* OOB bits in nibbles per sector */
1114 }
1115 break;
1116 default:
1117 return;
1118 }
1119
1120 writel(ECC1, info->reg.gpmc_ecc_control);
1121
1122 /* Configure ecc size for BCH */
1123 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1124 writel(val, info->reg.gpmc_ecc_size_config);
1125
1126 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1127
1128 /* BCH configuration */
1129 val = ((1 << 16) | /* enable BCH */
1130 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
1131 (wr_mode << 8) | /* wrap mode */
1132 (dev_width << 7) | /* bus width */
1133 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1134 (info->gpmc_cs << 1) | /* ECC CS */
1135 (0x1)); /* enable ECC */
1136
1137 writel(val, info->reg.gpmc_ecc_config);
1138
1139 /* Clear ecc and enable bits */
1140 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1141 }
1142
1143 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1144 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1145 0x97, 0x79, 0xe5, 0x24, 0xb5};
1146
1147 /**
1148 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1149 * @mtd: MTD device structure
1150 * @dat: The pointer to data on which ecc is computed
1151 * @ecc_code: The ecc_code buffer
1152 *
1153 * Support calculating of BCH4/8 ecc vectors for the page
1154 */
1155 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1156 const u_char *dat, u_char *ecc_calc)
1157 {
1158 struct omap_nand_info *info = mtd_to_omap(mtd);
1159 int eccbytes = info->nand.ecc.bytes;
1160 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1161 u8 *ecc_code;
1162 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1163 u32 val;
1164 int i, j;
1165
1166 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1167 for (i = 0; i < nsectors; i++) {
1168 ecc_code = ecc_calc;
1169 switch (info->ecc_opt) {
1170 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1171 case OMAP_ECC_BCH8_CODE_HW:
1172 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1173 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1174 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1175 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1176 *ecc_code++ = (bch_val4 & 0xFF);
1177 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1178 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1179 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1180 *ecc_code++ = (bch_val3 & 0xFF);
1181 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1182 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1183 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1184 *ecc_code++ = (bch_val2 & 0xFF);
1185 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1186 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1187 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1188 *ecc_code++ = (bch_val1 & 0xFF);
1189 break;
1190 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1191 case OMAP_ECC_BCH4_CODE_HW:
1192 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1193 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1194 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1195 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1196 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1197 ((bch_val1 >> 28) & 0xF);
1198 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1199 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1200 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1201 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1202 break;
1203 case OMAP_ECC_BCH16_CODE_HW:
1204 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1205 ecc_code[0] = ((val >> 8) & 0xFF);
1206 ecc_code[1] = ((val >> 0) & 0xFF);
1207 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1208 ecc_code[2] = ((val >> 24) & 0xFF);
1209 ecc_code[3] = ((val >> 16) & 0xFF);
1210 ecc_code[4] = ((val >> 8) & 0xFF);
1211 ecc_code[5] = ((val >> 0) & 0xFF);
1212 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1213 ecc_code[6] = ((val >> 24) & 0xFF);
1214 ecc_code[7] = ((val >> 16) & 0xFF);
1215 ecc_code[8] = ((val >> 8) & 0xFF);
1216 ecc_code[9] = ((val >> 0) & 0xFF);
1217 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1218 ecc_code[10] = ((val >> 24) & 0xFF);
1219 ecc_code[11] = ((val >> 16) & 0xFF);
1220 ecc_code[12] = ((val >> 8) & 0xFF);
1221 ecc_code[13] = ((val >> 0) & 0xFF);
1222 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1223 ecc_code[14] = ((val >> 24) & 0xFF);
1224 ecc_code[15] = ((val >> 16) & 0xFF);
1225 ecc_code[16] = ((val >> 8) & 0xFF);
1226 ecc_code[17] = ((val >> 0) & 0xFF);
1227 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1228 ecc_code[18] = ((val >> 24) & 0xFF);
1229 ecc_code[19] = ((val >> 16) & 0xFF);
1230 ecc_code[20] = ((val >> 8) & 0xFF);
1231 ecc_code[21] = ((val >> 0) & 0xFF);
1232 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1233 ecc_code[22] = ((val >> 24) & 0xFF);
1234 ecc_code[23] = ((val >> 16) & 0xFF);
1235 ecc_code[24] = ((val >> 8) & 0xFF);
1236 ecc_code[25] = ((val >> 0) & 0xFF);
1237 break;
1238 default:
1239 return -EINVAL;
1240 }
1241
1242 /* ECC scheme specific syndrome customizations */
1243 switch (info->ecc_opt) {
1244 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1245 /* Add constant polynomial to remainder, so that
1246 * ECC of blank pages results in 0x0 on reading back */
1247 for (j = 0; j < eccbytes; j++)
1248 ecc_calc[j] ^= bch4_polynomial[j];
1249 break;
1250 case OMAP_ECC_BCH4_CODE_HW:
1251 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1252 ecc_calc[eccbytes - 1] = 0x0;
1253 break;
1254 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1255 /* Add constant polynomial to remainder, so that
1256 * ECC of blank pages results in 0x0 on reading back */
1257 for (j = 0; j < eccbytes; j++)
1258 ecc_calc[j] ^= bch8_polynomial[j];
1259 break;
1260 case OMAP_ECC_BCH8_CODE_HW:
1261 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1262 ecc_calc[eccbytes - 1] = 0x0;
1263 break;
1264 case OMAP_ECC_BCH16_CODE_HW:
1265 break;
1266 default:
1267 return -EINVAL;
1268 }
1269
1270 ecc_calc += eccbytes;
1271 }
1272
1273 return 0;
1274 }
1275
1276 /**
1277 * erased_sector_bitflips - count bit flips
1278 * @data: data sector buffer
1279 * @oob: oob buffer
1280 * @info: omap_nand_info
1281 *
1282 * Check the bit flips in erased page falls below correctable level.
1283 * If falls below, report the page as erased with correctable bit
1284 * flip, else report as uncorrectable page.
1285 */
1286 static int erased_sector_bitflips(u_char *data, u_char *oob,
1287 struct omap_nand_info *info)
1288 {
1289 int flip_bits = 0, i;
1290
1291 for (i = 0; i < info->nand.ecc.size; i++) {
1292 flip_bits += hweight8(~data[i]);
1293 if (flip_bits > info->nand.ecc.strength)
1294 return 0;
1295 }
1296
1297 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1298 flip_bits += hweight8(~oob[i]);
1299 if (flip_bits > info->nand.ecc.strength)
1300 return 0;
1301 }
1302
1303 /*
1304 * Bit flips falls in correctable level.
1305 * Fill data area with 0xFF
1306 */
1307 if (flip_bits) {
1308 memset(data, 0xFF, info->nand.ecc.size);
1309 memset(oob, 0xFF, info->nand.ecc.bytes);
1310 }
1311
1312 return flip_bits;
1313 }
1314
1315 /**
1316 * omap_elm_correct_data - corrects page data area in case error reported
1317 * @mtd: MTD device structure
1318 * @data: page data
1319 * @read_ecc: ecc read from nand flash
1320 * @calc_ecc: ecc read from HW ECC registers
1321 *
1322 * Calculated ecc vector reported as zero in case of non-error pages.
1323 * In case of non-zero ecc vector, first filter out erased-pages, and
1324 * then process data via ELM to detect bit-flips.
1325 */
1326 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1327 u_char *read_ecc, u_char *calc_ecc)
1328 {
1329 struct omap_nand_info *info = mtd_to_omap(mtd);
1330 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1331 int eccsteps = info->nand.ecc.steps;
1332 int i , j, stat = 0;
1333 int eccflag, actual_eccbytes;
1334 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1335 u_char *ecc_vec = calc_ecc;
1336 u_char *spare_ecc = read_ecc;
1337 u_char *erased_ecc_vec;
1338 u_char *buf;
1339 int bitflip_count;
1340 bool is_error_reported = false;
1341 u32 bit_pos, byte_pos, error_max, pos;
1342 int err;
1343
1344 switch (info->ecc_opt) {
1345 case OMAP_ECC_BCH4_CODE_HW:
1346 /* omit 7th ECC byte reserved for ROM code compatibility */
1347 actual_eccbytes = ecc->bytes - 1;
1348 erased_ecc_vec = bch4_vector;
1349 break;
1350 case OMAP_ECC_BCH8_CODE_HW:
1351 /* omit 14th ECC byte reserved for ROM code compatibility */
1352 actual_eccbytes = ecc->bytes - 1;
1353 erased_ecc_vec = bch8_vector;
1354 break;
1355 case OMAP_ECC_BCH16_CODE_HW:
1356 actual_eccbytes = ecc->bytes;
1357 erased_ecc_vec = bch16_vector;
1358 break;
1359 default:
1360 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1361 return -EINVAL;
1362 }
1363
1364 /* Initialize elm error vector to zero */
1365 memset(err_vec, 0, sizeof(err_vec));
1366
1367 for (i = 0; i < eccsteps ; i++) {
1368 eccflag = 0; /* initialize eccflag */
1369
1370 /*
1371 * Check any error reported,
1372 * In case of error, non zero ecc reported.
1373 */
1374 for (j = 0; j < actual_eccbytes; j++) {
1375 if (calc_ecc[j] != 0) {
1376 eccflag = 1; /* non zero ecc, error present */
1377 break;
1378 }
1379 }
1380
1381 if (eccflag == 1) {
1382 if (memcmp(calc_ecc, erased_ecc_vec,
1383 actual_eccbytes) == 0) {
1384 /*
1385 * calc_ecc[] matches pattern for ECC(all 0xff)
1386 * so this is definitely an erased-page
1387 */
1388 } else {
1389 buf = &data[info->nand.ecc.size * i];
1390 /*
1391 * count number of 0-bits in read_buf.
1392 * This check can be removed once a similar
1393 * check is introduced in generic NAND driver
1394 */
1395 bitflip_count = erased_sector_bitflips(
1396 buf, read_ecc, info);
1397 if (bitflip_count) {
1398 /*
1399 * number of 0-bits within ECC limits
1400 * So this may be an erased-page
1401 */
1402 stat += bitflip_count;
1403 } else {
1404 /*
1405 * Too many 0-bits. It may be a
1406 * - programmed-page, OR
1407 * - erased-page with many bit-flips
1408 * So this page requires check by ELM
1409 */
1410 err_vec[i].error_reported = true;
1411 is_error_reported = true;
1412 }
1413 }
1414 }
1415
1416 /* Update the ecc vector */
1417 calc_ecc += ecc->bytes;
1418 read_ecc += ecc->bytes;
1419 }
1420
1421 /* Check if any error reported */
1422 if (!is_error_reported)
1423 return stat;
1424
1425 /* Decode BCH error using ELM module */
1426 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1427
1428 err = 0;
1429 for (i = 0; i < eccsteps; i++) {
1430 if (err_vec[i].error_uncorrectable) {
1431 dev_err(&info->pdev->dev,
1432 "uncorrectable bit-flips found\n");
1433 err = -EBADMSG;
1434 } else if (err_vec[i].error_reported) {
1435 for (j = 0; j < err_vec[i].error_count; j++) {
1436 switch (info->ecc_opt) {
1437 case OMAP_ECC_BCH4_CODE_HW:
1438 /* Add 4 bits to take care of padding */
1439 pos = err_vec[i].error_loc[j] +
1440 BCH4_BIT_PAD;
1441 break;
1442 case OMAP_ECC_BCH8_CODE_HW:
1443 case OMAP_ECC_BCH16_CODE_HW:
1444 pos = err_vec[i].error_loc[j];
1445 break;
1446 default:
1447 return -EINVAL;
1448 }
1449 error_max = (ecc->size + actual_eccbytes) * 8;
1450 /* Calculate bit position of error */
1451 bit_pos = pos % 8;
1452
1453 /* Calculate byte position of error */
1454 byte_pos = (error_max - pos - 1) / 8;
1455
1456 if (pos < error_max) {
1457 if (byte_pos < 512) {
1458 pr_debug("bitflip@dat[%d]=%x\n",
1459 byte_pos, data[byte_pos]);
1460 data[byte_pos] ^= 1 << bit_pos;
1461 } else {
1462 pr_debug("bitflip@oob[%d]=%x\n",
1463 (byte_pos - 512),
1464 spare_ecc[byte_pos - 512]);
1465 spare_ecc[byte_pos - 512] ^=
1466 1 << bit_pos;
1467 }
1468 } else {
1469 dev_err(&info->pdev->dev,
1470 "invalid bit-flip @ %d:%d\n",
1471 byte_pos, bit_pos);
1472 err = -EBADMSG;
1473 }
1474 }
1475 }
1476
1477 /* Update number of correctable errors */
1478 stat += err_vec[i].error_count;
1479
1480 /* Update page data with sector size */
1481 data += ecc->size;
1482 spare_ecc += ecc->bytes;
1483 }
1484
1485 return (err) ? err : stat;
1486 }
1487
1488 /**
1489 * omap_write_page_bch - BCH ecc based write page function for entire page
1490 * @mtd: mtd info structure
1491 * @chip: nand chip info structure
1492 * @buf: data buffer
1493 * @oob_required: must write chip->oob_poi to OOB
1494 * @page: page
1495 *
1496 * Custom write page method evolved to support multi sector writing in one shot
1497 */
1498 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1499 const uint8_t *buf, int oob_required, int page)
1500 {
1501 int i;
1502 uint8_t *ecc_calc = chip->buffers->ecccalc;
1503 uint32_t *eccpos = chip->ecc.layout->eccpos;
1504
1505 /* Enable GPMC ecc engine */
1506 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1507
1508 /* Write data */
1509 chip->write_buf(mtd, buf, mtd->writesize);
1510
1511 /* Update ecc vector from GPMC result registers */
1512 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1513
1514 for (i = 0; i < chip->ecc.total; i++)
1515 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1516
1517 /* Write ecc vector to OOB area */
1518 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1519 return 0;
1520 }
1521
1522 /**
1523 * omap_read_page_bch - BCH ecc based page read function for entire page
1524 * @mtd: mtd info structure
1525 * @chip: nand chip info structure
1526 * @buf: buffer to store read data
1527 * @oob_required: caller requires OOB data read to chip->oob_poi
1528 * @page: page number to read
1529 *
1530 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1531 * used for error correction.
1532 * Custom method evolved to support ELM error correction & multi sector
1533 * reading. On reading page data area is read along with OOB data with
1534 * ecc engine enabled. ecc vector updated after read of OOB data.
1535 * For non error pages ecc vector reported as zero.
1536 */
1537 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1538 uint8_t *buf, int oob_required, int page)
1539 {
1540 uint8_t *ecc_calc = chip->buffers->ecccalc;
1541 uint8_t *ecc_code = chip->buffers->ecccode;
1542 uint32_t *eccpos = chip->ecc.layout->eccpos;
1543 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1544 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1545 int stat;
1546 unsigned int max_bitflips = 0;
1547
1548 /* Enable GPMC ecc engine */
1549 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1550
1551 /* Read data */
1552 chip->read_buf(mtd, buf, mtd->writesize);
1553
1554 /* Read oob bytes */
1555 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1556 chip->read_buf(mtd, oob, chip->ecc.total);
1557
1558 /* Calculate ecc bytes */
1559 chip->ecc.calculate(mtd, buf, ecc_calc);
1560
1561 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1562
1563 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1564
1565 if (stat < 0) {
1566 mtd->ecc_stats.failed++;
1567 } else {
1568 mtd->ecc_stats.corrected += stat;
1569 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1570 }
1571
1572 return max_bitflips;
1573 }
1574
1575 /**
1576 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1577 * @omap_nand_info: NAND device structure containing platform data
1578 */
1579 static bool is_elm_present(struct omap_nand_info *info,
1580 struct device_node *elm_node)
1581 {
1582 struct platform_device *pdev;
1583
1584 /* check whether elm-id is passed via DT */
1585 if (!elm_node) {
1586 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1587 return false;
1588 }
1589 pdev = of_find_device_by_node(elm_node);
1590 /* check whether ELM device is registered */
1591 if (!pdev) {
1592 dev_err(&info->pdev->dev, "ELM device not found\n");
1593 return false;
1594 }
1595 /* ELM module available, now configure it */
1596 info->elm_dev = &pdev->dev;
1597 return true;
1598 }
1599
1600 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1601 struct omap_nand_platform_data *pdata)
1602 {
1603 bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1604
1605 switch (info->ecc_opt) {
1606 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1607 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1608 ecc_needs_omap_bch = false;
1609 ecc_needs_bch = true;
1610 ecc_needs_elm = false;
1611 break;
1612 case OMAP_ECC_BCH4_CODE_HW:
1613 case OMAP_ECC_BCH8_CODE_HW:
1614 case OMAP_ECC_BCH16_CODE_HW:
1615 ecc_needs_omap_bch = true;
1616 ecc_needs_bch = false;
1617 ecc_needs_elm = true;
1618 break;
1619 default:
1620 ecc_needs_omap_bch = false;
1621 ecc_needs_bch = false;
1622 ecc_needs_elm = false;
1623 break;
1624 }
1625
1626 if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1627 dev_err(&info->pdev->dev,
1628 "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1629 return false;
1630 }
1631 if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1632 dev_err(&info->pdev->dev,
1633 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1634 return false;
1635 }
1636 if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) {
1637 dev_err(&info->pdev->dev, "ELM not available\n");
1638 return false;
1639 }
1640
1641 return true;
1642 }
1643
1644 static int omap_nand_probe(struct platform_device *pdev)
1645 {
1646 struct omap_nand_info *info;
1647 struct omap_nand_platform_data *pdata;
1648 struct mtd_info *mtd;
1649 struct nand_chip *nand_chip;
1650 struct nand_ecclayout *ecclayout;
1651 int err;
1652 int i;
1653 dma_cap_mask_t mask;
1654 unsigned sig;
1655 unsigned oob_index;
1656 struct resource *res;
1657
1658 pdata = dev_get_platdata(&pdev->dev);
1659 if (pdata == NULL) {
1660 dev_err(&pdev->dev, "platform data missing\n");
1661 return -ENODEV;
1662 }
1663
1664 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1665 GFP_KERNEL);
1666 if (!info)
1667 return -ENOMEM;
1668
1669 platform_set_drvdata(pdev, info);
1670
1671 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
1672 if (!info->ops) {
1673 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
1674 return -ENODEV;
1675 }
1676 info->pdev = pdev;
1677 info->gpmc_cs = pdata->cs;
1678 info->of_node = pdata->of_node;
1679 info->ecc_opt = pdata->ecc_opt;
1680 nand_chip = &info->nand;
1681 mtd = nand_to_mtd(nand_chip);
1682 mtd->dev.parent = &pdev->dev;
1683 nand_chip->ecc.priv = NULL;
1684 nand_set_flash_node(nand_chip, pdata->of_node);
1685
1686 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1687 nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1688 if (IS_ERR(nand_chip->IO_ADDR_R))
1689 return PTR_ERR(nand_chip->IO_ADDR_R);
1690
1691 info->phys_base = res->start;
1692
1693 nand_chip->controller = &omap_gpmc_controller;
1694
1695 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1696 nand_chip->cmd_ctrl = omap_hwcontrol;
1697
1698 /*
1699 * If RDY/BSY line is connected to OMAP then use the omap ready
1700 * function and the generic nand_wait function which reads the status
1701 * register after monitoring the RDY/BSY line. Otherwise use a standard
1702 * chip delay which is slightly more than tR (AC Timing) of the NAND
1703 * device and read status register until you get a failure or success
1704 */
1705 if (pdata->dev_ready) {
1706 nand_chip->dev_ready = omap_dev_ready;
1707 nand_chip->chip_delay = 0;
1708 } else {
1709 nand_chip->waitfunc = omap_wait;
1710 nand_chip->chip_delay = 50;
1711 }
1712
1713 if (pdata->flash_bbt)
1714 nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1715 else
1716 nand_chip->options |= NAND_SKIP_BBTSCAN;
1717
1718 /* scan NAND device connected to chip controller */
1719 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1720 if (nand_scan_ident(mtd, 1, NULL)) {
1721 dev_err(&info->pdev->dev, "scan failed, may be bus-width mismatch\n");
1722 err = -ENXIO;
1723 goto return_error;
1724 }
1725
1726 /* re-populate low-level callbacks based on xfer modes */
1727 switch (pdata->xfer_type) {
1728 case NAND_OMAP_PREFETCH_POLLED:
1729 nand_chip->read_buf = omap_read_buf_pref;
1730 nand_chip->write_buf = omap_write_buf_pref;
1731 break;
1732
1733 case NAND_OMAP_POLLED:
1734 /* Use nand_base defaults for {read,write}_buf */
1735 break;
1736
1737 case NAND_OMAP_PREFETCH_DMA:
1738 dma_cap_zero(mask);
1739 dma_cap_set(DMA_SLAVE, mask);
1740 sig = OMAP24XX_DMA_GPMC;
1741 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1742 if (!info->dma) {
1743 dev_err(&pdev->dev, "DMA engine request failed\n");
1744 err = -ENXIO;
1745 goto return_error;
1746 } else {
1747 struct dma_slave_config cfg;
1748
1749 memset(&cfg, 0, sizeof(cfg));
1750 cfg.src_addr = info->phys_base;
1751 cfg.dst_addr = info->phys_base;
1752 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1753 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1754 cfg.src_maxburst = 16;
1755 cfg.dst_maxburst = 16;
1756 err = dmaengine_slave_config(info->dma, &cfg);
1757 if (err) {
1758 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1759 err);
1760 goto return_error;
1761 }
1762 nand_chip->read_buf = omap_read_buf_dma_pref;
1763 nand_chip->write_buf = omap_write_buf_dma_pref;
1764 }
1765 break;
1766
1767 case NAND_OMAP_PREFETCH_IRQ:
1768 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1769 if (info->gpmc_irq_fifo <= 0) {
1770 dev_err(&pdev->dev, "error getting fifo irq\n");
1771 err = -ENODEV;
1772 goto return_error;
1773 }
1774 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1775 omap_nand_irq, IRQF_SHARED,
1776 "gpmc-nand-fifo", info);
1777 if (err) {
1778 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1779 info->gpmc_irq_fifo, err);
1780 info->gpmc_irq_fifo = 0;
1781 goto return_error;
1782 }
1783
1784 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1785 if (info->gpmc_irq_count <= 0) {
1786 dev_err(&pdev->dev, "error getting count irq\n");
1787 err = -ENODEV;
1788 goto return_error;
1789 }
1790 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1791 omap_nand_irq, IRQF_SHARED,
1792 "gpmc-nand-count", info);
1793 if (err) {
1794 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1795 info->gpmc_irq_count, err);
1796 info->gpmc_irq_count = 0;
1797 goto return_error;
1798 }
1799
1800 nand_chip->read_buf = omap_read_buf_irq_pref;
1801 nand_chip->write_buf = omap_write_buf_irq_pref;
1802
1803 break;
1804
1805 default:
1806 dev_err(&pdev->dev,
1807 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1808 err = -EINVAL;
1809 goto return_error;
1810 }
1811
1812 if (!omap2_nand_ecc_check(info, pdata)) {
1813 err = -EINVAL;
1814 goto return_error;
1815 }
1816
1817 /*
1818 * Bail out earlier to let NAND_ECC_SOFT code create its own
1819 * ecclayout instead of using ours.
1820 */
1821 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
1822 nand_chip->ecc.mode = NAND_ECC_SOFT;
1823 goto scan_tail;
1824 }
1825
1826 /* populate MTD interface based on ECC scheme */
1827 ecclayout = &info->oobinfo;
1828 nand_chip->ecc.layout = ecclayout;
1829 switch (info->ecc_opt) {
1830 case OMAP_ECC_HAM1_CODE_HW:
1831 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1832 nand_chip->ecc.mode = NAND_ECC_HW;
1833 nand_chip->ecc.bytes = 3;
1834 nand_chip->ecc.size = 512;
1835 nand_chip->ecc.strength = 1;
1836 nand_chip->ecc.calculate = omap_calculate_ecc;
1837 nand_chip->ecc.hwctl = omap_enable_hwecc;
1838 nand_chip->ecc.correct = omap_correct_data;
1839 /* define ECC layout */
1840 ecclayout->eccbytes = nand_chip->ecc.bytes *
1841 (mtd->writesize /
1842 nand_chip->ecc.size);
1843 if (nand_chip->options & NAND_BUSWIDTH_16)
1844 oob_index = BADBLOCK_MARKER_LENGTH;
1845 else
1846 oob_index = 1;
1847 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1848 ecclayout->eccpos[i] = oob_index;
1849 /* no reserved-marker in ecclayout for this ecc-scheme */
1850 ecclayout->oobfree->offset =
1851 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1852 break;
1853
1854 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1855 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1856 nand_chip->ecc.mode = NAND_ECC_HW;
1857 nand_chip->ecc.size = 512;
1858 nand_chip->ecc.bytes = 7;
1859 nand_chip->ecc.strength = 4;
1860 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1861 nand_chip->ecc.correct = nand_bch_correct_data;
1862 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1863 /* define ECC layout */
1864 ecclayout->eccbytes = nand_chip->ecc.bytes *
1865 (mtd->writesize /
1866 nand_chip->ecc.size);
1867 oob_index = BADBLOCK_MARKER_LENGTH;
1868 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1869 ecclayout->eccpos[i] = oob_index;
1870 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1871 oob_index++;
1872 }
1873 /* include reserved-marker in ecclayout->oobfree calculation */
1874 ecclayout->oobfree->offset = 1 +
1875 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1876 /* software bch library is used for locating errors */
1877 nand_chip->ecc.priv = nand_bch_init(mtd);
1878 if (!nand_chip->ecc.priv) {
1879 dev_err(&info->pdev->dev, "unable to use BCH library\n");
1880 err = -EINVAL;
1881 goto return_error;
1882 }
1883 break;
1884
1885 case OMAP_ECC_BCH4_CODE_HW:
1886 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1887 nand_chip->ecc.mode = NAND_ECC_HW;
1888 nand_chip->ecc.size = 512;
1889 /* 14th bit is kept reserved for ROM-code compatibility */
1890 nand_chip->ecc.bytes = 7 + 1;
1891 nand_chip->ecc.strength = 4;
1892 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1893 nand_chip->ecc.correct = omap_elm_correct_data;
1894 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1895 nand_chip->ecc.read_page = omap_read_page_bch;
1896 nand_chip->ecc.write_page = omap_write_page_bch;
1897 /* define ECC layout */
1898 ecclayout->eccbytes = nand_chip->ecc.bytes *
1899 (mtd->writesize /
1900 nand_chip->ecc.size);
1901 oob_index = BADBLOCK_MARKER_LENGTH;
1902 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1903 ecclayout->eccpos[i] = oob_index;
1904 /* reserved marker already included in ecclayout->eccbytes */
1905 ecclayout->oobfree->offset =
1906 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1907
1908 err = elm_config(info->elm_dev, BCH4_ECC,
1909 mtd->writesize / nand_chip->ecc.size,
1910 nand_chip->ecc.size, nand_chip->ecc.bytes);
1911 if (err < 0)
1912 goto return_error;
1913 break;
1914
1915 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1916 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1917 nand_chip->ecc.mode = NAND_ECC_HW;
1918 nand_chip->ecc.size = 512;
1919 nand_chip->ecc.bytes = 13;
1920 nand_chip->ecc.strength = 8;
1921 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1922 nand_chip->ecc.correct = nand_bch_correct_data;
1923 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1924 /* define ECC layout */
1925 ecclayout->eccbytes = nand_chip->ecc.bytes *
1926 (mtd->writesize /
1927 nand_chip->ecc.size);
1928 oob_index = BADBLOCK_MARKER_LENGTH;
1929 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1930 ecclayout->eccpos[i] = oob_index;
1931 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1932 oob_index++;
1933 }
1934 /* include reserved-marker in ecclayout->oobfree calculation */
1935 ecclayout->oobfree->offset = 1 +
1936 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1937 /* software bch library is used for locating errors */
1938 nand_chip->ecc.priv = nand_bch_init(mtd);
1939 if (!nand_chip->ecc.priv) {
1940 dev_err(&info->pdev->dev, "unable to use BCH library\n");
1941 err = -EINVAL;
1942 goto return_error;
1943 }
1944 break;
1945
1946 case OMAP_ECC_BCH8_CODE_HW:
1947 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1948 nand_chip->ecc.mode = NAND_ECC_HW;
1949 nand_chip->ecc.size = 512;
1950 /* 14th bit is kept reserved for ROM-code compatibility */
1951 nand_chip->ecc.bytes = 13 + 1;
1952 nand_chip->ecc.strength = 8;
1953 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1954 nand_chip->ecc.correct = omap_elm_correct_data;
1955 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1956 nand_chip->ecc.read_page = omap_read_page_bch;
1957 nand_chip->ecc.write_page = omap_write_page_bch;
1958
1959 err = elm_config(info->elm_dev, BCH8_ECC,
1960 mtd->writesize / nand_chip->ecc.size,
1961 nand_chip->ecc.size, nand_chip->ecc.bytes);
1962 if (err < 0)
1963 goto return_error;
1964
1965 /* define ECC layout */
1966 ecclayout->eccbytes = nand_chip->ecc.bytes *
1967 (mtd->writesize /
1968 nand_chip->ecc.size);
1969 oob_index = BADBLOCK_MARKER_LENGTH;
1970 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1971 ecclayout->eccpos[i] = oob_index;
1972 /* reserved marker already included in ecclayout->eccbytes */
1973 ecclayout->oobfree->offset =
1974 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1975 break;
1976
1977 case OMAP_ECC_BCH16_CODE_HW:
1978 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
1979 nand_chip->ecc.mode = NAND_ECC_HW;
1980 nand_chip->ecc.size = 512;
1981 nand_chip->ecc.bytes = 26;
1982 nand_chip->ecc.strength = 16;
1983 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1984 nand_chip->ecc.correct = omap_elm_correct_data;
1985 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1986 nand_chip->ecc.read_page = omap_read_page_bch;
1987 nand_chip->ecc.write_page = omap_write_page_bch;
1988
1989 err = elm_config(info->elm_dev, BCH16_ECC,
1990 mtd->writesize / nand_chip->ecc.size,
1991 nand_chip->ecc.size, nand_chip->ecc.bytes);
1992 if (err < 0)
1993 goto return_error;
1994
1995 /* define ECC layout */
1996 ecclayout->eccbytes = nand_chip->ecc.bytes *
1997 (mtd->writesize /
1998 nand_chip->ecc.size);
1999 oob_index = BADBLOCK_MARKER_LENGTH;
2000 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2001 ecclayout->eccpos[i] = oob_index;
2002 /* reserved marker already included in ecclayout->eccbytes */
2003 ecclayout->oobfree->offset =
2004 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2005 break;
2006 default:
2007 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2008 err = -EINVAL;
2009 goto return_error;
2010 }
2011
2012 /* all OOB bytes from oobfree->offset till end off OOB are free */
2013 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2014 /* check if NAND device's OOB is enough to store ECC signatures */
2015 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2016 dev_err(&info->pdev->dev,
2017 "not enough OOB bytes required = %d, available=%d\n",
2018 ecclayout->eccbytes, mtd->oobsize);
2019 err = -EINVAL;
2020 goto return_error;
2021 }
2022
2023 scan_tail:
2024 /* second phase scan */
2025 if (nand_scan_tail(mtd)) {
2026 err = -ENXIO;
2027 goto return_error;
2028 }
2029
2030 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2031
2032 platform_set_drvdata(pdev, mtd);
2033
2034 return 0;
2035
2036 return_error:
2037 if (info->dma)
2038 dma_release_channel(info->dma);
2039 if (nand_chip->ecc.priv) {
2040 nand_bch_free(nand_chip->ecc.priv);
2041 nand_chip->ecc.priv = NULL;
2042 }
2043 return err;
2044 }
2045
2046 static int omap_nand_remove(struct platform_device *pdev)
2047 {
2048 struct mtd_info *mtd = platform_get_drvdata(pdev);
2049 struct nand_chip *nand_chip = mtd_to_nand(mtd);
2050 struct omap_nand_info *info = mtd_to_omap(mtd);
2051 if (nand_chip->ecc.priv) {
2052 nand_bch_free(nand_chip->ecc.priv);
2053 nand_chip->ecc.priv = NULL;
2054 }
2055 if (info->dma)
2056 dma_release_channel(info->dma);
2057 nand_release(mtd);
2058 return 0;
2059 }
2060
2061 static struct platform_driver omap_nand_driver = {
2062 .probe = omap_nand_probe,
2063 .remove = omap_nand_remove,
2064 .driver = {
2065 .name = DRIVER_NAME,
2066 },
2067 };
2068
2069 module_platform_driver(omap_nand_driver);
2070
2071 MODULE_ALIAS("platform:" DRIVER_NAME);
2072 MODULE_LICENSE("GPL");
2073 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux kernel - Deliverables
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