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mtd: nand: omap: ecc.hwctl: rename omap3_enable_hwecc_bch to omap_enable_hwecc_bch
[deliverable/linux.git] / drivers / mtd / nand / omap2.c
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/platform_data/mtd-nand-omap2.h>
32
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
35
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
48
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
61
62 #define TF(value) (value ? 1 : 0)
63
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
105 #define CS_MASK 0x7
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
112 #define ECC1 0x1
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
118
119 #define OMAP24XX_DMA_GPMC 4
120
121 #define SECTOR_BYTES 512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD 4
124
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
131
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136
137 #define BADBLOCK_MARKER_LENGTH 2
138
139 #ifdef CONFIG_MTD_NAND_OMAP_BCH
140 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
141 0xac, 0x6b, 0xff, 0x99, 0x7b};
142 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
143 #endif
144
145 /* oob info generated runtime depending on ecc algorithm and layout selected */
146 static struct nand_ecclayout omap_oobinfo;
147
148 struct omap_nand_info {
149 struct nand_hw_control controller;
150 struct omap_nand_platform_data *pdata;
151 struct mtd_info mtd;
152 struct nand_chip nand;
153 struct platform_device *pdev;
154
155 int gpmc_cs;
156 unsigned long phys_base;
157 unsigned long mem_size;
158 enum omap_ecc ecc_opt;
159 struct completion comp;
160 struct dma_chan *dma;
161 int gpmc_irq_fifo;
162 int gpmc_irq_count;
163 enum {
164 OMAP_NAND_IO_READ = 0, /* read */
165 OMAP_NAND_IO_WRITE, /* write */
166 } iomode;
167 u_char *buf;
168 int buf_len;
169 struct gpmc_nand_regs reg;
170 /* fields specific for BCHx_HW ECC scheme */
171 bool is_elm_used;
172 struct device *elm_dev;
173 struct device_node *of_node;
174 };
175
176 /**
177 * omap_prefetch_enable - configures and starts prefetch transfer
178 * @cs: cs (chip select) number
179 * @fifo_th: fifo threshold to be used for read/ write
180 * @dma_mode: dma mode enable (1) or disable (0)
181 * @u32_count: number of bytes to be transferred
182 * @is_write: prefetch read(0) or write post(1) mode
183 */
184 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
185 unsigned int u32_count, int is_write, struct omap_nand_info *info)
186 {
187 u32 val;
188
189 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
190 return -1;
191
192 if (readl(info->reg.gpmc_prefetch_control))
193 return -EBUSY;
194
195 /* Set the amount of bytes to be prefetched */
196 writel(u32_count, info->reg.gpmc_prefetch_config2);
197
198 /* Set dma/mpu mode, the prefetch read / post write and
199 * enable the engine. Set which cs is has requested for.
200 */
201 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
202 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
203 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
204 writel(val, info->reg.gpmc_prefetch_config1);
205
206 /* Start the prefetch engine */
207 writel(0x1, info->reg.gpmc_prefetch_control);
208
209 return 0;
210 }
211
212 /**
213 * omap_prefetch_reset - disables and stops the prefetch engine
214 */
215 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
216 {
217 u32 config1;
218
219 /* check if the same module/cs is trying to reset */
220 config1 = readl(info->reg.gpmc_prefetch_config1);
221 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
222 return -EINVAL;
223
224 /* Stop the PFPW engine */
225 writel(0x0, info->reg.gpmc_prefetch_control);
226
227 /* Reset/disable the PFPW engine */
228 writel(0x0, info->reg.gpmc_prefetch_config1);
229
230 return 0;
231 }
232
233 /**
234 * omap_hwcontrol - hardware specific access to control-lines
235 * @mtd: MTD device structure
236 * @cmd: command to device
237 * @ctrl:
238 * NAND_NCE: bit 0 -> don't care
239 * NAND_CLE: bit 1 -> Command Latch
240 * NAND_ALE: bit 2 -> Address Latch
241 *
242 * NOTE: boards may use different bits for these!!
243 */
244 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
245 {
246 struct omap_nand_info *info = container_of(mtd,
247 struct omap_nand_info, mtd);
248
249 if (cmd != NAND_CMD_NONE) {
250 if (ctrl & NAND_CLE)
251 writeb(cmd, info->reg.gpmc_nand_command);
252
253 else if (ctrl & NAND_ALE)
254 writeb(cmd, info->reg.gpmc_nand_address);
255
256 else /* NAND_NCE */
257 writeb(cmd, info->reg.gpmc_nand_data);
258 }
259 }
260
261 /**
262 * omap_read_buf8 - read data from NAND controller into buffer
263 * @mtd: MTD device structure
264 * @buf: buffer to store date
265 * @len: number of bytes to read
266 */
267 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
268 {
269 struct nand_chip *nand = mtd->priv;
270
271 ioread8_rep(nand->IO_ADDR_R, buf, len);
272 }
273
274 /**
275 * omap_write_buf8 - write buffer to NAND controller
276 * @mtd: MTD device structure
277 * @buf: data buffer
278 * @len: number of bytes to write
279 */
280 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
281 {
282 struct omap_nand_info *info = container_of(mtd,
283 struct omap_nand_info, mtd);
284 u_char *p = (u_char *)buf;
285 u32 status = 0;
286
287 while (len--) {
288 iowrite8(*p++, info->nand.IO_ADDR_W);
289 /* wait until buffer is available for write */
290 do {
291 status = readl(info->reg.gpmc_status) &
292 STATUS_BUFF_EMPTY;
293 } while (!status);
294 }
295 }
296
297 /**
298 * omap_read_buf16 - read data from NAND controller into buffer
299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
302 */
303 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
304 {
305 struct nand_chip *nand = mtd->priv;
306
307 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
308 }
309
310 /**
311 * omap_write_buf16 - write buffer to NAND controller
312 * @mtd: MTD device structure
313 * @buf: data buffer
314 * @len: number of bytes to write
315 */
316 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
317 {
318 struct omap_nand_info *info = container_of(mtd,
319 struct omap_nand_info, mtd);
320 u16 *p = (u16 *) buf;
321 u32 status = 0;
322 /* FIXME try bursts of writesw() or DMA ... */
323 len >>= 1;
324
325 while (len--) {
326 iowrite16(*p++, info->nand.IO_ADDR_W);
327 /* wait until buffer is available for write */
328 do {
329 status = readl(info->reg.gpmc_status) &
330 STATUS_BUFF_EMPTY;
331 } while (!status);
332 }
333 }
334
335 /**
336 * omap_read_buf_pref - read data from NAND controller into buffer
337 * @mtd: MTD device structure
338 * @buf: buffer to store date
339 * @len: number of bytes to read
340 */
341 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
342 {
343 struct omap_nand_info *info = container_of(mtd,
344 struct omap_nand_info, mtd);
345 uint32_t r_count = 0;
346 int ret = 0;
347 u32 *p = (u32 *)buf;
348
349 /* take care of subpage reads */
350 if (len % 4) {
351 if (info->nand.options & NAND_BUSWIDTH_16)
352 omap_read_buf16(mtd, buf, len % 4);
353 else
354 omap_read_buf8(mtd, buf, len % 4);
355 p = (u32 *) (buf + len % 4);
356 len -= len % 4;
357 }
358
359 /* configure and start prefetch transfer */
360 ret = omap_prefetch_enable(info->gpmc_cs,
361 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
362 if (ret) {
363 /* PFPW engine is busy, use cpu copy method */
364 if (info->nand.options & NAND_BUSWIDTH_16)
365 omap_read_buf16(mtd, (u_char *)p, len);
366 else
367 omap_read_buf8(mtd, (u_char *)p, len);
368 } else {
369 do {
370 r_count = readl(info->reg.gpmc_prefetch_status);
371 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
372 r_count = r_count >> 2;
373 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
374 p += r_count;
375 len -= r_count << 2;
376 } while (len);
377 /* disable and stop the PFPW engine */
378 omap_prefetch_reset(info->gpmc_cs, info);
379 }
380 }
381
382 /**
383 * omap_write_buf_pref - write buffer to NAND controller
384 * @mtd: MTD device structure
385 * @buf: data buffer
386 * @len: number of bytes to write
387 */
388 static void omap_write_buf_pref(struct mtd_info *mtd,
389 const u_char *buf, int len)
390 {
391 struct omap_nand_info *info = container_of(mtd,
392 struct omap_nand_info, mtd);
393 uint32_t w_count = 0;
394 int i = 0, ret = 0;
395 u16 *p = (u16 *)buf;
396 unsigned long tim, limit;
397 u32 val;
398
399 /* take care of subpage writes */
400 if (len % 2 != 0) {
401 writeb(*buf, info->nand.IO_ADDR_W);
402 p = (u16 *)(buf + 1);
403 len--;
404 }
405
406 /* configure and start prefetch transfer */
407 ret = omap_prefetch_enable(info->gpmc_cs,
408 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
409 if (ret) {
410 /* PFPW engine is busy, use cpu copy method */
411 if (info->nand.options & NAND_BUSWIDTH_16)
412 omap_write_buf16(mtd, (u_char *)p, len);
413 else
414 omap_write_buf8(mtd, (u_char *)p, len);
415 } else {
416 while (len) {
417 w_count = readl(info->reg.gpmc_prefetch_status);
418 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
419 w_count = w_count >> 1;
420 for (i = 0; (i < w_count) && len; i++, len -= 2)
421 iowrite16(*p++, info->nand.IO_ADDR_W);
422 }
423 /* wait for data to flushed-out before reset the prefetch */
424 tim = 0;
425 limit = (loops_per_jiffy *
426 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
427 do {
428 cpu_relax();
429 val = readl(info->reg.gpmc_prefetch_status);
430 val = PREFETCH_STATUS_COUNT(val);
431 } while (val && (tim++ < limit));
432
433 /* disable and stop the PFPW engine */
434 omap_prefetch_reset(info->gpmc_cs, info);
435 }
436 }
437
438 /*
439 * omap_nand_dma_callback: callback on the completion of dma transfer
440 * @data: pointer to completion data structure
441 */
442 static void omap_nand_dma_callback(void *data)
443 {
444 complete((struct completion *) data);
445 }
446
447 /*
448 * omap_nand_dma_transfer: configure and start dma transfer
449 * @mtd: MTD device structure
450 * @addr: virtual address in RAM of source/destination
451 * @len: number of data bytes to be transferred
452 * @is_write: flag for read/write operation
453 */
454 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
455 unsigned int len, int is_write)
456 {
457 struct omap_nand_info *info = container_of(mtd,
458 struct omap_nand_info, mtd);
459 struct dma_async_tx_descriptor *tx;
460 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
461 DMA_FROM_DEVICE;
462 struct scatterlist sg;
463 unsigned long tim, limit;
464 unsigned n;
465 int ret;
466 u32 val;
467
468 if (addr >= high_memory) {
469 struct page *p1;
470
471 if (((size_t)addr & PAGE_MASK) !=
472 ((size_t)(addr + len - 1) & PAGE_MASK))
473 goto out_copy;
474 p1 = vmalloc_to_page(addr);
475 if (!p1)
476 goto out_copy;
477 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
478 }
479
480 sg_init_one(&sg, addr, len);
481 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
482 if (n == 0) {
483 dev_err(&info->pdev->dev,
484 "Couldn't DMA map a %d byte buffer\n", len);
485 goto out_copy;
486 }
487
488 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
489 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
490 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
491 if (!tx)
492 goto out_copy_unmap;
493
494 tx->callback = omap_nand_dma_callback;
495 tx->callback_param = &info->comp;
496 dmaengine_submit(tx);
497
498 /* configure and start prefetch transfer */
499 ret = omap_prefetch_enable(info->gpmc_cs,
500 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
501 if (ret)
502 /* PFPW engine is busy, use cpu copy method */
503 goto out_copy_unmap;
504
505 init_completion(&info->comp);
506 dma_async_issue_pending(info->dma);
507
508 /* setup and start DMA using dma_addr */
509 wait_for_completion(&info->comp);
510 tim = 0;
511 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
512
513 do {
514 cpu_relax();
515 val = readl(info->reg.gpmc_prefetch_status);
516 val = PREFETCH_STATUS_COUNT(val);
517 } while (val && (tim++ < limit));
518
519 /* disable and stop the PFPW engine */
520 omap_prefetch_reset(info->gpmc_cs, info);
521
522 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
523 return 0;
524
525 out_copy_unmap:
526 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
527 out_copy:
528 if (info->nand.options & NAND_BUSWIDTH_16)
529 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
530 : omap_write_buf16(mtd, (u_char *) addr, len);
531 else
532 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
533 : omap_write_buf8(mtd, (u_char *) addr, len);
534 return 0;
535 }
536
537 /**
538 * omap_read_buf_dma_pref - read data from NAND controller into buffer
539 * @mtd: MTD device structure
540 * @buf: buffer to store date
541 * @len: number of bytes to read
542 */
543 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
544 {
545 if (len <= mtd->oobsize)
546 omap_read_buf_pref(mtd, buf, len);
547 else
548 /* start transfer in DMA mode */
549 omap_nand_dma_transfer(mtd, buf, len, 0x0);
550 }
551
552 /**
553 * omap_write_buf_dma_pref - write buffer to NAND controller
554 * @mtd: MTD device structure
555 * @buf: data buffer
556 * @len: number of bytes to write
557 */
558 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
559 const u_char *buf, int len)
560 {
561 if (len <= mtd->oobsize)
562 omap_write_buf_pref(mtd, buf, len);
563 else
564 /* start transfer in DMA mode */
565 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
566 }
567
568 /*
569 * omap_nand_irq - GPMC irq handler
570 * @this_irq: gpmc irq number
571 * @dev: omap_nand_info structure pointer is passed here
572 */
573 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
574 {
575 struct omap_nand_info *info = (struct omap_nand_info *) dev;
576 u32 bytes;
577
578 bytes = readl(info->reg.gpmc_prefetch_status);
579 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
580 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
581 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
582 if (this_irq == info->gpmc_irq_count)
583 goto done;
584
585 if (info->buf_len && (info->buf_len < bytes))
586 bytes = info->buf_len;
587 else if (!info->buf_len)
588 bytes = 0;
589 iowrite32_rep(info->nand.IO_ADDR_W,
590 (u32 *)info->buf, bytes >> 2);
591 info->buf = info->buf + bytes;
592 info->buf_len -= bytes;
593
594 } else {
595 ioread32_rep(info->nand.IO_ADDR_R,
596 (u32 *)info->buf, bytes >> 2);
597 info->buf = info->buf + bytes;
598
599 if (this_irq == info->gpmc_irq_count)
600 goto done;
601 }
602
603 return IRQ_HANDLED;
604
605 done:
606 complete(&info->comp);
607
608 disable_irq_nosync(info->gpmc_irq_fifo);
609 disable_irq_nosync(info->gpmc_irq_count);
610
611 return IRQ_HANDLED;
612 }
613
614 /*
615 * omap_read_buf_irq_pref - read data from NAND controller into buffer
616 * @mtd: MTD device structure
617 * @buf: buffer to store date
618 * @len: number of bytes to read
619 */
620 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
621 {
622 struct omap_nand_info *info = container_of(mtd,
623 struct omap_nand_info, mtd);
624 int ret = 0;
625
626 if (len <= mtd->oobsize) {
627 omap_read_buf_pref(mtd, buf, len);
628 return;
629 }
630
631 info->iomode = OMAP_NAND_IO_READ;
632 info->buf = buf;
633 init_completion(&info->comp);
634
635 /* configure and start prefetch transfer */
636 ret = omap_prefetch_enable(info->gpmc_cs,
637 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
638 if (ret)
639 /* PFPW engine is busy, use cpu copy method */
640 goto out_copy;
641
642 info->buf_len = len;
643
644 enable_irq(info->gpmc_irq_count);
645 enable_irq(info->gpmc_irq_fifo);
646
647 /* waiting for read to complete */
648 wait_for_completion(&info->comp);
649
650 /* disable and stop the PFPW engine */
651 omap_prefetch_reset(info->gpmc_cs, info);
652 return;
653
654 out_copy:
655 if (info->nand.options & NAND_BUSWIDTH_16)
656 omap_read_buf16(mtd, buf, len);
657 else
658 omap_read_buf8(mtd, buf, len);
659 }
660
661 /*
662 * omap_write_buf_irq_pref - write buffer to NAND controller
663 * @mtd: MTD device structure
664 * @buf: data buffer
665 * @len: number of bytes to write
666 */
667 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
668 const u_char *buf, int len)
669 {
670 struct omap_nand_info *info = container_of(mtd,
671 struct omap_nand_info, mtd);
672 int ret = 0;
673 unsigned long tim, limit;
674 u32 val;
675
676 if (len <= mtd->oobsize) {
677 omap_write_buf_pref(mtd, buf, len);
678 return;
679 }
680
681 info->iomode = OMAP_NAND_IO_WRITE;
682 info->buf = (u_char *) buf;
683 init_completion(&info->comp);
684
685 /* configure and start prefetch transfer : size=24 */
686 ret = omap_prefetch_enable(info->gpmc_cs,
687 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
688 if (ret)
689 /* PFPW engine is busy, use cpu copy method */
690 goto out_copy;
691
692 info->buf_len = len;
693
694 enable_irq(info->gpmc_irq_count);
695 enable_irq(info->gpmc_irq_fifo);
696
697 /* waiting for write to complete */
698 wait_for_completion(&info->comp);
699
700 /* wait for data to flushed-out before reset the prefetch */
701 tim = 0;
702 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
703 do {
704 val = readl(info->reg.gpmc_prefetch_status);
705 val = PREFETCH_STATUS_COUNT(val);
706 cpu_relax();
707 } while (val && (tim++ < limit));
708
709 /* disable and stop the PFPW engine */
710 omap_prefetch_reset(info->gpmc_cs, info);
711 return;
712
713 out_copy:
714 if (info->nand.options & NAND_BUSWIDTH_16)
715 omap_write_buf16(mtd, buf, len);
716 else
717 omap_write_buf8(mtd, buf, len);
718 }
719
720 /**
721 * gen_true_ecc - This function will generate true ECC value
722 * @ecc_buf: buffer to store ecc code
723 *
724 * This generated true ECC value can be used when correcting
725 * data read from NAND flash memory core
726 */
727 static void gen_true_ecc(u8 *ecc_buf)
728 {
729 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
730 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
731
732 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
733 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
734 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
735 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
736 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
737 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
738 }
739
740 /**
741 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
742 * @ecc_data1: ecc code from nand spare area
743 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
744 * @page_data: page data
745 *
746 * This function compares two ECC's and indicates if there is an error.
747 * If the error can be corrected it will be corrected to the buffer.
748 * If there is no error, %0 is returned. If there is an error but it
749 * was corrected, %1 is returned. Otherwise, %-1 is returned.
750 */
751 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
752 u8 *ecc_data2, /* read from register */
753 u8 *page_data)
754 {
755 uint i;
756 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
757 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
758 u8 ecc_bit[24];
759 u8 ecc_sum = 0;
760 u8 find_bit = 0;
761 uint find_byte = 0;
762 int isEccFF;
763
764 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
765
766 gen_true_ecc(ecc_data1);
767 gen_true_ecc(ecc_data2);
768
769 for (i = 0; i <= 2; i++) {
770 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
771 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
772 }
773
774 for (i = 0; i < 8; i++) {
775 tmp0_bit[i] = *ecc_data1 % 2;
776 *ecc_data1 = *ecc_data1 / 2;
777 }
778
779 for (i = 0; i < 8; i++) {
780 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
781 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
782 }
783
784 for (i = 0; i < 8; i++) {
785 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
786 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
787 }
788
789 for (i = 0; i < 8; i++) {
790 comp0_bit[i] = *ecc_data2 % 2;
791 *ecc_data2 = *ecc_data2 / 2;
792 }
793
794 for (i = 0; i < 8; i++) {
795 comp1_bit[i] = *(ecc_data2 + 1) % 2;
796 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
797 }
798
799 for (i = 0; i < 8; i++) {
800 comp2_bit[i] = *(ecc_data2 + 2) % 2;
801 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
802 }
803
804 for (i = 0; i < 6; i++)
805 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
806
807 for (i = 0; i < 8; i++)
808 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
809
810 for (i = 0; i < 8; i++)
811 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
812
813 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
814 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
815
816 for (i = 0; i < 24; i++)
817 ecc_sum += ecc_bit[i];
818
819 switch (ecc_sum) {
820 case 0:
821 /* Not reached because this function is not called if
822 * ECC values are equal
823 */
824 return 0;
825
826 case 1:
827 /* Uncorrectable error */
828 pr_debug("ECC UNCORRECTED_ERROR 1\n");
829 return -1;
830
831 case 11:
832 /* UN-Correctable error */
833 pr_debug("ECC UNCORRECTED_ERROR B\n");
834 return -1;
835
836 case 12:
837 /* Correctable error */
838 find_byte = (ecc_bit[23] << 8) +
839 (ecc_bit[21] << 7) +
840 (ecc_bit[19] << 6) +
841 (ecc_bit[17] << 5) +
842 (ecc_bit[15] << 4) +
843 (ecc_bit[13] << 3) +
844 (ecc_bit[11] << 2) +
845 (ecc_bit[9] << 1) +
846 ecc_bit[7];
847
848 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
849
850 pr_debug("Correcting single bit ECC error at offset: "
851 "%d, bit: %d\n", find_byte, find_bit);
852
853 page_data[find_byte] ^= (1 << find_bit);
854
855 return 1;
856 default:
857 if (isEccFF) {
858 if (ecc_data2[0] == 0 &&
859 ecc_data2[1] == 0 &&
860 ecc_data2[2] == 0)
861 return 0;
862 }
863 pr_debug("UNCORRECTED_ERROR default\n");
864 return -1;
865 }
866 }
867
868 /**
869 * omap_correct_data - Compares the ECC read with HW generated ECC
870 * @mtd: MTD device structure
871 * @dat: page data
872 * @read_ecc: ecc read from nand flash
873 * @calc_ecc: ecc read from HW ECC registers
874 *
875 * Compares the ecc read from nand spare area with ECC registers values
876 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
877 * detection and correction. If there are no errors, %0 is returned. If
878 * there were errors and all of the errors were corrected, the number of
879 * corrected errors is returned. If uncorrectable errors exist, %-1 is
880 * returned.
881 */
882 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
883 u_char *read_ecc, u_char *calc_ecc)
884 {
885 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
886 mtd);
887 int blockCnt = 0, i = 0, ret = 0;
888 int stat = 0;
889
890 /* Ex NAND_ECC_HW12_2048 */
891 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
892 (info->nand.ecc.size == 2048))
893 blockCnt = 4;
894 else
895 blockCnt = 1;
896
897 for (i = 0; i < blockCnt; i++) {
898 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
899 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
900 if (ret < 0)
901 return ret;
902 /* keep track of the number of corrected errors */
903 stat += ret;
904 }
905 read_ecc += 3;
906 calc_ecc += 3;
907 dat += 512;
908 }
909 return stat;
910 }
911
912 /**
913 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
914 * @mtd: MTD device structure
915 * @dat: The pointer to data on which ecc is computed
916 * @ecc_code: The ecc_code buffer
917 *
918 * Using noninverted ECC can be considered ugly since writing a blank
919 * page ie. padding will clear the ECC bytes. This is no problem as long
920 * nobody is trying to write data on the seemingly unused page. Reading
921 * an erased page will produce an ECC mismatch between generated and read
922 * ECC bytes that has to be dealt with separately.
923 */
924 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
925 u_char *ecc_code)
926 {
927 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
928 mtd);
929 u32 val;
930
931 val = readl(info->reg.gpmc_ecc_config);
932 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
933 return -EINVAL;
934
935 /* read ecc result */
936 val = readl(info->reg.gpmc_ecc1_result);
937 *ecc_code++ = val; /* P128e, ..., P1e */
938 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
939 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
940 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
941
942 return 0;
943 }
944
945 /**
946 * omap_enable_hwecc - This function enables the hardware ecc functionality
947 * @mtd: MTD device structure
948 * @mode: Read/Write mode
949 */
950 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
951 {
952 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
953 mtd);
954 struct nand_chip *chip = mtd->priv;
955 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
956 u32 val;
957
958 /* clear ecc and enable bits */
959 val = ECCCLEAR | ECC1;
960 writel(val, info->reg.gpmc_ecc_control);
961
962 /* program ecc and result sizes */
963 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
964 ECC1RESULTSIZE);
965 writel(val, info->reg.gpmc_ecc_size_config);
966
967 switch (mode) {
968 case NAND_ECC_READ:
969 case NAND_ECC_WRITE:
970 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
971 break;
972 case NAND_ECC_READSYN:
973 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
974 break;
975 default:
976 dev_info(&info->pdev->dev,
977 "error: unrecognized Mode[%d]!\n", mode);
978 break;
979 }
980
981 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
982 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
983 writel(val, info->reg.gpmc_ecc_config);
984 }
985
986 /**
987 * omap_wait - wait until the command is done
988 * @mtd: MTD device structure
989 * @chip: NAND Chip structure
990 *
991 * Wait function is called during Program and erase operations and
992 * the way it is called from MTD layer, we should wait till the NAND
993 * chip is ready after the programming/erase operation has completed.
994 *
995 * Erase can take up to 400ms and program up to 20ms according to
996 * general NAND and SmartMedia specs
997 */
998 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
999 {
1000 struct nand_chip *this = mtd->priv;
1001 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1002 mtd);
1003 unsigned long timeo = jiffies;
1004 int status, state = this->state;
1005
1006 if (state == FL_ERASING)
1007 timeo += msecs_to_jiffies(400);
1008 else
1009 timeo += msecs_to_jiffies(20);
1010
1011 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1012 while (time_before(jiffies, timeo)) {
1013 status = readb(info->reg.gpmc_nand_data);
1014 if (status & NAND_STATUS_READY)
1015 break;
1016 cond_resched();
1017 }
1018
1019 status = readb(info->reg.gpmc_nand_data);
1020 return status;
1021 }
1022
1023 /**
1024 * omap_dev_ready - calls the platform specific dev_ready function
1025 * @mtd: MTD device structure
1026 */
1027 static int omap_dev_ready(struct mtd_info *mtd)
1028 {
1029 unsigned int val = 0;
1030 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1031 mtd);
1032
1033 val = readl(info->reg.gpmc_status);
1034
1035 if ((val & 0x100) == 0x100) {
1036 return 1;
1037 } else {
1038 return 0;
1039 }
1040 }
1041
1042 /**
1043 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1044 * @mtd: MTD device structure
1045 * @mode: Read/Write mode
1046 *
1047 * When using BCH, sector size is hardcoded to 512 bytes.
1048 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1049 * for error correction.
1050 * On writing,
1051 * eccsize0 = 0 (no additional protected byte in spare area)
1052 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1053 */
1054 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1055 {
1056 int nerrors;
1057 unsigned int dev_width, nsectors;
1058 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1059 mtd);
1060 struct nand_chip *chip = mtd->priv;
1061 u32 val, wr_mode;
1062 unsigned int ecc_size1, ecc_size0;
1063
1064 /* Using wrapping mode 6 for writing */
1065 wr_mode = BCH_WRAPMODE_6;
1066
1067 /*
1068 * ECC engine enabled for valid ecc_size0 nibbles
1069 * and disabled for ecc_size1 nibbles.
1070 */
1071 ecc_size0 = BCH_ECC_SIZE0;
1072 ecc_size1 = BCH_ECC_SIZE1;
1073
1074 /* Perform ecc calculation on 512-byte sector */
1075 nsectors = 1;
1076
1077 /* Update number of error correction */
1078 nerrors = info->nand.ecc.strength;
1079
1080 /* Multi sector reading/writing for NAND flash with page size < 4096 */
1081 if (info->is_elm_used && (mtd->writesize <= 4096)) {
1082 if (mode == NAND_ECC_READ) {
1083 /* Using wrapping mode 1 for reading */
1084 wr_mode = BCH_WRAPMODE_1;
1085
1086 /*
1087 * ECC engine enabled for ecc_size0 nibbles
1088 * and disabled for ecc_size1 nibbles.
1089 */
1090 ecc_size0 = (nerrors == 8) ?
1091 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1092 ecc_size1 = (nerrors == 8) ?
1093 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1094 }
1095
1096 /* Perform ecc calculation for one page (< 4096) */
1097 nsectors = info->nand.ecc.steps;
1098 }
1099
1100 writel(ECC1, info->reg.gpmc_ecc_control);
1101
1102 /* Configure ecc size for BCH */
1103 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1104 writel(val, info->reg.gpmc_ecc_size_config);
1105
1106 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1107
1108 /* BCH configuration */
1109 val = ((1 << 16) | /* enable BCH */
1110 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1111 (wr_mode << 8) | /* wrap mode */
1112 (dev_width << 7) | /* bus width */
1113 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1114 (info->gpmc_cs << 1) | /* ECC CS */
1115 (0x1)); /* enable ECC */
1116
1117 writel(val, info->reg.gpmc_ecc_config);
1118
1119 /* Clear ecc and enable bits */
1120 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1121 }
1122
1123 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1124 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1125 0x97, 0x79, 0xe5, 0x24, 0xb5};
1126
1127 /**
1128 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1129 * @mtd: MTD device structure
1130 * @dat: The pointer to data on which ecc is computed
1131 * @ecc_code: The ecc_code buffer
1132 *
1133 * Support calculating of BCH4/8 ecc vectors for the page
1134 */
1135 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1136 const u_char *dat, u_char *ecc_calc)
1137 {
1138 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1139 mtd);
1140 int eccbytes = info->nand.ecc.bytes;
1141 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1142 u8 *ecc_code;
1143 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1144 int i;
1145
1146 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1147 for (i = 0; i < nsectors; i++) {
1148 ecc_code = ecc_calc;
1149 switch (info->ecc_opt) {
1150 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1151 case OMAP_ECC_BCH8_CODE_HW:
1152 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1153 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1154 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1155 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1156 *ecc_code++ = (bch_val4 & 0xFF);
1157 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1158 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1159 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1160 *ecc_code++ = (bch_val3 & 0xFF);
1161 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1162 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1163 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1164 *ecc_code++ = (bch_val2 & 0xFF);
1165 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1166 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1167 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1168 *ecc_code++ = (bch_val1 & 0xFF);
1169 break;
1170 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1171 case OMAP_ECC_BCH4_CODE_HW:
1172 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1173 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1174 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1175 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1176 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1177 ((bch_val1 >> 28) & 0xF);
1178 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1179 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1180 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1181 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1182 break;
1183 default:
1184 return -EINVAL;
1185 }
1186
1187 /* ECC scheme specific syndrome customizations */
1188 switch (info->ecc_opt) {
1189 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1190 /* Add constant polynomial to remainder, so that
1191 * ECC of blank pages results in 0x0 on reading back */
1192 for (i = 0; i < eccbytes; i++)
1193 ecc_calc[i] ^= bch4_polynomial[i];
1194 break;
1195 case OMAP_ECC_BCH4_CODE_HW:
1196 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1197 ecc_calc[eccbytes - 1] = 0x0;
1198 break;
1199 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1200 /* Add constant polynomial to remainder, so that
1201 * ECC of blank pages results in 0x0 on reading back */
1202 for (i = 0; i < eccbytes; i++)
1203 ecc_calc[i] ^= bch8_polynomial[i];
1204 break;
1205 case OMAP_ECC_BCH8_CODE_HW:
1206 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1207 ecc_calc[eccbytes - 1] = 0x0;
1208 break;
1209 default:
1210 return -EINVAL;
1211 }
1212
1213 ecc_calc += eccbytes;
1214 }
1215
1216 return 0;
1217 }
1218
1219 /**
1220 * erased_sector_bitflips - count bit flips
1221 * @data: data sector buffer
1222 * @oob: oob buffer
1223 * @info: omap_nand_info
1224 *
1225 * Check the bit flips in erased page falls below correctable level.
1226 * If falls below, report the page as erased with correctable bit
1227 * flip, else report as uncorrectable page.
1228 */
1229 static int erased_sector_bitflips(u_char *data, u_char *oob,
1230 struct omap_nand_info *info)
1231 {
1232 int flip_bits = 0, i;
1233
1234 for (i = 0; i < info->nand.ecc.size; i++) {
1235 flip_bits += hweight8(~data[i]);
1236 if (flip_bits > info->nand.ecc.strength)
1237 return 0;
1238 }
1239
1240 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1241 flip_bits += hweight8(~oob[i]);
1242 if (flip_bits > info->nand.ecc.strength)
1243 return 0;
1244 }
1245
1246 /*
1247 * Bit flips falls in correctable level.
1248 * Fill data area with 0xFF
1249 */
1250 if (flip_bits) {
1251 memset(data, 0xFF, info->nand.ecc.size);
1252 memset(oob, 0xFF, info->nand.ecc.bytes);
1253 }
1254
1255 return flip_bits;
1256 }
1257
1258 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1259 /**
1260 * omap_elm_correct_data - corrects page data area in case error reported
1261 * @mtd: MTD device structure
1262 * @data: page data
1263 * @read_ecc: ecc read from nand flash
1264 * @calc_ecc: ecc read from HW ECC registers
1265 *
1266 * Calculated ecc vector reported as zero in case of non-error pages.
1267 * In case of non-zero ecc vector, first filter out erased-pages, and
1268 * then process data via ELM to detect bit-flips.
1269 */
1270 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1271 u_char *read_ecc, u_char *calc_ecc)
1272 {
1273 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1274 mtd);
1275 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1276 int eccsteps = info->nand.ecc.steps;
1277 int i , j, stat = 0;
1278 int eccflag, actual_eccbytes;
1279 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1280 u_char *ecc_vec = calc_ecc;
1281 u_char *spare_ecc = read_ecc;
1282 u_char *erased_ecc_vec;
1283 u_char *buf;
1284 int bitflip_count;
1285 bool is_error_reported = false;
1286 u32 bit_pos, byte_pos, error_max, pos;
1287 int err;
1288
1289 switch (info->ecc_opt) {
1290 case OMAP_ECC_BCH4_CODE_HW:
1291 /* omit 7th ECC byte reserved for ROM code compatibility */
1292 actual_eccbytes = ecc->bytes - 1;
1293 erased_ecc_vec = bch4_vector;
1294 break;
1295 case OMAP_ECC_BCH8_CODE_HW:
1296 /* omit 14th ECC byte reserved for ROM code compatibility */
1297 actual_eccbytes = ecc->bytes - 1;
1298 erased_ecc_vec = bch8_vector;
1299 break;
1300 default:
1301 pr_err("invalid driver configuration\n");
1302 return -EINVAL;
1303 }
1304
1305 /* Initialize elm error vector to zero */
1306 memset(err_vec, 0, sizeof(err_vec));
1307
1308 for (i = 0; i < eccsteps ; i++) {
1309 eccflag = 0; /* initialize eccflag */
1310
1311 /*
1312 * Check any error reported,
1313 * In case of error, non zero ecc reported.
1314 */
1315 for (j = 0; j < actual_eccbytes; j++) {
1316 if (calc_ecc[j] != 0) {
1317 eccflag = 1; /* non zero ecc, error present */
1318 break;
1319 }
1320 }
1321
1322 if (eccflag == 1) {
1323 if (memcmp(calc_ecc, erased_ecc_vec,
1324 actual_eccbytes) == 0) {
1325 /*
1326 * calc_ecc[] matches pattern for ECC(all 0xff)
1327 * so this is definitely an erased-page
1328 */
1329 } else {
1330 buf = &data[info->nand.ecc.size * i];
1331 /*
1332 * count number of 0-bits in read_buf.
1333 * This check can be removed once a similar
1334 * check is introduced in generic NAND driver
1335 */
1336 bitflip_count = erased_sector_bitflips(
1337 buf, read_ecc, info);
1338 if (bitflip_count) {
1339 /*
1340 * number of 0-bits within ECC limits
1341 * So this may be an erased-page
1342 */
1343 stat += bitflip_count;
1344 } else {
1345 /*
1346 * Too many 0-bits. It may be a
1347 * - programmed-page, OR
1348 * - erased-page with many bit-flips
1349 * So this page requires check by ELM
1350 */
1351 err_vec[i].error_reported = true;
1352 is_error_reported = true;
1353 }
1354 }
1355 }
1356
1357 /* Update the ecc vector */
1358 calc_ecc += ecc->bytes;
1359 read_ecc += ecc->bytes;
1360 }
1361
1362 /* Check if any error reported */
1363 if (!is_error_reported)
1364 return 0;
1365
1366 /* Decode BCH error using ELM module */
1367 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1368
1369 err = 0;
1370 for (i = 0; i < eccsteps; i++) {
1371 if (err_vec[i].error_uncorrectable) {
1372 pr_err("nand: uncorrectable bit-flips found\n");
1373 err = -EBADMSG;
1374 } else if (err_vec[i].error_reported) {
1375 for (j = 0; j < err_vec[i].error_count; j++) {
1376 switch (info->ecc_opt) {
1377 case OMAP_ECC_BCH4_CODE_HW:
1378 /* Add 4 bits to take care of padding */
1379 pos = err_vec[i].error_loc[j] +
1380 BCH4_BIT_PAD;
1381 break;
1382 case OMAP_ECC_BCH8_CODE_HW:
1383 pos = err_vec[i].error_loc[j];
1384 break;
1385 default:
1386 return -EINVAL;
1387 }
1388 error_max = (ecc->size + actual_eccbytes) * 8;
1389 /* Calculate bit position of error */
1390 bit_pos = pos % 8;
1391
1392 /* Calculate byte position of error */
1393 byte_pos = (error_max - pos - 1) / 8;
1394
1395 if (pos < error_max) {
1396 if (byte_pos < 512) {
1397 pr_debug("bitflip@dat[%d]=%x\n",
1398 byte_pos, data[byte_pos]);
1399 data[byte_pos] ^= 1 << bit_pos;
1400 } else {
1401 pr_debug("bitflip@oob[%d]=%x\n",
1402 (byte_pos - 512),
1403 spare_ecc[byte_pos - 512]);
1404 spare_ecc[byte_pos - 512] ^=
1405 1 << bit_pos;
1406 }
1407 } else {
1408 pr_err("invalid bit-flip @ %d:%d\n",
1409 byte_pos, bit_pos);
1410 err = -EBADMSG;
1411 }
1412 }
1413 }
1414
1415 /* Update number of correctable errors */
1416 stat += err_vec[i].error_count;
1417
1418 /* Update page data with sector size */
1419 data += ecc->size;
1420 spare_ecc += ecc->bytes;
1421 }
1422
1423 return (err) ? err : stat;
1424 }
1425
1426 /**
1427 * omap_write_page_bch - BCH ecc based write page function for entire page
1428 * @mtd: mtd info structure
1429 * @chip: nand chip info structure
1430 * @buf: data buffer
1431 * @oob_required: must write chip->oob_poi to OOB
1432 *
1433 * Custom write page method evolved to support multi sector writing in one shot
1434 */
1435 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1436 const uint8_t *buf, int oob_required)
1437 {
1438 int i;
1439 uint8_t *ecc_calc = chip->buffers->ecccalc;
1440 uint32_t *eccpos = chip->ecc.layout->eccpos;
1441
1442 /* Enable GPMC ecc engine */
1443 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1444
1445 /* Write data */
1446 chip->write_buf(mtd, buf, mtd->writesize);
1447
1448 /* Update ecc vector from GPMC result registers */
1449 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1450
1451 for (i = 0; i < chip->ecc.total; i++)
1452 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1453
1454 /* Write ecc vector to OOB area */
1455 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1456 return 0;
1457 }
1458
1459 /**
1460 * omap_read_page_bch - BCH ecc based page read function for entire page
1461 * @mtd: mtd info structure
1462 * @chip: nand chip info structure
1463 * @buf: buffer to store read data
1464 * @oob_required: caller requires OOB data read to chip->oob_poi
1465 * @page: page number to read
1466 *
1467 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1468 * used for error correction.
1469 * Custom method evolved to support ELM error correction & multi sector
1470 * reading. On reading page data area is read along with OOB data with
1471 * ecc engine enabled. ecc vector updated after read of OOB data.
1472 * For non error pages ecc vector reported as zero.
1473 */
1474 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1475 uint8_t *buf, int oob_required, int page)
1476 {
1477 uint8_t *ecc_calc = chip->buffers->ecccalc;
1478 uint8_t *ecc_code = chip->buffers->ecccode;
1479 uint32_t *eccpos = chip->ecc.layout->eccpos;
1480 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1481 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1482 int stat;
1483 unsigned int max_bitflips = 0;
1484
1485 /* Enable GPMC ecc engine */
1486 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1487
1488 /* Read data */
1489 chip->read_buf(mtd, buf, mtd->writesize);
1490
1491 /* Read oob bytes */
1492 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1493 chip->read_buf(mtd, oob, chip->ecc.total);
1494
1495 /* Calculate ecc bytes */
1496 chip->ecc.calculate(mtd, buf, ecc_calc);
1497
1498 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1499
1500 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1501
1502 if (stat < 0) {
1503 mtd->ecc_stats.failed++;
1504 } else {
1505 mtd->ecc_stats.corrected += stat;
1506 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1507 }
1508
1509 return max_bitflips;
1510 }
1511
1512 /**
1513 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1514 * @omap_nand_info: NAND device structure containing platform data
1515 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1516 */
1517 static int is_elm_present(struct omap_nand_info *info,
1518 struct device_node *elm_node, enum bch_ecc bch_type)
1519 {
1520 struct platform_device *pdev;
1521 info->is_elm_used = false;
1522 /* check whether elm-id is passed via DT */
1523 if (!elm_node) {
1524 pr_err("nand: error: ELM DT node not found\n");
1525 return -ENODEV;
1526 }
1527 pdev = of_find_device_by_node(elm_node);
1528 /* check whether ELM device is registered */
1529 if (!pdev) {
1530 pr_err("nand: error: ELM device not found\n");
1531 return -ENODEV;
1532 }
1533 /* ELM module available, now configure it */
1534 info->elm_dev = &pdev->dev;
1535 if (elm_config(info->elm_dev, bch_type))
1536 return -ENODEV;
1537 info->is_elm_used = true;
1538 return 0;
1539 }
1540 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1541
1542 static int omap_nand_probe(struct platform_device *pdev)
1543 {
1544 struct omap_nand_info *info;
1545 struct omap_nand_platform_data *pdata;
1546 struct mtd_info *mtd;
1547 struct nand_chip *nand_chip;
1548 struct nand_ecclayout *ecclayout;
1549 int err;
1550 int i;
1551 dma_cap_mask_t mask;
1552 unsigned sig;
1553 unsigned oob_index;
1554 struct resource *res;
1555 struct mtd_part_parser_data ppdata = {};
1556
1557 pdata = dev_get_platdata(&pdev->dev);
1558 if (pdata == NULL) {
1559 dev_err(&pdev->dev, "platform data missing\n");
1560 return -ENODEV;
1561 }
1562
1563 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1564 GFP_KERNEL);
1565 if (!info)
1566 return -ENOMEM;
1567
1568 platform_set_drvdata(pdev, info);
1569
1570 spin_lock_init(&info->controller.lock);
1571 init_waitqueue_head(&info->controller.wq);
1572
1573 info->pdev = pdev;
1574 info->gpmc_cs = pdata->cs;
1575 info->reg = pdata->reg;
1576 info->of_node = pdata->of_node;
1577 info->ecc_opt = pdata->ecc_opt;
1578 mtd = &info->mtd;
1579 mtd->priv = &info->nand;
1580 mtd->name = dev_name(&pdev->dev);
1581 mtd->owner = THIS_MODULE;
1582 nand_chip = &info->nand;
1583 nand_chip->ecc.priv = NULL;
1584 nand_chip->options |= NAND_SKIP_BBTSCAN;
1585
1586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1587 if (res == NULL) {
1588 err = -EINVAL;
1589 dev_err(&pdev->dev, "error getting memory resource\n");
1590 goto return_error;
1591 }
1592
1593 info->phys_base = res->start;
1594 info->mem_size = resource_size(res);
1595
1596 if (!devm_request_mem_region(&pdev->dev, info->phys_base,
1597 info->mem_size, pdev->dev.driver->name)) {
1598 err = -EBUSY;
1599 goto return_error;
1600 }
1601
1602 nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base,
1603 info->mem_size);
1604 if (!nand_chip->IO_ADDR_R) {
1605 err = -ENOMEM;
1606 goto return_error;
1607 }
1608
1609 nand_chip->controller = &info->controller;
1610
1611 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1612 nand_chip->cmd_ctrl = omap_hwcontrol;
1613
1614 /*
1615 * If RDY/BSY line is connected to OMAP then use the omap ready
1616 * function and the generic nand_wait function which reads the status
1617 * register after monitoring the RDY/BSY line. Otherwise use a standard
1618 * chip delay which is slightly more than tR (AC Timing) of the NAND
1619 * device and read status register until you get a failure or success
1620 */
1621 if (pdata->dev_ready) {
1622 nand_chip->dev_ready = omap_dev_ready;
1623 nand_chip->chip_delay = 0;
1624 } else {
1625 nand_chip->waitfunc = omap_wait;
1626 nand_chip->chip_delay = 50;
1627 }
1628
1629 /* scan NAND device connected to chip controller */
1630 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1631 if (nand_scan_ident(mtd, 1, NULL)) {
1632 pr_err("nand device scan failed, may be bus-width mismatch\n");
1633 err = -ENXIO;
1634 goto return_error;
1635 }
1636
1637 /* check for small page devices */
1638 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1639 pr_err("small page devices are not supported\n");
1640 err = -EINVAL;
1641 goto return_error;
1642 }
1643
1644 /* re-populate low-level callbacks based on xfer modes */
1645 switch (pdata->xfer_type) {
1646 case NAND_OMAP_PREFETCH_POLLED:
1647 nand_chip->read_buf = omap_read_buf_pref;
1648 nand_chip->write_buf = omap_write_buf_pref;
1649 break;
1650
1651 case NAND_OMAP_POLLED:
1652 /* Use nand_base defaults for {read,write}_buf */
1653 break;
1654
1655 case NAND_OMAP_PREFETCH_DMA:
1656 dma_cap_zero(mask);
1657 dma_cap_set(DMA_SLAVE, mask);
1658 sig = OMAP24XX_DMA_GPMC;
1659 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1660 if (!info->dma) {
1661 dev_err(&pdev->dev, "DMA engine request failed\n");
1662 err = -ENXIO;
1663 goto return_error;
1664 } else {
1665 struct dma_slave_config cfg;
1666
1667 memset(&cfg, 0, sizeof(cfg));
1668 cfg.src_addr = info->phys_base;
1669 cfg.dst_addr = info->phys_base;
1670 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1671 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1672 cfg.src_maxburst = 16;
1673 cfg.dst_maxburst = 16;
1674 err = dmaengine_slave_config(info->dma, &cfg);
1675 if (err) {
1676 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1677 err);
1678 goto return_error;
1679 }
1680 nand_chip->read_buf = omap_read_buf_dma_pref;
1681 nand_chip->write_buf = omap_write_buf_dma_pref;
1682 }
1683 break;
1684
1685 case NAND_OMAP_PREFETCH_IRQ:
1686 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1687 if (info->gpmc_irq_fifo <= 0) {
1688 dev_err(&pdev->dev, "error getting fifo irq\n");
1689 err = -ENODEV;
1690 goto return_error;
1691 }
1692 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1693 omap_nand_irq, IRQF_SHARED,
1694 "gpmc-nand-fifo", info);
1695 if (err) {
1696 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1697 info->gpmc_irq_fifo, err);
1698 info->gpmc_irq_fifo = 0;
1699 goto return_error;
1700 }
1701
1702 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1703 if (info->gpmc_irq_count <= 0) {
1704 dev_err(&pdev->dev, "error getting count irq\n");
1705 err = -ENODEV;
1706 goto return_error;
1707 }
1708 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1709 omap_nand_irq, IRQF_SHARED,
1710 "gpmc-nand-count", info);
1711 if (err) {
1712 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1713 info->gpmc_irq_count, err);
1714 info->gpmc_irq_count = 0;
1715 goto return_error;
1716 }
1717
1718 nand_chip->read_buf = omap_read_buf_irq_pref;
1719 nand_chip->write_buf = omap_write_buf_irq_pref;
1720
1721 break;
1722
1723 default:
1724 dev_err(&pdev->dev,
1725 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1726 err = -EINVAL;
1727 goto return_error;
1728 }
1729
1730 /* populate MTD interface based on ECC scheme */
1731 nand_chip->ecc.layout = &omap_oobinfo;
1732 ecclayout = &omap_oobinfo;
1733 switch (info->ecc_opt) {
1734 case OMAP_ECC_HAM1_CODE_HW:
1735 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1736 nand_chip->ecc.mode = NAND_ECC_HW;
1737 nand_chip->ecc.bytes = 3;
1738 nand_chip->ecc.size = 512;
1739 nand_chip->ecc.strength = 1;
1740 nand_chip->ecc.calculate = omap_calculate_ecc;
1741 nand_chip->ecc.hwctl = omap_enable_hwecc;
1742 nand_chip->ecc.correct = omap_correct_data;
1743 /* define ECC layout */
1744 ecclayout->eccbytes = nand_chip->ecc.bytes *
1745 (mtd->writesize /
1746 nand_chip->ecc.size);
1747 if (nand_chip->options & NAND_BUSWIDTH_16)
1748 oob_index = BADBLOCK_MARKER_LENGTH;
1749 else
1750 oob_index = 1;
1751 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1752 ecclayout->eccpos[i] = oob_index;
1753 /* no reserved-marker in ecclayout for this ecc-scheme */
1754 ecclayout->oobfree->offset =
1755 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1756 break;
1757
1758 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1759 #ifdef CONFIG_MTD_NAND_ECC_BCH
1760 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1761 nand_chip->ecc.mode = NAND_ECC_HW;
1762 nand_chip->ecc.size = 512;
1763 nand_chip->ecc.bytes = 7;
1764 nand_chip->ecc.strength = 4;
1765 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1766 nand_chip->ecc.correct = nand_bch_correct_data;
1767 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1768 /* define ECC layout */
1769 ecclayout->eccbytes = nand_chip->ecc.bytes *
1770 (mtd->writesize /
1771 nand_chip->ecc.size);
1772 oob_index = BADBLOCK_MARKER_LENGTH;
1773 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1774 ecclayout->eccpos[i] = oob_index;
1775 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1776 oob_index++;
1777 }
1778 /* include reserved-marker in ecclayout->oobfree calculation */
1779 ecclayout->oobfree->offset = 1 +
1780 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1781 /* software bch library is used for locating errors */
1782 nand_chip->ecc.priv = nand_bch_init(mtd,
1783 nand_chip->ecc.size,
1784 nand_chip->ecc.bytes,
1785 &nand_chip->ecc.layout);
1786 if (!nand_chip->ecc.priv) {
1787 pr_err("nand: error: unable to use s/w BCH library\n");
1788 err = -EINVAL;
1789 }
1790 break;
1791 #else
1792 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1793 err = -EINVAL;
1794 goto return_error;
1795 #endif
1796
1797 case OMAP_ECC_BCH4_CODE_HW:
1798 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1799 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1800 nand_chip->ecc.mode = NAND_ECC_HW;
1801 nand_chip->ecc.size = 512;
1802 /* 14th bit is kept reserved for ROM-code compatibility */
1803 nand_chip->ecc.bytes = 7 + 1;
1804 nand_chip->ecc.strength = 4;
1805 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1806 nand_chip->ecc.correct = omap_elm_correct_data;
1807 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1808 nand_chip->ecc.read_page = omap_read_page_bch;
1809 nand_chip->ecc.write_page = omap_write_page_bch;
1810 /* define ECC layout */
1811 ecclayout->eccbytes = nand_chip->ecc.bytes *
1812 (mtd->writesize /
1813 nand_chip->ecc.size);
1814 oob_index = BADBLOCK_MARKER_LENGTH;
1815 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1816 ecclayout->eccpos[i] = oob_index;
1817 /* reserved marker already included in ecclayout->eccbytes */
1818 ecclayout->oobfree->offset =
1819 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1820 /* This ECC scheme requires ELM H/W block */
1821 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1822 pr_err("nand: error: could not initialize ELM\n");
1823 err = -ENODEV;
1824 goto return_error;
1825 }
1826 break;
1827 #else
1828 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1829 err = -EINVAL;
1830 goto return_error;
1831 #endif
1832
1833 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1834 #ifdef CONFIG_MTD_NAND_ECC_BCH
1835 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1836 nand_chip->ecc.mode = NAND_ECC_HW;
1837 nand_chip->ecc.size = 512;
1838 nand_chip->ecc.bytes = 13;
1839 nand_chip->ecc.strength = 8;
1840 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1841 nand_chip->ecc.correct = nand_bch_correct_data;
1842 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1843 /* define ECC layout */
1844 ecclayout->eccbytes = nand_chip->ecc.bytes *
1845 (mtd->writesize /
1846 nand_chip->ecc.size);
1847 oob_index = BADBLOCK_MARKER_LENGTH;
1848 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1849 ecclayout->eccpos[i] = oob_index;
1850 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1851 oob_index++;
1852 }
1853 /* include reserved-marker in ecclayout->oobfree calculation */
1854 ecclayout->oobfree->offset = 1 +
1855 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1856 /* software bch library is used for locating errors */
1857 nand_chip->ecc.priv = nand_bch_init(mtd,
1858 nand_chip->ecc.size,
1859 nand_chip->ecc.bytes,
1860 &nand_chip->ecc.layout);
1861 if (!nand_chip->ecc.priv) {
1862 pr_err("nand: error: unable to use s/w BCH library\n");
1863 err = -EINVAL;
1864 goto return_error;
1865 }
1866 break;
1867 #else
1868 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1869 err = -EINVAL;
1870 goto return_error;
1871 #endif
1872
1873 case OMAP_ECC_BCH8_CODE_HW:
1874 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1875 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1876 nand_chip->ecc.mode = NAND_ECC_HW;
1877 nand_chip->ecc.size = 512;
1878 /* 14th bit is kept reserved for ROM-code compatibility */
1879 nand_chip->ecc.bytes = 13 + 1;
1880 nand_chip->ecc.strength = 8;
1881 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1882 nand_chip->ecc.correct = omap_elm_correct_data;
1883 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1884 nand_chip->ecc.read_page = omap_read_page_bch;
1885 nand_chip->ecc.write_page = omap_write_page_bch;
1886 /* This ECC scheme requires ELM H/W block */
1887 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1888 if (err < 0) {
1889 pr_err("nand: error: could not initialize ELM\n");
1890 goto return_error;
1891 }
1892 /* define ECC layout */
1893 ecclayout->eccbytes = nand_chip->ecc.bytes *
1894 (mtd->writesize /
1895 nand_chip->ecc.size);
1896 oob_index = BADBLOCK_MARKER_LENGTH;
1897 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1898 ecclayout->eccpos[i] = oob_index;
1899 /* reserved marker already included in ecclayout->eccbytes */
1900 ecclayout->oobfree->offset =
1901 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1902 break;
1903 #else
1904 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1905 err = -EINVAL;
1906 goto return_error;
1907 #endif
1908
1909 default:
1910 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1911 err = -EINVAL;
1912 goto return_error;
1913 }
1914
1915 /* all OOB bytes from oobfree->offset till end off OOB are free */
1916 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1917 /* check if NAND device's OOB is enough to store ECC signatures */
1918 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1919 pr_err("not enough OOB bytes required = %d, available=%d\n",
1920 ecclayout->eccbytes, mtd->oobsize);
1921 err = -EINVAL;
1922 goto return_error;
1923 }
1924
1925 /* second phase scan */
1926 if (nand_scan_tail(mtd)) {
1927 err = -ENXIO;
1928 goto return_error;
1929 }
1930
1931 ppdata.of_node = pdata->of_node;
1932 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
1933 pdata->nr_parts);
1934
1935 platform_set_drvdata(pdev, mtd);
1936
1937 return 0;
1938
1939 return_error:
1940 if (info->dma)
1941 dma_release_channel(info->dma);
1942 if (nand_chip->ecc.priv) {
1943 nand_bch_free(nand_chip->ecc.priv);
1944 nand_chip->ecc.priv = NULL;
1945 }
1946 return err;
1947 }
1948
1949 static int omap_nand_remove(struct platform_device *pdev)
1950 {
1951 struct mtd_info *mtd = platform_get_drvdata(pdev);
1952 struct nand_chip *nand_chip = mtd->priv;
1953 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1954 mtd);
1955 if (nand_chip->ecc.priv) {
1956 nand_bch_free(nand_chip->ecc.priv);
1957 nand_chip->ecc.priv = NULL;
1958 }
1959 if (info->dma)
1960 dma_release_channel(info->dma);
1961 nand_release(mtd);
1962 return 0;
1963 }
1964
1965 static struct platform_driver omap_nand_driver = {
1966 .probe = omap_nand_probe,
1967 .remove = omap_nand_remove,
1968 .driver = {
1969 .name = DRIVER_NAME,
1970 .owner = THIS_MODULE,
1971 },
1972 };
1973
1974 module_platform_driver(omap_nand_driver);
1975
1976 MODULE_ALIAS("platform:" DRIVER_NAME);
1977 MODULE_LICENSE("GPL");
1978 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux kernel - Deliverables
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