2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
14 #include <linux/jiffies.h>
15 #include <linux/sched.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
20 #include <linux/slab.h>
23 #include <plat/gpmc.h>
24 #include <plat/nand.h>
26 #define DRIVER_NAME "omap2-nand"
28 #define NAND_Ecc_P1e (1 << 0)
29 #define NAND_Ecc_P2e (1 << 1)
30 #define NAND_Ecc_P4e (1 << 2)
31 #define NAND_Ecc_P8e (1 << 3)
32 #define NAND_Ecc_P16e (1 << 4)
33 #define NAND_Ecc_P32e (1 << 5)
34 #define NAND_Ecc_P64e (1 << 6)
35 #define NAND_Ecc_P128e (1 << 7)
36 #define NAND_Ecc_P256e (1 << 8)
37 #define NAND_Ecc_P512e (1 << 9)
38 #define NAND_Ecc_P1024e (1 << 10)
39 #define NAND_Ecc_P2048e (1 << 11)
41 #define NAND_Ecc_P1o (1 << 16)
42 #define NAND_Ecc_P2o (1 << 17)
43 #define NAND_Ecc_P4o (1 << 18)
44 #define NAND_Ecc_P8o (1 << 19)
45 #define NAND_Ecc_P16o (1 << 20)
46 #define NAND_Ecc_P32o (1 << 21)
47 #define NAND_Ecc_P64o (1 << 22)
48 #define NAND_Ecc_P128o (1 << 23)
49 #define NAND_Ecc_P256o (1 << 24)
50 #define NAND_Ecc_P512o (1 << 25)
51 #define NAND_Ecc_P1024o (1 << 26)
52 #define NAND_Ecc_P2048o (1 << 27)
54 #define TF(value) (value ? 1 : 0)
56 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
57 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
58 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
59 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
60 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
61 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
62 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
63 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
65 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
66 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
67 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
68 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
69 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
70 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
71 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
72 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
74 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
75 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
76 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
77 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
78 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
79 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
80 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
81 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
83 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
84 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
85 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
86 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
87 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
88 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
89 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
90 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
92 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
93 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
95 #ifdef CONFIG_MTD_PARTITIONS
96 static const char *part_probes
[] = { "cmdlinepart", NULL
};
99 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
100 static int use_prefetch
= 1;
102 /* "modprobe ... use_prefetch=0" etc */
103 module_param(use_prefetch
, bool, 0);
104 MODULE_PARM_DESC(use_prefetch
, "enable/disable use of PREFETCH");
106 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
107 static int use_dma
= 1;
109 /* "modprobe ... use_dma=0" etc */
110 module_param(use_dma
, bool, 0);
111 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
113 static const int use_dma
;
116 const int use_prefetch
;
117 static const int use_dma
;
120 struct omap_nand_info
{
121 struct nand_hw_control controller
;
122 struct omap_nand_platform_data
*pdata
;
124 struct mtd_partition
*parts
;
125 struct nand_chip nand
;
126 struct platform_device
*pdev
;
129 unsigned long phys_base
;
130 struct completion comp
;
135 * omap_hwcontrol - hardware specific access to control-lines
136 * @mtd: MTD device structure
137 * @cmd: command to device
139 * NAND_NCE: bit 0 -> don't care
140 * NAND_CLE: bit 1 -> Command Latch
141 * NAND_ALE: bit 2 -> Address Latch
143 * NOTE: boards may use different bits for these!!
145 static void omap_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
147 struct omap_nand_info
*info
= container_of(mtd
,
148 struct omap_nand_info
, mtd
);
150 if (cmd
!= NAND_CMD_NONE
) {
152 gpmc_nand_write(info
->gpmc_cs
, GPMC_NAND_COMMAND
, cmd
);
154 else if (ctrl
& NAND_ALE
)
155 gpmc_nand_write(info
->gpmc_cs
, GPMC_NAND_ADDRESS
, cmd
);
158 gpmc_nand_write(info
->gpmc_cs
, GPMC_NAND_DATA
, cmd
);
163 * omap_read_buf8 - read data from NAND controller into buffer
164 * @mtd: MTD device structure
165 * @buf: buffer to store date
166 * @len: number of bytes to read
168 static void omap_read_buf8(struct mtd_info
*mtd
, u_char
*buf
, int len
)
170 struct nand_chip
*nand
= mtd
->priv
;
172 ioread8_rep(nand
->IO_ADDR_R
, buf
, len
);
176 * omap_write_buf8 - write buffer to NAND controller
177 * @mtd: MTD device structure
179 * @len: number of bytes to write
181 static void omap_write_buf8(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
183 struct omap_nand_info
*info
= container_of(mtd
,
184 struct omap_nand_info
, mtd
);
185 u_char
*p
= (u_char
*)buf
;
189 iowrite8(*p
++, info
->nand
.IO_ADDR_W
);
190 /* wait until buffer is available for write */
192 status
= gpmc_read_status(GPMC_STATUS_BUFFER
);
198 * omap_read_buf16 - read data from NAND controller into buffer
199 * @mtd: MTD device structure
200 * @buf: buffer to store date
201 * @len: number of bytes to read
203 static void omap_read_buf16(struct mtd_info
*mtd
, u_char
*buf
, int len
)
205 struct nand_chip
*nand
= mtd
->priv
;
207 ioread16_rep(nand
->IO_ADDR_R
, buf
, len
/ 2);
211 * omap_write_buf16 - write buffer to NAND controller
212 * @mtd: MTD device structure
214 * @len: number of bytes to write
216 static void omap_write_buf16(struct mtd_info
*mtd
, const u_char
* buf
, int len
)
218 struct omap_nand_info
*info
= container_of(mtd
,
219 struct omap_nand_info
, mtd
);
220 u16
*p
= (u16
*) buf
;
222 /* FIXME try bursts of writesw() or DMA ... */
226 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
227 /* wait until buffer is available for write */
229 status
= gpmc_read_status(GPMC_STATUS_BUFFER
);
235 * omap_read_buf_pref - read data from NAND controller into buffer
236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
240 static void omap_read_buf_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
242 struct omap_nand_info
*info
= container_of(mtd
,
243 struct omap_nand_info
, mtd
);
244 uint32_t r_count
= 0;
248 /* take care of subpage reads */
250 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
251 omap_read_buf16(mtd
, buf
, len
% 4);
253 omap_read_buf8(mtd
, buf
, len
% 4);
254 p
= (u32
*) (buf
+ len
% 4);
258 /* configure and start prefetch transfer */
259 ret
= gpmc_prefetch_enable(info
->gpmc_cs
, 0x0, len
, 0x0);
261 /* PFPW engine is busy, use cpu copy method */
262 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
263 omap_read_buf16(mtd
, buf
, len
);
265 omap_read_buf8(mtd
, buf
, len
);
269 r_count
= gpmc_read_status(GPMC_PREFETCH_FIFO_CNT
);
270 r_count
= r_count
>> 2;
271 ioread32_rep(info
->nand
.IO_ADDR_R
, p
, r_count
);
275 /* disable and stop the PFPW engine */
276 gpmc_prefetch_reset(info
->gpmc_cs
);
281 * omap_write_buf_pref - write buffer to NAND controller
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 static void omap_write_buf_pref(struct mtd_info
*mtd
,
287 const u_char
*buf
, int len
)
289 struct omap_nand_info
*info
= container_of(mtd
,
290 struct omap_nand_info
, mtd
);
291 uint32_t pref_count
= 0, w_count
= 0;
295 /* take care of subpage writes */
297 writeb(*buf
, info
->nand
.IO_ADDR_W
);
298 p
= (u16
*)(buf
+ 1);
302 /* configure and start prefetch transfer */
303 ret
= gpmc_prefetch_enable(info
->gpmc_cs
, 0x0, len
, 0x1);
305 /* PFPW engine is busy, use cpu copy method */
306 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
307 omap_write_buf16(mtd
, buf
, len
);
309 omap_write_buf8(mtd
, buf
, len
);
313 w_count
= gpmc_read_status(GPMC_PREFETCH_FIFO_CNT
);
314 w_count
= w_count
>> 1;
315 for (i
= 0; (i
< w_count
) && len
; i
++, len
-= 2)
316 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
318 /* wait for data to flushed-out before reset the prefetch */
320 pref_count
= gpmc_read_status(GPMC_PREFETCH_COUNT
);
321 } while (pref_count
);
322 /* disable and stop the PFPW engine */
323 gpmc_prefetch_reset(info
->gpmc_cs
);
327 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
329 * omap_nand_dma_cb: callback on the completion of dma transfer
330 * @lch: logical channel
331 * @ch_satuts: channel status
332 * @data: pointer to completion data structure
334 static void omap_nand_dma_cb(int lch
, u16 ch_status
, void *data
)
336 complete((struct completion
*) data
);
340 * omap_nand_dma_transfer: configer and start dma transfer
341 * @mtd: MTD device structure
342 * @addr: virtual address in RAM of source/destination
343 * @len: number of data bytes to be transferred
344 * @is_write: flag for read/write operation
346 static inline int omap_nand_dma_transfer(struct mtd_info
*mtd
, void *addr
,
347 unsigned int len
, int is_write
)
349 struct omap_nand_info
*info
= container_of(mtd
,
350 struct omap_nand_info
, mtd
);
351 uint32_t prefetch_status
= 0;
352 enum dma_data_direction dir
= is_write
? DMA_TO_DEVICE
:
357 /* The fifo depth is 64 bytes. We have a sync at each frame and frame
358 * length is 64 bytes.
360 int buf_len
= len
>> 6;
362 if (addr
>= high_memory
) {
365 if (((size_t)addr
& PAGE_MASK
) !=
366 ((size_t)(addr
+ len
- 1) & PAGE_MASK
))
368 p1
= vmalloc_to_page(addr
);
371 addr
= page_address(p1
) + ((size_t)addr
& ~PAGE_MASK
);
374 dma_addr
= dma_map_single(&info
->pdev
->dev
, addr
, len
, dir
);
375 if (dma_mapping_error(&info
->pdev
->dev
, dma_addr
)) {
376 dev_err(&info
->pdev
->dev
,
377 "Couldn't DMA map a %d byte buffer\n", len
);
382 omap_set_dma_dest_params(info
->dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
383 info
->phys_base
, 0, 0);
384 omap_set_dma_src_params(info
->dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
386 omap_set_dma_transfer_params(info
->dma_ch
, OMAP_DMA_DATA_TYPE_S32
,
387 0x10, buf_len
, OMAP_DMA_SYNC_FRAME
,
388 OMAP24XX_DMA_GPMC
, OMAP_DMA_DST_SYNC
);
390 omap_set_dma_src_params(info
->dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
391 info
->phys_base
, 0, 0);
392 omap_set_dma_dest_params(info
->dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
394 omap_set_dma_transfer_params(info
->dma_ch
, OMAP_DMA_DATA_TYPE_S32
,
395 0x10, buf_len
, OMAP_DMA_SYNC_FRAME
,
396 OMAP24XX_DMA_GPMC
, OMAP_DMA_SRC_SYNC
);
398 /* configure and start prefetch transfer */
399 ret
= gpmc_prefetch_enable(info
->gpmc_cs
, 0x1, len
, is_write
);
401 /* PFPW engine is busy, use cpu copy methode */
404 init_completion(&info
->comp
);
406 omap_start_dma(info
->dma_ch
);
408 /* setup and start DMA using dma_addr */
409 wait_for_completion(&info
->comp
);
412 prefetch_status
= gpmc_read_status(GPMC_PREFETCH_COUNT
);
413 } while (prefetch_status
);
414 /* disable and stop the PFPW engine */
415 gpmc_prefetch_reset(info
->gpmc_cs
);
417 dma_unmap_single(&info
->pdev
->dev
, dma_addr
, len
, dir
);
421 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
422 is_write
== 0 ? omap_read_buf16(mtd
, (u_char
*) addr
, len
)
423 : omap_write_buf16(mtd
, (u_char
*) addr
, len
);
425 is_write
== 0 ? omap_read_buf8(mtd
, (u_char
*) addr
, len
)
426 : omap_write_buf8(mtd
, (u_char
*) addr
, len
);
430 static void omap_nand_dma_cb(int lch
, u16 ch_status
, void *data
) {}
431 static inline int omap_nand_dma_transfer(struct mtd_info
*mtd
, void *addr
,
432 unsigned int len
, int is_write
)
439 * omap_read_buf_dma_pref - read data from NAND controller into buffer
440 * @mtd: MTD device structure
441 * @buf: buffer to store date
442 * @len: number of bytes to read
444 static void omap_read_buf_dma_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
446 if (len
<= mtd
->oobsize
)
447 omap_read_buf_pref(mtd
, buf
, len
);
449 /* start transfer in DMA mode */
450 omap_nand_dma_transfer(mtd
, buf
, len
, 0x0);
454 * omap_write_buf_dma_pref - write buffer to NAND controller
455 * @mtd: MTD device structure
457 * @len: number of bytes to write
459 static void omap_write_buf_dma_pref(struct mtd_info
*mtd
,
460 const u_char
*buf
, int len
)
462 if (len
<= mtd
->oobsize
)
463 omap_write_buf_pref(mtd
, buf
, len
);
465 /* start transfer in DMA mode */
466 omap_nand_dma_transfer(mtd
, (u_char
*) buf
, len
, 0x1);
470 * omap_verify_buf - Verify chip data against buffer
471 * @mtd: MTD device structure
472 * @buf: buffer containing the data to compare
473 * @len: number of bytes to compare
475 static int omap_verify_buf(struct mtd_info
*mtd
, const u_char
* buf
, int len
)
477 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
479 u16
*p
= (u16
*) buf
;
483 if (*p
++ != cpu_to_le16(readw(info
->nand
.IO_ADDR_R
)))
490 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
493 * gen_true_ecc - This function will generate true ECC value
494 * @ecc_buf: buffer to store ecc code
496 * This generated true ECC value can be used when correcting
497 * data read from NAND flash memory core
499 static void gen_true_ecc(u8
*ecc_buf
)
501 u32 tmp
= ecc_buf
[0] | (ecc_buf
[1] << 16) |
502 ((ecc_buf
[2] & 0xF0) << 20) | ((ecc_buf
[2] & 0x0F) << 8);
504 ecc_buf
[0] = ~(P64o(tmp
) | P64e(tmp
) | P32o(tmp
) | P32e(tmp
) |
505 P16o(tmp
) | P16e(tmp
) | P8o(tmp
) | P8e(tmp
));
506 ecc_buf
[1] = ~(P1024o(tmp
) | P1024e(tmp
) | P512o(tmp
) | P512e(tmp
) |
507 P256o(tmp
) | P256e(tmp
) | P128o(tmp
) | P128e(tmp
));
508 ecc_buf
[2] = ~(P4o(tmp
) | P4e(tmp
) | P2o(tmp
) | P2e(tmp
) | P1o(tmp
) |
509 P1e(tmp
) | P2048o(tmp
) | P2048e(tmp
));
513 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
514 * @ecc_data1: ecc code from nand spare area
515 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
516 * @page_data: page data
518 * This function compares two ECC's and indicates if there is an error.
519 * If the error can be corrected it will be corrected to the buffer.
521 static int omap_compare_ecc(u8
*ecc_data1
, /* read from NAND memory */
522 u8
*ecc_data2
, /* read from register */
526 u8 tmp0_bit
[8], tmp1_bit
[8], tmp2_bit
[8];
527 u8 comp0_bit
[8], comp1_bit
[8], comp2_bit
[8];
534 isEccFF
= ((*(u32
*)ecc_data1
& 0xFFFFFF) == 0xFFFFFF);
536 gen_true_ecc(ecc_data1
);
537 gen_true_ecc(ecc_data2
);
539 for (i
= 0; i
<= 2; i
++) {
540 *(ecc_data1
+ i
) = ~(*(ecc_data1
+ i
));
541 *(ecc_data2
+ i
) = ~(*(ecc_data2
+ i
));
544 for (i
= 0; i
< 8; i
++) {
545 tmp0_bit
[i
] = *ecc_data1
% 2;
546 *ecc_data1
= *ecc_data1
/ 2;
549 for (i
= 0; i
< 8; i
++) {
550 tmp1_bit
[i
] = *(ecc_data1
+ 1) % 2;
551 *(ecc_data1
+ 1) = *(ecc_data1
+ 1) / 2;
554 for (i
= 0; i
< 8; i
++) {
555 tmp2_bit
[i
] = *(ecc_data1
+ 2) % 2;
556 *(ecc_data1
+ 2) = *(ecc_data1
+ 2) / 2;
559 for (i
= 0; i
< 8; i
++) {
560 comp0_bit
[i
] = *ecc_data2
% 2;
561 *ecc_data2
= *ecc_data2
/ 2;
564 for (i
= 0; i
< 8; i
++) {
565 comp1_bit
[i
] = *(ecc_data2
+ 1) % 2;
566 *(ecc_data2
+ 1) = *(ecc_data2
+ 1) / 2;
569 for (i
= 0; i
< 8; i
++) {
570 comp2_bit
[i
] = *(ecc_data2
+ 2) % 2;
571 *(ecc_data2
+ 2) = *(ecc_data2
+ 2) / 2;
574 for (i
= 0; i
< 6; i
++)
575 ecc_bit
[i
] = tmp2_bit
[i
+ 2] ^ comp2_bit
[i
+ 2];
577 for (i
= 0; i
< 8; i
++)
578 ecc_bit
[i
+ 6] = tmp0_bit
[i
] ^ comp0_bit
[i
];
580 for (i
= 0; i
< 8; i
++)
581 ecc_bit
[i
+ 14] = tmp1_bit
[i
] ^ comp1_bit
[i
];
583 ecc_bit
[22] = tmp2_bit
[0] ^ comp2_bit
[0];
584 ecc_bit
[23] = tmp2_bit
[1] ^ comp2_bit
[1];
586 for (i
= 0; i
< 24; i
++)
587 ecc_sum
+= ecc_bit
[i
];
591 /* Not reached because this function is not called if
592 * ECC values are equal
597 /* Uncorrectable error */
598 DEBUG(MTD_DEBUG_LEVEL0
, "ECC UNCORRECTED_ERROR 1\n");
602 /* UN-Correctable error */
603 DEBUG(MTD_DEBUG_LEVEL0
, "ECC UNCORRECTED_ERROR B\n");
607 /* Correctable error */
608 find_byte
= (ecc_bit
[23] << 8) +
618 find_bit
= (ecc_bit
[5] << 2) + (ecc_bit
[3] << 1) + ecc_bit
[1];
620 DEBUG(MTD_DEBUG_LEVEL0
, "Correcting single bit ECC error at "
621 "offset: %d, bit: %d\n", find_byte
, find_bit
);
623 page_data
[find_byte
] ^= (1 << find_bit
);
628 if (ecc_data2
[0] == 0 &&
633 DEBUG(MTD_DEBUG_LEVEL0
, "UNCORRECTED_ERROR default\n");
639 * omap_correct_data - Compares the ECC read with HW generated ECC
640 * @mtd: MTD device structure
642 * @read_ecc: ecc read from nand flash
643 * @calc_ecc: ecc read from HW ECC registers
645 * Compares the ecc read from nand spare area with ECC registers values
646 * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
649 static int omap_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
650 u_char
*read_ecc
, u_char
*calc_ecc
)
652 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
654 int blockCnt
= 0, i
= 0, ret
= 0;
656 /* Ex NAND_ECC_HW12_2048 */
657 if ((info
->nand
.ecc
.mode
== NAND_ECC_HW
) &&
658 (info
->nand
.ecc
.size
== 2048))
663 for (i
= 0; i
< blockCnt
; i
++) {
664 if (memcmp(read_ecc
, calc_ecc
, 3) != 0) {
665 ret
= omap_compare_ecc(read_ecc
, calc_ecc
, dat
);
677 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
678 * @mtd: MTD device structure
679 * @dat: The pointer to data on which ecc is computed
680 * @ecc_code: The ecc_code buffer
682 * Using noninverted ECC can be considered ugly since writing a blank
683 * page ie. padding will clear the ECC bytes. This is no problem as long
684 * nobody is trying to write data on the seemingly unused page. Reading
685 * an erased page will produce an ECC mismatch between generated and read
686 * ECC bytes that has to be dealt with separately.
688 static int omap_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
691 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
693 return gpmc_calculate_ecc(info
->gpmc_cs
, dat
, ecc_code
);
697 * omap_enable_hwecc - This function enables the hardware ecc functionality
698 * @mtd: MTD device structure
699 * @mode: Read/Write mode
701 static void omap_enable_hwecc(struct mtd_info
*mtd
, int mode
)
703 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
705 struct nand_chip
*chip
= mtd
->priv
;
706 unsigned int dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
708 gpmc_enable_hwecc(info
->gpmc_cs
, mode
, dev_width
, info
->nand
.ecc
.size
);
714 * omap_wait - wait until the command is done
715 * @mtd: MTD device structure
716 * @chip: NAND Chip structure
718 * Wait function is called during Program and erase operations and
719 * the way it is called from MTD layer, we should wait till the NAND
720 * chip is ready after the programming/erase operation has completed.
722 * Erase can take up to 400ms and program up to 20ms according to
723 * general NAND and SmartMedia specs
725 static int omap_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
727 struct nand_chip
*this = mtd
->priv
;
728 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
730 unsigned long timeo
= jiffies
;
731 int status
= NAND_STATUS_FAIL
, state
= this->state
;
733 if (state
== FL_ERASING
)
734 timeo
+= (HZ
* 400) / 1000;
736 timeo
+= (HZ
* 20) / 1000;
738 gpmc_nand_write(info
->gpmc_cs
,
739 GPMC_NAND_COMMAND
, (NAND_CMD_STATUS
& 0xFF));
740 while (time_before(jiffies
, timeo
)) {
741 status
= gpmc_nand_read(info
->gpmc_cs
, GPMC_NAND_DATA
);
742 if (status
& NAND_STATUS_READY
)
750 * omap_dev_ready - calls the platform specific dev_ready function
751 * @mtd: MTD device structure
753 static int omap_dev_ready(struct mtd_info
*mtd
)
755 unsigned int val
= 0;
756 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
759 val
= gpmc_read_status(GPMC_GET_IRQ_STATUS
);
760 if ((val
& 0x100) == 0x100) {
761 /* Clear IRQ Interrupt */
764 gpmc_cs_configure(info
->gpmc_cs
, GPMC_SET_IRQ_STATUS
, val
);
766 unsigned int cnt
= 0;
767 while (cnt
++ < 0x1FF) {
768 if ((val
& 0x100) == 0x100)
770 val
= gpmc_read_status(GPMC_GET_IRQ_STATUS
);
777 static int __devinit
omap_nand_probe(struct platform_device
*pdev
)
779 struct omap_nand_info
*info
;
780 struct omap_nand_platform_data
*pdata
;
783 pdata
= pdev
->dev
.platform_data
;
785 dev_err(&pdev
->dev
, "platform data missing\n");
789 info
= kzalloc(sizeof(struct omap_nand_info
), GFP_KERNEL
);
793 platform_set_drvdata(pdev
, info
);
795 spin_lock_init(&info
->controller
.lock
);
796 init_waitqueue_head(&info
->controller
.wq
);
800 info
->gpmc_cs
= pdata
->cs
;
801 info
->phys_base
= pdata
->phys_base
;
803 info
->mtd
.priv
= &info
->nand
;
804 info
->mtd
.name
= dev_name(&pdev
->dev
);
805 info
->mtd
.owner
= THIS_MODULE
;
807 info
->nand
.options
|= pdata
->devsize
? NAND_BUSWIDTH_16
: 0;
808 info
->nand
.options
|= NAND_SKIP_BBTSCAN
;
810 /* NAND write protect off */
811 gpmc_cs_configure(info
->gpmc_cs
, GPMC_CONFIG_WP
, 0);
813 if (!request_mem_region(info
->phys_base
, NAND_IO_SIZE
,
814 pdev
->dev
.driver
->name
)) {
819 info
->nand
.IO_ADDR_R
= ioremap(info
->phys_base
, NAND_IO_SIZE
);
820 if (!info
->nand
.IO_ADDR_R
) {
822 goto out_release_mem_region
;
825 info
->nand
.controller
= &info
->controller
;
827 info
->nand
.IO_ADDR_W
= info
->nand
.IO_ADDR_R
;
828 info
->nand
.cmd_ctrl
= omap_hwcontrol
;
831 * If RDY/BSY line is connected to OMAP then use the omap ready
832 * funcrtion and the generic nand_wait function which reads the status
833 * register after monitoring the RDY/BSY line.Otherwise use a standard
834 * chip delay which is slightly more than tR (AC Timing) of the NAND
835 * device and read status register until you get a failure or success
837 if (pdata
->dev_ready
) {
838 info
->nand
.dev_ready
= omap_dev_ready
;
839 info
->nand
.chip_delay
= 0;
841 info
->nand
.waitfunc
= omap_wait
;
842 info
->nand
.chip_delay
= 50;
847 info
->nand
.read_buf
= omap_read_buf_pref
;
848 info
->nand
.write_buf
= omap_write_buf_pref
;
850 err
= omap_request_dma(OMAP24XX_DMA_GPMC
, "NAND",
851 omap_nand_dma_cb
, &info
->comp
, &info
->dma_ch
);
854 printk(KERN_WARNING
"DMA request failed."
855 " Non-dma data transfer mode\n");
857 omap_set_dma_dest_burst_mode(info
->dma_ch
,
858 OMAP_DMA_DATA_BURST_16
);
859 omap_set_dma_src_burst_mode(info
->dma_ch
,
860 OMAP_DMA_DATA_BURST_16
);
862 info
->nand
.read_buf
= omap_read_buf_dma_pref
;
863 info
->nand
.write_buf
= omap_write_buf_dma_pref
;
867 if (info
->nand
.options
& NAND_BUSWIDTH_16
) {
868 info
->nand
.read_buf
= omap_read_buf16
;
869 info
->nand
.write_buf
= omap_write_buf16
;
871 info
->nand
.read_buf
= omap_read_buf8
;
872 info
->nand
.write_buf
= omap_write_buf8
;
875 info
->nand
.verify_buf
= omap_verify_buf
;
877 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
878 info
->nand
.ecc
.bytes
= 3;
879 info
->nand
.ecc
.size
= 512;
880 info
->nand
.ecc
.calculate
= omap_calculate_ecc
;
881 info
->nand
.ecc
.hwctl
= omap_enable_hwecc
;
882 info
->nand
.ecc
.correct
= omap_correct_data
;
883 info
->nand
.ecc
.mode
= NAND_ECC_HW
;
886 info
->nand
.ecc
.mode
= NAND_ECC_SOFT
;
889 /* DIP switches on some boards change between 8 and 16 bit
890 * bus widths for flash. Try the other width if the first try fails.
892 if (nand_scan(&info
->mtd
, 1)) {
893 info
->nand
.options
^= NAND_BUSWIDTH_16
;
894 if (nand_scan(&info
->mtd
, 1)) {
896 goto out_release_mem_region
;
900 #ifdef CONFIG_MTD_PARTITIONS
901 err
= parse_mtd_partitions(&info
->mtd
, part_probes
, &info
->parts
, 0);
903 add_mtd_partitions(&info
->mtd
, info
->parts
, err
);
904 else if (pdata
->parts
)
905 add_mtd_partitions(&info
->mtd
, pdata
->parts
, pdata
->nr_parts
);
908 add_mtd_device(&info
->mtd
);
910 platform_set_drvdata(pdev
, &info
->mtd
);
914 out_release_mem_region
:
915 release_mem_region(info
->phys_base
, NAND_IO_SIZE
);
922 static int omap_nand_remove(struct platform_device
*pdev
)
924 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
925 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
928 platform_set_drvdata(pdev
, NULL
);
930 omap_free_dma(info
->dma_ch
);
932 /* Release NAND device, its internal structures and partitions */
933 nand_release(&info
->mtd
);
934 iounmap(info
->nand
.IO_ADDR_R
);
939 static struct platform_driver omap_nand_driver
= {
940 .probe
= omap_nand_probe
,
941 .remove
= omap_nand_remove
,
944 .owner
= THIS_MODULE
,
948 static int __init
omap_nand_init(void)
950 printk(KERN_INFO
"%s driver initializing\n", DRIVER_NAME
);
952 /* This check is required if driver is being
953 * loaded run time as a module
955 if ((1 == use_dma
) && (0 == use_prefetch
)) {
956 printk(KERN_INFO
"Wrong parameters: 'use_dma' can not be 1 "
957 "without use_prefetch'. Prefetch will not be"
958 " used in either mode (mpu or dma)\n");
960 return platform_driver_register(&omap_nand_driver
);
963 static void __exit
omap_nand_exit(void)
965 platform_driver_unregister(&omap_nand_driver
);
968 module_init(omap_nand_init
);
969 module_exit(omap_nand_exit
);
971 MODULE_ALIAS("platform:" DRIVER_NAME
);
972 MODULE_LICENSE("GPL");
973 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");