2 * drivers/mtd/nand/pxa3xx_nand.c
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
23 #include <linux/irq.h>
26 #include <mach/pxa3xx_nand.h>
28 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
30 /* registers and bit definitions */
31 #define NDCR (0x00) /* Control register */
32 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
33 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
34 #define NDSR (0x14) /* Status Register */
35 #define NDPCR (0x18) /* Page Count Register */
36 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
37 #define NDBDR1 (0x20) /* Bad Block Register 1 */
38 #define NDDB (0x40) /* Data Buffer */
39 #define NDCB0 (0x48) /* Command Buffer0 */
40 #define NDCB1 (0x4C) /* Command Buffer1 */
41 #define NDCB2 (0x50) /* Command Buffer2 */
43 #define NDCR_SPARE_EN (0x1 << 31)
44 #define NDCR_ECC_EN (0x1 << 30)
45 #define NDCR_DMA_EN (0x1 << 29)
46 #define NDCR_ND_RUN (0x1 << 28)
47 #define NDCR_DWIDTH_C (0x1 << 27)
48 #define NDCR_DWIDTH_M (0x1 << 26)
49 #define NDCR_PAGE_SZ (0x1 << 24)
50 #define NDCR_NCSX (0x1 << 23)
51 #define NDCR_ND_MODE (0x3 << 21)
52 #define NDCR_NAND_MODE (0x0)
53 #define NDCR_CLR_PG_CNT (0x1 << 20)
54 #define NDCR_CLR_ECC (0x1 << 19)
55 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
56 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
58 #define NDCR_RA_START (0x1 << 15)
59 #define NDCR_PG_PER_BLK (0x1 << 14)
60 #define NDCR_ND_ARB_EN (0x1 << 12)
62 #define NDSR_MASK (0xfff)
63 #define NDSR_RDY (0x1 << 11)
64 #define NDSR_CS0_PAGED (0x1 << 10)
65 #define NDSR_CS1_PAGED (0x1 << 9)
66 #define NDSR_CS0_CMDD (0x1 << 8)
67 #define NDSR_CS1_CMDD (0x1 << 7)
68 #define NDSR_CS0_BBD (0x1 << 6)
69 #define NDSR_CS1_BBD (0x1 << 5)
70 #define NDSR_DBERR (0x1 << 4)
71 #define NDSR_SBERR (0x1 << 3)
72 #define NDSR_WRDREQ (0x1 << 2)
73 #define NDSR_RDDREQ (0x1 << 1)
74 #define NDSR_WRCMDREQ (0x1)
76 #define NDCB0_AUTO_RS (0x1 << 25)
77 #define NDCB0_CSEL (0x1 << 24)
78 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
79 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80 #define NDCB0_NC (0x1 << 20)
81 #define NDCB0_DBC (0x1 << 19)
82 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
83 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84 #define NDCB0_CMD2_MASK (0xff << 8)
85 #define NDCB0_CMD1_MASK (0xff)
86 #define NDCB0_ADDR_CYC_SHIFT (16)
88 /* macros for registers read/write */
89 #define nand_writel(info, off, val) \
90 __raw_writel((val), (info)->mmio_base + (off))
92 #define nand_readl(info, off) \
93 __raw_readl((info)->mmio_base + (off))
95 /* error code and state */
115 struct pxa3xx_nand_info
{
116 struct nand_chip nand_chip
;
118 struct platform_device
*pdev
;
119 const struct pxa3xx_nand_flash
*flash_info
;
122 void __iomem
*mmio_base
;
123 unsigned long mmio_phys
;
125 unsigned int buf_start
;
126 unsigned int buf_count
;
128 /* DMA information */
132 unsigned char *data_buff
;
133 dma_addr_t data_buff_phys
;
134 size_t data_buff_size
;
136 struct pxa_dma_desc
*data_desc
;
137 dma_addr_t data_desc_addr
;
141 /* saved column/page_addr during CMD_SEQIN */
145 /* relate to the command */
148 int use_ecc
; /* use HW ECC ? */
149 int use_dma
; /* use DMA ? */
151 size_t data_size
; /* data size in FIFO */
153 struct completion cmd_complete
;
155 /* generated NDCBx register values */
160 /* calculated from pxa3xx_nand_flash data */
162 size_t read_id_bytes
;
164 unsigned int col_addr_cycles
;
165 unsigned int row_addr_cycles
;
168 static int use_dma
= 1;
169 module_param(use_dma
, bool, 0444);
170 MODULE_PARM_DESC(use_dma
, "enable DMA for data transfering to/from NAND HW");
173 * Default NAND flash controller configuration setup by the
174 * bootloader. This configuration is used only when pdata->keep_config is set
176 static struct pxa3xx_nand_timing default_timing
;
177 static struct pxa3xx_nand_flash default_flash
;
179 static struct pxa3xx_nand_cmdset smallpage_cmdset
= {
183 .read_status
= 0x0070,
189 .lock_status
= 0x007A,
192 static struct pxa3xx_nand_cmdset largepage_cmdset
= {
196 .read_status
= 0x0070,
202 .lock_status
= 0x007A,
205 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
206 static struct pxa3xx_nand_timing samsung512MbX16_timing
= {
218 static struct pxa3xx_nand_flash samsung512MbX16
= {
219 .timing
= &samsung512MbX16_timing
,
220 .cmdset
= &smallpage_cmdset
,
221 .page_per_block
= 32,
229 static struct pxa3xx_nand_timing micron_timing
= {
241 static struct pxa3xx_nand_flash micron1GbX8
= {
242 .timing
= µn_timing
,
243 .cmdset
= &largepage_cmdset
,
244 .page_per_block
= 64,
252 static struct pxa3xx_nand_flash micron1GbX16
= {
253 .timing
= µn_timing
,
254 .cmdset
= &largepage_cmdset
,
255 .page_per_block
= 64,
263 static struct pxa3xx_nand_timing stm2GbX16_timing
= {
275 static struct pxa3xx_nand_flash stm2GbX16
= {
276 .timing
= &stm2GbX16_timing
,
277 .cmdset
= &largepage_cmdset
,
278 .page_per_block
= 64,
286 static struct pxa3xx_nand_flash
*builtin_flash_types
[] = {
292 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
294 #define NDTR0_tCH(c) (min((c), 7) << 19)
295 #define NDTR0_tCS(c) (min((c), 7) << 16)
296 #define NDTR0_tWH(c) (min((c), 7) << 11)
297 #define NDTR0_tWP(c) (min((c), 7) << 8)
298 #define NDTR0_tRH(c) (min((c), 7) << 3)
299 #define NDTR0_tRP(c) (min((c), 7) << 0)
301 #define NDTR1_tR(c) (min((c), 65535) << 16)
302 #define NDTR1_tWHR(c) (min((c), 15) << 4)
303 #define NDTR1_tAR(c) (min((c), 15) << 0)
305 #define tCH_NDTR0(r) (((r) >> 19) & 0x7)
306 #define tCS_NDTR0(r) (((r) >> 16) & 0x7)
307 #define tWH_NDTR0(r) (((r) >> 11) & 0x7)
308 #define tWP_NDTR0(r) (((r) >> 8) & 0x7)
309 #define tRH_NDTR0(r) (((r) >> 3) & 0x7)
310 #define tRP_NDTR0(r) (((r) >> 0) & 0x7)
312 #define tR_NDTR1(r) (((r) >> 16) & 0xffff)
313 #define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
314 #define tAR_NDTR1(r) (((r) >> 0) & 0xf)
316 /* convert nano-seconds to nand flash controller clock cycles */
317 #define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1)
319 /* convert nand flash controller clock cycles to nano-seconds */
320 #define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
322 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info
*info
,
323 const struct pxa3xx_nand_timing
*t
)
325 unsigned long nand_clk
= clk_get_rate(info
->clk
);
326 uint32_t ndtr0
, ndtr1
;
328 ndtr0
= NDTR0_tCH(ns2cycle(t
->tCH
, nand_clk
)) |
329 NDTR0_tCS(ns2cycle(t
->tCS
, nand_clk
)) |
330 NDTR0_tWH(ns2cycle(t
->tWH
, nand_clk
)) |
331 NDTR0_tWP(ns2cycle(t
->tWP
, nand_clk
)) |
332 NDTR0_tRH(ns2cycle(t
->tRH
, nand_clk
)) |
333 NDTR0_tRP(ns2cycle(t
->tRP
, nand_clk
));
335 ndtr1
= NDTR1_tR(ns2cycle(t
->tR
, nand_clk
)) |
336 NDTR1_tWHR(ns2cycle(t
->tWHR
, nand_clk
)) |
337 NDTR1_tAR(ns2cycle(t
->tAR
, nand_clk
));
339 nand_writel(info
, NDTR0CS0
, ndtr0
);
340 nand_writel(info
, NDTR1CS0
, ndtr1
);
343 #define WAIT_EVENT_TIMEOUT 10
345 static int wait_for_event(struct pxa3xx_nand_info
*info
, uint32_t event
)
347 int timeout
= WAIT_EVENT_TIMEOUT
;
351 ndsr
= nand_readl(info
, NDSR
) & NDSR_MASK
;
353 nand_writel(info
, NDSR
, ndsr
);
362 static int prepare_read_prog_cmd(struct pxa3xx_nand_info
*info
,
363 uint16_t cmd
, int column
, int page_addr
)
365 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
366 const struct pxa3xx_nand_cmdset
*cmdset
= f
->cmdset
;
368 /* calculate data size */
369 switch (f
->page_size
) {
371 info
->data_size
= (info
->use_ecc
) ? 2088 : 2112;
374 info
->data_size
= (info
->use_ecc
) ? 520 : 528;
380 /* generate values for NDCBx registers */
381 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
384 info
->ndcb0
|= NDCB0_ADDR_CYC(info
->row_addr_cycles
+ info
->col_addr_cycles
);
386 if (info
->col_addr_cycles
== 2) {
387 /* large block, 2 cycles for column address
388 * row address starts from 3rd cycle
390 info
->ndcb1
|= page_addr
<< 16;
391 if (info
->row_addr_cycles
== 3)
392 info
->ndcb2
= (page_addr
>> 16) & 0xff;
394 /* small block, 1 cycles for column address
395 * row address starts from 2nd cycle
397 info
->ndcb1
= page_addr
<< 8;
399 if (cmd
== cmdset
->program
)
400 info
->ndcb0
|= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS
;
405 static int prepare_erase_cmd(struct pxa3xx_nand_info
*info
,
406 uint16_t cmd
, int page_addr
)
408 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
409 info
->ndcb0
|= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS
| NDCB0_ADDR_CYC(3);
410 info
->ndcb1
= page_addr
;
415 static int prepare_other_cmd(struct pxa3xx_nand_info
*info
, uint16_t cmd
)
417 const struct pxa3xx_nand_cmdset
*cmdset
= info
->flash_info
->cmdset
;
419 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
423 if (cmd
== cmdset
->read_id
) {
424 info
->ndcb0
|= NDCB0_CMD_TYPE(3);
426 } else if (cmd
== cmdset
->read_status
) {
427 info
->ndcb0
|= NDCB0_CMD_TYPE(4);
429 } else if (cmd
== cmdset
->reset
|| cmd
== cmdset
->lock
||
430 cmd
== cmdset
->unlock
) {
431 info
->ndcb0
|= NDCB0_CMD_TYPE(5);
438 static void enable_int(struct pxa3xx_nand_info
*info
, uint32_t int_mask
)
442 ndcr
= nand_readl(info
, NDCR
);
443 nand_writel(info
, NDCR
, ndcr
& ~int_mask
);
446 static void disable_int(struct pxa3xx_nand_info
*info
, uint32_t int_mask
)
450 ndcr
= nand_readl(info
, NDCR
);
451 nand_writel(info
, NDCR
, ndcr
| int_mask
);
454 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
455 * otherwise, it does not work
457 static int write_cmd(struct pxa3xx_nand_info
*info
)
461 /* clear status bits and run */
462 nand_writel(info
, NDSR
, NDSR_MASK
);
464 ndcr
= info
->reg_ndcr
;
466 ndcr
|= info
->use_ecc
? NDCR_ECC_EN
: 0;
467 ndcr
|= info
->use_dma
? NDCR_DMA_EN
: 0;
470 nand_writel(info
, NDCR
, ndcr
);
472 if (wait_for_event(info
, NDSR_WRCMDREQ
)) {
473 printk(KERN_ERR
"timed out writing command\n");
477 nand_writel(info
, NDCB0
, info
->ndcb0
);
478 nand_writel(info
, NDCB0
, info
->ndcb1
);
479 nand_writel(info
, NDCB0
, info
->ndcb2
);
483 static int handle_data_pio(struct pxa3xx_nand_info
*info
)
485 int ret
, timeout
= CHIP_DELAY_TIMEOUT
;
487 switch (info
->state
) {
488 case STATE_PIO_WRITING
:
489 __raw_writesl(info
->mmio_base
+ NDDB
, info
->data_buff
,
490 DIV_ROUND_UP(info
->data_size
, 4));
492 enable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
494 ret
= wait_for_completion_timeout(&info
->cmd_complete
, timeout
);
496 printk(KERN_ERR
"program command time out\n");
500 case STATE_PIO_READING
:
501 __raw_readsl(info
->mmio_base
+ NDDB
, info
->data_buff
,
502 DIV_ROUND_UP(info
->data_size
, 4));
505 printk(KERN_ERR
"%s: invalid state %d\n", __func__
,
510 info
->state
= STATE_READY
;
514 static void start_data_dma(struct pxa3xx_nand_info
*info
, int dir_out
)
516 struct pxa_dma_desc
*desc
= info
->data_desc
;
517 int dma_len
= ALIGN(info
->data_size
, 32);
519 desc
->ddadr
= DDADR_STOP
;
520 desc
->dcmd
= DCMD_ENDIRQEN
| DCMD_WIDTH4
| DCMD_BURST32
| dma_len
;
523 desc
->dsadr
= info
->data_buff_phys
;
524 desc
->dtadr
= info
->mmio_phys
+ NDDB
;
525 desc
->dcmd
|= DCMD_INCSRCADDR
| DCMD_FLOWTRG
;
527 desc
->dtadr
= info
->data_buff_phys
;
528 desc
->dsadr
= info
->mmio_phys
+ NDDB
;
529 desc
->dcmd
|= DCMD_INCTRGADDR
| DCMD_FLOWSRC
;
532 DRCMR(info
->drcmr_dat
) = DRCMR_MAPVLD
| info
->data_dma_ch
;
533 DDADR(info
->data_dma_ch
) = info
->data_desc_addr
;
534 DCSR(info
->data_dma_ch
) |= DCSR_RUN
;
537 static void pxa3xx_nand_data_dma_irq(int channel
, void *data
)
539 struct pxa3xx_nand_info
*info
= data
;
542 dcsr
= DCSR(channel
);
543 DCSR(channel
) = dcsr
;
545 if (dcsr
& DCSR_BUSERR
) {
546 info
->retcode
= ERR_DMABUSERR
;
547 complete(&info
->cmd_complete
);
550 if (info
->state
== STATE_DMA_WRITING
) {
551 info
->state
= STATE_DMA_DONE
;
552 enable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
554 info
->state
= STATE_READY
;
555 complete(&info
->cmd_complete
);
559 static irqreturn_t
pxa3xx_nand_irq(int irq
, void *devid
)
561 struct pxa3xx_nand_info
*info
= devid
;
564 status
= nand_readl(info
, NDSR
);
566 if (status
& (NDSR_RDDREQ
| NDSR_DBERR
| NDSR_SBERR
)) {
567 if (status
& NDSR_DBERR
)
568 info
->retcode
= ERR_DBERR
;
569 else if (status
& NDSR_SBERR
)
570 info
->retcode
= ERR_SBERR
;
572 disable_int(info
, NDSR_RDDREQ
| NDSR_DBERR
| NDSR_SBERR
);
575 info
->state
= STATE_DMA_READING
;
576 start_data_dma(info
, 0);
578 info
->state
= STATE_PIO_READING
;
579 complete(&info
->cmd_complete
);
581 } else if (status
& NDSR_WRDREQ
) {
582 disable_int(info
, NDSR_WRDREQ
);
584 info
->state
= STATE_DMA_WRITING
;
585 start_data_dma(info
, 1);
587 info
->state
= STATE_PIO_WRITING
;
588 complete(&info
->cmd_complete
);
590 } else if (status
& (NDSR_CS0_BBD
| NDSR_CS0_CMDD
)) {
591 if (status
& NDSR_CS0_BBD
)
592 info
->retcode
= ERR_BBERR
;
594 disable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
595 info
->state
= STATE_READY
;
596 complete(&info
->cmd_complete
);
598 nand_writel(info
, NDSR
, status
);
602 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info
*info
, uint32_t event
)
605 int ret
, timeout
= CHIP_DELAY_TIMEOUT
;
607 if (write_cmd(info
)) {
608 info
->retcode
= ERR_SENDCMD
;
612 info
->state
= STATE_CMD_HANDLE
;
614 enable_int(info
, event
);
616 ret
= wait_for_completion_timeout(&info
->cmd_complete
, timeout
);
618 printk(KERN_ERR
"command execution timed out\n");
619 info
->retcode
= ERR_SENDCMD
;
623 if (info
->use_dma
== 0 && info
->data_size
> 0)
624 if (handle_data_pio(info
))
630 ndcr
= nand_readl(info
, NDCR
);
631 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
636 static int pxa3xx_nand_dev_ready(struct mtd_info
*mtd
)
638 struct pxa3xx_nand_info
*info
= mtd
->priv
;
639 return (nand_readl(info
, NDSR
) & NDSR_RDY
) ? 1 : 0;
642 static inline int is_buf_blank(uint8_t *buf
, size_t len
)
644 for (; len
> 0; len
--)
650 static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd
, unsigned command
,
651 int column
, int page_addr
)
653 struct pxa3xx_nand_info
*info
= mtd
->priv
;
654 const struct pxa3xx_nand_flash
*flash_info
= info
->flash_info
;
655 const struct pxa3xx_nand_cmdset
*cmdset
= flash_info
->cmdset
;
658 info
->use_dma
= (use_dma
) ? 1 : 0;
661 info
->state
= STATE_READY
;
663 init_completion(&info
->cmd_complete
);
666 case NAND_CMD_READOOB
:
667 /* disable HW ECC to get all the OOB data */
668 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
669 info
->buf_start
= mtd
->writesize
+ column
;
670 memset(info
->data_buff
, 0xFF, info
->buf_count
);
672 if (prepare_read_prog_cmd(info
, cmdset
->read1
, column
, page_addr
))
675 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
| NDSR_DBERR
| NDSR_SBERR
);
677 /* We only are OOB, so if the data has error, does not matter */
678 if (info
->retcode
== ERR_DBERR
)
679 info
->retcode
= ERR_NONE
;
684 info
->retcode
= ERR_NONE
;
685 info
->buf_start
= column
;
686 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
687 memset(info
->data_buff
, 0xFF, info
->buf_count
);
689 if (prepare_read_prog_cmd(info
, cmdset
->read1
, column
, page_addr
))
692 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
| NDSR_DBERR
| NDSR_SBERR
);
694 if (info
->retcode
== ERR_DBERR
) {
695 /* for blank page (all 0xff), HW will calculate its ECC as
696 * 0, which is different from the ECC information within
697 * OOB, ignore such double bit errors
699 if (is_buf_blank(info
->data_buff
, mtd
->writesize
))
700 info
->retcode
= ERR_NONE
;
704 info
->buf_start
= column
;
705 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
706 memset(info
->data_buff
, 0xff, info
->buf_count
);
708 /* save column/page_addr for next CMD_PAGEPROG */
709 info
->seqin_column
= column
;
710 info
->seqin_page_addr
= page_addr
;
712 case NAND_CMD_PAGEPROG
:
713 info
->use_ecc
= (info
->seqin_column
>= mtd
->writesize
) ? 0 : 1;
715 if (prepare_read_prog_cmd(info
, cmdset
->program
,
716 info
->seqin_column
, info
->seqin_page_addr
))
719 pxa3xx_nand_do_cmd(info
, NDSR_WRDREQ
);
721 case NAND_CMD_ERASE1
:
722 if (prepare_erase_cmd(info
, cmdset
->erase
, page_addr
))
725 pxa3xx_nand_do_cmd(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
727 case NAND_CMD_ERASE2
:
729 case NAND_CMD_READID
:
730 case NAND_CMD_STATUS
:
731 info
->use_dma
= 0; /* force PIO read */
733 info
->buf_count
= (command
== NAND_CMD_READID
) ?
734 info
->read_id_bytes
: 1;
736 if (prepare_other_cmd(info
, (command
== NAND_CMD_READID
) ?
737 cmdset
->read_id
: cmdset
->read_status
))
740 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
);
743 if (prepare_other_cmd(info
, cmdset
->reset
))
746 ret
= pxa3xx_nand_do_cmd(info
, NDSR_CS0_CMDD
);
752 if (nand_readl(info
, NDSR
) & NDSR_RDY
)
757 ndcr
= nand_readl(info
, NDCR
);
758 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
762 printk(KERN_ERR
"non-supported command.\n");
766 if (info
->retcode
== ERR_DBERR
) {
767 printk(KERN_ERR
"double bit error @ page %08x\n", page_addr
);
768 info
->retcode
= ERR_NONE
;
772 static uint8_t pxa3xx_nand_read_byte(struct mtd_info
*mtd
)
774 struct pxa3xx_nand_info
*info
= mtd
->priv
;
777 if (info
->buf_start
< info
->buf_count
)
778 /* Has just send a new command? */
779 retval
= info
->data_buff
[info
->buf_start
++];
784 static u16
pxa3xx_nand_read_word(struct mtd_info
*mtd
)
786 struct pxa3xx_nand_info
*info
= mtd
->priv
;
789 if (!(info
->buf_start
& 0x01) && info
->buf_start
< info
->buf_count
) {
790 retval
= *((u16
*)(info
->data_buff
+info
->buf_start
));
791 info
->buf_start
+= 2;
796 static void pxa3xx_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
798 struct pxa3xx_nand_info
*info
= mtd
->priv
;
799 int real_len
= min_t(size_t, len
, info
->buf_count
- info
->buf_start
);
801 memcpy(buf
, info
->data_buff
+ info
->buf_start
, real_len
);
802 info
->buf_start
+= real_len
;
805 static void pxa3xx_nand_write_buf(struct mtd_info
*mtd
,
806 const uint8_t *buf
, int len
)
808 struct pxa3xx_nand_info
*info
= mtd
->priv
;
809 int real_len
= min_t(size_t, len
, info
->buf_count
- info
->buf_start
);
811 memcpy(info
->data_buff
+ info
->buf_start
, buf
, real_len
);
812 info
->buf_start
+= real_len
;
815 static int pxa3xx_nand_verify_buf(struct mtd_info
*mtd
,
816 const uint8_t *buf
, int len
)
821 static void pxa3xx_nand_select_chip(struct mtd_info
*mtd
, int chip
)
826 static int pxa3xx_nand_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*this)
828 struct pxa3xx_nand_info
*info
= mtd
->priv
;
830 /* pxa3xx_nand_send_command has waited for command complete */
831 if (this->state
== FL_WRITING
|| this->state
== FL_ERASING
) {
832 if (info
->retcode
== ERR_NONE
)
836 * any error make it return 0x01 which will tell
837 * the caller the erase and write fail
846 static void pxa3xx_nand_ecc_hwctl(struct mtd_info
*mtd
, int mode
)
851 static int pxa3xx_nand_ecc_calculate(struct mtd_info
*mtd
,
852 const uint8_t *dat
, uint8_t *ecc_code
)
857 static int pxa3xx_nand_ecc_correct(struct mtd_info
*mtd
,
858 uint8_t *dat
, uint8_t *read_ecc
, uint8_t *calc_ecc
)
860 struct pxa3xx_nand_info
*info
= mtd
->priv
;
862 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
863 * consider it as a ecc error which will tell the caller the
864 * read fail We have distinguish all the errors, but the
865 * nand_read_ecc only check this function return value
867 * Corrected (single-bit) errors must also be noted.
869 if (info
->retcode
== ERR_SBERR
)
871 else if (info
->retcode
!= ERR_NONE
)
877 static int __readid(struct pxa3xx_nand_info
*info
, uint32_t *id
)
879 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
880 const struct pxa3xx_nand_cmdset
*cmdset
= f
->cmdset
;
884 if (prepare_other_cmd(info
, cmdset
->read_id
)) {
885 printk(KERN_ERR
"failed to prepare command\n");
893 /* Wait for CMDDM(command done successfully) */
894 if (wait_for_event(info
, NDSR_RDDREQ
))
897 __raw_readsl(info
->mmio_base
+ NDDB
, id_buff
, 2);
898 *id
= id_buff
[0] | (id_buff
[1] << 8);
902 ndcr
= nand_readl(info
, NDCR
);
903 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
908 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info
*info
,
909 const struct pxa3xx_nand_flash
*f
)
911 struct platform_device
*pdev
= info
->pdev
;
912 struct pxa3xx_nand_platform_data
*pdata
= pdev
->dev
.platform_data
;
913 uint32_t ndcr
= 0x00000FFF; /* disable all interrupts */
915 if (f
->page_size
!= 2048 && f
->page_size
!= 512)
918 if (f
->flash_width
!= 16 && f
->flash_width
!= 8)
921 /* calculate flash information */
922 info
->oob_size
= (f
->page_size
== 2048) ? 64 : 16;
923 info
->read_id_bytes
= (f
->page_size
== 2048) ? 4 : 2;
925 /* calculate addressing information */
926 info
->col_addr_cycles
= (f
->page_size
== 2048) ? 2 : 1;
928 if (f
->num_blocks
* f
->page_per_block
> 65536)
929 info
->row_addr_cycles
= 3;
931 info
->row_addr_cycles
= 2;
933 ndcr
|= (pdata
->enable_arbiter
) ? NDCR_ND_ARB_EN
: 0;
934 ndcr
|= (info
->col_addr_cycles
== 2) ? NDCR_RA_START
: 0;
935 ndcr
|= (f
->page_per_block
== 64) ? NDCR_PG_PER_BLK
: 0;
936 ndcr
|= (f
->page_size
== 2048) ? NDCR_PAGE_SZ
: 0;
937 ndcr
|= (f
->flash_width
== 16) ? NDCR_DWIDTH_M
: 0;
938 ndcr
|= (f
->dfc_width
== 16) ? NDCR_DWIDTH_C
: 0;
940 ndcr
|= NDCR_RD_ID_CNT(info
->read_id_bytes
);
941 ndcr
|= NDCR_SPARE_EN
; /* enable spare by default */
943 info
->reg_ndcr
= ndcr
;
945 pxa3xx_nand_set_timing(info
, f
->timing
);
946 info
->flash_info
= f
;
950 static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info
*info
,
951 struct pxa3xx_nand_timing
*t
)
953 unsigned long nand_clk
= clk_get_rate(info
->clk
);
954 uint32_t ndtr0
= nand_readl(info
, NDTR0CS0
);
955 uint32_t ndtr1
= nand_readl(info
, NDTR1CS0
);
957 t
->tCH
= cycle2ns(tCH_NDTR0(ndtr0
), nand_clk
);
958 t
->tCS
= cycle2ns(tCS_NDTR0(ndtr0
), nand_clk
);
959 t
->tWH
= cycle2ns(tWH_NDTR0(ndtr0
), nand_clk
);
960 t
->tWP
= cycle2ns(tWP_NDTR0(ndtr0
), nand_clk
);
961 t
->tRH
= cycle2ns(tRH_NDTR0(ndtr0
), nand_clk
);
962 t
->tRP
= cycle2ns(tRP_NDTR0(ndtr0
), nand_clk
);
964 t
->tR
= cycle2ns(tR_NDTR1(ndtr1
), nand_clk
);
965 t
->tWHR
= cycle2ns(tWHR_NDTR1(ndtr1
), nand_clk
);
966 t
->tAR
= cycle2ns(tAR_NDTR1(ndtr1
), nand_clk
);
969 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info
*info
)
971 uint32_t ndcr
= nand_readl(info
, NDCR
);
972 struct nand_flash_dev
*type
= NULL
;
976 default_flash
.page_per_block
= ndcr
& NDCR_PG_PER_BLK
? 64 : 32;
977 default_flash
.page_size
= ndcr
& NDCR_PAGE_SZ
? 2048 : 512;
978 default_flash
.flash_width
= ndcr
& NDCR_DWIDTH_M
? 16 : 8;
979 default_flash
.dfc_width
= ndcr
& NDCR_DWIDTH_C
? 16 : 8;
981 if (default_flash
.page_size
== 2048)
982 default_flash
.cmdset
= &largepage_cmdset
;
984 default_flash
.cmdset
= &smallpage_cmdset
;
986 /* set info fields needed to __readid */
987 info
->flash_info
= &default_flash
;
988 info
->read_id_bytes
= (default_flash
.page_size
== 2048) ? 4 : 2;
989 info
->reg_ndcr
= ndcr
;
991 if (__readid(info
, &id
))
994 /* Lookup the flash id */
995 id
= (id
>> 8) & 0xff; /* device id is byte 2 */
996 for (i
= 0; nand_flash_ids
[i
].name
!= NULL
; i
++) {
997 if (id
== nand_flash_ids
[i
].id
) {
998 type
= &nand_flash_ids
[i
];
1006 /* fill the missing flash information */
1007 i
= __ffs(default_flash
.page_per_block
* default_flash
.page_size
);
1008 default_flash
.num_blocks
= type
->chipsize
<< (20 - i
);
1010 info
->oob_size
= (default_flash
.page_size
== 2048) ? 64 : 16;
1012 /* calculate addressing information */
1013 info
->col_addr_cycles
= (default_flash
.page_size
== 2048) ? 2 : 1;
1015 if (default_flash
.num_blocks
* default_flash
.page_per_block
> 65536)
1016 info
->row_addr_cycles
= 3;
1018 info
->row_addr_cycles
= 2;
1020 pxa3xx_nand_detect_timing(info
, &default_timing
);
1021 default_flash
.timing
= &default_timing
;
1026 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info
*info
,
1027 const struct pxa3xx_nand_platform_data
*pdata
)
1029 const struct pxa3xx_nand_flash
*f
;
1033 if (pdata
->keep_config
)
1034 if (pxa3xx_nand_detect_config(info
) == 0)
1037 for (i
= 0; i
<pdata
->num_flash
; ++i
) {
1038 f
= pdata
->flash
+ i
;
1040 if (pxa3xx_nand_config_flash(info
, f
))
1043 if (__readid(info
, &id
))
1046 if (id
== f
->chip_id
)
1050 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
1051 for (i
= 0; i
< ARRAY_SIZE(builtin_flash_types
); i
++) {
1053 f
= builtin_flash_types
[i
];
1055 if (pxa3xx_nand_config_flash(info
, f
))
1058 if (__readid(info
, &id
))
1061 if (id
== f
->chip_id
)
1066 dev_warn(&info
->pdev
->dev
,
1067 "failed to detect configured nand flash; found %04x instead of\n",
1072 /* the maximum possible buffer size for large page with OOB data
1073 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
1074 * data buffer and the DMA descriptor
1076 #define MAX_BUFF_SIZE PAGE_SIZE
1078 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info
*info
)
1080 struct platform_device
*pdev
= info
->pdev
;
1081 int data_desc_offset
= MAX_BUFF_SIZE
- sizeof(struct pxa_dma_desc
);
1084 info
->data_buff
= kmalloc(MAX_BUFF_SIZE
, GFP_KERNEL
);
1085 if (info
->data_buff
== NULL
)
1090 info
->data_buff
= dma_alloc_coherent(&pdev
->dev
, MAX_BUFF_SIZE
,
1091 &info
->data_buff_phys
, GFP_KERNEL
);
1092 if (info
->data_buff
== NULL
) {
1093 dev_err(&pdev
->dev
, "failed to allocate dma buffer\n");
1097 info
->data_buff_size
= MAX_BUFF_SIZE
;
1098 info
->data_desc
= (void *)info
->data_buff
+ data_desc_offset
;
1099 info
->data_desc_addr
= info
->data_buff_phys
+ data_desc_offset
;
1101 info
->data_dma_ch
= pxa_request_dma("nand-data", DMA_PRIO_LOW
,
1102 pxa3xx_nand_data_dma_irq
, info
);
1103 if (info
->data_dma_ch
< 0) {
1104 dev_err(&pdev
->dev
, "failed to request data dma\n");
1105 dma_free_coherent(&pdev
->dev
, info
->data_buff_size
,
1106 info
->data_buff
, info
->data_buff_phys
);
1107 return info
->data_dma_ch
;
1113 static struct nand_ecclayout hw_smallpage_ecclayout
= {
1115 .eccpos
= {8, 9, 10, 11, 12, 13 },
1116 .oobfree
= { {2, 6} }
1119 static struct nand_ecclayout hw_largepage_ecclayout
= {
1122 40, 41, 42, 43, 44, 45, 46, 47,
1123 48, 49, 50, 51, 52, 53, 54, 55,
1124 56, 57, 58, 59, 60, 61, 62, 63},
1125 .oobfree
= { {2, 38} }
1128 static void pxa3xx_nand_init_mtd(struct mtd_info
*mtd
,
1129 struct pxa3xx_nand_info
*info
)
1131 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
1132 struct nand_chip
*this = &info
->nand_chip
;
1134 this->options
= (f
->flash_width
== 16) ? NAND_BUSWIDTH_16
: 0;
1136 this->waitfunc
= pxa3xx_nand_waitfunc
;
1137 this->select_chip
= pxa3xx_nand_select_chip
;
1138 this->dev_ready
= pxa3xx_nand_dev_ready
;
1139 this->cmdfunc
= pxa3xx_nand_cmdfunc
;
1140 this->read_word
= pxa3xx_nand_read_word
;
1141 this->read_byte
= pxa3xx_nand_read_byte
;
1142 this->read_buf
= pxa3xx_nand_read_buf
;
1143 this->write_buf
= pxa3xx_nand_write_buf
;
1144 this->verify_buf
= pxa3xx_nand_verify_buf
;
1146 this->ecc
.mode
= NAND_ECC_HW
;
1147 this->ecc
.hwctl
= pxa3xx_nand_ecc_hwctl
;
1148 this->ecc
.calculate
= pxa3xx_nand_ecc_calculate
;
1149 this->ecc
.correct
= pxa3xx_nand_ecc_correct
;
1150 this->ecc
.size
= f
->page_size
;
1152 if (f
->page_size
== 2048)
1153 this->ecc
.layout
= &hw_largepage_ecclayout
;
1155 this->ecc
.layout
= &hw_smallpage_ecclayout
;
1157 this->chip_delay
= 25;
1160 static int pxa3xx_nand_probe(struct platform_device
*pdev
)
1162 struct pxa3xx_nand_platform_data
*pdata
;
1163 struct pxa3xx_nand_info
*info
;
1164 struct nand_chip
*this;
1165 struct mtd_info
*mtd
;
1169 pdata
= pdev
->dev
.platform_data
;
1172 dev_err(&pdev
->dev
, "no platform data defined\n");
1176 mtd
= kzalloc(sizeof(struct mtd_info
) + sizeof(struct pxa3xx_nand_info
),
1179 dev_err(&pdev
->dev
, "failed to allocate memory\n");
1183 info
= (struct pxa3xx_nand_info
*)(&mtd
[1]);
1186 this = &info
->nand_chip
;
1188 mtd
->owner
= THIS_MODULE
;
1190 info
->clk
= clk_get(&pdev
->dev
, NULL
);
1191 if (IS_ERR(info
->clk
)) {
1192 dev_err(&pdev
->dev
, "failed to get nand clock\n");
1193 ret
= PTR_ERR(info
->clk
);
1196 clk_enable(info
->clk
);
1198 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1200 dev_err(&pdev
->dev
, "no resource defined for data DMA\n");
1204 info
->drcmr_dat
= r
->start
;
1206 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1208 dev_err(&pdev
->dev
, "no resource defined for command DMA\n");
1212 info
->drcmr_cmd
= r
->start
;
1214 irq
= platform_get_irq(pdev
, 0);
1216 dev_err(&pdev
->dev
, "no IRQ resource defined\n");
1221 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1223 dev_err(&pdev
->dev
, "no IO memory resource defined\n");
1228 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
1230 dev_err(&pdev
->dev
, "failed to request memory resource\n");
1235 info
->mmio_base
= ioremap(r
->start
, resource_size(r
));
1236 if (info
->mmio_base
== NULL
) {
1237 dev_err(&pdev
->dev
, "ioremap() failed\n");
1241 info
->mmio_phys
= r
->start
;
1243 ret
= pxa3xx_nand_init_buff(info
);
1247 /* initialize all interrupts to be disabled */
1248 disable_int(info
, NDSR_MASK
);
1250 ret
= request_irq(irq
, pxa3xx_nand_irq
, IRQF_DISABLED
,
1253 dev_err(&pdev
->dev
, "failed to request IRQ\n");
1257 ret
= pxa3xx_nand_detect_flash(info
, pdata
);
1259 dev_err(&pdev
->dev
, "failed to detect flash\n");
1264 pxa3xx_nand_init_mtd(mtd
, info
);
1266 platform_set_drvdata(pdev
, mtd
);
1268 if (nand_scan(mtd
, 1)) {
1269 dev_err(&pdev
->dev
, "failed to scan nand\n");
1274 return add_mtd_partitions(mtd
, pdata
->parts
, pdata
->nr_parts
);
1277 free_irq(irq
, info
);
1280 pxa_free_dma(info
->data_dma_ch
);
1281 dma_free_coherent(&pdev
->dev
, info
->data_buff_size
,
1282 info
->data_buff
, info
->data_buff_phys
);
1284 kfree(info
->data_buff
);
1286 iounmap(info
->mmio_base
);
1288 release_mem_region(r
->start
, resource_size(r
));
1290 clk_disable(info
->clk
);
1297 static int pxa3xx_nand_remove(struct platform_device
*pdev
)
1299 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1300 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1304 platform_set_drvdata(pdev
, NULL
);
1306 del_mtd_device(mtd
);
1307 del_mtd_partitions(mtd
);
1308 irq
= platform_get_irq(pdev
, 0);
1310 free_irq(irq
, info
);
1312 pxa_free_dma(info
->data_dma_ch
);
1313 dma_free_writecombine(&pdev
->dev
, info
->data_buff_size
,
1314 info
->data_buff
, info
->data_buff_phys
);
1316 kfree(info
->data_buff
);
1318 iounmap(info
->mmio_base
);
1319 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1320 release_mem_region(r
->start
, resource_size(r
));
1322 clk_disable(info
->clk
);
1330 static int pxa3xx_nand_suspend(struct platform_device
*pdev
, pm_message_t state
)
1332 struct mtd_info
*mtd
= (struct mtd_info
*)platform_get_drvdata(pdev
);
1333 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1335 if (info
->state
!= STATE_READY
) {
1336 dev_err(&pdev
->dev
, "driver busy, state = %d\n", info
->state
);
1343 static int pxa3xx_nand_resume(struct platform_device
*pdev
)
1345 struct mtd_info
*mtd
= (struct mtd_info
*)platform_get_drvdata(pdev
);
1346 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1348 clk_enable(info
->clk
);
1350 return pxa3xx_nand_config_flash(info
, info
->flash_info
);
1353 #define pxa3xx_nand_suspend NULL
1354 #define pxa3xx_nand_resume NULL
1357 static struct platform_driver pxa3xx_nand_driver
= {
1359 .name
= "pxa3xx-nand",
1361 .probe
= pxa3xx_nand_probe
,
1362 .remove
= pxa3xx_nand_remove
,
1363 .suspend
= pxa3xx_nand_suspend
,
1364 .resume
= pxa3xx_nand_resume
,
1367 static int __init
pxa3xx_nand_init(void)
1369 return platform_driver_register(&pxa3xx_nand_driver
);
1371 module_init(pxa3xx_nand_init
);
1373 static void __exit
pxa3xx_nand_exit(void)
1375 platform_driver_unregister(&pxa3xx_nand_driver
);
1377 module_exit(pxa3xx_nand_exit
);
1379 MODULE_LICENSE("GPL");
1380 MODULE_DESCRIPTION("PXA3xx NAND controller driver");