1 /* linux/drivers/mtd/nand/s3c2410.c
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Samsung S3C2410/S3C240 NAND driver
10 * 21-Sep-2004 BJD Initial version
11 * 23-Sep-2004 BJD Mulitple device support
12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
16 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
20 * 20-Oct-2005 BJD Fix timing calculation bug
21 * 14-Jan-2006 BJD Allow clock to be stopped when idle
23 * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
63 #include <asm/arch/regs-nand.h>
64 #include <asm/arch/nand.h>
66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67 static int hardware_ecc
= 1;
69 static int hardware_ecc
= 0;
72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73 static int clock_stop
= 1;
75 static const int clock_stop
= 0;
79 /* new oob placement block for use with hardware ecc generation
82 static struct nand_ecclayout nand_hw_eccoob
= {
88 /* controller and mtd information */
90 struct s3c2410_nand_info
;
92 struct s3c2410_nand_mtd
{
94 struct nand_chip chip
;
95 struct s3c2410_nand_set
*set
;
96 struct s3c2410_nand_info
*info
;
100 /* overview of the s3c2410 nand state */
102 struct s3c2410_nand_info
{
104 struct nand_hw_control controller
;
105 struct s3c2410_nand_mtd
*mtds
;
106 struct s3c2410_platform_nand
*platform
;
109 struct device
*device
;
110 struct resource
*area
;
115 unsigned char is_s3c2440
;
118 /* conversion functions */
120 static struct s3c2410_nand_mtd
*s3c2410_nand_mtd_toours(struct mtd_info
*mtd
)
122 return container_of(mtd
, struct s3c2410_nand_mtd
, mtd
);
125 static struct s3c2410_nand_info
*s3c2410_nand_mtd_toinfo(struct mtd_info
*mtd
)
127 return s3c2410_nand_mtd_toours(mtd
)->info
;
130 static struct s3c2410_nand_info
*to_nand_info(struct platform_device
*dev
)
132 return platform_get_drvdata(dev
);
135 static struct s3c2410_platform_nand
*to_nand_plat(struct platform_device
*dev
)
137 return dev
->dev
.platform_data
;
140 static inline int allow_clk_stop(struct s3c2410_nand_info
*info
)
145 /* timing calculations */
147 #define NS_IN_KHZ 1000000
149 static int s3c2410_nand_calc_rate(int wanted
, unsigned long clk
, int max
)
153 result
= (wanted
* clk
) / NS_IN_KHZ
;
156 pr_debug("result %d from %ld, %d\n", result
, clk
, wanted
);
159 printk("%d ns is too big for current clock rate %ld\n", wanted
, clk
);
169 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
171 /* controller setup */
173 static int s3c2410_nand_inithw(struct s3c2410_nand_info
*info
, struct platform_device
*pdev
)
175 struct s3c2410_platform_nand
*plat
= to_nand_plat(pdev
);
176 unsigned long clkrate
= clk_get_rate(info
->clk
);
177 int tacls
, twrph0
, twrph1
;
180 /* calculate the timing information for the controller */
182 clkrate
/= 1000; /* turn clock into kHz for ease of use */
185 tacls
= s3c2410_nand_calc_rate(plat
->tacls
, clkrate
, 4);
186 twrph0
= s3c2410_nand_calc_rate(plat
->twrph0
, clkrate
, 8);
187 twrph1
= s3c2410_nand_calc_rate(plat
->twrph1
, clkrate
, 8);
189 /* default timings */
195 if (tacls
< 0 || twrph0
< 0 || twrph1
< 0) {
196 dev_err(info
->device
, "cannot get suitable timings\n");
200 dev_info(info
->device
, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
201 tacls
, to_ns(tacls
, clkrate
), twrph0
, to_ns(twrph0
, clkrate
), twrph1
, to_ns(twrph1
, clkrate
));
203 if (!info
->is_s3c2440
) {
204 cfg
= S3C2410_NFCONF_EN
;
205 cfg
|= S3C2410_NFCONF_TACLS(tacls
- 1);
206 cfg
|= S3C2410_NFCONF_TWRPH0(twrph0
- 1);
207 cfg
|= S3C2410_NFCONF_TWRPH1(twrph1
- 1);
209 cfg
= S3C2440_NFCONF_TACLS(tacls
- 1);
210 cfg
|= S3C2440_NFCONF_TWRPH0(twrph0
- 1);
211 cfg
|= S3C2440_NFCONF_TWRPH1(twrph1
- 1);
213 /* enable the controller and de-assert nFCE */
215 writel(S3C2440_NFCONT_ENABLE
| S3C2440_NFCONT_ENABLE
,
216 info
->regs
+ S3C2440_NFCONT
);
219 dev_dbg(info
->device
, "NF_CONF is 0x%lx\n", cfg
);
221 writel(cfg
, info
->regs
+ S3C2410_NFCONF
);
227 static void s3c2410_nand_select_chip(struct mtd_info
*mtd
, int chip
)
229 struct s3c2410_nand_info
*info
;
230 struct s3c2410_nand_mtd
*nmtd
;
231 struct nand_chip
*this = mtd
->priv
;
239 bit
= (info
->is_s3c2440
) ? S3C2440_NFCONT_nFCE
: S3C2410_NFCONF_nFCE
;
240 reg
= info
->regs
+ ((info
->is_s3c2440
) ? S3C2440_NFCONT
: S3C2410_NFCONF
);
242 if (chip
!= -1 && allow_clk_stop(info
))
243 clk_enable(info
->clk
);
250 if (nmtd
->set
!= NULL
&& chip
> nmtd
->set
->nr_chips
) {
251 dev_err(info
->device
, "invalid chip %d\n", chip
);
255 if (info
->platform
!= NULL
) {
256 if (info
->platform
->select_chip
!= NULL
)
257 (info
->platform
->select_chip
) (nmtd
->set
, chip
);
265 if (chip
== -1 && allow_clk_stop(info
))
266 clk_disable(info
->clk
);
269 /* s3c2410_nand_hwcontrol
271 * Issue command and address cycles to the chip
274 static void s3c2410_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
277 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
279 if (cmd
== NAND_CMD_NONE
)
283 writeb(cmd
, info
->regs
+ S3C2410_NFCMD
);
285 writeb(cmd
, info
->regs
+ S3C2410_NFADDR
);
288 /* command and control functions */
290 static void s3c2440_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
293 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
295 if (cmd
== NAND_CMD_NONE
)
299 writeb(cmd
, info
->regs
+ S3C2440_NFCMD
);
301 writeb(cmd
, info
->regs
+ S3C2440_NFADDR
);
304 /* s3c2410_nand_devready()
306 * returns 0 if the nand is busy, 1 if it is ready
309 static int s3c2410_nand_devready(struct mtd_info
*mtd
)
311 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
313 if (info
->is_s3c2440
)
314 return readb(info
->regs
+ S3C2440_NFSTAT
) & S3C2440_NFSTAT_READY
;
315 return readb(info
->regs
+ S3C2410_NFSTAT
) & S3C2410_NFSTAT_BUSY
;
318 /* ECC handling functions */
320 static int s3c2410_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
, u_char
*read_ecc
, u_char
*calc_ecc
)
322 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd
, dat
, read_ecc
, calc_ecc
);
324 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
325 read_ecc
[0], read_ecc
[1], read_ecc
[2], calc_ecc
[0], calc_ecc
[1], calc_ecc
[2]);
327 if (read_ecc
[0] == calc_ecc
[0] && read_ecc
[1] == calc_ecc
[1] && read_ecc
[2] == calc_ecc
[2])
330 /* we curently have no method for correcting the error */
337 * These allow the s3c2410 and s3c2440 to use the controller's ECC
338 * generator block to ECC the data as it passes through]
341 static void s3c2410_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
343 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
346 ctrl
= readl(info
->regs
+ S3C2410_NFCONF
);
347 ctrl
|= S3C2410_NFCONF_INITECC
;
348 writel(ctrl
, info
->regs
+ S3C2410_NFCONF
);
351 static void s3c2440_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
353 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
356 ctrl
= readl(info
->regs
+ S3C2440_NFCONT
);
357 writel(ctrl
| S3C2440_NFCONT_INITECC
, info
->regs
+ S3C2440_NFCONT
);
360 static int s3c2410_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
, u_char
*ecc_code
)
362 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
364 ecc_code
[0] = readb(info
->regs
+ S3C2410_NFECC
+ 0);
365 ecc_code
[1] = readb(info
->regs
+ S3C2410_NFECC
+ 1);
366 ecc_code
[2] = readb(info
->regs
+ S3C2410_NFECC
+ 2);
368 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code
[0], ecc_code
[1], ecc_code
[2]);
373 static int s3c2440_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
, u_char
*ecc_code
)
375 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
376 unsigned long ecc
= readl(info
->regs
+ S3C2440_NFMECC0
);
379 ecc_code
[1] = ecc
>> 8;
380 ecc_code
[2] = ecc
>> 16;
382 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code
[0], ecc_code
[1], ecc_code
[2]);
387 /* over-ride the standard functions for a little more speed. We can
388 * use read/write block to move the data buffers to/from the controller
391 static void s3c2410_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
393 struct nand_chip
*this = mtd
->priv
;
394 readsb(this->IO_ADDR_R
, buf
, len
);
397 static void s3c2410_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
399 struct nand_chip
*this = mtd
->priv
;
400 writesb(this->IO_ADDR_W
, buf
, len
);
403 /* device management functions */
405 static int s3c2410_nand_remove(struct platform_device
*pdev
)
407 struct s3c2410_nand_info
*info
= to_nand_info(pdev
);
409 platform_set_drvdata(pdev
, NULL
);
414 /* first thing we need to do is release all our mtds
415 * and their partitions, then go through freeing the
419 if (info
->mtds
!= NULL
) {
420 struct s3c2410_nand_mtd
*ptr
= info
->mtds
;
423 for (mtdno
= 0; mtdno
< info
->mtd_count
; mtdno
++, ptr
++) {
424 pr_debug("releasing mtd %d (%p)\n", mtdno
, ptr
);
425 nand_release(&ptr
->mtd
);
431 /* free the common resources */
433 if (info
->clk
!= NULL
&& !IS_ERR(info
->clk
)) {
434 if (!allow_clk_stop(info
))
435 clk_disable(info
->clk
);
439 if (info
->regs
!= NULL
) {
444 if (info
->area
!= NULL
) {
445 release_resource(info
->area
);
455 #ifdef CONFIG_MTD_PARTITIONS
456 static int s3c2410_nand_add_partition(struct s3c2410_nand_info
*info
,
457 struct s3c2410_nand_mtd
*mtd
,
458 struct s3c2410_nand_set
*set
)
461 return add_mtd_device(&mtd
->mtd
);
463 if (set
->nr_partitions
> 0 && set
->partitions
!= NULL
) {
464 return add_mtd_partitions(&mtd
->mtd
, set
->partitions
, set
->nr_partitions
);
467 return add_mtd_device(&mtd
->mtd
);
470 static int s3c2410_nand_add_partition(struct s3c2410_nand_info
*info
,
471 struct s3c2410_nand_mtd
*mtd
,
472 struct s3c2410_nand_set
*set
)
474 return add_mtd_device(&mtd
->mtd
);
478 /* s3c2410_nand_init_chip
480 * init a single instance of an chip
483 static void s3c2410_nand_init_chip(struct s3c2410_nand_info
*info
,
484 struct s3c2410_nand_mtd
*nmtd
,
485 struct s3c2410_nand_set
*set
)
487 struct nand_chip
*chip
= &nmtd
->chip
;
489 chip
->IO_ADDR_R
= info
->regs
+ S3C2410_NFDATA
;
490 chip
->IO_ADDR_W
= info
->regs
+ S3C2410_NFDATA
;
491 chip
->cmd_ctrl
= s3c2410_nand_hwcontrol
;
492 chip
->dev_ready
= s3c2410_nand_devready
;
493 chip
->write_buf
= s3c2410_nand_write_buf
;
494 chip
->read_buf
= s3c2410_nand_read_buf
;
495 chip
->select_chip
= s3c2410_nand_select_chip
;
496 chip
->chip_delay
= 50;
499 chip
->controller
= &info
->controller
;
501 if (info
->is_s3c2440
) {
502 chip
->IO_ADDR_R
= info
->regs
+ S3C2440_NFDATA
;
503 chip
->IO_ADDR_W
= info
->regs
+ S3C2440_NFDATA
;
504 chip
->cmd_ctrl
= s3c2440_nand_hwcontrol
;
508 nmtd
->mtd
.priv
= chip
;
509 nmtd
->mtd
.owner
= THIS_MODULE
;
513 chip
->ecc
.correct
= s3c2410_nand_correct_data
;
514 chip
->ecc
.hwctl
= s3c2410_nand_enable_hwecc
;
515 chip
->ecc
.calculate
= s3c2410_nand_calculate_ecc
;
516 chip
->ecc
.mode
= NAND_ECC_HW
;
517 chip
->ecc
.size
= 512;
519 chip
->ecc
.layout
= &nand_hw_eccoob
;
521 if (info
->is_s3c2440
) {
522 chip
->ecc
.hwctl
= s3c2440_nand_enable_hwecc
;
523 chip
->ecc
.calculate
= s3c2440_nand_calculate_ecc
;
526 chip
->ecc
.mode
= NAND_ECC_SOFT
;
530 /* s3c2410_nand_probe
532 * called by device layer when it finds a device matching
533 * one our driver can handled. This code checks to see if
534 * it can allocate all necessary resources then calls the
535 * nand layer to look for devices
538 static int s3c24xx_nand_probe(struct platform_device
*pdev
, int is_s3c2440
)
540 struct s3c2410_platform_nand
*plat
= to_nand_plat(pdev
);
541 struct s3c2410_nand_info
*info
;
542 struct s3c2410_nand_mtd
*nmtd
;
543 struct s3c2410_nand_set
*sets
;
544 struct resource
*res
;
550 pr_debug("s3c2410_nand_probe(%p)\n", pdev
);
552 info
= kmalloc(sizeof(*info
), GFP_KERNEL
);
554 dev_err(&pdev
->dev
, "no memory for flash info\n");
559 memzero(info
, sizeof(*info
));
560 platform_set_drvdata(pdev
, info
);
562 spin_lock_init(&info
->controller
.lock
);
563 init_waitqueue_head(&info
->controller
.wq
);
565 /* get the clock source and enable it */
567 info
->clk
= clk_get(&pdev
->dev
, "nand");
568 if (IS_ERR(info
->clk
)) {
569 dev_err(&pdev
->dev
, "failed to get clock");
574 clk_enable(info
->clk
);
576 /* allocate and map the resource */
578 /* currently we assume we have the one resource */
579 res
= pdev
->resource
;
580 size
= res
->end
- res
->start
+ 1;
582 info
->area
= request_mem_region(res
->start
, size
, pdev
->name
);
584 if (info
->area
== NULL
) {
585 dev_err(&pdev
->dev
, "cannot reserve register region\n");
590 info
->device
= &pdev
->dev
;
591 info
->platform
= plat
;
592 info
->regs
= ioremap(res
->start
, size
);
593 info
->is_s3c2440
= is_s3c2440
;
595 if (info
->regs
== NULL
) {
596 dev_err(&pdev
->dev
, "cannot reserve register region\n");
601 dev_dbg(&pdev
->dev
, "mapped registers at %p\n", info
->regs
);
603 /* initialise the hardware */
605 err
= s3c2410_nand_inithw(info
, pdev
);
609 sets
= (plat
!= NULL
) ? plat
->sets
: NULL
;
610 nr_sets
= (plat
!= NULL
) ? plat
->nr_sets
: 1;
612 info
->mtd_count
= nr_sets
;
614 /* allocate our information */
616 size
= nr_sets
* sizeof(*info
->mtds
);
617 info
->mtds
= kmalloc(size
, GFP_KERNEL
);
618 if (info
->mtds
== NULL
) {
619 dev_err(&pdev
->dev
, "failed to allocate mtd storage\n");
624 memzero(info
->mtds
, size
);
626 /* initialise all possible chips */
630 for (setno
= 0; setno
< nr_sets
; setno
++, nmtd
++) {
631 pr_debug("initialising set %d (%p, info %p)\n", setno
, nmtd
, info
);
633 s3c2410_nand_init_chip(info
, nmtd
, sets
);
635 nmtd
->scan_res
= nand_scan(&nmtd
->mtd
, (sets
) ? sets
->nr_chips
: 1);
637 if (nmtd
->scan_res
== 0) {
638 s3c2410_nand_add_partition(info
, nmtd
, sets
);
645 if (allow_clk_stop(info
)) {
646 dev_info(&pdev
->dev
, "clock idle support enabled\n");
647 clk_disable(info
->clk
);
650 pr_debug("initialised ok\n");
654 s3c2410_nand_remove(pdev
);
664 static int s3c24xx_nand_suspend(struct platform_device
*dev
, pm_message_t pm
)
666 struct s3c2410_nand_info
*info
= platform_get_drvdata(dev
);
669 if (!allow_clk_stop(info
))
670 clk_disable(info
->clk
);
676 static int s3c24xx_nand_resume(struct platform_device
*dev
)
678 struct s3c2410_nand_info
*info
= platform_get_drvdata(dev
);
681 clk_enable(info
->clk
);
682 s3c2410_nand_inithw(info
, dev
);
684 if (allow_clk_stop(info
))
685 clk_disable(info
->clk
);
692 #define s3c24xx_nand_suspend NULL
693 #define s3c24xx_nand_resume NULL
696 /* driver device registration */
698 static int s3c2410_nand_probe(struct platform_device
*dev
)
700 return s3c24xx_nand_probe(dev
, 0);
703 static int s3c2440_nand_probe(struct platform_device
*dev
)
705 return s3c24xx_nand_probe(dev
, 1);
708 static struct platform_driver s3c2410_nand_driver
= {
709 .probe
= s3c2410_nand_probe
,
710 .remove
= s3c2410_nand_remove
,
711 .suspend
= s3c24xx_nand_suspend
,
712 .resume
= s3c24xx_nand_resume
,
714 .name
= "s3c2410-nand",
715 .owner
= THIS_MODULE
,
719 static struct platform_driver s3c2440_nand_driver
= {
720 .probe
= s3c2440_nand_probe
,
721 .remove
= s3c2410_nand_remove
,
722 .suspend
= s3c24xx_nand_suspend
,
723 .resume
= s3c24xx_nand_resume
,
725 .name
= "s3c2440-nand",
726 .owner
= THIS_MODULE
,
730 static int __init
s3c2410_nand_init(void)
732 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
734 platform_driver_register(&s3c2440_nand_driver
);
735 return platform_driver_register(&s3c2410_nand_driver
);
738 static void __exit
s3c2410_nand_exit(void)
740 platform_driver_unregister(&s3c2440_nand_driver
);
741 platform_driver_unregister(&s3c2410_nand_driver
);
744 module_init(s3c2410_nand_init
);
745 module_exit(s3c2410_nand_exit
);
747 MODULE_LICENSE("GPL");
748 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
749 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");