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Merge branch 'master' into upstream
[deliverable/linux.git] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Samsung S3C2410/S3C240 NAND driver
8 *
9 * Changelog:
10 * 21-Sep-2004 BJD Initial version
11 * 23-Sep-2004 BJD Mulitple device support
12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
16 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
20 * 20-Oct-2005 BJD Fix timing calculation bug
21 * 14-Jan-2006 BJD Allow clock to be stopped when idle
22 *
23 * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/arch/regs-nand.h>
64 #include <asm/arch/nand.h>
65
66 #define PFX "s3c2410-nand: "
67
68 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
69 static int hardware_ecc = 1;
70 #else
71 static int hardware_ecc = 0;
72 #endif
73
74 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
75 static int clock_stop = 1;
76 #else
77 static const int clock_stop = 0;
78 #endif
79
80
81 /* new oob placement block for use with hardware ecc generation
82 */
83
84 static struct nand_ecclayout nand_hw_eccoob = {
85 .eccbytes = 3,
86 .eccpos = {0, 1, 2},
87 .oobfree = {{8, 8}}
88 };
89
90 /* controller and mtd information */
91
92 struct s3c2410_nand_info;
93
94 struct s3c2410_nand_mtd {
95 struct mtd_info mtd;
96 struct nand_chip chip;
97 struct s3c2410_nand_set *set;
98 struct s3c2410_nand_info *info;
99 int scan_res;
100 };
101
102 /* overview of the s3c2410 nand state */
103
104 struct s3c2410_nand_info {
105 /* mtd info */
106 struct nand_hw_control controller;
107 struct s3c2410_nand_mtd *mtds;
108 struct s3c2410_platform_nand *platform;
109
110 /* device info */
111 struct device *device;
112 struct resource *area;
113 struct clk *clk;
114 void __iomem *regs;
115 int mtd_count;
116
117 unsigned char is_s3c2440;
118 };
119
120 /* conversion functions */
121
122 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
123 {
124 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
125 }
126
127 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
128 {
129 return s3c2410_nand_mtd_toours(mtd)->info;
130 }
131
132 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
133 {
134 return platform_get_drvdata(dev);
135 }
136
137 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
138 {
139 return dev->dev.platform_data;
140 }
141
142 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
143 {
144 return clock_stop;
145 }
146
147 /* timing calculations */
148
149 #define NS_IN_KHZ 1000000
150
151 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
152 {
153 int result;
154
155 result = (wanted * clk) / NS_IN_KHZ;
156 result++;
157
158 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
159
160 if (result > max) {
161 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
162 return -1;
163 }
164
165 if (result < 1)
166 result = 1;
167
168 return result;
169 }
170
171 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
172
173 /* controller setup */
174
175 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev)
176 {
177 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
178 unsigned long clkrate = clk_get_rate(info->clk);
179 int tacls, twrph0, twrph1;
180 unsigned long cfg;
181
182 /* calculate the timing information for the controller */
183
184 clkrate /= 1000; /* turn clock into kHz for ease of use */
185
186 if (plat != NULL) {
187 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
188 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
189 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
190 } else {
191 /* default timings */
192 tacls = 4;
193 twrph0 = 8;
194 twrph1 = 8;
195 }
196
197 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
198 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
199 return -EINVAL;
200 }
201
202 printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
203 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
204
205 if (!info->is_s3c2440) {
206 cfg = S3C2410_NFCONF_EN;
207 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
208 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
209 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
210 } else {
211 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
212 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
213 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
214
215 /* enable the controller and de-assert nFCE */
216
217 writel(S3C2440_NFCONT_ENABLE | S3C2440_NFCONT_ENABLE,
218 info->regs + S3C2440_NFCONT);
219 }
220
221 pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
222
223 writel(cfg, info->regs + S3C2410_NFCONF);
224 return 0;
225 }
226
227 /* select chip */
228
229 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
230 {
231 struct s3c2410_nand_info *info;
232 struct s3c2410_nand_mtd *nmtd;
233 struct nand_chip *this = mtd->priv;
234 void __iomem *reg;
235 unsigned long cur;
236 unsigned long bit;
237
238 nmtd = this->priv;
239 info = nmtd->info;
240
241 bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
242 reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF);
243
244 if (chip != -1 && allow_clk_stop(info))
245 clk_enable(info->clk);
246
247 cur = readl(reg);
248
249 if (chip == -1) {
250 cur |= bit;
251 } else {
252 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
253 printk(KERN_ERR PFX "chip %d out of range\n", chip);
254 return;
255 }
256
257 if (info->platform != NULL) {
258 if (info->platform->select_chip != NULL)
259 (info->platform->select_chip) (nmtd->set, chip);
260 }
261
262 cur &= ~bit;
263 }
264
265 writel(cur, reg);
266
267 if (chip == -1 && allow_clk_stop(info))
268 clk_disable(info->clk);
269 }
270
271 /* s3c2410_nand_hwcontrol
272 *
273 * Issue command and address cycles to the chip
274 */
275
276 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
277 unsigned int ctrl)
278 {
279 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
280
281 if (cmd == NAND_CMD_NONE)
282 return;
283
284 if (ctrl & NAND_CLE)
285 writeb(cmd, info->regs + S3C2410_NFCMD);
286 else
287 writeb(cmd, info->regs + S3C2410_NFADDR);
288 }
289
290 /* command and control functions */
291
292 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
293 unsigned int ctrl)
294 {
295 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
296
297 if (cmd == NAND_CMD_NONE)
298 return;
299
300 if (ctrl & NAND_CLE)
301 writeb(cmd, info->regs + S3C2440_NFCMD);
302 else
303 writeb(cmd, info->regs + S3C2440_NFADDR);
304 }
305
306 /* s3c2410_nand_devready()
307 *
308 * returns 0 if the nand is busy, 1 if it is ready
309 */
310
311 static int s3c2410_nand_devready(struct mtd_info *mtd)
312 {
313 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
314
315 if (info->is_s3c2440)
316 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
317 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
318 }
319
320 /* ECC handling functions */
321
322 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
323 {
324 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
325
326 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
327 read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
328
329 if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
330 return 0;
331
332 /* we curently have no method for correcting the error */
333
334 return -1;
335 }
336
337 /* ECC functions
338 *
339 * These allow the s3c2410 and s3c2440 to use the controller's ECC
340 * generator block to ECC the data as it passes through]
341 */
342
343 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
344 {
345 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
346 unsigned long ctrl;
347
348 ctrl = readl(info->regs + S3C2410_NFCONF);
349 ctrl |= S3C2410_NFCONF_INITECC;
350 writel(ctrl, info->regs + S3C2410_NFCONF);
351 }
352
353 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
354 {
355 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
356 unsigned long ctrl;
357
358 ctrl = readl(info->regs + S3C2440_NFCONT);
359 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
360 }
361
362 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
363 {
364 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
365
366 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
367 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
368 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
369
370 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
371
372 return 0;
373 }
374
375 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
376 {
377 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
378 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
379
380 ecc_code[0] = ecc;
381 ecc_code[1] = ecc >> 8;
382 ecc_code[2] = ecc >> 16;
383
384 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
385
386 return 0;
387 }
388
389 /* over-ride the standard functions for a little more speed. We can
390 * use read/write block to move the data buffers to/from the controller
391 */
392
393 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
394 {
395 struct nand_chip *this = mtd->priv;
396 readsb(this->IO_ADDR_R, buf, len);
397 }
398
399 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
400 {
401 struct nand_chip *this = mtd->priv;
402 writesb(this->IO_ADDR_W, buf, len);
403 }
404
405 /* device management functions */
406
407 static int s3c2410_nand_remove(struct platform_device *pdev)
408 {
409 struct s3c2410_nand_info *info = to_nand_info(pdev);
410
411 platform_set_drvdata(pdev, NULL);
412
413 if (info == NULL)
414 return 0;
415
416 /* first thing we need to do is release all our mtds
417 * and their partitions, then go through freeing the
418 * resources used
419 */
420
421 if (info->mtds != NULL) {
422 struct s3c2410_nand_mtd *ptr = info->mtds;
423 int mtdno;
424
425 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
426 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
427 nand_release(&ptr->mtd);
428 }
429
430 kfree(info->mtds);
431 }
432
433 /* free the common resources */
434
435 if (info->clk != NULL && !IS_ERR(info->clk)) {
436 if (!allow_clk_stop(info))
437 clk_disable(info->clk);
438 clk_put(info->clk);
439 }
440
441 if (info->regs != NULL) {
442 iounmap(info->regs);
443 info->regs = NULL;
444 }
445
446 if (info->area != NULL) {
447 release_resource(info->area);
448 kfree(info->area);
449 info->area = NULL;
450 }
451
452 kfree(info);
453
454 return 0;
455 }
456
457 #ifdef CONFIG_MTD_PARTITIONS
458 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
459 struct s3c2410_nand_mtd *mtd,
460 struct s3c2410_nand_set *set)
461 {
462 if (set == NULL)
463 return add_mtd_device(&mtd->mtd);
464
465 if (set->nr_partitions > 0 && set->partitions != NULL) {
466 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
467 }
468
469 return add_mtd_device(&mtd->mtd);
470 }
471 #else
472 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
473 struct s3c2410_nand_mtd *mtd,
474 struct s3c2410_nand_set *set)
475 {
476 return add_mtd_device(&mtd->mtd);
477 }
478 #endif
479
480 /* s3c2410_nand_init_chip
481 *
482 * init a single instance of an chip
483 */
484
485 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
486 struct s3c2410_nand_mtd *nmtd,
487 struct s3c2410_nand_set *set)
488 {
489 struct nand_chip *chip = &nmtd->chip;
490
491 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA;
492 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
493 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
494 chip->dev_ready = s3c2410_nand_devready;
495 chip->write_buf = s3c2410_nand_write_buf;
496 chip->read_buf = s3c2410_nand_read_buf;
497 chip->select_chip = s3c2410_nand_select_chip;
498 chip->chip_delay = 50;
499 chip->priv = nmtd;
500 chip->options = 0;
501 chip->controller = &info->controller;
502
503 if (info->is_s3c2440) {
504 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA;
505 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
506 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
507 }
508
509 nmtd->info = info;
510 nmtd->mtd.priv = chip;
511 nmtd->mtd.owner = THIS_MODULE;
512 nmtd->set = set;
513
514 if (hardware_ecc) {
515 chip->ecc.correct = s3c2410_nand_correct_data;
516 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
517 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
518 chip->ecc.mode = NAND_ECC_HW;
519 chip->ecc.size = 512;
520 chip->ecc.bytes = 3;
521 chip->ecc.layout = &nand_hw_eccoob;
522
523 if (info->is_s3c2440) {
524 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
525 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
526 }
527 } else {
528 chip->ecc.mode = NAND_ECC_SOFT;
529 }
530 }
531
532 /* s3c2410_nand_probe
533 *
534 * called by device layer when it finds a device matching
535 * one our driver can handled. This code checks to see if
536 * it can allocate all necessary resources then calls the
537 * nand layer to look for devices
538 */
539
540 static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
541 {
542 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
543 struct s3c2410_nand_info *info;
544 struct s3c2410_nand_mtd *nmtd;
545 struct s3c2410_nand_set *sets;
546 struct resource *res;
547 int err = 0;
548 int size;
549 int nr_sets;
550 int setno;
551
552 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
553
554 info = kmalloc(sizeof(*info), GFP_KERNEL);
555 if (info == NULL) {
556 dev_err(&pdev->dev, "no memory for flash info\n");
557 err = -ENOMEM;
558 goto exit_error;
559 }
560
561 memzero(info, sizeof(*info));
562 platform_set_drvdata(pdev, info);
563
564 spin_lock_init(&info->controller.lock);
565 init_waitqueue_head(&info->controller.wq);
566
567 /* get the clock source and enable it */
568
569 info->clk = clk_get(&pdev->dev, "nand");
570 if (IS_ERR(info->clk)) {
571 dev_err(&pdev->dev, "failed to get clock");
572 err = -ENOENT;
573 goto exit_error;
574 }
575
576 clk_enable(info->clk);
577
578 /* allocate and map the resource */
579
580 /* currently we assume we have the one resource */
581 res = pdev->resource;
582 size = res->end - res->start + 1;
583
584 info->area = request_mem_region(res->start, size, pdev->name);
585
586 if (info->area == NULL) {
587 dev_err(&pdev->dev, "cannot reserve register region\n");
588 err = -ENOENT;
589 goto exit_error;
590 }
591
592 info->device = &pdev->dev;
593 info->platform = plat;
594 info->regs = ioremap(res->start, size);
595 info->is_s3c2440 = is_s3c2440;
596
597 if (info->regs == NULL) {
598 dev_err(&pdev->dev, "cannot reserve register region\n");
599 err = -EIO;
600 goto exit_error;
601 }
602
603 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
604
605 /* initialise the hardware */
606
607 err = s3c2410_nand_inithw(info, pdev);
608 if (err != 0)
609 goto exit_error;
610
611 sets = (plat != NULL) ? plat->sets : NULL;
612 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
613
614 info->mtd_count = nr_sets;
615
616 /* allocate our information */
617
618 size = nr_sets * sizeof(*info->mtds);
619 info->mtds = kmalloc(size, GFP_KERNEL);
620 if (info->mtds == NULL) {
621 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
622 err = -ENOMEM;
623 goto exit_error;
624 }
625
626 memzero(info->mtds, size);
627
628 /* initialise all possible chips */
629
630 nmtd = info->mtds;
631
632 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
633 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
634
635 s3c2410_nand_init_chip(info, nmtd, sets);
636
637 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
638
639 if (nmtd->scan_res == 0) {
640 s3c2410_nand_add_partition(info, nmtd, sets);
641 }
642
643 if (sets != NULL)
644 sets++;
645 }
646
647 if (allow_clk_stop(info)) {
648 dev_info(&pdev->dev, "clock idle support enabled\n");
649 clk_disable(info->clk);
650 }
651
652 pr_debug("initialised ok\n");
653 return 0;
654
655 exit_error:
656 s3c2410_nand_remove(pdev);
657
658 if (err == 0)
659 err = -EINVAL;
660 return err;
661 }
662
663 /* PM Support */
664 #ifdef CONFIG_PM
665
666 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
667 {
668 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
669
670 if (info) {
671 if (!allow_clk_stop(info))
672 clk_disable(info->clk);
673 }
674
675 return 0;
676 }
677
678 static int s3c24xx_nand_resume(struct platform_device *dev)
679 {
680 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
681
682 if (info) {
683 clk_enable(info->clk);
684 s3c2410_nand_inithw(info, dev);
685
686 if (allow_clk_stop(info))
687 clk_disable(info->clk);
688 }
689
690 return 0;
691 }
692
693 #else
694 #define s3c24xx_nand_suspend NULL
695 #define s3c24xx_nand_resume NULL
696 #endif
697
698 /* driver device registration */
699
700 static int s3c2410_nand_probe(struct platform_device *dev)
701 {
702 return s3c24xx_nand_probe(dev, 0);
703 }
704
705 static int s3c2440_nand_probe(struct platform_device *dev)
706 {
707 return s3c24xx_nand_probe(dev, 1);
708 }
709
710 static struct platform_driver s3c2410_nand_driver = {
711 .probe = s3c2410_nand_probe,
712 .remove = s3c2410_nand_remove,
713 .suspend = s3c24xx_nand_suspend,
714 .resume = s3c24xx_nand_resume,
715 .driver = {
716 .name = "s3c2410-nand",
717 .owner = THIS_MODULE,
718 },
719 };
720
721 static struct platform_driver s3c2440_nand_driver = {
722 .probe = s3c2440_nand_probe,
723 .remove = s3c2410_nand_remove,
724 .suspend = s3c24xx_nand_suspend,
725 .resume = s3c24xx_nand_resume,
726 .driver = {
727 .name = "s3c2440-nand",
728 .owner = THIS_MODULE,
729 },
730 };
731
732 static int __init s3c2410_nand_init(void)
733 {
734 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
735
736 platform_driver_register(&s3c2440_nand_driver);
737 return platform_driver_register(&s3c2410_nand_driver);
738 }
739
740 static void __exit s3c2410_nand_exit(void)
741 {
742 platform_driver_unregister(&s3c2440_nand_driver);
743 platform_driver_unregister(&s3c2410_nand_driver);
744 }
745
746 module_init(s3c2410_nand_init);
747 module_exit(s3c2410_nand_exit);
748
749 MODULE_LICENSE("GPL");
750 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
751 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
Linux kernel - Deliverables
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