2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
28 #include <linux/platform_device.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/mtd/sh_flctl.h>
35 static struct nand_ecclayout flctl_4secc_oob_16
= {
37 .eccpos
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
43 static struct nand_ecclayout flctl_4secc_oob_64
= {
45 .eccpos
= {48, 49, 50, 51, 52, 53, 54, 55, 56, 57},
51 static uint8_t scan_ff_pattern
[] = { 0xff, 0xff };
53 static struct nand_bbt_descr flctl_4secc_smallpage
= {
54 .options
= NAND_BBT_SCAN2NDPAGE
,
57 .pattern
= scan_ff_pattern
,
60 static struct nand_bbt_descr flctl_4secc_largepage
= {
61 .options
= NAND_BBT_SCAN2NDPAGE
,
64 .pattern
= scan_ff_pattern
,
67 static void empty_fifo(struct sh_flctl
*flctl
)
69 writel(0x000c0000, FLINTDMACR(flctl
)); /* FIFO Clear */
70 writel(0x00000000, FLINTDMACR(flctl
)); /* Clear Error flags */
73 static void start_translation(struct sh_flctl
*flctl
)
75 writeb(TRSTRT
, FLTRCR(flctl
));
78 static void timeout_error(struct sh_flctl
*flctl
, const char *str
)
80 dev_err(&flctl
->pdev
->dev
, "Timeout occured in %s\n", str
);
83 static void wait_completion(struct sh_flctl
*flctl
)
85 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
88 if (readb(FLTRCR(flctl
)) & TREND
) {
89 writeb(0x0, FLTRCR(flctl
));
95 timeout_error(flctl
, __func__
);
96 writeb(0x0, FLTRCR(flctl
));
99 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
101 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
105 addr
= page_addr
; /* ERASE1 */
106 } else if (page_addr
!= -1) {
107 /* SEQIN, READ0, etc.. */
108 if (flctl
->page_size
) {
109 addr
= column
& 0x0FFF;
110 addr
|= (page_addr
& 0xff) << 16;
111 addr
|= ((page_addr
>> 8) & 0xff) << 24;
113 if (flctl
->rw_ADRCNT
== ADRCNT2_E
) {
115 addr2
= (page_addr
>> 16) & 0xff;
116 writel(addr2
, FLADR2(flctl
));
120 addr
|= (page_addr
& 0xff) << 8;
121 addr
|= ((page_addr
>> 8) & 0xff) << 16;
122 addr
|= ((page_addr
>> 16) & 0xff) << 24;
125 writel(addr
, FLADR(flctl
));
128 static void wait_rfifo_ready(struct sh_flctl
*flctl
)
130 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
135 val
= readl(FLDTCNTR(flctl
)) >> 16;
140 timeout_error(flctl
, __func__
);
143 static void wait_wfifo_ready(struct sh_flctl
*flctl
)
145 uint32_t len
, timeout
= LOOP_TIMEOUT_MAX
;
149 len
= (readl(FLDTCNTR(flctl
)) >> 16) & 0xFF;
154 timeout_error(flctl
, __func__
);
157 static int wait_recfifo_ready(struct sh_flctl
*flctl
, int sector_number
)
159 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
161 void __iomem
*ecc_reg
[4];
165 memset(checked
, 0, sizeof(checked
));
168 size
= readl(FLDTCNTR(flctl
)) >> 24;
170 return 0; /* success */
172 if (readl(FL4ECCCR(flctl
)) & _4ECCFA
)
173 return 1; /* can't correct */
176 if (!(readl(FL4ECCCR(flctl
)) & _4ECCEND
))
179 /* start error correction */
180 ecc_reg
[0] = FL4ECCRESULT0(flctl
);
181 ecc_reg
[1] = FL4ECCRESULT1(flctl
);
182 ecc_reg
[2] = FL4ECCRESULT2(flctl
);
183 ecc_reg
[3] = FL4ECCRESULT3(flctl
);
185 for (i
= 0; i
< 3; i
++) {
186 data
= readl(ecc_reg
[i
]);
187 if (data
!= INIT_FL4ECCRESULT_VAL
&& !checked
[i
]) {
191 if (flctl
->page_size
)
192 index
= (512 * sector_number
) +
197 org
= flctl
->done_buff
[index
];
198 flctl
->done_buff
[index
] = org
^ (data
& 0xFF);
203 writel(0, FL4ECCCR(flctl
));
206 timeout_error(flctl
, __func__
);
207 return 1; /* timeout */
210 static void wait_wecfifo_ready(struct sh_flctl
*flctl
)
212 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
217 len
= (readl(FLDTCNTR(flctl
)) >> 24) & 0xFF;
222 timeout_error(flctl
, __func__
);
225 static void read_datareg(struct sh_flctl
*flctl
, int offset
)
228 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
230 wait_completion(flctl
);
232 data
= readl(FLDATAR(flctl
));
233 *buf
= le32_to_cpu(data
);
236 static void read_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
239 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
240 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
242 len_4align
= (rlen
+ 3) / 4;
244 for (i
= 0; i
< len_4align
; i
++) {
245 wait_rfifo_ready(flctl
);
246 buf
[i
] = readl(fifo_addr
);
247 buf
[i
] = be32_to_cpu(buf
[i
]);
251 static int read_ecfiforeg(struct sh_flctl
*flctl
, uint8_t *buff
, int sector
)
254 unsigned long *ecc_buf
= (unsigned long *)buff
;
255 void *fifo_addr
= (void *)FLECFIFO(flctl
);
257 for (i
= 0; i
< 4; i
++) {
258 if (wait_recfifo_ready(flctl
, sector
))
260 ecc_buf
[i
] = readl(fifo_addr
);
261 ecc_buf
[i
] = be32_to_cpu(ecc_buf
[i
]);
267 static void write_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
270 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
271 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
273 len_4align
= (rlen
+ 3) / 4;
274 for (i
= 0; i
< len_4align
; i
++) {
275 wait_wfifo_ready(flctl
);
276 writel(cpu_to_be32(data
[i
]), fifo_addr
);
280 static void set_cmd_regs(struct mtd_info
*mtd
, uint32_t cmd
, uint32_t flcmcdr_val
)
282 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
283 uint32_t flcmncr_val
= readl(FLCMNCR(flctl
));
284 uint32_t flcmdcr_val
, addr_len_bytes
= 0;
286 /* Set SNAND bit if page size is 2048byte */
287 if (flctl
->page_size
)
288 flcmncr_val
|= SNAND_E
;
290 flcmncr_val
&= ~SNAND_E
;
292 /* default FLCMDCR val */
293 flcmdcr_val
= DOCMD1_E
| DOADR_E
;
295 /* Set for FLCMDCR */
297 case NAND_CMD_ERASE1
:
298 addr_len_bytes
= flctl
->erase_ADRCNT
;
299 flcmdcr_val
|= DOCMD2_E
;
302 case NAND_CMD_READOOB
:
303 addr_len_bytes
= flctl
->rw_ADRCNT
;
304 flcmdcr_val
|= CDSRC_E
;
307 /* This case is that cmd is READ0 or READ1 or READ00 */
308 flcmdcr_val
&= ~DOADR_E
; /* ONLY execute 1st cmd */
310 case NAND_CMD_PAGEPROG
:
311 addr_len_bytes
= flctl
->rw_ADRCNT
;
312 flcmdcr_val
|= DOCMD2_E
| CDSRC_E
| SELRW
;
314 case NAND_CMD_READID
:
315 flcmncr_val
&= ~SNAND_E
;
316 addr_len_bytes
= ADRCNT_1
;
318 case NAND_CMD_STATUS
:
320 flcmncr_val
&= ~SNAND_E
;
321 flcmdcr_val
&= ~(DOADR_E
| DOSR_E
);
327 /* Set address bytes parameter */
328 flcmdcr_val
|= addr_len_bytes
;
330 /* Now actually write */
331 writel(flcmncr_val
, FLCMNCR(flctl
));
332 writel(flcmdcr_val
, FLCMDCR(flctl
));
333 writel(flcmcdr_val
, FLCMCDR(flctl
));
336 static int flctl_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
337 uint8_t *buf
, int page
)
339 int i
, eccsize
= chip
->ecc
.size
;
340 int eccbytes
= chip
->ecc
.bytes
;
341 int eccsteps
= chip
->ecc
.steps
;
343 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
345 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
346 chip
->read_buf(mtd
, p
, eccsize
);
348 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
349 if (flctl
->hwecc_cant_correct
[i
])
350 mtd
->ecc_stats
.failed
++;
352 mtd
->ecc_stats
.corrected
+= 0;
358 static void flctl_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
361 int i
, eccsize
= chip
->ecc
.size
;
362 int eccbytes
= chip
->ecc
.bytes
;
363 int eccsteps
= chip
->ecc
.steps
;
364 const uint8_t *p
= buf
;
366 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
367 chip
->write_buf(mtd
, p
, eccsize
);
370 static void execmd_read_page_sector(struct mtd_info
*mtd
, int page_addr
)
372 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
373 int sector
, page_sectors
;
375 if (flctl
->page_size
)
380 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
| _4ECCCORRECT
,
383 set_cmd_regs(mtd
, NAND_CMD_READ0
,
384 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
386 for (sector
= 0; sector
< page_sectors
; sector
++) {
390 writel(readl(FLCMDCR(flctl
)) | 1, FLCMDCR(flctl
));
391 writel(page_addr
<< 2 | sector
, FLADR(flctl
));
393 start_translation(flctl
);
394 read_fiforeg(flctl
, 512, 512 * sector
);
396 ret
= read_ecfiforeg(flctl
,
397 &flctl
->done_buff
[mtd
->writesize
+ 16 * sector
],
401 flctl
->hwecc_cant_correct
[sector
] = 1;
403 writel(0x0, FL4ECCCR(flctl
));
404 wait_completion(flctl
);
406 writel(readl(FLCMNCR(flctl
)) & ~(ACM_SACCES_MODE
| _4ECCCORRECT
),
410 static void execmd_read_oob(struct mtd_info
*mtd
, int page_addr
)
412 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
414 set_cmd_regs(mtd
, NAND_CMD_READ0
,
415 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
418 if (flctl
->page_size
) {
420 /* In case that the page size is 2k */
421 for (i
= 0; i
< 16 * 3; i
++)
422 flctl
->done_buff
[i
] = 0xFF;
424 set_addr(mtd
, 3 * 528 + 512, page_addr
);
425 writel(16, FLDTCNTR(flctl
));
427 start_translation(flctl
);
428 read_fiforeg(flctl
, 16, 16 * 3);
429 wait_completion(flctl
);
431 /* In case that the page size is 512b */
432 set_addr(mtd
, 512, page_addr
);
433 writel(16, FLDTCNTR(flctl
));
435 start_translation(flctl
);
436 read_fiforeg(flctl
, 16, 0);
437 wait_completion(flctl
);
441 static void execmd_write_page_sector(struct mtd_info
*mtd
)
443 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
444 int i
, page_addr
= flctl
->seqin_page_addr
;
445 int sector
, page_sectors
;
447 if (flctl
->page_size
)
452 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
, FLCMNCR(flctl
));
454 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
455 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
457 for (sector
= 0; sector
< page_sectors
; sector
++) {
459 writel(readl(FLCMDCR(flctl
)) | 1, FLCMDCR(flctl
));
460 writel(page_addr
<< 2 | sector
, FLADR(flctl
));
462 start_translation(flctl
);
463 write_fiforeg(flctl
, 512, 512 * sector
);
465 for (i
= 0; i
< 4; i
++) {
466 wait_wecfifo_ready(flctl
); /* wait for write ready */
467 writel(0xFFFFFFFF, FLECFIFO(flctl
));
469 wait_completion(flctl
);
472 writel(readl(FLCMNCR(flctl
)) & ~ACM_SACCES_MODE
, FLCMNCR(flctl
));
475 static void execmd_write_oob(struct mtd_info
*mtd
)
477 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
478 int page_addr
= flctl
->seqin_page_addr
;
479 int sector
, page_sectors
;
481 if (flctl
->page_size
) {
489 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
490 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
492 for (; sector
< page_sectors
; sector
++) {
494 set_addr(mtd
, sector
* 528 + 512, page_addr
);
495 writel(16, FLDTCNTR(flctl
)); /* set read size */
497 start_translation(flctl
);
498 write_fiforeg(flctl
, 16, 16 * sector
);
499 wait_completion(flctl
);
503 static void flctl_cmdfunc(struct mtd_info
*mtd
, unsigned int command
,
504 int column
, int page_addr
)
506 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
507 uint32_t read_cmd
= 0;
509 flctl
->read_bytes
= 0;
510 if (command
!= NAND_CMD_PAGEPROG
)
517 /* read page with hwecc */
518 execmd_read_page_sector(mtd
, page_addr
);
522 if (flctl
->page_size
)
523 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
526 set_cmd_regs(mtd
, command
, command
);
528 set_addr(mtd
, 0, page_addr
);
530 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
531 flctl
->index
+= column
;
532 goto read_normal_exit
;
534 case NAND_CMD_READOOB
:
536 /* read page with hwecc */
537 execmd_read_oob(mtd
, page_addr
);
542 if (flctl
->page_size
) {
543 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
545 set_addr(mtd
, mtd
->writesize
, page_addr
);
547 set_cmd_regs(mtd
, command
, command
);
548 set_addr(mtd
, 0, page_addr
);
550 flctl
->read_bytes
= mtd
->oobsize
;
551 goto read_normal_exit
;
553 case NAND_CMD_READID
:
555 set_cmd_regs(mtd
, command
, command
);
558 flctl
->read_bytes
= 4;
559 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
560 start_translation(flctl
);
561 read_datareg(flctl
, 0); /* read and end */
564 case NAND_CMD_ERASE1
:
565 flctl
->erase1_page_addr
= page_addr
;
568 case NAND_CMD_ERASE2
:
569 set_cmd_regs(mtd
, NAND_CMD_ERASE1
,
570 (command
<< 8) | NAND_CMD_ERASE1
);
571 set_addr(mtd
, -1, flctl
->erase1_page_addr
);
572 start_translation(flctl
);
573 wait_completion(flctl
);
577 if (!flctl
->page_size
) {
578 /* output read command */
579 if (column
>= mtd
->writesize
) {
580 column
-= mtd
->writesize
;
581 read_cmd
= NAND_CMD_READOOB
;
582 } else if (column
< 256) {
583 read_cmd
= NAND_CMD_READ0
;
586 read_cmd
= NAND_CMD_READ1
;
589 flctl
->seqin_column
= column
;
590 flctl
->seqin_page_addr
= page_addr
;
591 flctl
->seqin_read_cmd
= read_cmd
;
594 case NAND_CMD_PAGEPROG
:
596 if (!flctl
->page_size
) {
597 set_cmd_regs(mtd
, NAND_CMD_SEQIN
,
598 flctl
->seqin_read_cmd
);
599 set_addr(mtd
, -1, -1);
600 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
601 start_translation(flctl
);
602 wait_completion(flctl
);
605 /* write page with hwecc */
606 if (flctl
->seqin_column
== mtd
->writesize
)
607 execmd_write_oob(mtd
);
608 else if (!flctl
->seqin_column
)
609 execmd_write_page_sector(mtd
);
611 printk(KERN_ERR
"Invalid address !?\n");
614 set_cmd_regs(mtd
, command
, (command
<< 8) | NAND_CMD_SEQIN
);
615 set_addr(mtd
, flctl
->seqin_column
, flctl
->seqin_page_addr
);
616 writel(flctl
->index
, FLDTCNTR(flctl
)); /* set write size */
617 start_translation(flctl
);
618 write_fiforeg(flctl
, flctl
->index
, 0);
619 wait_completion(flctl
);
622 case NAND_CMD_STATUS
:
623 set_cmd_regs(mtd
, command
, command
);
624 set_addr(mtd
, -1, -1);
626 flctl
->read_bytes
= 1;
627 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
628 start_translation(flctl
);
629 read_datareg(flctl
, 0); /* read and end */
633 set_cmd_regs(mtd
, command
, command
);
634 set_addr(mtd
, -1, -1);
636 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
637 start_translation(flctl
);
638 wait_completion(flctl
);
647 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
648 start_translation(flctl
);
649 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
650 wait_completion(flctl
);
654 static void flctl_select_chip(struct mtd_info
*mtd
, int chipnr
)
656 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
657 uint32_t flcmncr_val
= readl(FLCMNCR(flctl
));
661 flcmncr_val
&= ~CE0_ENABLE
;
662 writel(flcmncr_val
, FLCMNCR(flctl
));
665 flcmncr_val
|= CE0_ENABLE
;
666 writel(flcmncr_val
, FLCMNCR(flctl
));
673 static void flctl_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
675 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
676 int i
, index
= flctl
->index
;
678 for (i
= 0; i
< len
; i
++)
679 flctl
->done_buff
[index
+ i
] = buf
[i
];
683 static uint8_t flctl_read_byte(struct mtd_info
*mtd
)
685 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
686 int index
= flctl
->index
;
689 data
= flctl
->done_buff
[index
];
694 static void flctl_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
698 for (i
= 0; i
< len
; i
++)
699 buf
[i
] = flctl_read_byte(mtd
);
702 static int flctl_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
706 for (i
= 0; i
< len
; i
++)
707 if (buf
[i
] != flctl_read_byte(mtd
))
712 static void flctl_register_init(struct sh_flctl
*flctl
, unsigned long val
)
714 writel(val
, FLCMNCR(flctl
));
717 static int flctl_chip_init_tail(struct mtd_info
*mtd
)
719 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
720 struct nand_chip
*chip
= &flctl
->chip
;
722 if (mtd
->writesize
== 512) {
723 flctl
->page_size
= 0;
724 if (chip
->chipsize
> (32 << 20)) {
726 flctl
->rw_ADRCNT
= ADRCNT_4
;
727 flctl
->erase_ADRCNT
= ADRCNT_3
;
728 } else if (chip
->chipsize
> (2 << 16)) {
730 flctl
->rw_ADRCNT
= ADRCNT_3
;
731 flctl
->erase_ADRCNT
= ADRCNT_2
;
733 flctl
->rw_ADRCNT
= ADRCNT_2
;
734 flctl
->erase_ADRCNT
= ADRCNT_1
;
737 flctl
->page_size
= 1;
738 if (chip
->chipsize
> (128 << 20)) {
740 flctl
->rw_ADRCNT
= ADRCNT2_E
;
741 flctl
->erase_ADRCNT
= ADRCNT_3
;
742 } else if (chip
->chipsize
> (8 << 16)) {
744 flctl
->rw_ADRCNT
= ADRCNT_4
;
745 flctl
->erase_ADRCNT
= ADRCNT_2
;
747 flctl
->rw_ADRCNT
= ADRCNT_3
;
748 flctl
->erase_ADRCNT
= ADRCNT_1
;
753 if (mtd
->writesize
== 512) {
754 chip
->ecc
.layout
= &flctl_4secc_oob_16
;
755 chip
->badblock_pattern
= &flctl_4secc_smallpage
;
757 chip
->ecc
.layout
= &flctl_4secc_oob_64
;
758 chip
->badblock_pattern
= &flctl_4secc_largepage
;
761 chip
->ecc
.size
= 512;
762 chip
->ecc
.bytes
= 10;
763 chip
->ecc
.read_page
= flctl_read_page_hwecc
;
764 chip
->ecc
.write_page
= flctl_write_page_hwecc
;
765 chip
->ecc
.mode
= NAND_ECC_HW
;
767 /* 4 symbols ECC enabled */
768 writel(readl(FLCMNCR(flctl
)) | _4ECCEN
| ECCPOS2
| ECCPOS_02
,
771 chip
->ecc
.mode
= NAND_ECC_SOFT
;
777 static int __devinit
flctl_probe(struct platform_device
*pdev
)
779 struct resource
*res
;
780 struct sh_flctl
*flctl
;
781 struct mtd_info
*flctl_mtd
;
782 struct nand_chip
*nand
;
783 struct sh_flctl_platform_data
*pdata
;
786 pdata
= pdev
->dev
.platform_data
;
788 dev_err(&pdev
->dev
, "no platform data defined\n");
792 flctl
= kzalloc(sizeof(struct sh_flctl
), GFP_KERNEL
);
794 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
798 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
800 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
804 flctl
->reg
= ioremap(res
->start
, resource_size(res
));
805 if (flctl
->reg
== NULL
) {
806 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
810 platform_set_drvdata(pdev
, flctl
);
811 flctl_mtd
= &flctl
->mtd
;
813 flctl_mtd
->priv
= nand
;
815 flctl
->hwecc
= pdata
->has_hwecc
;
817 flctl_register_init(flctl
, pdata
->flcmncr_val
);
819 nand
->options
= NAND_NO_AUTOINCR
;
821 /* Set address of hardware control function */
822 /* 20 us command delay time */
823 nand
->chip_delay
= 20;
825 nand
->read_byte
= flctl_read_byte
;
826 nand
->write_buf
= flctl_write_buf
;
827 nand
->read_buf
= flctl_read_buf
;
828 nand
->verify_buf
= flctl_verify_buf
;
829 nand
->select_chip
= flctl_select_chip
;
830 nand
->cmdfunc
= flctl_cmdfunc
;
832 ret
= nand_scan_ident(flctl_mtd
, 1);
836 ret
= flctl_chip_init_tail(flctl_mtd
);
840 ret
= nand_scan_tail(flctl_mtd
);
844 add_mtd_partitions(flctl_mtd
, pdata
->parts
, pdata
->nr_parts
);
853 static int __devexit
flctl_remove(struct platform_device
*pdev
)
855 struct sh_flctl
*flctl
= platform_get_drvdata(pdev
);
857 nand_release(&flctl
->mtd
);
863 static struct platform_driver flctl_driver
= {
864 .remove
= flctl_remove
,
867 .owner
= THIS_MODULE
,
871 static int __init
flctl_nand_init(void)
873 return platform_driver_probe(&flctl_driver
, flctl_probe
);
876 static void __exit
flctl_nand_cleanup(void)
878 platform_driver_unregister(&flctl_driver
);
881 module_init(flctl_nand_init
);
882 module_exit(flctl_nand_cleanup
);
884 MODULE_LICENSE("GPL");
885 MODULE_AUTHOR("Yoshihiro Shimoda");
886 MODULE_DESCRIPTION("SuperH FLCTL driver");
887 MODULE_ALIAS("platform:sh_flctl");