2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/mtd/sh_flctl.h>
38 static struct nand_ecclayout flctl_4secc_oob_16
= {
40 .eccpos
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
46 static struct nand_ecclayout flctl_4secc_oob_64
= {
49 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
50 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
51 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
52 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 },
54 {.offset
= 2, .length
= 4},
55 {.offset
= 16, .length
= 6},
56 {.offset
= 32, .length
= 6},
57 {.offset
= 48, .length
= 6} },
60 static uint8_t scan_ff_pattern
[] = { 0xff, 0xff };
62 static struct nand_bbt_descr flctl_4secc_smallpage
= {
63 .options
= NAND_BBT_SCAN2NDPAGE
,
66 .pattern
= scan_ff_pattern
,
69 static struct nand_bbt_descr flctl_4secc_largepage
= {
70 .options
= NAND_BBT_SCAN2NDPAGE
,
73 .pattern
= scan_ff_pattern
,
76 static void empty_fifo(struct sh_flctl
*flctl
)
78 writel(flctl
->flintdmacr_base
| AC1CLR
| AC0CLR
, FLINTDMACR(flctl
));
79 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
82 static void start_translation(struct sh_flctl
*flctl
)
84 writeb(TRSTRT
, FLTRCR(flctl
));
87 static void timeout_error(struct sh_flctl
*flctl
, const char *str
)
89 dev_err(&flctl
->pdev
->dev
, "Timeout occurred in %s\n", str
);
92 static void wait_completion(struct sh_flctl
*flctl
)
94 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
97 if (readb(FLTRCR(flctl
)) & TREND
) {
98 writeb(0x0, FLTRCR(flctl
));
104 timeout_error(flctl
, __func__
);
105 writeb(0x0, FLTRCR(flctl
));
108 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
110 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
114 addr
= page_addr
; /* ERASE1 */
115 } else if (page_addr
!= -1) {
116 /* SEQIN, READ0, etc.. */
117 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
119 if (flctl
->page_size
) {
120 addr
= column
& 0x0FFF;
121 addr
|= (page_addr
& 0xff) << 16;
122 addr
|= ((page_addr
>> 8) & 0xff) << 24;
124 if (flctl
->rw_ADRCNT
== ADRCNT2_E
) {
126 addr2
= (page_addr
>> 16) & 0xff;
127 writel(addr2
, FLADR2(flctl
));
131 addr
|= (page_addr
& 0xff) << 8;
132 addr
|= ((page_addr
>> 8) & 0xff) << 16;
133 addr
|= ((page_addr
>> 16) & 0xff) << 24;
136 writel(addr
, FLADR(flctl
));
139 static void wait_rfifo_ready(struct sh_flctl
*flctl
)
141 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
146 val
= readl(FLDTCNTR(flctl
)) >> 16;
151 timeout_error(flctl
, __func__
);
154 static void wait_wfifo_ready(struct sh_flctl
*flctl
)
156 uint32_t len
, timeout
= LOOP_TIMEOUT_MAX
;
160 len
= (readl(FLDTCNTR(flctl
)) >> 16) & 0xFF;
165 timeout_error(flctl
, __func__
);
168 static enum flctl_ecc_res_t wait_recfifo_ready
169 (struct sh_flctl
*flctl
, int sector_number
)
171 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
172 void __iomem
*ecc_reg
[4];
174 int state
= FL_SUCCESS
;
178 * First this loops checks in FLDTCNTR if we are ready to read out the
179 * oob data. This is the case if either all went fine without errors or
180 * if the bottom part of the loop corrected the errors or marked them as
181 * uncorrectable and the controller is given time to push the data into
185 /* check if all is ok and we can read out the OOB */
186 size
= readl(FLDTCNTR(flctl
)) >> 24;
187 if ((size
& 0xFF) == 4)
190 /* check if a correction code has been calculated */
191 if (!(readl(FL4ECCCR(flctl
)) & _4ECCEND
)) {
193 * either we wait for the fifo to be filled or a
194 * correction pattern is being generated
200 /* check for an uncorrectable error */
201 if (readl(FL4ECCCR(flctl
)) & _4ECCFA
) {
202 /* check if we face a non-empty page */
203 for (i
= 0; i
< 512; i
++) {
204 if (flctl
->done_buff
[i
] != 0xff) {
205 state
= FL_ERROR
; /* can't correct */
210 if (state
== FL_SUCCESS
)
211 dev_dbg(&flctl
->pdev
->dev
,
212 "reading empty sector %d, ecc error ignored\n",
215 writel(0, FL4ECCCR(flctl
));
219 /* start error correction */
220 ecc_reg
[0] = FL4ECCRESULT0(flctl
);
221 ecc_reg
[1] = FL4ECCRESULT1(flctl
);
222 ecc_reg
[2] = FL4ECCRESULT2(flctl
);
223 ecc_reg
[3] = FL4ECCRESULT3(flctl
);
225 for (i
= 0; i
< 3; i
++) {
229 data
= readl(ecc_reg
[i
]);
231 if (flctl
->page_size
)
232 index
= (512 * sector_number
) +
237 org
= flctl
->done_buff
[index
];
238 flctl
->done_buff
[index
] = org
^ (data
& 0xFF);
240 state
= FL_REPAIRABLE
;
241 writel(0, FL4ECCCR(flctl
));
244 timeout_error(flctl
, __func__
);
245 return FL_TIMEOUT
; /* timeout */
248 static void wait_wecfifo_ready(struct sh_flctl
*flctl
)
250 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
255 len
= (readl(FLDTCNTR(flctl
)) >> 24) & 0xFF;
260 timeout_error(flctl
, __func__
);
263 static void read_datareg(struct sh_flctl
*flctl
, int offset
)
266 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
268 wait_completion(flctl
);
270 data
= readl(FLDATAR(flctl
));
271 *buf
= le32_to_cpu(data
);
274 static void read_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
277 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
279 len_4align
= (rlen
+ 3) / 4;
281 for (i
= 0; i
< len_4align
; i
++) {
282 wait_rfifo_ready(flctl
);
283 buf
[i
] = readl(FLDTFIFO(flctl
));
284 buf
[i
] = be32_to_cpu(buf
[i
]);
288 static enum flctl_ecc_res_t read_ecfiforeg
289 (struct sh_flctl
*flctl
, uint8_t *buff
, int sector
)
292 enum flctl_ecc_res_t res
;
293 unsigned long *ecc_buf
= (unsigned long *)buff
;
295 res
= wait_recfifo_ready(flctl
, sector
);
297 if (res
!= FL_ERROR
) {
298 for (i
= 0; i
< 4; i
++) {
299 ecc_buf
[i
] = readl(FLECFIFO(flctl
));
300 ecc_buf
[i
] = be32_to_cpu(ecc_buf
[i
]);
307 static void write_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
310 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
311 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
313 len_4align
= (rlen
+ 3) / 4;
314 for (i
= 0; i
< len_4align
; i
++) {
315 wait_wfifo_ready(flctl
);
316 writel(cpu_to_be32(data
[i
]), fifo_addr
);
320 static void write_ec_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
323 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
325 len_4align
= (rlen
+ 3) / 4;
326 for (i
= 0; i
< len_4align
; i
++) {
327 wait_wecfifo_ready(flctl
);
328 writel(cpu_to_be32(data
[i
]), FLECFIFO(flctl
));
332 static void set_cmd_regs(struct mtd_info
*mtd
, uint32_t cmd
, uint32_t flcmcdr_val
)
334 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
335 uint32_t flcmncr_val
= flctl
->flcmncr_base
& ~SEL_16BIT
;
336 uint32_t flcmdcr_val
, addr_len_bytes
= 0;
338 /* Set SNAND bit if page size is 2048byte */
339 if (flctl
->page_size
)
340 flcmncr_val
|= SNAND_E
;
342 flcmncr_val
&= ~SNAND_E
;
344 /* default FLCMDCR val */
345 flcmdcr_val
= DOCMD1_E
| DOADR_E
;
347 /* Set for FLCMDCR */
349 case NAND_CMD_ERASE1
:
350 addr_len_bytes
= flctl
->erase_ADRCNT
;
351 flcmdcr_val
|= DOCMD2_E
;
354 case NAND_CMD_READOOB
:
355 case NAND_CMD_RNDOUT
:
356 addr_len_bytes
= flctl
->rw_ADRCNT
;
357 flcmdcr_val
|= CDSRC_E
;
358 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
359 flcmncr_val
|= SEL_16BIT
;
362 /* This case is that cmd is READ0 or READ1 or READ00 */
363 flcmdcr_val
&= ~DOADR_E
; /* ONLY execute 1st cmd */
365 case NAND_CMD_PAGEPROG
:
366 addr_len_bytes
= flctl
->rw_ADRCNT
;
367 flcmdcr_val
|= DOCMD2_E
| CDSRC_E
| SELRW
;
368 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
369 flcmncr_val
|= SEL_16BIT
;
371 case NAND_CMD_READID
:
372 flcmncr_val
&= ~SNAND_E
;
373 flcmdcr_val
|= CDSRC_E
;
374 addr_len_bytes
= ADRCNT_1
;
376 case NAND_CMD_STATUS
:
378 flcmncr_val
&= ~SNAND_E
;
379 flcmdcr_val
&= ~(DOADR_E
| DOSR_E
);
385 /* Set address bytes parameter */
386 flcmdcr_val
|= addr_len_bytes
;
388 /* Now actually write */
389 writel(flcmncr_val
, FLCMNCR(flctl
));
390 writel(flcmdcr_val
, FLCMDCR(flctl
));
391 writel(flcmcdr_val
, FLCMCDR(flctl
));
394 static int flctl_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
395 uint8_t *buf
, int oob_required
, int page
)
397 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
398 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
402 static int flctl_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
403 const uint8_t *buf
, int oob_required
)
405 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
406 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
410 static void execmd_read_page_sector(struct mtd_info
*mtd
, int page_addr
)
412 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
413 int sector
, page_sectors
;
414 enum flctl_ecc_res_t ecc_result
;
416 page_sectors
= flctl
->page_size
? 4 : 1;
418 set_cmd_regs(mtd
, NAND_CMD_READ0
,
419 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
421 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
| _4ECCCORRECT
,
423 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
424 writel(page_addr
<< 2, FLADR(flctl
));
427 start_translation(flctl
);
429 for (sector
= 0; sector
< page_sectors
; sector
++) {
430 read_fiforeg(flctl
, 512, 512 * sector
);
432 ecc_result
= read_ecfiforeg(flctl
,
433 &flctl
->done_buff
[mtd
->writesize
+ 16 * sector
],
436 switch (ecc_result
) {
438 dev_info(&flctl
->pdev
->dev
,
439 "applied ecc on page 0x%x", page_addr
);
440 flctl
->mtd
.ecc_stats
.corrected
++;
443 dev_warn(&flctl
->pdev
->dev
,
444 "page 0x%x contains corrupted data\n",
446 flctl
->mtd
.ecc_stats
.failed
++;
453 wait_completion(flctl
);
455 writel(readl(FLCMNCR(flctl
)) & ~(ACM_SACCES_MODE
| _4ECCCORRECT
),
459 static void execmd_read_oob(struct mtd_info
*mtd
, int page_addr
)
461 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
462 int page_sectors
= flctl
->page_size
? 4 : 1;
465 set_cmd_regs(mtd
, NAND_CMD_READ0
,
466 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
470 for (i
= 0; i
< page_sectors
; i
++) {
471 set_addr(mtd
, (512 + 16) * i
+ 512 , page_addr
);
472 writel(16, FLDTCNTR(flctl
));
474 start_translation(flctl
);
475 read_fiforeg(flctl
, 16, 16 * i
);
476 wait_completion(flctl
);
480 static void execmd_write_page_sector(struct mtd_info
*mtd
)
482 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
483 int page_addr
= flctl
->seqin_page_addr
;
484 int sector
, page_sectors
;
486 page_sectors
= flctl
->page_size
? 4 : 1;
488 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
489 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
492 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
, FLCMNCR(flctl
));
493 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
494 writel(page_addr
<< 2, FLADR(flctl
));
495 start_translation(flctl
);
497 for (sector
= 0; sector
< page_sectors
; sector
++) {
498 write_fiforeg(flctl
, 512, 512 * sector
);
499 write_ec_fiforeg(flctl
, 16, mtd
->writesize
+ 16 * sector
);
502 wait_completion(flctl
);
503 writel(readl(FLCMNCR(flctl
)) & ~ACM_SACCES_MODE
, FLCMNCR(flctl
));
506 static void execmd_write_oob(struct mtd_info
*mtd
)
508 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
509 int page_addr
= flctl
->seqin_page_addr
;
510 int sector
, page_sectors
;
512 page_sectors
= flctl
->page_size
? 4 : 1;
514 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
515 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
517 for (sector
= 0; sector
< page_sectors
; sector
++) {
519 set_addr(mtd
, sector
* 528 + 512, page_addr
);
520 writel(16, FLDTCNTR(flctl
)); /* set read size */
522 start_translation(flctl
);
523 write_fiforeg(flctl
, 16, 16 * sector
);
524 wait_completion(flctl
);
528 static void flctl_cmdfunc(struct mtd_info
*mtd
, unsigned int command
,
529 int column
, int page_addr
)
531 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
532 uint32_t read_cmd
= 0;
534 pm_runtime_get_sync(&flctl
->pdev
->dev
);
536 flctl
->read_bytes
= 0;
537 if (command
!= NAND_CMD_PAGEPROG
)
544 /* read page with hwecc */
545 execmd_read_page_sector(mtd
, page_addr
);
548 if (flctl
->page_size
)
549 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
552 set_cmd_regs(mtd
, command
, command
);
554 set_addr(mtd
, 0, page_addr
);
556 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
557 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
559 flctl
->index
+= column
;
560 goto read_normal_exit
;
562 case NAND_CMD_READOOB
:
564 /* read page with hwecc */
565 execmd_read_oob(mtd
, page_addr
);
569 if (flctl
->page_size
) {
570 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
572 set_addr(mtd
, mtd
->writesize
, page_addr
);
574 set_cmd_regs(mtd
, command
, command
);
575 set_addr(mtd
, 0, page_addr
);
577 flctl
->read_bytes
= mtd
->oobsize
;
578 goto read_normal_exit
;
580 case NAND_CMD_RNDOUT
:
584 if (flctl
->page_size
)
585 set_cmd_regs(mtd
, command
, (NAND_CMD_RNDOUTSTART
<< 8)
588 set_cmd_regs(mtd
, command
, command
);
590 set_addr(mtd
, column
, 0);
592 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
- column
;
593 goto read_normal_exit
;
595 case NAND_CMD_READID
:
596 set_cmd_regs(mtd
, command
, command
);
598 /* READID is always performed using an 8-bit bus */
599 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
601 set_addr(mtd
, column
, 0);
603 flctl
->read_bytes
= 8;
604 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
606 start_translation(flctl
);
607 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
608 wait_completion(flctl
);
611 case NAND_CMD_ERASE1
:
612 flctl
->erase1_page_addr
= page_addr
;
615 case NAND_CMD_ERASE2
:
616 set_cmd_regs(mtd
, NAND_CMD_ERASE1
,
617 (command
<< 8) | NAND_CMD_ERASE1
);
618 set_addr(mtd
, -1, flctl
->erase1_page_addr
);
619 start_translation(flctl
);
620 wait_completion(flctl
);
624 if (!flctl
->page_size
) {
625 /* output read command */
626 if (column
>= mtd
->writesize
) {
627 column
-= mtd
->writesize
;
628 read_cmd
= NAND_CMD_READOOB
;
629 } else if (column
< 256) {
630 read_cmd
= NAND_CMD_READ0
;
633 read_cmd
= NAND_CMD_READ1
;
636 flctl
->seqin_column
= column
;
637 flctl
->seqin_page_addr
= page_addr
;
638 flctl
->seqin_read_cmd
= read_cmd
;
641 case NAND_CMD_PAGEPROG
:
643 if (!flctl
->page_size
) {
644 set_cmd_regs(mtd
, NAND_CMD_SEQIN
,
645 flctl
->seqin_read_cmd
);
646 set_addr(mtd
, -1, -1);
647 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
648 start_translation(flctl
);
649 wait_completion(flctl
);
652 /* write page with hwecc */
653 if (flctl
->seqin_column
== mtd
->writesize
)
654 execmd_write_oob(mtd
);
655 else if (!flctl
->seqin_column
)
656 execmd_write_page_sector(mtd
);
658 printk(KERN_ERR
"Invalid address !?\n");
661 set_cmd_regs(mtd
, command
, (command
<< 8) | NAND_CMD_SEQIN
);
662 set_addr(mtd
, flctl
->seqin_column
, flctl
->seqin_page_addr
);
663 writel(flctl
->index
, FLDTCNTR(flctl
)); /* set write size */
664 start_translation(flctl
);
665 write_fiforeg(flctl
, flctl
->index
, 0);
666 wait_completion(flctl
);
669 case NAND_CMD_STATUS
:
670 set_cmd_regs(mtd
, command
, command
);
671 set_addr(mtd
, -1, -1);
673 flctl
->read_bytes
= 1;
674 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
675 start_translation(flctl
);
676 read_datareg(flctl
, 0); /* read and end */
680 set_cmd_regs(mtd
, command
, command
);
681 set_addr(mtd
, -1, -1);
683 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
684 start_translation(flctl
);
685 wait_completion(flctl
);
694 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
696 start_translation(flctl
);
697 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
698 wait_completion(flctl
);
700 pm_runtime_put_sync(&flctl
->pdev
->dev
);
704 static void flctl_select_chip(struct mtd_info
*mtd
, int chipnr
)
706 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
711 flctl
->flcmncr_base
&= ~CE0_ENABLE
;
713 pm_runtime_get_sync(&flctl
->pdev
->dev
);
714 writel(flctl
->flcmncr_base
, FLCMNCR(flctl
));
716 if (flctl
->qos_request
) {
717 dev_pm_qos_remove_request(&flctl
->pm_qos
);
718 flctl
->qos_request
= 0;
721 pm_runtime_put_sync(&flctl
->pdev
->dev
);
724 flctl
->flcmncr_base
|= CE0_ENABLE
;
726 if (!flctl
->qos_request
) {
727 ret
= dev_pm_qos_add_request(&flctl
->pdev
->dev
,
728 &flctl
->pm_qos
, 100);
730 dev_err(&flctl
->pdev
->dev
,
731 "PM QoS request failed: %d\n", ret
);
732 flctl
->qos_request
= 1;
736 pm_runtime_get_sync(&flctl
->pdev
->dev
);
737 writel(HOLDEN
, FLHOLDCR(flctl
));
738 pm_runtime_put_sync(&flctl
->pdev
->dev
);
746 static void flctl_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
748 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
749 int i
, index
= flctl
->index
;
751 for (i
= 0; i
< len
; i
++)
752 flctl
->done_buff
[index
+ i
] = buf
[i
];
756 static uint8_t flctl_read_byte(struct mtd_info
*mtd
)
758 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
759 int index
= flctl
->index
;
762 data
= flctl
->done_buff
[index
];
767 static uint16_t flctl_read_word(struct mtd_info
*mtd
)
769 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
770 int index
= flctl
->index
;
772 uint16_t *buf
= (uint16_t *)&flctl
->done_buff
[index
];
779 static void flctl_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
783 for (i
= 0; i
< len
; i
++)
784 buf
[i
] = flctl_read_byte(mtd
);
787 static int flctl_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
791 for (i
= 0; i
< len
; i
++)
792 if (buf
[i
] != flctl_read_byte(mtd
))
797 static int flctl_chip_init_tail(struct mtd_info
*mtd
)
799 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
800 struct nand_chip
*chip
= &flctl
->chip
;
802 if (mtd
->writesize
== 512) {
803 flctl
->page_size
= 0;
804 if (chip
->chipsize
> (32 << 20)) {
806 flctl
->rw_ADRCNT
= ADRCNT_4
;
807 flctl
->erase_ADRCNT
= ADRCNT_3
;
808 } else if (chip
->chipsize
> (2 << 16)) {
810 flctl
->rw_ADRCNT
= ADRCNT_3
;
811 flctl
->erase_ADRCNT
= ADRCNT_2
;
813 flctl
->rw_ADRCNT
= ADRCNT_2
;
814 flctl
->erase_ADRCNT
= ADRCNT_1
;
817 flctl
->page_size
= 1;
818 if (chip
->chipsize
> (128 << 20)) {
820 flctl
->rw_ADRCNT
= ADRCNT2_E
;
821 flctl
->erase_ADRCNT
= ADRCNT_3
;
822 } else if (chip
->chipsize
> (8 << 16)) {
824 flctl
->rw_ADRCNT
= ADRCNT_4
;
825 flctl
->erase_ADRCNT
= ADRCNT_2
;
827 flctl
->rw_ADRCNT
= ADRCNT_3
;
828 flctl
->erase_ADRCNT
= ADRCNT_1
;
833 if (mtd
->writesize
== 512) {
834 chip
->ecc
.layout
= &flctl_4secc_oob_16
;
835 chip
->badblock_pattern
= &flctl_4secc_smallpage
;
837 chip
->ecc
.layout
= &flctl_4secc_oob_64
;
838 chip
->badblock_pattern
= &flctl_4secc_largepage
;
841 chip
->ecc
.size
= 512;
842 chip
->ecc
.bytes
= 10;
843 chip
->ecc
.strength
= 4;
844 chip
->ecc
.read_page
= flctl_read_page_hwecc
;
845 chip
->ecc
.write_page
= flctl_write_page_hwecc
;
846 chip
->ecc
.mode
= NAND_ECC_HW
;
848 /* 4 symbols ECC enabled */
849 flctl
->flcmncr_base
|= _4ECCEN
;
851 chip
->ecc
.mode
= NAND_ECC_SOFT
;
857 static irqreturn_t
flctl_handle_flste(int irq
, void *dev_id
)
859 struct sh_flctl
*flctl
= dev_id
;
861 dev_err(&flctl
->pdev
->dev
, "flste irq: %x\n", readl(FLINTDMACR(flctl
)));
862 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
867 static int __devinit
flctl_probe(struct platform_device
*pdev
)
869 struct resource
*res
;
870 struct sh_flctl
*flctl
;
871 struct mtd_info
*flctl_mtd
;
872 struct nand_chip
*nand
;
873 struct sh_flctl_platform_data
*pdata
;
877 pdata
= pdev
->dev
.platform_data
;
879 dev_err(&pdev
->dev
, "no platform data defined\n");
883 flctl
= kzalloc(sizeof(struct sh_flctl
), GFP_KERNEL
);
885 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
889 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
891 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
895 flctl
->reg
= ioremap(res
->start
, resource_size(res
));
896 if (flctl
->reg
== NULL
) {
897 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
901 irq
= platform_get_irq(pdev
, 0);
903 dev_err(&pdev
->dev
, "failed to get flste irq data\n");
907 ret
= request_irq(irq
, flctl_handle_flste
, IRQF_SHARED
, "flste", flctl
);
909 dev_err(&pdev
->dev
, "request interrupt failed.\n");
913 platform_set_drvdata(pdev
, flctl
);
914 flctl_mtd
= &flctl
->mtd
;
916 flctl_mtd
->priv
= nand
;
918 flctl
->hwecc
= pdata
->has_hwecc
;
919 flctl
->holden
= pdata
->use_holden
;
920 flctl
->flcmncr_base
= pdata
->flcmncr_val
;
921 flctl
->flintdmacr_base
= flctl
->hwecc
? (STERINTE
| ECERB
) : STERINTE
;
923 /* Set address of hardware control function */
924 /* 20 us command delay time */
925 nand
->chip_delay
= 20;
927 nand
->read_byte
= flctl_read_byte
;
928 nand
->write_buf
= flctl_write_buf
;
929 nand
->read_buf
= flctl_read_buf
;
930 nand
->verify_buf
= flctl_verify_buf
;
931 nand
->select_chip
= flctl_select_chip
;
932 nand
->cmdfunc
= flctl_cmdfunc
;
934 if (pdata
->flcmncr_val
& SEL_16BIT
) {
935 nand
->options
|= NAND_BUSWIDTH_16
;
936 nand
->read_word
= flctl_read_word
;
939 pm_runtime_enable(&pdev
->dev
);
940 pm_runtime_resume(&pdev
->dev
);
942 ret
= nand_scan_ident(flctl_mtd
, 1, NULL
);
946 ret
= flctl_chip_init_tail(flctl_mtd
);
950 ret
= nand_scan_tail(flctl_mtd
);
954 mtd_device_register(flctl_mtd
, pdata
->parts
, pdata
->nr_parts
);
959 pm_runtime_disable(&pdev
->dev
);
960 free_irq(irq
, flctl
);
968 static int __devexit
flctl_remove(struct platform_device
*pdev
)
970 struct sh_flctl
*flctl
= platform_get_drvdata(pdev
);
972 nand_release(&flctl
->mtd
);
973 pm_runtime_disable(&pdev
->dev
);
974 free_irq(platform_get_irq(pdev
, 0), flctl
);
981 static struct platform_driver flctl_driver
= {
982 .remove
= flctl_remove
,
985 .owner
= THIS_MODULE
,
989 static int __init
flctl_nand_init(void)
991 return platform_driver_probe(&flctl_driver
, flctl_probe
);
994 static void __exit
flctl_nand_cleanup(void)
996 platform_driver_unregister(&flctl_driver
);
999 module_init(flctl_nand_init
);
1000 module_exit(flctl_nand_cleanup
);
1002 MODULE_LICENSE("GPL");
1003 MODULE_AUTHOR("Yoshihiro Shimoda");
1004 MODULE_DESCRIPTION("SuperH FLCTL driver");
1005 MODULE_ALIAS("platform:sh_flctl");