2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/mtd/sh_flctl.h>
38 static struct nand_ecclayout flctl_4secc_oob_16
= {
40 .eccpos
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
46 static struct nand_ecclayout flctl_4secc_oob_64
= {
49 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
50 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
51 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
52 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 },
54 {.offset
= 2, .length
= 4},
55 {.offset
= 16, .length
= 6},
56 {.offset
= 32, .length
= 6},
57 {.offset
= 48, .length
= 6} },
60 static uint8_t scan_ff_pattern
[] = { 0xff, 0xff };
62 static struct nand_bbt_descr flctl_4secc_smallpage
= {
63 .options
= NAND_BBT_SCAN2NDPAGE
,
66 .pattern
= scan_ff_pattern
,
69 static struct nand_bbt_descr flctl_4secc_largepage
= {
70 .options
= NAND_BBT_SCAN2NDPAGE
,
73 .pattern
= scan_ff_pattern
,
76 static void empty_fifo(struct sh_flctl
*flctl
)
78 writel(flctl
->flintdmacr_base
| AC1CLR
| AC0CLR
, FLINTDMACR(flctl
));
79 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
82 static void start_translation(struct sh_flctl
*flctl
)
84 writeb(TRSTRT
, FLTRCR(flctl
));
87 static void timeout_error(struct sh_flctl
*flctl
, const char *str
)
89 dev_err(&flctl
->pdev
->dev
, "Timeout occurred in %s\n", str
);
92 static void wait_completion(struct sh_flctl
*flctl
)
94 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
97 if (readb(FLTRCR(flctl
)) & TREND
) {
98 writeb(0x0, FLTRCR(flctl
));
104 timeout_error(flctl
, __func__
);
105 writeb(0x0, FLTRCR(flctl
));
108 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
110 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
114 addr
= page_addr
; /* ERASE1 */
115 } else if (page_addr
!= -1) {
116 /* SEQIN, READ0, etc.. */
117 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
119 if (flctl
->page_size
) {
120 addr
= column
& 0x0FFF;
121 addr
|= (page_addr
& 0xff) << 16;
122 addr
|= ((page_addr
>> 8) & 0xff) << 24;
124 if (flctl
->rw_ADRCNT
== ADRCNT2_E
) {
126 addr2
= (page_addr
>> 16) & 0xff;
127 writel(addr2
, FLADR2(flctl
));
131 addr
|= (page_addr
& 0xff) << 8;
132 addr
|= ((page_addr
>> 8) & 0xff) << 16;
133 addr
|= ((page_addr
>> 16) & 0xff) << 24;
136 writel(addr
, FLADR(flctl
));
139 static void wait_rfifo_ready(struct sh_flctl
*flctl
)
141 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
146 val
= readl(FLDTCNTR(flctl
)) >> 16;
151 timeout_error(flctl
, __func__
);
154 static void wait_wfifo_ready(struct sh_flctl
*flctl
)
156 uint32_t len
, timeout
= LOOP_TIMEOUT_MAX
;
160 len
= (readl(FLDTCNTR(flctl
)) >> 16) & 0xFF;
165 timeout_error(flctl
, __func__
);
168 static enum flctl_ecc_res_t wait_recfifo_ready
169 (struct sh_flctl
*flctl
, int sector_number
)
171 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
172 void __iomem
*ecc_reg
[4];
174 int state
= FL_SUCCESS
;
178 * First this loops checks in FLDTCNTR if we are ready to read out the
179 * oob data. This is the case if either all went fine without errors or
180 * if the bottom part of the loop corrected the errors or marked them as
181 * uncorrectable and the controller is given time to push the data into
185 /* check if all is ok and we can read out the OOB */
186 size
= readl(FLDTCNTR(flctl
)) >> 24;
187 if ((size
& 0xFF) == 4)
190 /* check if a correction code has been calculated */
191 if (!(readl(FL4ECCCR(flctl
)) & _4ECCEND
)) {
193 * either we wait for the fifo to be filled or a
194 * correction pattern is being generated
200 /* check for an uncorrectable error */
201 if (readl(FL4ECCCR(flctl
)) & _4ECCFA
) {
202 /* check if we face a non-empty page */
203 for (i
= 0; i
< 512; i
++) {
204 if (flctl
->done_buff
[i
] != 0xff) {
205 state
= FL_ERROR
; /* can't correct */
210 if (state
== FL_SUCCESS
)
211 dev_dbg(&flctl
->pdev
->dev
,
212 "reading empty sector %d, ecc error ignored\n",
215 writel(0, FL4ECCCR(flctl
));
219 /* start error correction */
220 ecc_reg
[0] = FL4ECCRESULT0(flctl
);
221 ecc_reg
[1] = FL4ECCRESULT1(flctl
);
222 ecc_reg
[2] = FL4ECCRESULT2(flctl
);
223 ecc_reg
[3] = FL4ECCRESULT3(flctl
);
225 for (i
= 0; i
< 3; i
++) {
229 data
= readl(ecc_reg
[i
]);
231 if (flctl
->page_size
)
232 index
= (512 * sector_number
) +
237 org
= flctl
->done_buff
[index
];
238 flctl
->done_buff
[index
] = org
^ (data
& 0xFF);
240 state
= FL_REPAIRABLE
;
241 writel(0, FL4ECCCR(flctl
));
244 timeout_error(flctl
, __func__
);
245 return FL_TIMEOUT
; /* timeout */
248 static void wait_wecfifo_ready(struct sh_flctl
*flctl
)
250 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
255 len
= (readl(FLDTCNTR(flctl
)) >> 24) & 0xFF;
260 timeout_error(flctl
, __func__
);
263 static void read_datareg(struct sh_flctl
*flctl
, int offset
)
266 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
268 wait_completion(flctl
);
270 data
= readl(FLDATAR(flctl
));
271 *buf
= le32_to_cpu(data
);
274 static void read_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
277 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
278 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
280 len_4align
= (rlen
+ 3) / 4;
282 for (i
= 0; i
< len_4align
; i
++) {
283 wait_rfifo_ready(flctl
);
284 buf
[i
] = readl(fifo_addr
);
285 buf
[i
] = be32_to_cpu(buf
[i
]);
289 static enum flctl_ecc_res_t read_ecfiforeg
290 (struct sh_flctl
*flctl
, uint8_t *buff
, int sector
)
293 enum flctl_ecc_res_t res
;
294 unsigned long *ecc_buf
= (unsigned long *)buff
;
296 res
= wait_recfifo_ready(flctl
, sector
);
298 if (res
!= FL_ERROR
) {
299 for (i
= 0; i
< 4; i
++) {
300 ecc_buf
[i
] = readl(FLECFIFO(flctl
));
301 ecc_buf
[i
] = be32_to_cpu(ecc_buf
[i
]);
308 static void write_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
311 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
312 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
314 len_4align
= (rlen
+ 3) / 4;
315 for (i
= 0; i
< len_4align
; i
++) {
316 wait_wfifo_ready(flctl
);
317 writel(cpu_to_be32(data
[i
]), fifo_addr
);
321 static void set_cmd_regs(struct mtd_info
*mtd
, uint32_t cmd
, uint32_t flcmcdr_val
)
323 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
324 uint32_t flcmncr_val
= flctl
->flcmncr_base
& ~SEL_16BIT
;
325 uint32_t flcmdcr_val
, addr_len_bytes
= 0;
327 /* Set SNAND bit if page size is 2048byte */
328 if (flctl
->page_size
)
329 flcmncr_val
|= SNAND_E
;
331 flcmncr_val
&= ~SNAND_E
;
333 /* default FLCMDCR val */
334 flcmdcr_val
= DOCMD1_E
| DOADR_E
;
336 /* Set for FLCMDCR */
338 case NAND_CMD_ERASE1
:
339 addr_len_bytes
= flctl
->erase_ADRCNT
;
340 flcmdcr_val
|= DOCMD2_E
;
343 case NAND_CMD_READOOB
:
344 case NAND_CMD_RNDOUT
:
345 addr_len_bytes
= flctl
->rw_ADRCNT
;
346 flcmdcr_val
|= CDSRC_E
;
347 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
348 flcmncr_val
|= SEL_16BIT
;
351 /* This case is that cmd is READ0 or READ1 or READ00 */
352 flcmdcr_val
&= ~DOADR_E
; /* ONLY execute 1st cmd */
354 case NAND_CMD_PAGEPROG
:
355 addr_len_bytes
= flctl
->rw_ADRCNT
;
356 flcmdcr_val
|= DOCMD2_E
| CDSRC_E
| SELRW
;
357 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
358 flcmncr_val
|= SEL_16BIT
;
360 case NAND_CMD_READID
:
361 flcmncr_val
&= ~SNAND_E
;
362 flcmdcr_val
|= CDSRC_E
;
363 addr_len_bytes
= ADRCNT_1
;
365 case NAND_CMD_STATUS
:
367 flcmncr_val
&= ~SNAND_E
;
368 flcmdcr_val
&= ~(DOADR_E
| DOSR_E
);
374 /* Set address bytes parameter */
375 flcmdcr_val
|= addr_len_bytes
;
377 /* Now actually write */
378 writel(flcmncr_val
, FLCMNCR(flctl
));
379 writel(flcmdcr_val
, FLCMDCR(flctl
));
380 writel(flcmcdr_val
, FLCMCDR(flctl
));
383 static int flctl_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
384 uint8_t *buf
, int oob_required
, int page
)
386 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
390 static void flctl_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
391 const uint8_t *buf
, int oob_required
)
393 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
396 static void execmd_read_page_sector(struct mtd_info
*mtd
, int page_addr
)
398 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
399 int sector
, page_sectors
;
400 enum flctl_ecc_res_t ecc_result
;
402 page_sectors
= flctl
->page_size
? 4 : 1;
404 set_cmd_regs(mtd
, NAND_CMD_READ0
,
405 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
407 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
| _4ECCCORRECT
,
409 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
410 writel(page_addr
<< 2, FLADR(flctl
));
413 start_translation(flctl
);
415 for (sector
= 0; sector
< page_sectors
; sector
++) {
416 read_fiforeg(flctl
, 512, 512 * sector
);
418 ecc_result
= read_ecfiforeg(flctl
,
419 &flctl
->done_buff
[mtd
->writesize
+ 16 * sector
],
422 switch (ecc_result
) {
424 dev_info(&flctl
->pdev
->dev
,
425 "applied ecc on page 0x%x", page_addr
);
426 flctl
->mtd
.ecc_stats
.corrected
++;
429 dev_warn(&flctl
->pdev
->dev
,
430 "page 0x%x contains corrupted data\n",
432 flctl
->mtd
.ecc_stats
.failed
++;
439 wait_completion(flctl
);
441 writel(readl(FLCMNCR(flctl
)) & ~(ACM_SACCES_MODE
| _4ECCCORRECT
),
445 static void execmd_read_oob(struct mtd_info
*mtd
, int page_addr
)
447 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
448 int page_sectors
= flctl
->page_size
? 4 : 1;
451 set_cmd_regs(mtd
, NAND_CMD_READ0
,
452 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
456 for (i
= 0; i
< page_sectors
; i
++) {
457 set_addr(mtd
, (512 + 16) * i
+ 512 , page_addr
);
458 writel(16, FLDTCNTR(flctl
));
460 start_translation(flctl
);
461 read_fiforeg(flctl
, 16, 16 * i
);
462 wait_completion(flctl
);
466 static void execmd_write_page_sector(struct mtd_info
*mtd
)
468 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
469 int i
, page_addr
= flctl
->seqin_page_addr
;
470 int sector
, page_sectors
;
472 page_sectors
= flctl
->page_size
? 4 : 1;
474 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
475 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
478 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
, FLCMNCR(flctl
));
479 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
480 writel(page_addr
<< 2, FLADR(flctl
));
481 start_translation(flctl
);
483 for (sector
= 0; sector
< page_sectors
; sector
++) {
484 write_fiforeg(flctl
, 512, 512 * sector
);
486 for (i
= 0; i
< 4; i
++) {
487 wait_wecfifo_ready(flctl
); /* wait for write ready */
488 writel(0xFFFFFFFF, FLECFIFO(flctl
));
492 wait_completion(flctl
);
493 writel(readl(FLCMNCR(flctl
)) & ~ACM_SACCES_MODE
, FLCMNCR(flctl
));
496 static void execmd_write_oob(struct mtd_info
*mtd
)
498 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
499 int page_addr
= flctl
->seqin_page_addr
;
500 int sector
, page_sectors
;
502 page_sectors
= flctl
->page_size
? 4 : 1;
504 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
505 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
507 for (sector
= 0; sector
< page_sectors
; sector
++) {
509 set_addr(mtd
, sector
* 528 + 512, page_addr
);
510 writel(16, FLDTCNTR(flctl
)); /* set read size */
512 start_translation(flctl
);
513 write_fiforeg(flctl
, 16, 16 * sector
);
514 wait_completion(flctl
);
518 static void flctl_cmdfunc(struct mtd_info
*mtd
, unsigned int command
,
519 int column
, int page_addr
)
521 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
522 uint32_t read_cmd
= 0;
524 pm_runtime_get_sync(&flctl
->pdev
->dev
);
526 flctl
->read_bytes
= 0;
527 if (command
!= NAND_CMD_PAGEPROG
)
534 /* read page with hwecc */
535 execmd_read_page_sector(mtd
, page_addr
);
538 if (flctl
->page_size
)
539 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
542 set_cmd_regs(mtd
, command
, command
);
544 set_addr(mtd
, 0, page_addr
);
546 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
547 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
549 flctl
->index
+= column
;
550 goto read_normal_exit
;
552 case NAND_CMD_READOOB
:
554 /* read page with hwecc */
555 execmd_read_oob(mtd
, page_addr
);
559 if (flctl
->page_size
) {
560 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
562 set_addr(mtd
, mtd
->writesize
, page_addr
);
564 set_cmd_regs(mtd
, command
, command
);
565 set_addr(mtd
, 0, page_addr
);
567 flctl
->read_bytes
= mtd
->oobsize
;
568 goto read_normal_exit
;
570 case NAND_CMD_RNDOUT
:
574 if (flctl
->page_size
)
575 set_cmd_regs(mtd
, command
, (NAND_CMD_RNDOUTSTART
<< 8)
578 set_cmd_regs(mtd
, command
, command
);
580 set_addr(mtd
, column
, 0);
582 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
- column
;
583 goto read_normal_exit
;
585 case NAND_CMD_READID
:
586 set_cmd_regs(mtd
, command
, command
);
588 /* READID is always performed using an 8-bit bus */
589 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
591 set_addr(mtd
, column
, 0);
593 flctl
->read_bytes
= 8;
594 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
596 start_translation(flctl
);
597 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
598 wait_completion(flctl
);
601 case NAND_CMD_ERASE1
:
602 flctl
->erase1_page_addr
= page_addr
;
605 case NAND_CMD_ERASE2
:
606 set_cmd_regs(mtd
, NAND_CMD_ERASE1
,
607 (command
<< 8) | NAND_CMD_ERASE1
);
608 set_addr(mtd
, -1, flctl
->erase1_page_addr
);
609 start_translation(flctl
);
610 wait_completion(flctl
);
614 if (!flctl
->page_size
) {
615 /* output read command */
616 if (column
>= mtd
->writesize
) {
617 column
-= mtd
->writesize
;
618 read_cmd
= NAND_CMD_READOOB
;
619 } else if (column
< 256) {
620 read_cmd
= NAND_CMD_READ0
;
623 read_cmd
= NAND_CMD_READ1
;
626 flctl
->seqin_column
= column
;
627 flctl
->seqin_page_addr
= page_addr
;
628 flctl
->seqin_read_cmd
= read_cmd
;
631 case NAND_CMD_PAGEPROG
:
633 if (!flctl
->page_size
) {
634 set_cmd_regs(mtd
, NAND_CMD_SEQIN
,
635 flctl
->seqin_read_cmd
);
636 set_addr(mtd
, -1, -1);
637 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
638 start_translation(flctl
);
639 wait_completion(flctl
);
642 /* write page with hwecc */
643 if (flctl
->seqin_column
== mtd
->writesize
)
644 execmd_write_oob(mtd
);
645 else if (!flctl
->seqin_column
)
646 execmd_write_page_sector(mtd
);
648 printk(KERN_ERR
"Invalid address !?\n");
651 set_cmd_regs(mtd
, command
, (command
<< 8) | NAND_CMD_SEQIN
);
652 set_addr(mtd
, flctl
->seqin_column
, flctl
->seqin_page_addr
);
653 writel(flctl
->index
, FLDTCNTR(flctl
)); /* set write size */
654 start_translation(flctl
);
655 write_fiforeg(flctl
, flctl
->index
, 0);
656 wait_completion(flctl
);
659 case NAND_CMD_STATUS
:
660 set_cmd_regs(mtd
, command
, command
);
661 set_addr(mtd
, -1, -1);
663 flctl
->read_bytes
= 1;
664 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
665 start_translation(flctl
);
666 read_datareg(flctl
, 0); /* read and end */
670 set_cmd_regs(mtd
, command
, command
);
671 set_addr(mtd
, -1, -1);
673 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
674 start_translation(flctl
);
675 wait_completion(flctl
);
684 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
686 start_translation(flctl
);
687 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
688 wait_completion(flctl
);
690 pm_runtime_put_sync(&flctl
->pdev
->dev
);
694 static void flctl_select_chip(struct mtd_info
*mtd
, int chipnr
)
696 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
701 flctl
->flcmncr_base
&= ~CE0_ENABLE
;
703 pm_runtime_get_sync(&flctl
->pdev
->dev
);
704 writel(flctl
->flcmncr_base
, FLCMNCR(flctl
));
706 if (flctl
->qos_request
) {
707 dev_pm_qos_remove_request(&flctl
->pm_qos
);
708 flctl
->qos_request
= 0;
711 pm_runtime_put_sync(&flctl
->pdev
->dev
);
714 flctl
->flcmncr_base
|= CE0_ENABLE
;
716 if (!flctl
->qos_request
) {
717 ret
= dev_pm_qos_add_request(&flctl
->pdev
->dev
,
718 &flctl
->pm_qos
, 100);
720 dev_err(&flctl
->pdev
->dev
,
721 "PM QoS request failed: %d\n", ret
);
722 flctl
->qos_request
= 1;
726 pm_runtime_get_sync(&flctl
->pdev
->dev
);
727 writel(HOLDEN
, FLHOLDCR(flctl
));
728 pm_runtime_put_sync(&flctl
->pdev
->dev
);
736 static void flctl_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
738 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
739 int i
, index
= flctl
->index
;
741 for (i
= 0; i
< len
; i
++)
742 flctl
->done_buff
[index
+ i
] = buf
[i
];
746 static uint8_t flctl_read_byte(struct mtd_info
*mtd
)
748 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
749 int index
= flctl
->index
;
752 data
= flctl
->done_buff
[index
];
757 static uint16_t flctl_read_word(struct mtd_info
*mtd
)
759 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
760 int index
= flctl
->index
;
762 uint16_t *buf
= (uint16_t *)&flctl
->done_buff
[index
];
769 static void flctl_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
773 for (i
= 0; i
< len
; i
++)
774 buf
[i
] = flctl_read_byte(mtd
);
777 static int flctl_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
781 for (i
= 0; i
< len
; i
++)
782 if (buf
[i
] != flctl_read_byte(mtd
))
787 static int flctl_chip_init_tail(struct mtd_info
*mtd
)
789 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
790 struct nand_chip
*chip
= &flctl
->chip
;
792 if (mtd
->writesize
== 512) {
793 flctl
->page_size
= 0;
794 if (chip
->chipsize
> (32 << 20)) {
796 flctl
->rw_ADRCNT
= ADRCNT_4
;
797 flctl
->erase_ADRCNT
= ADRCNT_3
;
798 } else if (chip
->chipsize
> (2 << 16)) {
800 flctl
->rw_ADRCNT
= ADRCNT_3
;
801 flctl
->erase_ADRCNT
= ADRCNT_2
;
803 flctl
->rw_ADRCNT
= ADRCNT_2
;
804 flctl
->erase_ADRCNT
= ADRCNT_1
;
807 flctl
->page_size
= 1;
808 if (chip
->chipsize
> (128 << 20)) {
810 flctl
->rw_ADRCNT
= ADRCNT2_E
;
811 flctl
->erase_ADRCNT
= ADRCNT_3
;
812 } else if (chip
->chipsize
> (8 << 16)) {
814 flctl
->rw_ADRCNT
= ADRCNT_4
;
815 flctl
->erase_ADRCNT
= ADRCNT_2
;
817 flctl
->rw_ADRCNT
= ADRCNT_3
;
818 flctl
->erase_ADRCNT
= ADRCNT_1
;
823 if (mtd
->writesize
== 512) {
824 chip
->ecc
.layout
= &flctl_4secc_oob_16
;
825 chip
->badblock_pattern
= &flctl_4secc_smallpage
;
827 chip
->ecc
.layout
= &flctl_4secc_oob_64
;
828 chip
->badblock_pattern
= &flctl_4secc_largepage
;
831 chip
->ecc
.size
= 512;
832 chip
->ecc
.bytes
= 10;
833 chip
->ecc
.strength
= 4;
834 chip
->ecc
.read_page
= flctl_read_page_hwecc
;
835 chip
->ecc
.write_page
= flctl_write_page_hwecc
;
836 chip
->ecc
.mode
= NAND_ECC_HW
;
838 /* 4 symbols ECC enabled */
839 flctl
->flcmncr_base
|= _4ECCEN
;
841 chip
->ecc
.mode
= NAND_ECC_SOFT
;
847 static irqreturn_t
flctl_handle_flste(int irq
, void *dev_id
)
849 struct sh_flctl
*flctl
= dev_id
;
851 dev_err(&flctl
->pdev
->dev
, "flste irq: %x\n", readl(FLINTDMACR(flctl
)));
852 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
857 static int __devinit
flctl_probe(struct platform_device
*pdev
)
859 struct resource
*res
;
860 struct sh_flctl
*flctl
;
861 struct mtd_info
*flctl_mtd
;
862 struct nand_chip
*nand
;
863 struct sh_flctl_platform_data
*pdata
;
867 pdata
= pdev
->dev
.platform_data
;
869 dev_err(&pdev
->dev
, "no platform data defined\n");
873 flctl
= kzalloc(sizeof(struct sh_flctl
), GFP_KERNEL
);
875 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
879 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
881 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
885 flctl
->reg
= ioremap(res
->start
, resource_size(res
));
886 if (flctl
->reg
== NULL
) {
887 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
891 irq
= platform_get_irq(pdev
, 0);
893 dev_err(&pdev
->dev
, "failed to get flste irq data\n");
897 ret
= request_irq(irq
, flctl_handle_flste
, IRQF_SHARED
, "flste", flctl
);
899 dev_err(&pdev
->dev
, "request interrupt failed.\n");
903 platform_set_drvdata(pdev
, flctl
);
904 flctl_mtd
= &flctl
->mtd
;
906 flctl_mtd
->priv
= nand
;
908 flctl
->hwecc
= pdata
->has_hwecc
;
909 flctl
->holden
= pdata
->use_holden
;
910 flctl
->flcmncr_base
= pdata
->flcmncr_val
;
911 flctl
->flintdmacr_base
= flctl
->hwecc
? (STERINTE
| ECERB
) : STERINTE
;
913 /* Set address of hardware control function */
914 /* 20 us command delay time */
915 nand
->chip_delay
= 20;
917 nand
->read_byte
= flctl_read_byte
;
918 nand
->write_buf
= flctl_write_buf
;
919 nand
->read_buf
= flctl_read_buf
;
920 nand
->verify_buf
= flctl_verify_buf
;
921 nand
->select_chip
= flctl_select_chip
;
922 nand
->cmdfunc
= flctl_cmdfunc
;
924 if (pdata
->flcmncr_val
& SEL_16BIT
) {
925 nand
->options
|= NAND_BUSWIDTH_16
;
926 nand
->read_word
= flctl_read_word
;
929 pm_runtime_enable(&pdev
->dev
);
930 pm_runtime_resume(&pdev
->dev
);
932 ret
= nand_scan_ident(flctl_mtd
, 1, NULL
);
936 ret
= flctl_chip_init_tail(flctl_mtd
);
940 ret
= nand_scan_tail(flctl_mtd
);
944 mtd_device_register(flctl_mtd
, pdata
->parts
, pdata
->nr_parts
);
949 pm_runtime_disable(&pdev
->dev
);
950 free_irq(irq
, flctl
);
958 static int __devexit
flctl_remove(struct platform_device
*pdev
)
960 struct sh_flctl
*flctl
= platform_get_drvdata(pdev
);
962 nand_release(&flctl
->mtd
);
963 pm_runtime_disable(&pdev
->dev
);
964 free_irq(platform_get_irq(pdev
, 0), flctl
);
971 static struct platform_driver flctl_driver
= {
972 .remove
= flctl_remove
,
975 .owner
= THIS_MODULE
,
979 static int __init
flctl_nand_init(void)
981 return platform_driver_probe(&flctl_driver
, flctl_probe
);
984 static void __exit
flctl_nand_cleanup(void)
986 platform_driver_unregister(&flctl_driver
);
989 module_init(flctl_nand_init
);
990 module_exit(flctl_nand_cleanup
);
992 MODULE_LICENSE("GPL");
993 MODULE_AUTHOR("Yoshihiro Shimoda");
994 MODULE_DESCRIPTION("SuperH FLCTL driver");
995 MODULE_ALIAS("platform:sh_flctl");