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[deliverable/linux.git] / drivers / mtd / nand / sunxi_nand.c
1 /*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
3 *
4 * Derived from:
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
7 *
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
10 *
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mtd.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/clk.h>
38 #include <linux/delay.h>
39 #include <linux/dmaengine.h>
40 #include <linux/gpio.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43
44 #define NFC_REG_CTL 0x0000
45 #define NFC_REG_ST 0x0004
46 #define NFC_REG_INT 0x0008
47 #define NFC_REG_TIMING_CTL 0x000C
48 #define NFC_REG_TIMING_CFG 0x0010
49 #define NFC_REG_ADDR_LOW 0x0014
50 #define NFC_REG_ADDR_HIGH 0x0018
51 #define NFC_REG_SECTOR_NUM 0x001C
52 #define NFC_REG_CNT 0x0020
53 #define NFC_REG_CMD 0x0024
54 #define NFC_REG_RCMD_SET 0x0028
55 #define NFC_REG_WCMD_SET 0x002C
56 #define NFC_REG_IO_DATA 0x0030
57 #define NFC_REG_ECC_CTL 0x0034
58 #define NFC_REG_ECC_ST 0x0038
59 #define NFC_REG_DEBUG 0x003C
60 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
61 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
62 #define NFC_REG_SPARE_AREA 0x00A0
63 #define NFC_RAM0_BASE 0x0400
64 #define NFC_RAM1_BASE 0x0800
65
66 /* define bit use in NFC_CTL */
67 #define NFC_EN BIT(0)
68 #define NFC_RESET BIT(1)
69 #define NFC_BUS_WIDTH_MSK BIT(2)
70 #define NFC_BUS_WIDTH_8 (0 << 2)
71 #define NFC_BUS_WIDTH_16 (1 << 2)
72 #define NFC_RB_SEL_MSK BIT(3)
73 #define NFC_RB_SEL(x) ((x) << 3)
74 #define NFC_CE_SEL_MSK GENMASK(26, 24)
75 #define NFC_CE_SEL(x) ((x) << 24)
76 #define NFC_CE_CTL BIT(6)
77 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
79 #define NFC_SAM BIT(12)
80 #define NFC_RAM_METHOD BIT(14)
81 #define NFC_DEBUG_CTL BIT(31)
82
83 /* define bit use in NFC_ST */
84 #define NFC_RB_B2R BIT(0)
85 #define NFC_CMD_INT_FLAG BIT(1)
86 #define NFC_DMA_INT_FLAG BIT(2)
87 #define NFC_CMD_FIFO_STATUS BIT(3)
88 #define NFC_STA BIT(4)
89 #define NFC_NATCH_INT_FLAG BIT(5)
90 #define NFC_RB_STATE(x) BIT(x + 8)
91
92 /* define bit use in NFC_INT */
93 #define NFC_B2R_INT_ENABLE BIT(0)
94 #define NFC_CMD_INT_ENABLE BIT(1)
95 #define NFC_DMA_INT_ENABLE BIT(2)
96 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
98 NFC_DMA_INT_ENABLE)
99
100 /* define bit use in NFC_TIMING_CTL */
101 #define NFC_TIMING_CTL_EDO BIT(8)
102
103 /* define NFC_TIMING_CFG register layout */
104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
108
109 /* define bit use in NFC_CMD */
110 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
112 #define NFC_CMD(x) (x)
113 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
127 #define NFC_NORMAL_OP (0 << 30)
128 #define NFC_ECC_OP (1 << 30)
129 #define NFC_PAGE_OP (2 << 30)
130
131 /* define bit use in NFC_RCMD_SET */
132 #define NFC_READ_CMD_MSK GENMASK(7, 0)
133 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
135
136 /* define bit use in NFC_WCMD_SET */
137 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
138 #define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
139 #define NFC_READ_CMD0_MSK GENMASK(23, 16)
140 #define NFC_READ_CMD1_MSK GENMASK(31, 24)
141
142 /* define bit use in NFC_ECC_CTL */
143 #define NFC_ECC_EN BIT(0)
144 #define NFC_ECC_PIPELINE BIT(3)
145 #define NFC_ECC_EXCEPTION BIT(4)
146 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
147 #define NFC_RANDOM_EN BIT(9)
148 #define NFC_RANDOM_DIRECTION BIT(10)
149 #define NFC_ECC_MODE_MSK GENMASK(15, 12)
150 #define NFC_ECC_MODE(x) ((x) << 12)
151 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
152 #define NFC_RANDOM_SEED(x) ((x) << 16)
153
154 /* define bit use in NFC_ECC_ST */
155 #define NFC_ECC_ERR(x) BIT(x)
156 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
157 #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
158
159 /* NFC_USER_DATA helper macros */
160 #define NFC_BUF_TO_USER_DATA(buf) ((buf)[0] | ((buf)[1] << 8) | \
161 ((buf)[2] << 16) | ((buf)[3] << 24))
162
163 #define NFC_DEFAULT_TIMEOUT_MS 1000
164
165 #define NFC_SRAM_SIZE 1024
166
167 #define NFC_MAX_CS 7
168
169 /*
170 * Ready/Busy detection type: describes the Ready/Busy detection modes
171 *
172 * @RB_NONE: no external detection available, rely on STATUS command
173 * and software timeouts
174 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
175 * pin of the NAND flash chip must be connected to one of the
176 * native NAND R/B pins (those which can be muxed to the NAND
177 * Controller)
178 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
179 * pin of the NAND flash chip must be connected to a GPIO capable
180 * pin.
181 */
182 enum sunxi_nand_rb_type {
183 RB_NONE,
184 RB_NATIVE,
185 RB_GPIO,
186 };
187
188 /*
189 * Ready/Busy structure: stores information related to Ready/Busy detection
190 *
191 * @type: the Ready/Busy detection mode
192 * @info: information related to the R/B detection mode. Either a gpio
193 * id or a native R/B id (those supported by the NAND controller).
194 */
195 struct sunxi_nand_rb {
196 enum sunxi_nand_rb_type type;
197 union {
198 int gpio;
199 int nativeid;
200 } info;
201 };
202
203 /*
204 * Chip Select structure: stores information related to NAND Chip Select
205 *
206 * @cs: the NAND CS id used to communicate with a NAND Chip
207 * @rb: the Ready/Busy description
208 */
209 struct sunxi_nand_chip_sel {
210 u8 cs;
211 struct sunxi_nand_rb rb;
212 };
213
214 /*
215 * sunxi HW ECC infos: stores information related to HW ECC support
216 *
217 * @mode: the sunxi ECC mode field deduced from ECC requirements
218 * @layout: the OOB layout depending on the ECC requirements and the
219 * selected ECC mode
220 */
221 struct sunxi_nand_hw_ecc {
222 int mode;
223 struct nand_ecclayout layout;
224 };
225
226 /*
227 * NAND chip structure: stores NAND chip device related information
228 *
229 * @node: used to store NAND chips into a list
230 * @nand: base NAND chip structure
231 * @mtd: base MTD structure
232 * @clk_rate: clk_rate required for this NAND chip
233 * @timing_cfg TIMING_CFG register value for this NAND chip
234 * @selected: current active CS
235 * @nsels: number of CS lines required by the NAND chip
236 * @sels: array of CS lines descriptions
237 */
238 struct sunxi_nand_chip {
239 struct list_head node;
240 struct nand_chip nand;
241 struct mtd_info mtd;
242 unsigned long clk_rate;
243 u32 timing_cfg;
244 u32 timing_ctl;
245 int selected;
246 int nsels;
247 struct sunxi_nand_chip_sel sels[0];
248 };
249
250 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
251 {
252 return container_of(nand, struct sunxi_nand_chip, nand);
253 }
254
255 /*
256 * NAND Controller structure: stores sunxi NAND controller information
257 *
258 * @controller: base controller structure
259 * @dev: parent device (used to print error messages)
260 * @regs: NAND controller registers
261 * @ahb_clk: NAND Controller AHB clock
262 * @mod_clk: NAND Controller mod clock
263 * @assigned_cs: bitmask describing already assigned CS lines
264 * @clk_rate: NAND controller current clock rate
265 * @chips: a list containing all the NAND chips attached to
266 * this NAND controller
267 * @complete: a completion object used to wait for NAND
268 * controller events
269 */
270 struct sunxi_nfc {
271 struct nand_hw_control controller;
272 struct device *dev;
273 void __iomem *regs;
274 struct clk *ahb_clk;
275 struct clk *mod_clk;
276 unsigned long assigned_cs;
277 unsigned long clk_rate;
278 struct list_head chips;
279 struct completion complete;
280 };
281
282 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
283 {
284 return container_of(ctrl, struct sunxi_nfc, controller);
285 }
286
287 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
288 {
289 struct sunxi_nfc *nfc = dev_id;
290 u32 st = readl(nfc->regs + NFC_REG_ST);
291 u32 ien = readl(nfc->regs + NFC_REG_INT);
292
293 if (!(ien & st))
294 return IRQ_NONE;
295
296 if ((ien & st) == ien)
297 complete(&nfc->complete);
298
299 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
300 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
301
302 return IRQ_HANDLED;
303 }
304
305 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
306 unsigned int timeout_ms)
307 {
308 init_completion(&nfc->complete);
309
310 writel(flags, nfc->regs + NFC_REG_INT);
311
312 if (!timeout_ms)
313 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
314
315 if (!wait_for_completion_timeout(&nfc->complete,
316 msecs_to_jiffies(timeout_ms))) {
317 dev_err(nfc->dev, "wait interrupt timedout\n");
318 return -ETIMEDOUT;
319 }
320
321 return 0;
322 }
323
324 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
325 {
326 unsigned long timeout = jiffies +
327 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
328
329 do {
330 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
331 return 0;
332 } while (time_before(jiffies, timeout));
333
334 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
335 return -ETIMEDOUT;
336 }
337
338 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
339 {
340 unsigned long timeout = jiffies +
341 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
342
343 writel(0, nfc->regs + NFC_REG_ECC_CTL);
344 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
345
346 do {
347 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
348 return 0;
349 } while (time_before(jiffies, timeout));
350
351 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
352 return -ETIMEDOUT;
353 }
354
355 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
356 {
357 struct nand_chip *nand = mtd->priv;
358 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
359 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
360 struct sunxi_nand_rb *rb;
361 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
362 int ret;
363
364 if (sunxi_nand->selected < 0)
365 return 0;
366
367 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
368
369 switch (rb->type) {
370 case RB_NATIVE:
371 ret = !!(readl(nfc->regs + NFC_REG_ST) &
372 NFC_RB_STATE(rb->info.nativeid));
373 if (ret)
374 break;
375
376 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
377 ret = !!(readl(nfc->regs + NFC_REG_ST) &
378 NFC_RB_STATE(rb->info.nativeid));
379 break;
380 case RB_GPIO:
381 ret = gpio_get_value(rb->info.gpio);
382 break;
383 case RB_NONE:
384 default:
385 ret = 0;
386 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
387 break;
388 }
389
390 return ret;
391 }
392
393 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
394 {
395 struct nand_chip *nand = mtd->priv;
396 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
397 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
398 struct sunxi_nand_chip_sel *sel;
399 u32 ctl;
400
401 if (chip > 0 && chip >= sunxi_nand->nsels)
402 return;
403
404 if (chip == sunxi_nand->selected)
405 return;
406
407 ctl = readl(nfc->regs + NFC_REG_CTL) &
408 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
409
410 if (chip >= 0) {
411 sel = &sunxi_nand->sels[chip];
412
413 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
414 NFC_PAGE_SHIFT(nand->page_shift - 10);
415 if (sel->rb.type == RB_NONE) {
416 nand->dev_ready = NULL;
417 } else {
418 nand->dev_ready = sunxi_nfc_dev_ready;
419 if (sel->rb.type == RB_NATIVE)
420 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
421 }
422
423 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
424
425 if (nfc->clk_rate != sunxi_nand->clk_rate) {
426 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
427 nfc->clk_rate = sunxi_nand->clk_rate;
428 }
429 }
430
431 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
432 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
433 writel(ctl, nfc->regs + NFC_REG_CTL);
434
435 sunxi_nand->selected = chip;
436 }
437
438 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
439 {
440 struct nand_chip *nand = mtd->priv;
441 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
442 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
443 int ret;
444 int cnt;
445 int offs = 0;
446 u32 tmp;
447
448 while (len > offs) {
449 cnt = min(len - offs, NFC_SRAM_SIZE);
450
451 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
452 if (ret)
453 break;
454
455 writel(cnt, nfc->regs + NFC_REG_CNT);
456 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
457 writel(tmp, nfc->regs + NFC_REG_CMD);
458
459 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
460 if (ret)
461 break;
462
463 if (buf)
464 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
465 cnt);
466 offs += cnt;
467 }
468 }
469
470 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
471 int len)
472 {
473 struct nand_chip *nand = mtd->priv;
474 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
475 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
476 int ret;
477 int cnt;
478 int offs = 0;
479 u32 tmp;
480
481 while (len > offs) {
482 cnt = min(len - offs, NFC_SRAM_SIZE);
483
484 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
485 if (ret)
486 break;
487
488 writel(cnt, nfc->regs + NFC_REG_CNT);
489 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
490 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
491 NFC_ACCESS_DIR;
492 writel(tmp, nfc->regs + NFC_REG_CMD);
493
494 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
495 if (ret)
496 break;
497
498 offs += cnt;
499 }
500 }
501
502 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
503 {
504 uint8_t ret;
505
506 sunxi_nfc_read_buf(mtd, &ret, 1);
507
508 return ret;
509 }
510
511 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
512 unsigned int ctrl)
513 {
514 struct nand_chip *nand = mtd->priv;
515 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
516 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
517 int ret;
518 u32 tmp;
519
520 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
521 if (ret)
522 return;
523
524 if (ctrl & NAND_CTRL_CHANGE) {
525 tmp = readl(nfc->regs + NFC_REG_CTL);
526 if (ctrl & NAND_NCE)
527 tmp |= NFC_CE_CTL;
528 else
529 tmp &= ~NFC_CE_CTL;
530 writel(tmp, nfc->regs + NFC_REG_CTL);
531 }
532
533 if (dat == NAND_CMD_NONE)
534 return;
535
536 if (ctrl & NAND_CLE) {
537 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
538 } else {
539 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
540 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
541 }
542
543 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
544 }
545
546 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
547 {
548 struct nand_chip *nand = mtd->priv;
549 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
550 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
551 u32 ecc_ctl;
552
553 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
554 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
555 NFC_ECC_BLOCK_SIZE_MSK);
556 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
557
558 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
559 }
560
561 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
562 {
563 struct nand_chip *nand = mtd->priv;
564 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
565
566 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
567 nfc->regs + NFC_REG_ECC_CTL);
568 }
569
570 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
571 u8 *data, int data_off,
572 u8 *oob, int oob_off,
573 int *cur_off,
574 unsigned int *max_bitflips)
575 {
576 struct nand_chip *nand = mtd->priv;
577 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
578 struct nand_ecc_ctrl *ecc = &nand->ecc;
579 u32 status;
580 int ret;
581
582 if (*cur_off != data_off)
583 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
584
585 sunxi_nfc_read_buf(mtd, data, ecc->size);
586
587 if (data_off + ecc->bytes != oob_off)
588 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
589
590 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
591 if (ret)
592 return ret;
593
594 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
595 nfc->regs + NFC_REG_CMD);
596
597 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
598 if (ret)
599 return ret;
600
601 status = readl(nfc->regs + NFC_REG_ECC_ST);
602 ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
603
604 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
605
606 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
607 sunxi_nfc_read_buf(mtd, oob, ecc->bytes + 4);
608
609 if (status & NFC_ECC_ERR(0))
610 ret = -EIO;
611
612 if (ret < 0) {
613 mtd->ecc_stats.failed++;
614 } else {
615 mtd->ecc_stats.corrected += ret;
616 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
617 }
618
619 *cur_off = oob_off + ecc->bytes + 4;
620
621 return 0;
622 }
623
624 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
625 u8 *oob, int *cur_off)
626 {
627 struct nand_chip *nand = mtd->priv;
628 struct nand_ecc_ctrl *ecc = &nand->ecc;
629 int offset = ((ecc->bytes + 4) * ecc->steps);
630 int len = mtd->oobsize - offset;
631
632 if (len <= 0)
633 return;
634
635 if (*cur_off != offset)
636 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
637 offset + mtd->writesize, -1);
638
639 sunxi_nfc_read_buf(mtd, oob + offset, len);
640
641 *cur_off = mtd->oobsize + mtd->writesize;
642 }
643
644 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
645 const u8 *data, int data_off,
646 const u8 *oob, int oob_off,
647 int *cur_off)
648 {
649 struct nand_chip *nand = mtd->priv;
650 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
651 struct nand_ecc_ctrl *ecc = &nand->ecc;
652 int ret;
653
654 if (data_off != *cur_off)
655 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
656
657 sunxi_nfc_write_buf(mtd, data, ecc->size);
658
659 /* Fill OOB data in */
660 writel(NFC_BUF_TO_USER_DATA(oob), nfc->regs + NFC_REG_USER_DATA(0));
661
662 if (data_off + ecc->bytes != oob_off)
663 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
664
665 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
666 if (ret)
667 return ret;
668
669 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
670 NFC_ACCESS_DIR | NFC_ECC_OP,
671 nfc->regs + NFC_REG_CMD);
672
673 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
674 if (ret)
675 return ret;
676
677 *cur_off = oob_off + ecc->bytes + 4;
678
679 return 0;
680 }
681
682 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
683 u8 *oob, int *cur_off)
684 {
685 struct nand_chip *nand = mtd->priv;
686 struct nand_ecc_ctrl *ecc = &nand->ecc;
687 int offset = ((ecc->bytes + 4) * ecc->steps);
688 int len = mtd->oobsize - offset;
689
690 if (len <= 0)
691 return;
692
693 if (*cur_off != offset)
694 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
695 offset + mtd->writesize, -1);
696
697 sunxi_nfc_write_buf(mtd, oob + offset, len);
698
699 *cur_off = mtd->oobsize + mtd->writesize;
700 }
701
702 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
703 struct nand_chip *chip, uint8_t *buf,
704 int oob_required, int page)
705 {
706 struct nand_ecc_ctrl *ecc = &chip->ecc;
707 unsigned int max_bitflips = 0;
708 int ret, i, cur_off = 0;
709
710 sunxi_nfc_hw_ecc_enable(mtd);
711
712 for (i = 0; i < ecc->steps; i++) {
713 int data_off = i * ecc->size;
714 int oob_off = i * (ecc->bytes + 4);
715 u8 *data = buf + data_off;
716 u8 *oob = chip->oob_poi + oob_off;
717
718 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
719 oob_off + mtd->writesize,
720 &cur_off, &max_bitflips);
721 if (ret)
722 return ret;
723 }
724
725 if (oob_required)
726 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
727
728 sunxi_nfc_hw_ecc_disable(mtd);
729
730 return max_bitflips;
731 }
732
733 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
734 struct nand_chip *chip,
735 const uint8_t *buf, int oob_required)
736 {
737 struct nand_ecc_ctrl *ecc = &chip->ecc;
738 int ret, i, cur_off = 0;
739
740 sunxi_nfc_hw_ecc_enable(mtd);
741
742 for (i = 0; i < ecc->steps; i++) {
743 int data_off = i * ecc->size;
744 int oob_off = i * (ecc->bytes + 4);
745 const u8 *data = buf + data_off;
746 const u8 *oob = chip->oob_poi + oob_off;
747
748 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
749 oob_off + mtd->writesize,
750 &cur_off);
751 if (ret)
752 return ret;
753 }
754
755 if (oob_required)
756 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
757
758 sunxi_nfc_hw_ecc_disable(mtd);
759
760 return 0;
761 }
762
763 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
764 struct nand_chip *chip,
765 uint8_t *buf, int oob_required,
766 int page)
767 {
768 struct nand_ecc_ctrl *ecc = &chip->ecc;
769 unsigned int max_bitflips = 0;
770 int ret, i, cur_off = 0;
771
772 sunxi_nfc_hw_ecc_enable(mtd);
773
774 for (i = 0; i < ecc->steps; i++) {
775 int data_off = i * (ecc->size + ecc->bytes + 4);
776 int oob_off = data_off + ecc->size;
777 u8 *data = buf + (i * ecc->size);
778 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
779
780 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
781 oob_off, &cur_off,
782 &max_bitflips);
783 if (ret)
784 return ret;
785 }
786
787 if (oob_required)
788 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
789
790 sunxi_nfc_hw_ecc_disable(mtd);
791
792 return max_bitflips;
793 }
794
795 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
796 struct nand_chip *chip,
797 const uint8_t *buf,
798 int oob_required)
799 {
800 struct nand_ecc_ctrl *ecc = &chip->ecc;
801 int ret, i, cur_off = 0;
802
803 sunxi_nfc_hw_ecc_enable(mtd);
804
805 for (i = 0; i < ecc->steps; i++) {
806 int data_off = i * (ecc->size + ecc->bytes + 4);
807 int oob_off = data_off + ecc->size;
808 const u8 *data = buf + (i * ecc->size);
809 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
810
811 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
812 oob, oob_off, &cur_off);
813 if (ret)
814 return ret;
815 }
816
817 if (oob_required)
818 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
819
820 sunxi_nfc_hw_ecc_disable(mtd);
821
822 return 0;
823 }
824
825 static const s32 tWB_lut[] = {6, 12, 16, 20};
826 static const s32 tRHW_lut[] = {4, 8, 12, 20};
827
828 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
829 u32 clk_period)
830 {
831 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
832 int i;
833
834 for (i = 0; i < lut_size; i++) {
835 if (clk_cycles <= lut[i])
836 return i;
837 }
838
839 /* Doesn't fit */
840 return -EINVAL;
841 }
842
843 #define sunxi_nand_lookup_timing(l, p, c) \
844 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
845
846 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
847 const struct nand_sdr_timings *timings)
848 {
849 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
850 u32 min_clk_period = 0;
851 s32 tWB, tADL, tWHR, tRHW, tCAD;
852
853 /* T1 <=> tCLS */
854 if (timings->tCLS_min > min_clk_period)
855 min_clk_period = timings->tCLS_min;
856
857 /* T2 <=> tCLH */
858 if (timings->tCLH_min > min_clk_period)
859 min_clk_period = timings->tCLH_min;
860
861 /* T3 <=> tCS */
862 if (timings->tCS_min > min_clk_period)
863 min_clk_period = timings->tCS_min;
864
865 /* T4 <=> tCH */
866 if (timings->tCH_min > min_clk_period)
867 min_clk_period = timings->tCH_min;
868
869 /* T5 <=> tWP */
870 if (timings->tWP_min > min_clk_period)
871 min_clk_period = timings->tWP_min;
872
873 /* T6 <=> tWH */
874 if (timings->tWH_min > min_clk_period)
875 min_clk_period = timings->tWH_min;
876
877 /* T7 <=> tALS */
878 if (timings->tALS_min > min_clk_period)
879 min_clk_period = timings->tALS_min;
880
881 /* T8 <=> tDS */
882 if (timings->tDS_min > min_clk_period)
883 min_clk_period = timings->tDS_min;
884
885 /* T9 <=> tDH */
886 if (timings->tDH_min > min_clk_period)
887 min_clk_period = timings->tDH_min;
888
889 /* T10 <=> tRR */
890 if (timings->tRR_min > (min_clk_period * 3))
891 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
892
893 /* T11 <=> tALH */
894 if (timings->tALH_min > min_clk_period)
895 min_clk_period = timings->tALH_min;
896
897 /* T12 <=> tRP */
898 if (timings->tRP_min > min_clk_period)
899 min_clk_period = timings->tRP_min;
900
901 /* T13 <=> tREH */
902 if (timings->tREH_min > min_clk_period)
903 min_clk_period = timings->tREH_min;
904
905 /* T14 <=> tRC */
906 if (timings->tRC_min > (min_clk_period * 2))
907 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
908
909 /* T15 <=> tWC */
910 if (timings->tWC_min > (min_clk_period * 2))
911 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
912
913 /* T16 - T19 + tCAD */
914 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
915 min_clk_period);
916 if (tWB < 0) {
917 dev_err(nfc->dev, "unsupported tWB\n");
918 return tWB;
919 }
920
921 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
922 if (tADL > 3) {
923 dev_err(nfc->dev, "unsupported tADL\n");
924 return -EINVAL;
925 }
926
927 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
928 if (tWHR > 3) {
929 dev_err(nfc->dev, "unsupported tWHR\n");
930 return -EINVAL;
931 }
932
933 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
934 min_clk_period);
935 if (tRHW < 0) {
936 dev_err(nfc->dev, "unsupported tRHW\n");
937 return tRHW;
938 }
939
940 /*
941 * TODO: according to ONFI specs this value only applies for DDR NAND,
942 * but Allwinner seems to set this to 0x7. Mimic them for now.
943 */
944 tCAD = 0x7;
945
946 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
947 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
948
949 /*
950 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
951 * output cycle timings shall be used if the host drives tRC less than
952 * 30 ns.
953 */
954 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
955
956 /* Convert min_clk_period from picoseconds to nanoseconds */
957 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
958
959 /*
960 * Convert min_clk_period into a clk frequency, then get the
961 * appropriate rate for the NAND controller IP given this formula
962 * (specified in the datasheet):
963 * nand clk_rate = 2 * min_clk_rate
964 */
965 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
966
967 return 0;
968 }
969
970 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
971 struct device_node *np)
972 {
973 const struct nand_sdr_timings *timings;
974 int ret;
975 int mode;
976
977 mode = onfi_get_async_timing_mode(&chip->nand);
978 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
979 mode = chip->nand.onfi_timing_mode_default;
980 } else {
981 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
982 int i;
983
984 mode = fls(mode) - 1;
985 if (mode < 0)
986 mode = 0;
987
988 feature[0] = mode;
989 for (i = 0; i < chip->nsels; i++) {
990 chip->nand.select_chip(&chip->mtd, i);
991 ret = chip->nand.onfi_set_features(&chip->mtd,
992 &chip->nand,
993 ONFI_FEATURE_ADDR_TIMING_MODE,
994 feature);
995 chip->nand.select_chip(&chip->mtd, -1);
996 if (ret)
997 return ret;
998 }
999 }
1000
1001 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1002 if (IS_ERR(timings))
1003 return PTR_ERR(timings);
1004
1005 return sunxi_nand_chip_set_timings(chip, timings);
1006 }
1007
1008 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1009 struct nand_ecc_ctrl *ecc,
1010 struct device_node *np)
1011 {
1012 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1013 struct nand_chip *nand = mtd->priv;
1014 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1015 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1016 struct sunxi_nand_hw_ecc *data;
1017 struct nand_ecclayout *layout;
1018 int nsectors;
1019 int ret;
1020 int i;
1021
1022 data = kzalloc(sizeof(*data), GFP_KERNEL);
1023 if (!data)
1024 return -ENOMEM;
1025
1026 /* Add ECC info retrieval from DT */
1027 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1028 if (ecc->strength <= strengths[i])
1029 break;
1030 }
1031
1032 if (i >= ARRAY_SIZE(strengths)) {
1033 dev_err(nfc->dev, "unsupported strength\n");
1034 ret = -ENOTSUPP;
1035 goto err;
1036 }
1037
1038 data->mode = i;
1039
1040 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1041 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1042
1043 /* HW ECC always work with even numbers of ECC bytes */
1044 ecc->bytes = ALIGN(ecc->bytes, 2);
1045
1046 layout = &data->layout;
1047 nsectors = mtd->writesize / ecc->size;
1048
1049 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1050 ret = -EINVAL;
1051 goto err;
1052 }
1053
1054 layout->eccbytes = (ecc->bytes * nsectors);
1055
1056 ecc->layout = layout;
1057 ecc->priv = data;
1058
1059 return 0;
1060
1061 err:
1062 kfree(data);
1063
1064 return ret;
1065 }
1066
1067 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1068 {
1069 kfree(ecc->priv);
1070 }
1071
1072 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1073 struct nand_ecc_ctrl *ecc,
1074 struct device_node *np)
1075 {
1076 struct nand_ecclayout *layout;
1077 int nsectors;
1078 int i, j;
1079 int ret;
1080
1081 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1082 if (ret)
1083 return ret;
1084
1085 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1086 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1087 layout = ecc->layout;
1088 nsectors = mtd->writesize / ecc->size;
1089
1090 for (i = 0; i < nsectors; i++) {
1091 if (i) {
1092 layout->oobfree[i].offset =
1093 layout->oobfree[i - 1].offset +
1094 layout->oobfree[i - 1].length +
1095 ecc->bytes;
1096 layout->oobfree[i].length = 4;
1097 } else {
1098 /*
1099 * The first 2 bytes are used for BB markers, hence we
1100 * only have 2 bytes available in the first user data
1101 * section.
1102 */
1103 layout->oobfree[i].length = 2;
1104 layout->oobfree[i].offset = 2;
1105 }
1106
1107 for (j = 0; j < ecc->bytes; j++)
1108 layout->eccpos[(ecc->bytes * i) + j] =
1109 layout->oobfree[i].offset +
1110 layout->oobfree[i].length + j;
1111 }
1112
1113 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1114 layout->oobfree[nsectors].offset =
1115 layout->oobfree[nsectors - 1].offset +
1116 layout->oobfree[nsectors - 1].length +
1117 ecc->bytes;
1118 layout->oobfree[nsectors].length = mtd->oobsize -
1119 ((ecc->bytes + 4) * nsectors);
1120 }
1121
1122 return 0;
1123 }
1124
1125 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1126 struct nand_ecc_ctrl *ecc,
1127 struct device_node *np)
1128 {
1129 struct nand_ecclayout *layout;
1130 int nsectors;
1131 int i;
1132 int ret;
1133
1134 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1135 if (ret)
1136 return ret;
1137
1138 ecc->prepad = 4;
1139 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1140 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1141
1142 layout = ecc->layout;
1143 nsectors = mtd->writesize / ecc->size;
1144
1145 for (i = 0; i < (ecc->bytes * nsectors); i++)
1146 layout->eccpos[i] = i;
1147
1148 layout->oobfree[0].length = mtd->oobsize - i;
1149 layout->oobfree[0].offset = i;
1150
1151 return 0;
1152 }
1153
1154 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1155 {
1156 switch (ecc->mode) {
1157 case NAND_ECC_HW:
1158 case NAND_ECC_HW_SYNDROME:
1159 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1160 break;
1161 case NAND_ECC_NONE:
1162 kfree(ecc->layout);
1163 default:
1164 break;
1165 }
1166 }
1167
1168 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1169 struct device_node *np)
1170 {
1171 struct nand_chip *nand = mtd->priv;
1172 int ret;
1173
1174 if (!ecc->size) {
1175 ecc->size = nand->ecc_step_ds;
1176 ecc->strength = nand->ecc_strength_ds;
1177 }
1178
1179 if (!ecc->size || !ecc->strength)
1180 return -EINVAL;
1181
1182 switch (ecc->mode) {
1183 case NAND_ECC_SOFT_BCH:
1184 break;
1185 case NAND_ECC_HW:
1186 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1187 if (ret)
1188 return ret;
1189 break;
1190 case NAND_ECC_HW_SYNDROME:
1191 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1192 if (ret)
1193 return ret;
1194 break;
1195 case NAND_ECC_NONE:
1196 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1197 if (!ecc->layout)
1198 return -ENOMEM;
1199 ecc->layout->oobfree[0].length = mtd->oobsize;
1200 case NAND_ECC_SOFT:
1201 break;
1202 default:
1203 return -EINVAL;
1204 }
1205
1206 return 0;
1207 }
1208
1209 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1210 struct device_node *np)
1211 {
1212 const struct nand_sdr_timings *timings;
1213 struct sunxi_nand_chip *chip;
1214 struct mtd_part_parser_data ppdata;
1215 struct mtd_info *mtd;
1216 struct nand_chip *nand;
1217 int nsels;
1218 int ret;
1219 int i;
1220 u32 tmp;
1221
1222 if (!of_get_property(np, "reg", &nsels))
1223 return -EINVAL;
1224
1225 nsels /= sizeof(u32);
1226 if (!nsels) {
1227 dev_err(dev, "invalid reg property size\n");
1228 return -EINVAL;
1229 }
1230
1231 chip = devm_kzalloc(dev,
1232 sizeof(*chip) +
1233 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1234 GFP_KERNEL);
1235 if (!chip) {
1236 dev_err(dev, "could not allocate chip\n");
1237 return -ENOMEM;
1238 }
1239
1240 chip->nsels = nsels;
1241 chip->selected = -1;
1242
1243 for (i = 0; i < nsels; i++) {
1244 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1245 if (ret) {
1246 dev_err(dev, "could not retrieve reg property: %d\n",
1247 ret);
1248 return ret;
1249 }
1250
1251 if (tmp > NFC_MAX_CS) {
1252 dev_err(dev,
1253 "invalid reg value: %u (max CS = 7)\n",
1254 tmp);
1255 return -EINVAL;
1256 }
1257
1258 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1259 dev_err(dev, "CS %d already assigned\n", tmp);
1260 return -EINVAL;
1261 }
1262
1263 chip->sels[i].cs = tmp;
1264
1265 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1266 tmp < 2) {
1267 chip->sels[i].rb.type = RB_NATIVE;
1268 chip->sels[i].rb.info.nativeid = tmp;
1269 } else {
1270 ret = of_get_named_gpio(np, "rb-gpios", i);
1271 if (ret >= 0) {
1272 tmp = ret;
1273 chip->sels[i].rb.type = RB_GPIO;
1274 chip->sels[i].rb.info.gpio = tmp;
1275 ret = devm_gpio_request(dev, tmp, "nand-rb");
1276 if (ret)
1277 return ret;
1278
1279 ret = gpio_direction_input(tmp);
1280 if (ret)
1281 return ret;
1282 } else {
1283 chip->sels[i].rb.type = RB_NONE;
1284 }
1285 }
1286 }
1287
1288 timings = onfi_async_timing_mode_to_sdr_timings(0);
1289 if (IS_ERR(timings)) {
1290 ret = PTR_ERR(timings);
1291 dev_err(dev,
1292 "could not retrieve timings for ONFI mode 0: %d\n",
1293 ret);
1294 return ret;
1295 }
1296
1297 ret = sunxi_nand_chip_set_timings(chip, timings);
1298 if (ret) {
1299 dev_err(dev, "could not configure chip timings: %d\n", ret);
1300 return ret;
1301 }
1302
1303 nand = &chip->nand;
1304 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1305 nand->chip_delay = 200;
1306 nand->controller = &nfc->controller;
1307 /*
1308 * Set the ECC mode to the default value in case nothing is specified
1309 * in the DT.
1310 */
1311 nand->ecc.mode = NAND_ECC_HW;
1312 nand->flash_node = np;
1313 nand->select_chip = sunxi_nfc_select_chip;
1314 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1315 nand->read_buf = sunxi_nfc_read_buf;
1316 nand->write_buf = sunxi_nfc_write_buf;
1317 nand->read_byte = sunxi_nfc_read_byte;
1318
1319 mtd = &chip->mtd;
1320 mtd->dev.parent = dev;
1321 mtd->priv = nand;
1322 mtd->owner = THIS_MODULE;
1323
1324 ret = nand_scan_ident(mtd, nsels, NULL);
1325 if (ret)
1326 return ret;
1327
1328 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1329 nand->bbt_options |= NAND_BBT_NO_OOB;
1330
1331 ret = sunxi_nand_chip_init_timings(chip, np);
1332 if (ret) {
1333 dev_err(dev, "could not configure chip timings: %d\n", ret);
1334 return ret;
1335 }
1336
1337 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1338 if (ret) {
1339 dev_err(dev, "ECC init failed: %d\n", ret);
1340 return ret;
1341 }
1342
1343 ret = nand_scan_tail(mtd);
1344 if (ret) {
1345 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1346 return ret;
1347 }
1348
1349 ppdata.of_node = np;
1350 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1351 if (ret) {
1352 dev_err(dev, "failed to register mtd device: %d\n", ret);
1353 nand_release(mtd);
1354 return ret;
1355 }
1356
1357 list_add_tail(&chip->node, &nfc->chips);
1358
1359 return 0;
1360 }
1361
1362 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1363 {
1364 struct device_node *np = dev->of_node;
1365 struct device_node *nand_np;
1366 int nchips = of_get_child_count(np);
1367 int ret;
1368
1369 if (nchips > 8) {
1370 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1371 return -EINVAL;
1372 }
1373
1374 for_each_child_of_node(np, nand_np) {
1375 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1376 if (ret)
1377 return ret;
1378 }
1379
1380 return 0;
1381 }
1382
1383 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1384 {
1385 struct sunxi_nand_chip *chip;
1386
1387 while (!list_empty(&nfc->chips)) {
1388 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1389 node);
1390 nand_release(&chip->mtd);
1391 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1392 list_del(&chip->node);
1393 }
1394 }
1395
1396 static int sunxi_nfc_probe(struct platform_device *pdev)
1397 {
1398 struct device *dev = &pdev->dev;
1399 struct resource *r;
1400 struct sunxi_nfc *nfc;
1401 int irq;
1402 int ret;
1403
1404 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1405 if (!nfc)
1406 return -ENOMEM;
1407
1408 nfc->dev = dev;
1409 spin_lock_init(&nfc->controller.lock);
1410 init_waitqueue_head(&nfc->controller.wq);
1411 INIT_LIST_HEAD(&nfc->chips);
1412
1413 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1414 nfc->regs = devm_ioremap_resource(dev, r);
1415 if (IS_ERR(nfc->regs))
1416 return PTR_ERR(nfc->regs);
1417
1418 irq = platform_get_irq(pdev, 0);
1419 if (irq < 0) {
1420 dev_err(dev, "failed to retrieve irq\n");
1421 return irq;
1422 }
1423
1424 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1425 if (IS_ERR(nfc->ahb_clk)) {
1426 dev_err(dev, "failed to retrieve ahb clk\n");
1427 return PTR_ERR(nfc->ahb_clk);
1428 }
1429
1430 ret = clk_prepare_enable(nfc->ahb_clk);
1431 if (ret)
1432 return ret;
1433
1434 nfc->mod_clk = devm_clk_get(dev, "mod");
1435 if (IS_ERR(nfc->mod_clk)) {
1436 dev_err(dev, "failed to retrieve mod clk\n");
1437 ret = PTR_ERR(nfc->mod_clk);
1438 goto out_ahb_clk_unprepare;
1439 }
1440
1441 ret = clk_prepare_enable(nfc->mod_clk);
1442 if (ret)
1443 goto out_ahb_clk_unprepare;
1444
1445 ret = sunxi_nfc_rst(nfc);
1446 if (ret)
1447 goto out_mod_clk_unprepare;
1448
1449 writel(0, nfc->regs + NFC_REG_INT);
1450 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1451 0, "sunxi-nand", nfc);
1452 if (ret)
1453 goto out_mod_clk_unprepare;
1454
1455 platform_set_drvdata(pdev, nfc);
1456
1457 ret = sunxi_nand_chips_init(dev, nfc);
1458 if (ret) {
1459 dev_err(dev, "failed to init nand chips\n");
1460 goto out_mod_clk_unprepare;
1461 }
1462
1463 return 0;
1464
1465 out_mod_clk_unprepare:
1466 clk_disable_unprepare(nfc->mod_clk);
1467 out_ahb_clk_unprepare:
1468 clk_disable_unprepare(nfc->ahb_clk);
1469
1470 return ret;
1471 }
1472
1473 static int sunxi_nfc_remove(struct platform_device *pdev)
1474 {
1475 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1476
1477 sunxi_nand_chips_cleanup(nfc);
1478
1479 return 0;
1480 }
1481
1482 static const struct of_device_id sunxi_nfc_ids[] = {
1483 { .compatible = "allwinner,sun4i-a10-nand" },
1484 { /* sentinel */ }
1485 };
1486 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1487
1488 static struct platform_driver sunxi_nfc_driver = {
1489 .driver = {
1490 .name = "sunxi_nand",
1491 .of_match_table = sunxi_nfc_ids,
1492 },
1493 .probe = sunxi_nfc_probe,
1494 .remove = sunxi_nfc_remove,
1495 };
1496 module_platform_driver(sunxi_nfc_driver);
1497
1498 MODULE_LICENSE("GPL v2");
1499 MODULE_AUTHOR("Boris BREZILLON");
1500 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1501 MODULE_ALIAS("platform:sunxi_nand");
Linux kernel - Deliverables
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