2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/clk.h>
37 #include <linux/delay.h>
38 #include <linux/dmaengine.h>
39 #include <linux/gpio.h>
40 #include <linux/interrupt.h>
41 #include <linux/iopoll.h>
43 #define NFC_REG_CTL 0x0000
44 #define NFC_REG_ST 0x0004
45 #define NFC_REG_INT 0x0008
46 #define NFC_REG_TIMING_CTL 0x000C
47 #define NFC_REG_TIMING_CFG 0x0010
48 #define NFC_REG_ADDR_LOW 0x0014
49 #define NFC_REG_ADDR_HIGH 0x0018
50 #define NFC_REG_SECTOR_NUM 0x001C
51 #define NFC_REG_CNT 0x0020
52 #define NFC_REG_CMD 0x0024
53 #define NFC_REG_RCMD_SET 0x0028
54 #define NFC_REG_WCMD_SET 0x002C
55 #define NFC_REG_IO_DATA 0x0030
56 #define NFC_REG_ECC_CTL 0x0034
57 #define NFC_REG_ECC_ST 0x0038
58 #define NFC_REG_DEBUG 0x003C
59 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
60 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
61 #define NFC_REG_SPARE_AREA 0x00A0
62 #define NFC_REG_PAT_ID 0x00A4
63 #define NFC_RAM0_BASE 0x0400
64 #define NFC_RAM1_BASE 0x0800
66 /* define bit use in NFC_CTL */
68 #define NFC_RESET BIT(1)
69 #define NFC_BUS_WIDTH_MSK BIT(2)
70 #define NFC_BUS_WIDTH_8 (0 << 2)
71 #define NFC_BUS_WIDTH_16 (1 << 2)
72 #define NFC_RB_SEL_MSK BIT(3)
73 #define NFC_RB_SEL(x) ((x) << 3)
74 #define NFC_CE_SEL_MSK GENMASK(26, 24)
75 #define NFC_CE_SEL(x) ((x) << 24)
76 #define NFC_CE_CTL BIT(6)
77 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
79 #define NFC_SAM BIT(12)
80 #define NFC_RAM_METHOD BIT(14)
81 #define NFC_DEBUG_CTL BIT(31)
83 /* define bit use in NFC_ST */
84 #define NFC_RB_B2R BIT(0)
85 #define NFC_CMD_INT_FLAG BIT(1)
86 #define NFC_DMA_INT_FLAG BIT(2)
87 #define NFC_CMD_FIFO_STATUS BIT(3)
88 #define NFC_STA BIT(4)
89 #define NFC_NATCH_INT_FLAG BIT(5)
90 #define NFC_RB_STATE(x) BIT(x + 8)
92 /* define bit use in NFC_INT */
93 #define NFC_B2R_INT_ENABLE BIT(0)
94 #define NFC_CMD_INT_ENABLE BIT(1)
95 #define NFC_DMA_INT_ENABLE BIT(2)
96 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
100 /* define bit use in NFC_TIMING_CTL */
101 #define NFC_TIMING_CTL_EDO BIT(8)
103 /* define NFC_TIMING_CFG register layout */
104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
109 /* define bit use in NFC_CMD */
110 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
112 #define NFC_CMD(x) (x)
113 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
127 #define NFC_NORMAL_OP (0 << 30)
128 #define NFC_ECC_OP (1 << 30)
129 #define NFC_PAGE_OP (2 << 30)
131 /* define bit use in NFC_RCMD_SET */
132 #define NFC_READ_CMD_MSK GENMASK(7, 0)
133 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
136 /* define bit use in NFC_WCMD_SET */
137 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
138 #define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
139 #define NFC_READ_CMD0_MSK GENMASK(23, 16)
140 #define NFC_READ_CMD1_MSK GENMASK(31, 24)
142 /* define bit use in NFC_ECC_CTL */
143 #define NFC_ECC_EN BIT(0)
144 #define NFC_ECC_PIPELINE BIT(3)
145 #define NFC_ECC_EXCEPTION BIT(4)
146 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
147 #define NFC_RANDOM_EN BIT(9)
148 #define NFC_RANDOM_DIRECTION BIT(10)
149 #define NFC_ECC_MODE_MSK GENMASK(15, 12)
150 #define NFC_ECC_MODE(x) ((x) << 12)
151 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
152 #define NFC_RANDOM_SEED(x) ((x) << 16)
154 /* define bit use in NFC_ECC_ST */
155 #define NFC_ECC_ERR(x) BIT(x)
156 #define NFC_ECC_ERR_MSK GENMASK(15, 0)
157 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
158 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff)
160 #define NFC_DEFAULT_TIMEOUT_MS 1000
162 #define NFC_SRAM_SIZE 1024
167 * Ready/Busy detection type: describes the Ready/Busy detection modes
169 * @RB_NONE: no external detection available, rely on STATUS command
170 * and software timeouts
171 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
172 * pin of the NAND flash chip must be connected to one of the
173 * native NAND R/B pins (those which can be muxed to the NAND
175 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
176 * pin of the NAND flash chip must be connected to a GPIO capable
179 enum sunxi_nand_rb_type
{
186 * Ready/Busy structure: stores information related to Ready/Busy detection
188 * @type: the Ready/Busy detection mode
189 * @info: information related to the R/B detection mode. Either a gpio
190 * id or a native R/B id (those supported by the NAND controller).
192 struct sunxi_nand_rb
{
193 enum sunxi_nand_rb_type type
;
201 * Chip Select structure: stores information related to NAND Chip Select
203 * @cs: the NAND CS id used to communicate with a NAND Chip
204 * @rb: the Ready/Busy description
206 struct sunxi_nand_chip_sel
{
208 struct sunxi_nand_rb rb
;
212 * sunxi HW ECC infos: stores information related to HW ECC support
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
216 struct sunxi_nand_hw_ecc
{
221 * NAND chip structure: stores NAND chip device related information
223 * @node: used to store NAND chips into a list
224 * @nand: base NAND chip structure
225 * @mtd: base MTD structure
226 * @clk_rate: clk_rate required for this NAND chip
227 * @timing_cfg TIMING_CFG register value for this NAND chip
228 * @selected: current active CS
229 * @nsels: number of CS lines required by the NAND chip
230 * @sels: array of CS lines descriptions
232 struct sunxi_nand_chip
{
233 struct list_head node
;
234 struct nand_chip nand
;
235 unsigned long clk_rate
;
244 struct sunxi_nand_chip_sel sels
[0];
247 static inline struct sunxi_nand_chip
*to_sunxi_nand(struct nand_chip
*nand
)
249 return container_of(nand
, struct sunxi_nand_chip
, nand
);
253 * NAND Controller structure: stores sunxi NAND controller information
255 * @controller: base controller structure
256 * @dev: parent device (used to print error messages)
257 * @regs: NAND controller registers
258 * @ahb_clk: NAND Controller AHB clock
259 * @mod_clk: NAND Controller mod clock
260 * @assigned_cs: bitmask describing already assigned CS lines
261 * @clk_rate: NAND controller current clock rate
262 * @chips: a list containing all the NAND chips attached to
263 * this NAND controller
264 * @complete: a completion object used to wait for NAND
268 struct nand_hw_control controller
;
273 unsigned long assigned_cs
;
274 unsigned long clk_rate
;
275 struct list_head chips
;
276 struct completion complete
;
277 struct dma_chan
*dmac
;
280 static inline struct sunxi_nfc
*to_sunxi_nfc(struct nand_hw_control
*ctrl
)
282 return container_of(ctrl
, struct sunxi_nfc
, controller
);
285 static irqreturn_t
sunxi_nfc_interrupt(int irq
, void *dev_id
)
287 struct sunxi_nfc
*nfc
= dev_id
;
288 u32 st
= readl(nfc
->regs
+ NFC_REG_ST
);
289 u32 ien
= readl(nfc
->regs
+ NFC_REG_INT
);
294 if ((ien
& st
) == ien
)
295 complete(&nfc
->complete
);
297 writel(st
& NFC_INT_MASK
, nfc
->regs
+ NFC_REG_ST
);
298 writel(~st
& ien
& NFC_INT_MASK
, nfc
->regs
+ NFC_REG_INT
);
303 static int sunxi_nfc_wait_events(struct sunxi_nfc
*nfc
, u32 events
,
304 bool use_polling
, unsigned int timeout_ms
)
308 if (events
& ~NFC_INT_MASK
)
312 timeout_ms
= NFC_DEFAULT_TIMEOUT_MS
;
315 init_completion(&nfc
->complete
);
317 writel(events
, nfc
->regs
+ NFC_REG_INT
);
319 ret
= wait_for_completion_timeout(&nfc
->complete
,
320 msecs_to_jiffies(timeout_ms
));
322 writel(0, nfc
->regs
+ NFC_REG_INT
);
326 ret
= readl_poll_timeout(nfc
->regs
+ NFC_REG_ST
, status
,
327 (status
& events
) == events
, 1,
331 writel(events
& NFC_INT_MASK
, nfc
->regs
+ NFC_REG_ST
);
334 dev_err(nfc
->dev
, "wait interrupt timedout\n");
339 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc
*nfc
)
344 ret
= readl_poll_timeout(nfc
->regs
+ NFC_REG_ST
, status
,
345 !(status
& NFC_CMD_FIFO_STATUS
), 1,
346 NFC_DEFAULT_TIMEOUT_MS
* 1000);
348 dev_err(nfc
->dev
, "wait for empty cmd FIFO timedout\n");
353 static int sunxi_nfc_rst(struct sunxi_nfc
*nfc
)
358 writel(0, nfc
->regs
+ NFC_REG_ECC_CTL
);
359 writel(NFC_RESET
, nfc
->regs
+ NFC_REG_CTL
);
361 ret
= readl_poll_timeout(nfc
->regs
+ NFC_REG_CTL
, ctl
,
362 !(ctl
& NFC_RESET
), 1,
363 NFC_DEFAULT_TIMEOUT_MS
* 1000);
365 dev_err(nfc
->dev
, "wait for NAND controller reset timedout\n");
370 static int sunxi_nfc_dma_op_prepare(struct mtd_info
*mtd
, const void *buf
,
371 int chunksize
, int nchunks
,
372 enum dma_data_direction ddir
,
373 struct scatterlist
*sg
)
375 struct nand_chip
*nand
= mtd_to_nand(mtd
);
376 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
377 struct dma_async_tx_descriptor
*dmad
;
378 enum dma_transfer_direction tdir
;
382 if (ddir
== DMA_FROM_DEVICE
)
383 tdir
= DMA_DEV_TO_MEM
;
385 tdir
= DMA_MEM_TO_DEV
;
387 sg_init_one(sg
, buf
, nchunks
* chunksize
);
388 ret
= dma_map_sg(nfc
->dev
, sg
, 1, ddir
);
392 dmad
= dmaengine_prep_slave_sg(nfc
->dmac
, sg
, 1, tdir
, DMA_CTRL_ACK
);
398 writel(readl(nfc
->regs
+ NFC_REG_CTL
) | NFC_RAM_METHOD
,
399 nfc
->regs
+ NFC_REG_CTL
);
400 writel(nchunks
, nfc
->regs
+ NFC_REG_SECTOR_NUM
);
401 writel(chunksize
, nfc
->regs
+ NFC_REG_CNT
);
402 dmat
= dmaengine_submit(dmad
);
404 ret
= dma_submit_error(dmat
);
406 goto err_clr_dma_flag
;
411 writel(readl(nfc
->regs
+ NFC_REG_CTL
) & ~NFC_RAM_METHOD
,
412 nfc
->regs
+ NFC_REG_CTL
);
415 dma_unmap_sg(nfc
->dev
, sg
, 1, ddir
);
419 static void sunxi_nfc_dma_op_cleanup(struct mtd_info
*mtd
,
420 enum dma_data_direction ddir
,
421 struct scatterlist
*sg
)
423 struct nand_chip
*nand
= mtd_to_nand(mtd
);
424 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
426 dma_unmap_sg(nfc
->dev
, sg
, 1, ddir
);
427 writel(readl(nfc
->regs
+ NFC_REG_CTL
) & ~NFC_RAM_METHOD
,
428 nfc
->regs
+ NFC_REG_CTL
);
431 static int sunxi_nfc_dev_ready(struct mtd_info
*mtd
)
433 struct nand_chip
*nand
= mtd_to_nand(mtd
);
434 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
435 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
436 struct sunxi_nand_rb
*rb
;
439 if (sunxi_nand
->selected
< 0)
442 rb
= &sunxi_nand
->sels
[sunxi_nand
->selected
].rb
;
446 ret
= !!(readl(nfc
->regs
+ NFC_REG_ST
) &
447 NFC_RB_STATE(rb
->info
.nativeid
));
450 ret
= gpio_get_value(rb
->info
.gpio
);
455 dev_err(nfc
->dev
, "cannot check R/B NAND status!\n");
462 static void sunxi_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
464 struct nand_chip
*nand
= mtd_to_nand(mtd
);
465 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
466 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
467 struct sunxi_nand_chip_sel
*sel
;
470 if (chip
> 0 && chip
>= sunxi_nand
->nsels
)
473 if (chip
== sunxi_nand
->selected
)
476 ctl
= readl(nfc
->regs
+ NFC_REG_CTL
) &
477 ~(NFC_PAGE_SHIFT_MSK
| NFC_CE_SEL_MSK
| NFC_RB_SEL_MSK
| NFC_EN
);
480 sel
= &sunxi_nand
->sels
[chip
];
482 ctl
|= NFC_CE_SEL(sel
->cs
) | NFC_EN
|
483 NFC_PAGE_SHIFT(nand
->page_shift
);
484 if (sel
->rb
.type
== RB_NONE
) {
485 nand
->dev_ready
= NULL
;
487 nand
->dev_ready
= sunxi_nfc_dev_ready
;
488 if (sel
->rb
.type
== RB_NATIVE
)
489 ctl
|= NFC_RB_SEL(sel
->rb
.info
.nativeid
);
492 writel(mtd
->writesize
, nfc
->regs
+ NFC_REG_SPARE_AREA
);
494 if (nfc
->clk_rate
!= sunxi_nand
->clk_rate
) {
495 clk_set_rate(nfc
->mod_clk
, sunxi_nand
->clk_rate
);
496 nfc
->clk_rate
= sunxi_nand
->clk_rate
;
500 writel(sunxi_nand
->timing_ctl
, nfc
->regs
+ NFC_REG_TIMING_CTL
);
501 writel(sunxi_nand
->timing_cfg
, nfc
->regs
+ NFC_REG_TIMING_CFG
);
502 writel(ctl
, nfc
->regs
+ NFC_REG_CTL
);
504 sunxi_nand
->selected
= chip
;
507 static void sunxi_nfc_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
509 struct nand_chip
*nand
= mtd_to_nand(mtd
);
510 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
511 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
518 cnt
= min(len
- offs
, NFC_SRAM_SIZE
);
520 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
524 writel(cnt
, nfc
->regs
+ NFC_REG_CNT
);
525 tmp
= NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
;
526 writel(tmp
, nfc
->regs
+ NFC_REG_CMD
);
528 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
533 memcpy_fromio(buf
+ offs
, nfc
->regs
+ NFC_RAM0_BASE
,
539 static void sunxi_nfc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
542 struct nand_chip
*nand
= mtd_to_nand(mtd
);
543 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
544 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
551 cnt
= min(len
- offs
, NFC_SRAM_SIZE
);
553 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
557 writel(cnt
, nfc
->regs
+ NFC_REG_CNT
);
558 memcpy_toio(nfc
->regs
+ NFC_RAM0_BASE
, buf
+ offs
, cnt
);
559 tmp
= NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
|
561 writel(tmp
, nfc
->regs
+ NFC_REG_CMD
);
563 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
571 static uint8_t sunxi_nfc_read_byte(struct mtd_info
*mtd
)
575 sunxi_nfc_read_buf(mtd
, &ret
, 1);
580 static void sunxi_nfc_cmd_ctrl(struct mtd_info
*mtd
, int dat
,
583 struct nand_chip
*nand
= mtd_to_nand(mtd
);
584 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
585 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
588 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
592 if (dat
== NAND_CMD_NONE
&& (ctrl
& NAND_NCE
) &&
593 !(ctrl
& (NAND_CLE
| NAND_ALE
))) {
596 if (!sunxi_nand
->addr_cycles
&& !sunxi_nand
->cmd_cycles
)
599 if (sunxi_nand
->cmd_cycles
--)
600 cmd
|= NFC_SEND_CMD1
| sunxi_nand
->cmd
[0];
602 if (sunxi_nand
->cmd_cycles
--) {
603 cmd
|= NFC_SEND_CMD2
;
604 writel(sunxi_nand
->cmd
[1],
605 nfc
->regs
+ NFC_REG_RCMD_SET
);
608 sunxi_nand
->cmd_cycles
= 0;
610 if (sunxi_nand
->addr_cycles
) {
611 cmd
|= NFC_SEND_ADR
|
612 NFC_ADR_NUM(sunxi_nand
->addr_cycles
);
613 writel(sunxi_nand
->addr
[0],
614 nfc
->regs
+ NFC_REG_ADDR_LOW
);
617 if (sunxi_nand
->addr_cycles
> 4)
618 writel(sunxi_nand
->addr
[1],
619 nfc
->regs
+ NFC_REG_ADDR_HIGH
);
621 writel(cmd
, nfc
->regs
+ NFC_REG_CMD
);
622 sunxi_nand
->addr
[0] = 0;
623 sunxi_nand
->addr
[1] = 0;
624 sunxi_nand
->addr_cycles
= 0;
625 sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
628 if (ctrl
& NAND_CLE
) {
629 sunxi_nand
->cmd
[sunxi_nand
->cmd_cycles
++] = dat
;
630 } else if (ctrl
& NAND_ALE
) {
631 sunxi_nand
->addr
[sunxi_nand
->addr_cycles
/ 4] |=
632 dat
<< ((sunxi_nand
->addr_cycles
% 4) * 8);
633 sunxi_nand
->addr_cycles
++;
637 /* These seed values have been extracted from Allwinner's BSP */
638 static const u16 sunxi_nfc_randomizer_page_seeds
[] = {
639 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
640 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
641 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
642 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
643 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
644 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
645 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
646 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
647 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
648 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
649 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
650 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
651 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
652 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
653 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
654 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
658 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
659 * have been generated using
660 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
661 * the randomizer engine does internally before de/scrambling OOB data.
663 * Those tables are statically defined to avoid calculating randomizer state
666 static const u16 sunxi_nfc_randomizer_ecc512_seeds
[] = {
667 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
668 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
669 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
670 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
671 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
672 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
673 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
674 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
675 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
676 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
677 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
678 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
679 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
680 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
681 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
682 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
685 static const u16 sunxi_nfc_randomizer_ecc1024_seeds
[] = {
686 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
687 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
688 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
689 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
690 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
691 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
692 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
693 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
694 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
695 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
696 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
697 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
698 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
699 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
700 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
701 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
704 static u16
sunxi_nfc_randomizer_step(u16 state
, int count
)
709 * This loop is just a simple implementation of a Fibonacci LFSR using
710 * the x16 + x15 + 1 polynomial.
713 state
= ((state
>> 1) |
714 (((state
^ (state
>> 1)) & 1) << 14)) & 0x7fff;
719 static u16
sunxi_nfc_randomizer_state(struct mtd_info
*mtd
, int page
, bool ecc
)
721 const u16
*seeds
= sunxi_nfc_randomizer_page_seeds
;
722 int mod
= mtd_div_by_ws(mtd
->erasesize
, mtd
);
724 if (mod
> ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds
))
725 mod
= ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds
);
728 if (mtd
->ecc_step_size
== 512)
729 seeds
= sunxi_nfc_randomizer_ecc512_seeds
;
731 seeds
= sunxi_nfc_randomizer_ecc1024_seeds
;
734 return seeds
[page
% mod
];
737 static void sunxi_nfc_randomizer_config(struct mtd_info
*mtd
,
740 struct nand_chip
*nand
= mtd_to_nand(mtd
);
741 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
742 u32 ecc_ctl
= readl(nfc
->regs
+ NFC_REG_ECC_CTL
);
745 if (!(nand
->options
& NAND_NEED_SCRAMBLING
))
748 ecc_ctl
= readl(nfc
->regs
+ NFC_REG_ECC_CTL
);
749 state
= sunxi_nfc_randomizer_state(mtd
, page
, ecc
);
750 ecc_ctl
= readl(nfc
->regs
+ NFC_REG_ECC_CTL
) & ~NFC_RANDOM_SEED_MSK
;
751 writel(ecc_ctl
| NFC_RANDOM_SEED(state
), nfc
->regs
+ NFC_REG_ECC_CTL
);
754 static void sunxi_nfc_randomizer_enable(struct mtd_info
*mtd
)
756 struct nand_chip
*nand
= mtd_to_nand(mtd
);
757 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
759 if (!(nand
->options
& NAND_NEED_SCRAMBLING
))
762 writel(readl(nfc
->regs
+ NFC_REG_ECC_CTL
) | NFC_RANDOM_EN
,
763 nfc
->regs
+ NFC_REG_ECC_CTL
);
766 static void sunxi_nfc_randomizer_disable(struct mtd_info
*mtd
)
768 struct nand_chip
*nand
= mtd_to_nand(mtd
);
769 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
771 if (!(nand
->options
& NAND_NEED_SCRAMBLING
))
774 writel(readl(nfc
->regs
+ NFC_REG_ECC_CTL
) & ~NFC_RANDOM_EN
,
775 nfc
->regs
+ NFC_REG_ECC_CTL
);
778 static void sunxi_nfc_randomize_bbm(struct mtd_info
*mtd
, int page
, u8
*bbm
)
780 u16 state
= sunxi_nfc_randomizer_state(mtd
, page
, true);
783 bbm
[1] ^= sunxi_nfc_randomizer_step(state
, 8);
786 static void sunxi_nfc_randomizer_write_buf(struct mtd_info
*mtd
,
787 const uint8_t *buf
, int len
,
790 sunxi_nfc_randomizer_config(mtd
, page
, ecc
);
791 sunxi_nfc_randomizer_enable(mtd
);
792 sunxi_nfc_write_buf(mtd
, buf
, len
);
793 sunxi_nfc_randomizer_disable(mtd
);
796 static void sunxi_nfc_randomizer_read_buf(struct mtd_info
*mtd
, uint8_t *buf
,
797 int len
, bool ecc
, int page
)
799 sunxi_nfc_randomizer_config(mtd
, page
, ecc
);
800 sunxi_nfc_randomizer_enable(mtd
);
801 sunxi_nfc_read_buf(mtd
, buf
, len
);
802 sunxi_nfc_randomizer_disable(mtd
);
805 static void sunxi_nfc_hw_ecc_enable(struct mtd_info
*mtd
)
807 struct nand_chip
*nand
= mtd_to_nand(mtd
);
808 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
809 struct sunxi_nand_hw_ecc
*data
= nand
->ecc
.priv
;
812 ecc_ctl
= readl(nfc
->regs
+ NFC_REG_ECC_CTL
);
813 ecc_ctl
&= ~(NFC_ECC_MODE_MSK
| NFC_ECC_PIPELINE
|
814 NFC_ECC_BLOCK_SIZE_MSK
);
815 ecc_ctl
|= NFC_ECC_EN
| NFC_ECC_MODE(data
->mode
) | NFC_ECC_EXCEPTION
|
818 writel(ecc_ctl
, nfc
->regs
+ NFC_REG_ECC_CTL
);
821 static void sunxi_nfc_hw_ecc_disable(struct mtd_info
*mtd
)
823 struct nand_chip
*nand
= mtd_to_nand(mtd
);
824 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
826 writel(readl(nfc
->regs
+ NFC_REG_ECC_CTL
) & ~NFC_ECC_EN
,
827 nfc
->regs
+ NFC_REG_ECC_CTL
);
830 static inline void sunxi_nfc_user_data_to_buf(u32 user_data
, u8
*buf
)
833 buf
[1] = user_data
>> 8;
834 buf
[2] = user_data
>> 16;
835 buf
[3] = user_data
>> 24;
838 static inline u32
sunxi_nfc_buf_to_user_data(const u8
*buf
)
840 return buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
843 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info
*mtd
, u8
*oob
,
844 int step
, bool bbm
, int page
)
846 struct nand_chip
*nand
= mtd_to_nand(mtd
);
847 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
849 sunxi_nfc_user_data_to_buf(readl(nfc
->regs
+ NFC_REG_USER_DATA(step
)),
852 /* De-randomize the Bad Block Marker. */
853 if (bbm
&& (nand
->options
& NAND_NEED_SCRAMBLING
))
854 sunxi_nfc_randomize_bbm(mtd
, page
, oob
);
857 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info
*mtd
,
858 const u8
*oob
, int step
,
861 struct nand_chip
*nand
= mtd_to_nand(mtd
);
862 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
865 /* Randomize the Bad Block Marker. */
866 if (bbm
&& (nand
->options
& NAND_NEED_SCRAMBLING
)) {
867 memcpy(user_data
, oob
, sizeof(user_data
));
868 sunxi_nfc_randomize_bbm(mtd
, page
, user_data
);
872 writel(sunxi_nfc_buf_to_user_data(oob
),
873 nfc
->regs
+ NFC_REG_USER_DATA(step
));
876 static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info
*mtd
,
877 unsigned int *max_bitflips
, int ret
)
880 mtd
->ecc_stats
.failed
++;
882 mtd
->ecc_stats
.corrected
+= ret
;
883 *max_bitflips
= max_t(unsigned int, *max_bitflips
, ret
);
887 static int sunxi_nfc_hw_ecc_correct(struct mtd_info
*mtd
, u8
*data
, u8
*oob
,
888 int step
, u32 status
, bool *erased
)
890 struct nand_chip
*nand
= mtd_to_nand(mtd
);
891 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
892 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
897 if (status
& NFC_ECC_ERR(step
))
900 if (status
& NFC_ECC_PAT_FOUND(step
)) {
903 if (unlikely(!(readl(nfc
->regs
+ NFC_REG_PAT_ID
) & 0x1))) {
911 memset(data
, pattern
, ecc
->size
);
914 memset(oob
, pattern
, ecc
->bytes
+ 4);
919 tmp
= readl(nfc
->regs
+ NFC_REG_ECC_ERR_CNT(step
));
921 return NFC_ECC_ERR_CNT(step
, tmp
);
924 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info
*mtd
,
925 u8
*data
, int data_off
,
926 u8
*oob
, int oob_off
,
928 unsigned int *max_bitflips
,
929 bool bbm
, bool oob_required
, int page
)
931 struct nand_chip
*nand
= mtd_to_nand(mtd
);
932 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
933 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
938 if (*cur_off
!= data_off
)
939 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_off
, -1);
941 sunxi_nfc_randomizer_read_buf(mtd
, NULL
, ecc
->size
, false, page
);
943 if (data_off
+ ecc
->size
!= oob_off
)
944 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_off
, -1);
946 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
950 sunxi_nfc_randomizer_enable(mtd
);
951 writel(NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
| NFC_ECC_OP
,
952 nfc
->regs
+ NFC_REG_CMD
);
954 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
955 sunxi_nfc_randomizer_disable(mtd
);
959 *cur_off
= oob_off
+ ecc
->bytes
+ 4;
961 ret
= sunxi_nfc_hw_ecc_correct(mtd
, data
, oob_required
? oob
: NULL
, 0,
962 readl(nfc
->regs
+ NFC_REG_ECC_ST
),
969 * Re-read the data with the randomizer disabled to identify
970 * bitflips in erased pages.
972 if (nand
->options
& NAND_NEED_SCRAMBLING
) {
973 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_off
, -1);
974 nand
->read_buf(mtd
, data
, ecc
->size
);
976 memcpy_fromio(data
, nfc
->regs
+ NFC_RAM0_BASE
,
980 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_off
, -1);
981 nand
->read_buf(mtd
, oob
, ecc
->bytes
+ 4);
983 ret
= nand_check_erased_ecc_chunk(data
, ecc
->size
,
985 NULL
, 0, ecc
->strength
);
989 memcpy_fromio(data
, nfc
->regs
+ NFC_RAM0_BASE
, ecc
->size
);
992 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_off
, -1);
993 sunxi_nfc_randomizer_read_buf(mtd
, oob
, ecc
->bytes
+ 4,
996 sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd
, oob
, 0,
1001 sunxi_nfc_hw_ecc_update_stats(mtd
, max_bitflips
, ret
);
1006 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info
*mtd
,
1007 u8
*oob
, int *cur_off
,
1008 bool randomize
, int page
)
1010 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1011 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1012 int offset
= ((ecc
->bytes
+ 4) * ecc
->steps
);
1013 int len
= mtd
->oobsize
- offset
;
1018 if (!cur_off
|| *cur_off
!= offset
)
1019 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1020 offset
+ mtd
->writesize
, -1);
1023 sunxi_nfc_read_buf(mtd
, oob
+ offset
, len
);
1025 sunxi_nfc_randomizer_read_buf(mtd
, oob
+ offset
, len
,
1029 *cur_off
= mtd
->oobsize
+ mtd
->writesize
;
1032 static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info
*mtd
, uint8_t *buf
,
1033 int oob_required
, int page
,
1036 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1037 bool randomized
= nand
->options
& NAND_NEED_SCRAMBLING
;
1038 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
1039 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1040 unsigned int max_bitflips
= 0;
1041 int ret
, i
, raw_mode
= 0;
1042 struct scatterlist sg
;
1045 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
1049 ret
= sunxi_nfc_dma_op_prepare(mtd
, buf
, ecc
->size
, nchunks
,
1050 DMA_FROM_DEVICE
, &sg
);
1054 sunxi_nfc_hw_ecc_enable(mtd
);
1055 sunxi_nfc_randomizer_config(mtd
, page
, false);
1056 sunxi_nfc_randomizer_enable(mtd
);
1058 writel((NAND_CMD_RNDOUTSTART
<< 16) | (NAND_CMD_RNDOUT
<< 8) |
1059 NAND_CMD_READSTART
, nfc
->regs
+ NFC_REG_RCMD_SET
);
1061 dma_async_issue_pending(nfc
->dmac
);
1063 writel(NFC_PAGE_OP
| NFC_DATA_SWAP_METHOD
| NFC_DATA_TRANS
,
1064 nfc
->regs
+ NFC_REG_CMD
);
1066 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
1068 dmaengine_terminate_all(nfc
->dmac
);
1070 sunxi_nfc_randomizer_disable(mtd
);
1071 sunxi_nfc_hw_ecc_disable(mtd
);
1073 sunxi_nfc_dma_op_cleanup(mtd
, DMA_FROM_DEVICE
, &sg
);
1078 status
= readl(nfc
->regs
+ NFC_REG_ECC_ST
);
1080 for (i
= 0; i
< nchunks
; i
++) {
1081 int data_off
= i
* ecc
->size
;
1082 int oob_off
= i
* (ecc
->bytes
+ 4);
1083 u8
*data
= buf
+ data_off
;
1084 u8
*oob
= nand
->oob_poi
+ oob_off
;
1087 ret
= sunxi_nfc_hw_ecc_correct(mtd
, randomized
? data
: NULL
,
1088 oob_required
? oob
: NULL
,
1089 i
, status
, &erased
);
1091 /* ECC errors are handled in the second loop. */
1095 if (oob_required
&& !erased
) {
1096 /* TODO: use DMA to retrieve OOB */
1097 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1098 mtd
->writesize
+ oob_off
, -1);
1099 nand
->read_buf(mtd
, oob
, ecc
->bytes
+ 4);
1101 sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd
, oob
, i
,
1108 sunxi_nfc_hw_ecc_update_stats(mtd
, &max_bitflips
, ret
);
1111 if (status
& NFC_ECC_ERR_MSK
) {
1112 for (i
= 0; i
< nchunks
; i
++) {
1113 int data_off
= i
* ecc
->size
;
1114 int oob_off
= i
* (ecc
->bytes
+ 4);
1115 u8
*data
= buf
+ data_off
;
1116 u8
*oob
= nand
->oob_poi
+ oob_off
;
1118 if (!(status
& NFC_ECC_ERR(i
)))
1122 * Re-read the data with the randomizer disabled to
1123 * identify bitflips in erased pages.
1126 /* TODO: use DMA to read page in raw mode */
1127 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1129 nand
->read_buf(mtd
, data
, ecc
->size
);
1132 /* TODO: use DMA to retrieve OOB */
1133 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1134 mtd
->writesize
+ oob_off
, -1);
1135 nand
->read_buf(mtd
, oob
, ecc
->bytes
+ 4);
1137 ret
= nand_check_erased_ecc_chunk(data
, ecc
->size
,
1138 oob
, ecc
->bytes
+ 4,
1144 sunxi_nfc_hw_ecc_update_stats(mtd
, &max_bitflips
, ret
);
1149 sunxi_nfc_hw_ecc_read_extra_oob(mtd
, nand
->oob_poi
,
1153 return max_bitflips
;
1156 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info
*mtd
,
1157 const u8
*data
, int data_off
,
1158 const u8
*oob
, int oob_off
,
1159 int *cur_off
, bool bbm
,
1162 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1163 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
1164 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1167 if (data_off
!= *cur_off
)
1168 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
, data_off
, -1);
1170 sunxi_nfc_randomizer_write_buf(mtd
, data
, ecc
->size
, false, page
);
1172 if (data_off
+ ecc
->size
!= oob_off
)
1173 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
, oob_off
, -1);
1175 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
1179 sunxi_nfc_randomizer_enable(mtd
);
1180 sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd
, oob
, 0, bbm
, page
);
1182 writel(NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
|
1183 NFC_ACCESS_DIR
| NFC_ECC_OP
,
1184 nfc
->regs
+ NFC_REG_CMD
);
1186 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
1187 sunxi_nfc_randomizer_disable(mtd
);
1191 *cur_off
= oob_off
+ ecc
->bytes
+ 4;
1196 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info
*mtd
,
1197 u8
*oob
, int *cur_off
,
1200 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1201 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1202 int offset
= ((ecc
->bytes
+ 4) * ecc
->steps
);
1203 int len
= mtd
->oobsize
- offset
;
1208 if (!cur_off
|| *cur_off
!= offset
)
1209 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
,
1210 offset
+ mtd
->writesize
, -1);
1212 sunxi_nfc_randomizer_write_buf(mtd
, oob
+ offset
, len
, false, page
);
1215 *cur_off
= mtd
->oobsize
+ mtd
->writesize
;
1218 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info
*mtd
,
1219 struct nand_chip
*chip
, uint8_t *buf
,
1220 int oob_required
, int page
)
1222 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
1223 unsigned int max_bitflips
= 0;
1224 int ret
, i
, cur_off
= 0;
1225 bool raw_mode
= false;
1227 sunxi_nfc_hw_ecc_enable(mtd
);
1229 for (i
= 0; i
< ecc
->steps
; i
++) {
1230 int data_off
= i
* ecc
->size
;
1231 int oob_off
= i
* (ecc
->bytes
+ 4);
1232 u8
*data
= buf
+ data_off
;
1233 u8
*oob
= chip
->oob_poi
+ oob_off
;
1235 ret
= sunxi_nfc_hw_ecc_read_chunk(mtd
, data
, data_off
, oob
,
1236 oob_off
+ mtd
->writesize
,
1237 &cur_off
, &max_bitflips
,
1238 !i
, oob_required
, page
);
1246 sunxi_nfc_hw_ecc_read_extra_oob(mtd
, chip
->oob_poi
, &cur_off
,
1249 sunxi_nfc_hw_ecc_disable(mtd
);
1251 return max_bitflips
;
1254 static int sunxi_nfc_hw_ecc_read_page_dma(struct mtd_info
*mtd
,
1255 struct nand_chip
*chip
, u8
*buf
,
1256 int oob_required
, int page
)
1260 ret
= sunxi_nfc_hw_ecc_read_chunks_dma(mtd
, buf
, oob_required
, page
,
1265 /* Fallback to PIO mode */
1266 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, 0, -1);
1268 return sunxi_nfc_hw_ecc_read_page(mtd
, chip
, buf
, oob_required
, page
);
1271 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info
*mtd
,
1272 struct nand_chip
*chip
,
1273 u32 data_offs
, u32 readlen
,
1274 u8
*bufpoi
, int page
)
1276 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
1277 int ret
, i
, cur_off
= 0;
1278 unsigned int max_bitflips
= 0;
1280 sunxi_nfc_hw_ecc_enable(mtd
);
1282 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1283 for (i
= data_offs
/ ecc
->size
;
1284 i
< DIV_ROUND_UP(data_offs
+ readlen
, ecc
->size
); i
++) {
1285 int data_off
= i
* ecc
->size
;
1286 int oob_off
= i
* (ecc
->bytes
+ 4);
1287 u8
*data
= bufpoi
+ data_off
;
1288 u8
*oob
= chip
->oob_poi
+ oob_off
;
1290 ret
= sunxi_nfc_hw_ecc_read_chunk(mtd
, data
, data_off
,
1292 oob_off
+ mtd
->writesize
,
1293 &cur_off
, &max_bitflips
, !i
,
1299 sunxi_nfc_hw_ecc_disable(mtd
);
1301 return max_bitflips
;
1304 static int sunxi_nfc_hw_ecc_read_subpage_dma(struct mtd_info
*mtd
,
1305 struct nand_chip
*chip
,
1306 u32 data_offs
, u32 readlen
,
1309 int nchunks
= DIV_ROUND_UP(data_offs
+ readlen
, chip
->ecc
.size
);
1312 ret
= sunxi_nfc_hw_ecc_read_chunks_dma(mtd
, buf
, false, page
, nchunks
);
1316 /* Fallback to PIO mode */
1317 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, 0, -1);
1319 return sunxi_nfc_hw_ecc_read_subpage(mtd
, chip
, data_offs
, readlen
,
1323 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info
*mtd
,
1324 struct nand_chip
*chip
,
1325 const uint8_t *buf
, int oob_required
,
1328 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
1329 int ret
, i
, cur_off
= 0;
1331 sunxi_nfc_hw_ecc_enable(mtd
);
1333 for (i
= 0; i
< ecc
->steps
; i
++) {
1334 int data_off
= i
* ecc
->size
;
1335 int oob_off
= i
* (ecc
->bytes
+ 4);
1336 const u8
*data
= buf
+ data_off
;
1337 const u8
*oob
= chip
->oob_poi
+ oob_off
;
1339 ret
= sunxi_nfc_hw_ecc_write_chunk(mtd
, data
, data_off
, oob
,
1340 oob_off
+ mtd
->writesize
,
1341 &cur_off
, !i
, page
);
1346 if (oob_required
|| (chip
->options
& NAND_NEED_SCRAMBLING
))
1347 sunxi_nfc_hw_ecc_write_extra_oob(mtd
, chip
->oob_poi
,
1350 sunxi_nfc_hw_ecc_disable(mtd
);
1355 static int sunxi_nfc_hw_ecc_write_page_dma(struct mtd_info
*mtd
,
1356 struct nand_chip
*chip
,
1361 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1362 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
1363 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1364 struct scatterlist sg
;
1367 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
1371 ret
= sunxi_nfc_dma_op_prepare(mtd
, buf
, ecc
->size
, ecc
->steps
,
1372 DMA_TO_DEVICE
, &sg
);
1376 for (i
= 0; i
< ecc
->steps
; i
++) {
1377 const u8
*oob
= nand
->oob_poi
+ (i
* (ecc
->bytes
+ 4));
1379 sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd
, oob
, i
, !i
, page
);
1382 sunxi_nfc_hw_ecc_enable(mtd
);
1383 sunxi_nfc_randomizer_config(mtd
, page
, false);
1384 sunxi_nfc_randomizer_enable(mtd
);
1386 writel((NAND_CMD_RNDIN
<< 8) | NAND_CMD_PAGEPROG
,
1387 nfc
->regs
+ NFC_REG_RCMD_SET
);
1389 dma_async_issue_pending(nfc
->dmac
);
1391 writel(NFC_PAGE_OP
| NFC_DATA_SWAP_METHOD
|
1392 NFC_DATA_TRANS
| NFC_ACCESS_DIR
,
1393 nfc
->regs
+ NFC_REG_CMD
);
1395 ret
= sunxi_nfc_wait_events(nfc
, NFC_CMD_INT_FLAG
, true, 0);
1397 dmaengine_terminate_all(nfc
->dmac
);
1399 sunxi_nfc_randomizer_disable(mtd
);
1400 sunxi_nfc_hw_ecc_disable(mtd
);
1402 sunxi_nfc_dma_op_cleanup(mtd
, DMA_TO_DEVICE
, &sg
);
1407 if (oob_required
|| (chip
->options
& NAND_NEED_SCRAMBLING
))
1408 /* TODO: use DMA to transfer extra OOB bytes ? */
1409 sunxi_nfc_hw_ecc_write_extra_oob(mtd
, chip
->oob_poi
,
1415 return sunxi_nfc_hw_ecc_write_page(mtd
, chip
, buf
, oob_required
, page
);
1418 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info
*mtd
,
1419 struct nand_chip
*chip
,
1420 uint8_t *buf
, int oob_required
,
1423 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
1424 unsigned int max_bitflips
= 0;
1425 int ret
, i
, cur_off
= 0;
1426 bool raw_mode
= false;
1428 sunxi_nfc_hw_ecc_enable(mtd
);
1430 for (i
= 0; i
< ecc
->steps
; i
++) {
1431 int data_off
= i
* (ecc
->size
+ ecc
->bytes
+ 4);
1432 int oob_off
= data_off
+ ecc
->size
;
1433 u8
*data
= buf
+ (i
* ecc
->size
);
1434 u8
*oob
= chip
->oob_poi
+ (i
* (ecc
->bytes
+ 4));
1436 ret
= sunxi_nfc_hw_ecc_read_chunk(mtd
, data
, data_off
, oob
,
1448 sunxi_nfc_hw_ecc_read_extra_oob(mtd
, chip
->oob_poi
, &cur_off
,
1451 sunxi_nfc_hw_ecc_disable(mtd
);
1453 return max_bitflips
;
1456 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info
*mtd
,
1457 struct nand_chip
*chip
,
1459 int oob_required
, int page
)
1461 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
1462 int ret
, i
, cur_off
= 0;
1464 sunxi_nfc_hw_ecc_enable(mtd
);
1466 for (i
= 0; i
< ecc
->steps
; i
++) {
1467 int data_off
= i
* (ecc
->size
+ ecc
->bytes
+ 4);
1468 int oob_off
= data_off
+ ecc
->size
;
1469 const u8
*data
= buf
+ (i
* ecc
->size
);
1470 const u8
*oob
= chip
->oob_poi
+ (i
* (ecc
->bytes
+ 4));
1472 ret
= sunxi_nfc_hw_ecc_write_chunk(mtd
, data
, data_off
,
1473 oob
, oob_off
, &cur_off
,
1479 if (oob_required
|| (chip
->options
& NAND_NEED_SCRAMBLING
))
1480 sunxi_nfc_hw_ecc_write_extra_oob(mtd
, chip
->oob_poi
,
1483 sunxi_nfc_hw_ecc_disable(mtd
);
1488 static int sunxi_nfc_hw_common_ecc_read_oob(struct mtd_info
*mtd
,
1489 struct nand_chip
*chip
,
1492 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1496 return chip
->ecc
.read_page(mtd
, chip
, chip
->buffers
->databuf
, 1, page
);
1499 static int sunxi_nfc_hw_common_ecc_write_oob(struct mtd_info
*mtd
,
1500 struct nand_chip
*chip
,
1505 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0, page
);
1509 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
1510 ret
= chip
->ecc
.write_page(mtd
, chip
, chip
->buffers
->databuf
, 1, page
);
1514 /* Send command to program the OOB data */
1515 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1517 status
= chip
->waitfunc(mtd
, chip
);
1519 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1522 static const s32 tWB_lut
[] = {6, 12, 16, 20};
1523 static const s32 tRHW_lut
[] = {4, 8, 12, 20};
1525 static int _sunxi_nand_lookup_timing(const s32
*lut
, int lut_size
, u32 duration
,
1528 u32 clk_cycles
= DIV_ROUND_UP(duration
, clk_period
);
1531 for (i
= 0; i
< lut_size
; i
++) {
1532 if (clk_cycles
<= lut
[i
])
1540 #define sunxi_nand_lookup_timing(l, p, c) \
1541 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1543 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip
*chip
,
1544 const struct nand_sdr_timings
*timings
)
1546 struct sunxi_nfc
*nfc
= to_sunxi_nfc(chip
->nand
.controller
);
1547 u32 min_clk_period
= 0;
1548 s32 tWB
, tADL
, tWHR
, tRHW
, tCAD
;
1552 if (timings
->tCLS_min
> min_clk_period
)
1553 min_clk_period
= timings
->tCLS_min
;
1556 if (timings
->tCLH_min
> min_clk_period
)
1557 min_clk_period
= timings
->tCLH_min
;
1560 if (timings
->tCS_min
> min_clk_period
)
1561 min_clk_period
= timings
->tCS_min
;
1564 if (timings
->tCH_min
> min_clk_period
)
1565 min_clk_period
= timings
->tCH_min
;
1568 if (timings
->tWP_min
> min_clk_period
)
1569 min_clk_period
= timings
->tWP_min
;
1572 if (timings
->tWH_min
> min_clk_period
)
1573 min_clk_period
= timings
->tWH_min
;
1576 if (timings
->tALS_min
> min_clk_period
)
1577 min_clk_period
= timings
->tALS_min
;
1580 if (timings
->tDS_min
> min_clk_period
)
1581 min_clk_period
= timings
->tDS_min
;
1584 if (timings
->tDH_min
> min_clk_period
)
1585 min_clk_period
= timings
->tDH_min
;
1588 if (timings
->tRR_min
> (min_clk_period
* 3))
1589 min_clk_period
= DIV_ROUND_UP(timings
->tRR_min
, 3);
1592 if (timings
->tALH_min
> min_clk_period
)
1593 min_clk_period
= timings
->tALH_min
;
1596 if (timings
->tRP_min
> min_clk_period
)
1597 min_clk_period
= timings
->tRP_min
;
1600 if (timings
->tREH_min
> min_clk_period
)
1601 min_clk_period
= timings
->tREH_min
;
1604 if (timings
->tRC_min
> (min_clk_period
* 2))
1605 min_clk_period
= DIV_ROUND_UP(timings
->tRC_min
, 2);
1608 if (timings
->tWC_min
> (min_clk_period
* 2))
1609 min_clk_period
= DIV_ROUND_UP(timings
->tWC_min
, 2);
1611 /* T16 - T19 + tCAD */
1612 if (timings
->tWB_max
> (min_clk_period
* 20))
1613 min_clk_period
= DIV_ROUND_UP(timings
->tWB_max
, 20);
1615 if (timings
->tADL_min
> (min_clk_period
* 32))
1616 min_clk_period
= DIV_ROUND_UP(timings
->tADL_min
, 32);
1618 if (timings
->tWHR_min
> (min_clk_period
* 32))
1619 min_clk_period
= DIV_ROUND_UP(timings
->tWHR_min
, 32);
1621 if (timings
->tRHW_min
> (min_clk_period
* 20))
1622 min_clk_period
= DIV_ROUND_UP(timings
->tRHW_min
, 20);
1624 tWB
= sunxi_nand_lookup_timing(tWB_lut
, timings
->tWB_max
,
1627 dev_err(nfc
->dev
, "unsupported tWB\n");
1631 tADL
= DIV_ROUND_UP(timings
->tADL_min
, min_clk_period
) >> 3;
1633 dev_err(nfc
->dev
, "unsupported tADL\n");
1637 tWHR
= DIV_ROUND_UP(timings
->tWHR_min
, min_clk_period
) >> 3;
1639 dev_err(nfc
->dev
, "unsupported tWHR\n");
1643 tRHW
= sunxi_nand_lookup_timing(tRHW_lut
, timings
->tRHW_min
,
1646 dev_err(nfc
->dev
, "unsupported tRHW\n");
1651 * TODO: according to ONFI specs this value only applies for DDR NAND,
1652 * but Allwinner seems to set this to 0x7. Mimic them for now.
1656 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1657 chip
->timing_cfg
= NFC_TIMING_CFG(tWB
, tADL
, tWHR
, tRHW
, tCAD
);
1659 /* Convert min_clk_period from picoseconds to nanoseconds */
1660 min_clk_period
= DIV_ROUND_UP(min_clk_period
, 1000);
1663 * Unlike what is stated in Allwinner datasheet, the clk_rate should
1664 * be set to (1 / min_clk_period), and not (2 / min_clk_period).
1665 * This new formula was verified with a scope and validated by
1666 * Allwinner engineers.
1668 chip
->clk_rate
= NSEC_PER_SEC
/ min_clk_period
;
1669 real_clk_rate
= clk_round_rate(nfc
->mod_clk
, chip
->clk_rate
);
1672 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1673 * output cycle timings shall be used if the host drives tRC less than
1676 min_clk_period
= NSEC_PER_SEC
/ real_clk_rate
;
1677 chip
->timing_ctl
= ((min_clk_period
* 2) < 30) ?
1678 NFC_TIMING_CTL_EDO
: 0;
1683 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip
*chip
,
1684 struct device_node
*np
)
1686 struct mtd_info
*mtd
= nand_to_mtd(&chip
->nand
);
1687 const struct nand_sdr_timings
*timings
;
1691 mode
= onfi_get_async_timing_mode(&chip
->nand
);
1692 if (mode
== ONFI_TIMING_MODE_UNKNOWN
) {
1693 mode
= chip
->nand
.onfi_timing_mode_default
;
1695 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {};
1698 mode
= fls(mode
) - 1;
1703 for (i
= 0; i
< chip
->nsels
; i
++) {
1704 chip
->nand
.select_chip(mtd
, i
);
1705 ret
= chip
->nand
.onfi_set_features(mtd
, &chip
->nand
,
1706 ONFI_FEATURE_ADDR_TIMING_MODE
,
1708 chip
->nand
.select_chip(mtd
, -1);
1714 timings
= onfi_async_timing_mode_to_sdr_timings(mode
);
1715 if (IS_ERR(timings
))
1716 return PTR_ERR(timings
);
1718 return sunxi_nand_chip_set_timings(chip
, timings
);
1721 static int sunxi_nand_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1722 struct mtd_oob_region
*oobregion
)
1724 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1725 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1727 if (section
>= ecc
->steps
)
1730 oobregion
->offset
= section
* (ecc
->bytes
+ 4) + 4;
1731 oobregion
->length
= ecc
->bytes
;
1736 static int sunxi_nand_ooblayout_free(struct mtd_info
*mtd
, int section
,
1737 struct mtd_oob_region
*oobregion
)
1739 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1740 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
1742 if (section
> ecc
->steps
)
1746 * The first 2 bytes are used for BB markers, hence we
1747 * only have 2 bytes available in the first user data
1750 if (!section
&& ecc
->mode
== NAND_ECC_HW
) {
1751 oobregion
->offset
= 2;
1752 oobregion
->length
= 2;
1757 oobregion
->offset
= section
* (ecc
->bytes
+ 4);
1759 if (section
< ecc
->steps
)
1760 oobregion
->length
= 4;
1762 oobregion
->offset
= mtd
->oobsize
- oobregion
->offset
;
1767 static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops
= {
1768 .ecc
= sunxi_nand_ooblayout_ecc
,
1769 .free
= sunxi_nand_ooblayout_free
,
1772 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info
*mtd
,
1773 struct nand_ecc_ctrl
*ecc
,
1774 struct device_node
*np
)
1776 static const u8 strengths
[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1777 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1778 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
1779 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
1780 struct sunxi_nand_hw_ecc
*data
;
1785 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1789 /* Add ECC info retrieval from DT */
1790 for (i
= 0; i
< ARRAY_SIZE(strengths
); i
++) {
1791 if (ecc
->strength
<= strengths
[i
])
1795 if (i
>= ARRAY_SIZE(strengths
)) {
1796 dev_err(nfc
->dev
, "unsupported strength\n");
1803 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1804 ecc
->bytes
= DIV_ROUND_UP(ecc
->strength
* fls(8 * 1024), 8);
1806 /* HW ECC always work with even numbers of ECC bytes */
1807 ecc
->bytes
= ALIGN(ecc
->bytes
, 2);
1809 nsectors
= mtd
->writesize
/ ecc
->size
;
1811 if (mtd
->oobsize
< ((ecc
->bytes
+ 4) * nsectors
)) {
1816 ecc
->read_oob
= sunxi_nfc_hw_common_ecc_read_oob
;
1817 ecc
->write_oob
= sunxi_nfc_hw_common_ecc_write_oob
;
1818 mtd_set_ooblayout(mtd
, &sunxi_nand_ooblayout_ops
);
1829 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl
*ecc
)
1834 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info
*mtd
,
1835 struct nand_ecc_ctrl
*ecc
,
1836 struct device_node
*np
)
1838 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1839 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
1840 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
1843 ret
= sunxi_nand_hw_common_ecc_ctrl_init(mtd
, ecc
, np
);
1848 ecc
->read_page
= sunxi_nfc_hw_ecc_read_page_dma
;
1849 ecc
->read_subpage
= sunxi_nfc_hw_ecc_read_subpage_dma
;
1850 ecc
->write_page
= sunxi_nfc_hw_ecc_write_page_dma
;
1851 nand
->options
|= NAND_USE_BOUNCE_BUFFER
;
1853 ecc
->read_page
= sunxi_nfc_hw_ecc_read_page
;
1854 ecc
->read_subpage
= sunxi_nfc_hw_ecc_read_subpage
;
1855 ecc
->write_page
= sunxi_nfc_hw_ecc_write_page
;
1858 /* TODO: support DMA for raw accesses */
1859 ecc
->read_oob_raw
= nand_read_oob_std
;
1860 ecc
->write_oob_raw
= nand_write_oob_std
;
1861 ecc
->read_subpage
= sunxi_nfc_hw_ecc_read_subpage
;
1866 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info
*mtd
,
1867 struct nand_ecc_ctrl
*ecc
,
1868 struct device_node
*np
)
1872 ret
= sunxi_nand_hw_common_ecc_ctrl_init(mtd
, ecc
, np
);
1877 ecc
->read_page
= sunxi_nfc_hw_syndrome_ecc_read_page
;
1878 ecc
->write_page
= sunxi_nfc_hw_syndrome_ecc_write_page
;
1879 ecc
->read_oob_raw
= nand_read_oob_syndrome
;
1880 ecc
->write_oob_raw
= nand_write_oob_syndrome
;
1885 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl
*ecc
)
1887 switch (ecc
->mode
) {
1889 case NAND_ECC_HW_SYNDROME
:
1890 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc
);
1898 static int sunxi_nand_ecc_init(struct mtd_info
*mtd
, struct nand_ecc_ctrl
*ecc
,
1899 struct device_node
*np
)
1901 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1905 ecc
->size
= nand
->ecc_step_ds
;
1906 ecc
->strength
= nand
->ecc_strength_ds
;
1909 if (!ecc
->size
|| !ecc
->strength
)
1912 switch (ecc
->mode
) {
1914 ret
= sunxi_nand_hw_ecc_ctrl_init(mtd
, ecc
, np
);
1918 case NAND_ECC_HW_SYNDROME
:
1919 ret
= sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd
, ecc
, np
);
1933 static int sunxi_nand_chip_init(struct device
*dev
, struct sunxi_nfc
*nfc
,
1934 struct device_node
*np
)
1936 const struct nand_sdr_timings
*timings
;
1937 struct sunxi_nand_chip
*chip
;
1938 struct mtd_info
*mtd
;
1939 struct nand_chip
*nand
;
1945 if (!of_get_property(np
, "reg", &nsels
))
1948 nsels
/= sizeof(u32
);
1950 dev_err(dev
, "invalid reg property size\n");
1954 chip
= devm_kzalloc(dev
,
1956 (nsels
* sizeof(struct sunxi_nand_chip_sel
)),
1959 dev_err(dev
, "could not allocate chip\n");
1963 chip
->nsels
= nsels
;
1964 chip
->selected
= -1;
1966 for (i
= 0; i
< nsels
; i
++) {
1967 ret
= of_property_read_u32_index(np
, "reg", i
, &tmp
);
1969 dev_err(dev
, "could not retrieve reg property: %d\n",
1974 if (tmp
> NFC_MAX_CS
) {
1976 "invalid reg value: %u (max CS = 7)\n",
1981 if (test_and_set_bit(tmp
, &nfc
->assigned_cs
)) {
1982 dev_err(dev
, "CS %d already assigned\n", tmp
);
1986 chip
->sels
[i
].cs
= tmp
;
1988 if (!of_property_read_u32_index(np
, "allwinner,rb", i
, &tmp
) &&
1990 chip
->sels
[i
].rb
.type
= RB_NATIVE
;
1991 chip
->sels
[i
].rb
.info
.nativeid
= tmp
;
1993 ret
= of_get_named_gpio(np
, "rb-gpios", i
);
1996 chip
->sels
[i
].rb
.type
= RB_GPIO
;
1997 chip
->sels
[i
].rb
.info
.gpio
= tmp
;
1998 ret
= devm_gpio_request(dev
, tmp
, "nand-rb");
2002 ret
= gpio_direction_input(tmp
);
2006 chip
->sels
[i
].rb
.type
= RB_NONE
;
2012 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
2013 nand
->chip_delay
= 200;
2014 nand
->controller
= &nfc
->controller
;
2016 * Set the ECC mode to the default value in case nothing is specified
2019 nand
->ecc
.mode
= NAND_ECC_HW
;
2020 nand_set_flash_node(nand
, np
);
2021 nand
->select_chip
= sunxi_nfc_select_chip
;
2022 nand
->cmd_ctrl
= sunxi_nfc_cmd_ctrl
;
2023 nand
->read_buf
= sunxi_nfc_read_buf
;
2024 nand
->write_buf
= sunxi_nfc_write_buf
;
2025 nand
->read_byte
= sunxi_nfc_read_byte
;
2027 mtd
= nand_to_mtd(nand
);
2028 mtd
->dev
.parent
= dev
;
2030 timings
= onfi_async_timing_mode_to_sdr_timings(0);
2031 if (IS_ERR(timings
)) {
2032 ret
= PTR_ERR(timings
);
2034 "could not retrieve timings for ONFI mode 0: %d\n",
2039 ret
= sunxi_nand_chip_set_timings(chip
, timings
);
2041 dev_err(dev
, "could not configure chip timings: %d\n", ret
);
2045 ret
= nand_scan_ident(mtd
, nsels
, NULL
);
2049 if (nand
->bbt_options
& NAND_BBT_USE_FLASH
)
2050 nand
->bbt_options
|= NAND_BBT_NO_OOB
;
2052 if (nand
->options
& NAND_NEED_SCRAMBLING
)
2053 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
2055 nand
->options
|= NAND_SUBPAGE_READ
;
2057 ret
= sunxi_nand_chip_init_timings(chip
, np
);
2059 dev_err(dev
, "could not configure chip timings: %d\n", ret
);
2063 ret
= sunxi_nand_ecc_init(mtd
, &nand
->ecc
, np
);
2065 dev_err(dev
, "ECC init failed: %d\n", ret
);
2069 ret
= nand_scan_tail(mtd
);
2071 dev_err(dev
, "nand_scan_tail failed: %d\n", ret
);
2075 ret
= mtd_device_register(mtd
, NULL
, 0);
2077 dev_err(dev
, "failed to register mtd device: %d\n", ret
);
2082 list_add_tail(&chip
->node
, &nfc
->chips
);
2087 static int sunxi_nand_chips_init(struct device
*dev
, struct sunxi_nfc
*nfc
)
2089 struct device_node
*np
= dev
->of_node
;
2090 struct device_node
*nand_np
;
2091 int nchips
= of_get_child_count(np
);
2095 dev_err(dev
, "too many NAND chips: %d (max = 8)\n", nchips
);
2099 for_each_child_of_node(np
, nand_np
) {
2100 ret
= sunxi_nand_chip_init(dev
, nfc
, nand_np
);
2102 of_node_put(nand_np
);
2110 static void sunxi_nand_chips_cleanup(struct sunxi_nfc
*nfc
)
2112 struct sunxi_nand_chip
*chip
;
2114 while (!list_empty(&nfc
->chips
)) {
2115 chip
= list_first_entry(&nfc
->chips
, struct sunxi_nand_chip
,
2117 nand_release(nand_to_mtd(&chip
->nand
));
2118 sunxi_nand_ecc_cleanup(&chip
->nand
.ecc
);
2119 list_del(&chip
->node
);
2123 static int sunxi_nfc_probe(struct platform_device
*pdev
)
2125 struct device
*dev
= &pdev
->dev
;
2127 struct sunxi_nfc
*nfc
;
2131 nfc
= devm_kzalloc(dev
, sizeof(*nfc
), GFP_KERNEL
);
2136 spin_lock_init(&nfc
->controller
.lock
);
2137 init_waitqueue_head(&nfc
->controller
.wq
);
2138 INIT_LIST_HEAD(&nfc
->chips
);
2140 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2141 nfc
->regs
= devm_ioremap_resource(dev
, r
);
2142 if (IS_ERR(nfc
->regs
))
2143 return PTR_ERR(nfc
->regs
);
2145 irq
= platform_get_irq(pdev
, 0);
2147 dev_err(dev
, "failed to retrieve irq\n");
2151 nfc
->ahb_clk
= devm_clk_get(dev
, "ahb");
2152 if (IS_ERR(nfc
->ahb_clk
)) {
2153 dev_err(dev
, "failed to retrieve ahb clk\n");
2154 return PTR_ERR(nfc
->ahb_clk
);
2157 ret
= clk_prepare_enable(nfc
->ahb_clk
);
2161 nfc
->mod_clk
= devm_clk_get(dev
, "mod");
2162 if (IS_ERR(nfc
->mod_clk
)) {
2163 dev_err(dev
, "failed to retrieve mod clk\n");
2164 ret
= PTR_ERR(nfc
->mod_clk
);
2165 goto out_ahb_clk_unprepare
;
2168 ret
= clk_prepare_enable(nfc
->mod_clk
);
2170 goto out_ahb_clk_unprepare
;
2172 ret
= sunxi_nfc_rst(nfc
);
2174 goto out_mod_clk_unprepare
;
2176 writel(0, nfc
->regs
+ NFC_REG_INT
);
2177 ret
= devm_request_irq(dev
, irq
, sunxi_nfc_interrupt
,
2178 0, "sunxi-nand", nfc
);
2180 goto out_mod_clk_unprepare
;
2182 nfc
->dmac
= dma_request_slave_channel(dev
, "rxtx");
2184 struct dma_slave_config dmac_cfg
= { };
2186 dmac_cfg
.src_addr
= r
->start
+ NFC_REG_IO_DATA
;
2187 dmac_cfg
.dst_addr
= dmac_cfg
.src_addr
;
2188 dmac_cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
2189 dmac_cfg
.dst_addr_width
= dmac_cfg
.src_addr_width
;
2190 dmac_cfg
.src_maxburst
= 4;
2191 dmac_cfg
.dst_maxburst
= 4;
2192 dmaengine_slave_config(nfc
->dmac
, &dmac_cfg
);
2194 dev_warn(dev
, "failed to request rxtx DMA channel\n");
2197 platform_set_drvdata(pdev
, nfc
);
2199 ret
= sunxi_nand_chips_init(dev
, nfc
);
2201 dev_err(dev
, "failed to init nand chips\n");
2202 goto out_release_dmac
;
2209 dma_release_channel(nfc
->dmac
);
2210 out_mod_clk_unprepare
:
2211 clk_disable_unprepare(nfc
->mod_clk
);
2212 out_ahb_clk_unprepare
:
2213 clk_disable_unprepare(nfc
->ahb_clk
);
2218 static int sunxi_nfc_remove(struct platform_device
*pdev
)
2220 struct sunxi_nfc
*nfc
= platform_get_drvdata(pdev
);
2222 sunxi_nand_chips_cleanup(nfc
);
2224 dma_release_channel(nfc
->dmac
);
2225 clk_disable_unprepare(nfc
->mod_clk
);
2226 clk_disable_unprepare(nfc
->ahb_clk
);
2231 static const struct of_device_id sunxi_nfc_ids
[] = {
2232 { .compatible
= "allwinner,sun4i-a10-nand" },
2235 MODULE_DEVICE_TABLE(of
, sunxi_nfc_ids
);
2237 static struct platform_driver sunxi_nfc_driver
= {
2239 .name
= "sunxi_nand",
2240 .of_match_table
= sunxi_nfc_ids
,
2242 .probe
= sunxi_nfc_probe
,
2243 .remove
= sunxi_nfc_remove
,
2245 module_platform_driver(sunxi_nfc_driver
);
2247 MODULE_LICENSE("GPL v2");
2248 MODULE_AUTHOR("Boris BREZILLON");
2249 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
2250 MODULE_ALIAS("platform:sunxi_nand");