2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Jason ported to M54418TWR and MVFA5 (VF610).
6 * Authors: Stefan Agner <stefan.agner@toradex.com>
7 * Bill Pringlemeir <bpringlemeir@nbsps.com>
8 * Shaohui Xie <b21989@freescale.com>
9 * Jason Jin <Jason.jin@freescale.com>
11 * Based on original driver mpc5121_nfc.c.
13 * This is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
19 * - Untested on MPC5125 and M54418.
20 * - DMA and pipelining not used.
22 * - HW ECC: Only 2K page with 64+ OOB.
23 * - HW ECC: Only 24 and 32-bit error correction implemented.
26 #include <linux/module.h>
27 #include <linux/bitops.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/of_mtd.h>
37 #include <linux/of_device.h>
38 #include <linux/pinctrl/consumer.h>
39 #include <linux/platform_device.h>
40 #include <linux/slab.h>
42 #define DRV_NAME "vf610_nfc"
44 /* Register Offsets */
45 #define NFC_FLASH_CMD1 0x3F00
46 #define NFC_FLASH_CMD2 0x3F04
47 #define NFC_COL_ADDR 0x3F08
48 #define NFC_ROW_ADDR 0x3F0c
49 #define NFC_ROW_ADDR_INC 0x3F14
50 #define NFC_FLASH_STATUS1 0x3F18
51 #define NFC_FLASH_STATUS2 0x3F1c
52 #define NFC_CACHE_SWAP 0x3F28
53 #define NFC_SECTOR_SIZE 0x3F2c
54 #define NFC_FLASH_CONFIG 0x3F30
55 #define NFC_IRQ_STATUS 0x3F38
57 /* Addresses for NFC MAIN RAM BUFFER areas */
58 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
60 #define PAGE_2K 0x0800
62 #define OOB_MAX 0x0100
65 * NFC_CMD2[CODE] values. See section:
66 * - 31.4.7 Flash Command Code Description, Vybrid manual
67 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
69 * Briefly these are bitmasks of controller cycles.
71 #define READ_PAGE_CMD_CODE 0x7EE0
72 #define READ_ONFI_PARAM_CMD_CODE 0x4860
73 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
74 #define ERASE_CMD_CODE 0x4EC0
75 #define READ_ID_CMD_CODE 0x4804
76 #define RESET_CMD_CODE 0x4040
77 #define STATUS_READ_CMD_CODE 0x4068
79 /* NFC ECC mode define */
84 /*** Register Mask and bit definitions */
86 /* NFC_FLASH_CMD1 Field */
87 #define CMD_BYTE2_MASK 0xFF000000
88 #define CMD_BYTE2_SHIFT 24
90 /* NFC_FLASH_CM2 Field */
91 #define CMD_BYTE1_MASK 0xFF000000
92 #define CMD_BYTE1_SHIFT 24
93 #define CMD_CODE_MASK 0x00FFFF00
94 #define CMD_CODE_SHIFT 8
95 #define BUFNO_MASK 0x00000006
97 #define START_BIT BIT(0)
99 /* NFC_COL_ADDR Field */
100 #define COL_ADDR_MASK 0x0000FFFF
101 #define COL_ADDR_SHIFT 0
103 /* NFC_ROW_ADDR Field */
104 #define ROW_ADDR_MASK 0x00FFFFFF
105 #define ROW_ADDR_SHIFT 0
106 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
107 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
108 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
109 #define ROW_ADDR_CHIP_SEL_SHIFT 24
111 /* NFC_FLASH_STATUS2 Field */
112 #define STATUS_BYTE1_MASK 0x000000FF
114 /* NFC_FLASH_CONFIG Field */
115 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
116 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
117 #define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
118 #define CONFIG_DMA_REQ_BIT BIT(20)
119 #define CONFIG_ECC_MODE_MASK 0x000E0000
120 #define CONFIG_ECC_MODE_SHIFT 17
121 #define CONFIG_FAST_FLASH_BIT BIT(16)
122 #define CONFIG_16BIT BIT(7)
123 #define CONFIG_BOOT_MODE_BIT BIT(6)
124 #define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
125 #define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
126 #define CONFIG_PAGE_CNT_MASK 0xF
127 #define CONFIG_PAGE_CNT_SHIFT 0
129 /* NFC_IRQ_STATUS Field */
130 #define IDLE_IRQ_BIT BIT(29)
131 #define IDLE_EN_BIT BIT(20)
132 #define CMD_DONE_CLEAR_BIT BIT(18)
133 #define IDLE_CLEAR_BIT BIT(17)
136 * ECC status - seems to consume 8 bytes (double word). The documented
137 * status byte is located in the lowest byte of the second word (which is
138 * the 4th or 7th byte depending on endianness).
139 * Calculate an offset to store the ECC status at the end of the buffer.
141 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
143 #define ECC_STATUS 0x4
144 #define ECC_STATUS_MASK 0x80
145 #define ECC_STATUS_ERR_COUNT 0x3F
147 enum vf610_nfc_alt_buf
{
154 enum vf610_nfc_variant
{
159 struct nand_chip chip
;
162 struct completion cmd_done
;
165 /* Status and ID are in alternate locations. */
166 enum vf610_nfc_alt_buf alt_buf
;
167 enum vf610_nfc_variant variant
;
173 static inline struct vf610_nfc
*mtd_to_nfc(struct mtd_info
*mtd
)
175 return container_of(mtd_to_nand(mtd
), struct vf610_nfc
, chip
);
178 static struct nand_ecclayout vf610_nfc_ecc45
= {
180 .eccpos
= {19, 20, 21, 22, 23,
181 24, 25, 26, 27, 28, 29, 30, 31,
182 32, 33, 34, 35, 36, 37, 38, 39,
183 40, 41, 42, 43, 44, 45, 46, 47,
184 48, 49, 50, 51, 52, 53, 54, 55,
185 56, 57, 58, 59, 60, 61, 62, 63},
191 static struct nand_ecclayout vf610_nfc_ecc60
= {
193 .eccpos
= { 4, 5, 6, 7, 8, 9, 10, 11,
194 12, 13, 14, 15, 16, 17, 18, 19,
195 20, 21, 22, 23, 24, 25, 26, 27,
196 28, 29, 30, 31, 32, 33, 34, 35,
197 36, 37, 38, 39, 40, 41, 42, 43,
198 44, 45, 46, 47, 48, 49, 50, 51,
199 52, 53, 54, 55, 56, 57, 58, 59,
206 static inline u32
vf610_nfc_read(struct vf610_nfc
*nfc
, uint reg
)
208 return readl(nfc
->regs
+ reg
);
211 static inline void vf610_nfc_write(struct vf610_nfc
*nfc
, uint reg
, u32 val
)
213 writel(val
, nfc
->regs
+ reg
);
216 static inline void vf610_nfc_set(struct vf610_nfc
*nfc
, uint reg
, u32 bits
)
218 vf610_nfc_write(nfc
, reg
, vf610_nfc_read(nfc
, reg
) | bits
);
221 static inline void vf610_nfc_clear(struct vf610_nfc
*nfc
, uint reg
, u32 bits
)
223 vf610_nfc_write(nfc
, reg
, vf610_nfc_read(nfc
, reg
) & ~bits
);
226 static inline void vf610_nfc_set_field(struct vf610_nfc
*nfc
, u32 reg
,
227 u32 mask
, u32 shift
, u32 val
)
229 vf610_nfc_write(nfc
, reg
,
230 (vf610_nfc_read(nfc
, reg
) & (~mask
)) | val
<< shift
);
233 static inline void vf610_nfc_memcpy(void *dst
, const void __iomem
*src
,
237 * Use this accessor for the internal SRAM buffers. On the ARM
238 * Freescale Vybrid SoC it's known that the driver can treat
239 * the SRAM buffer as if it's memory. Other platform might need
240 * to treat the buffers differently.
242 * For the time being, use memcpy
247 /* Clear flags for upcoming command */
248 static inline void vf610_nfc_clear_status(struct vf610_nfc
*nfc
)
250 u32 tmp
= vf610_nfc_read(nfc
, NFC_IRQ_STATUS
);
252 tmp
|= CMD_DONE_CLEAR_BIT
| IDLE_CLEAR_BIT
;
253 vf610_nfc_write(nfc
, NFC_IRQ_STATUS
, tmp
);
256 static void vf610_nfc_done(struct vf610_nfc
*nfc
)
258 unsigned long timeout
= msecs_to_jiffies(100);
261 * Barrier is needed after this write. This write need
262 * to be done before reading the next register the first
264 * vf610_nfc_set implicates such a barrier by using writel
265 * to write to the register.
267 vf610_nfc_set(nfc
, NFC_IRQ_STATUS
, IDLE_EN_BIT
);
268 vf610_nfc_set(nfc
, NFC_FLASH_CMD2
, START_BIT
);
270 if (!wait_for_completion_timeout(&nfc
->cmd_done
, timeout
))
271 dev_warn(nfc
->dev
, "Timeout while waiting for BUSY.\n");
273 vf610_nfc_clear_status(nfc
);
276 static u8
vf610_nfc_get_id(struct vf610_nfc
*nfc
, int col
)
281 flash_id
= vf610_nfc_read(nfc
, NFC_FLASH_STATUS1
);
282 flash_id
>>= (3 - col
) * 8;
284 flash_id
= vf610_nfc_read(nfc
, NFC_FLASH_STATUS2
);
288 return flash_id
& 0xff;
291 static u8
vf610_nfc_get_status(struct vf610_nfc
*nfc
)
293 return vf610_nfc_read(nfc
, NFC_FLASH_STATUS2
) & STATUS_BYTE1_MASK
;
296 static void vf610_nfc_send_command(struct vf610_nfc
*nfc
, u32 cmd_byte1
,
301 vf610_nfc_clear_status(nfc
);
303 tmp
= vf610_nfc_read(nfc
, NFC_FLASH_CMD2
);
304 tmp
&= ~(CMD_BYTE1_MASK
| CMD_CODE_MASK
| BUFNO_MASK
);
305 tmp
|= cmd_byte1
<< CMD_BYTE1_SHIFT
;
306 tmp
|= cmd_code
<< CMD_CODE_SHIFT
;
307 vf610_nfc_write(nfc
, NFC_FLASH_CMD2
, tmp
);
310 static void vf610_nfc_send_commands(struct vf610_nfc
*nfc
, u32 cmd_byte1
,
311 u32 cmd_byte2
, u32 cmd_code
)
315 vf610_nfc_send_command(nfc
, cmd_byte1
, cmd_code
);
317 tmp
= vf610_nfc_read(nfc
, NFC_FLASH_CMD1
);
318 tmp
&= ~CMD_BYTE2_MASK
;
319 tmp
|= cmd_byte2
<< CMD_BYTE2_SHIFT
;
320 vf610_nfc_write(nfc
, NFC_FLASH_CMD1
, tmp
);
323 static irqreturn_t
vf610_nfc_irq(int irq
, void *data
)
325 struct mtd_info
*mtd
= data
;
326 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
328 vf610_nfc_clear(nfc
, NFC_IRQ_STATUS
, IDLE_EN_BIT
);
329 complete(&nfc
->cmd_done
);
334 static void vf610_nfc_addr_cycle(struct vf610_nfc
*nfc
, int column
, int page
)
337 if (nfc
->chip
.options
& NAND_BUSWIDTH_16
)
339 vf610_nfc_set_field(nfc
, NFC_COL_ADDR
, COL_ADDR_MASK
,
340 COL_ADDR_SHIFT
, column
);
343 vf610_nfc_set_field(nfc
, NFC_ROW_ADDR
, ROW_ADDR_MASK
,
344 ROW_ADDR_SHIFT
, page
);
347 static inline void vf610_nfc_ecc_mode(struct vf610_nfc
*nfc
, int ecc_mode
)
349 vf610_nfc_set_field(nfc
, NFC_FLASH_CONFIG
,
350 CONFIG_ECC_MODE_MASK
,
351 CONFIG_ECC_MODE_SHIFT
, ecc_mode
);
354 static inline void vf610_nfc_transfer_size(struct vf610_nfc
*nfc
, int size
)
356 vf610_nfc_write(nfc
, NFC_SECTOR_SIZE
, size
);
359 static void vf610_nfc_command(struct mtd_info
*mtd
, unsigned command
,
360 int column
, int page
)
362 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
363 int trfr_sz
= nfc
->chip
.options
& NAND_BUSWIDTH_16
? 1 : 0;
365 nfc
->buf_offset
= max(column
, 0);
366 nfc
->alt_buf
= ALT_BUF_DATA
;
370 /* Use valid column/page from preread... */
371 vf610_nfc_addr_cycle(nfc
, column
, page
);
375 * SEQIN => data => PAGEPROG sequence is done by the controller
376 * hence we do not need to issue the command here...
379 case NAND_CMD_PAGEPROG
:
380 trfr_sz
+= nfc
->write_sz
;
381 vf610_nfc_transfer_size(nfc
, trfr_sz
);
382 vf610_nfc_send_commands(nfc
, NAND_CMD_SEQIN
,
383 command
, PROGRAM_PAGE_CMD_CODE
);
385 vf610_nfc_ecc_mode(nfc
, nfc
->ecc_mode
);
387 vf610_nfc_ecc_mode(nfc
, ECC_BYPASS
);
391 vf610_nfc_transfer_size(nfc
, 0);
392 vf610_nfc_send_command(nfc
, command
, RESET_CMD_CODE
);
395 case NAND_CMD_READOOB
:
396 trfr_sz
+= mtd
->oobsize
;
397 column
= mtd
->writesize
;
398 vf610_nfc_transfer_size(nfc
, trfr_sz
);
399 vf610_nfc_send_commands(nfc
, NAND_CMD_READ0
,
400 NAND_CMD_READSTART
, READ_PAGE_CMD_CODE
);
401 vf610_nfc_addr_cycle(nfc
, column
, page
);
402 vf610_nfc_ecc_mode(nfc
, ECC_BYPASS
);
406 trfr_sz
+= mtd
->writesize
+ mtd
->oobsize
;
407 vf610_nfc_transfer_size(nfc
, trfr_sz
);
408 vf610_nfc_send_commands(nfc
, NAND_CMD_READ0
,
409 NAND_CMD_READSTART
, READ_PAGE_CMD_CODE
);
410 vf610_nfc_addr_cycle(nfc
, column
, page
);
411 vf610_nfc_ecc_mode(nfc
, nfc
->ecc_mode
);
415 nfc
->alt_buf
= ALT_BUF_ONFI
;
416 trfr_sz
= 3 * sizeof(struct nand_onfi_params
);
417 vf610_nfc_transfer_size(nfc
, trfr_sz
);
418 vf610_nfc_send_command(nfc
, command
, READ_ONFI_PARAM_CMD_CODE
);
419 vf610_nfc_addr_cycle(nfc
, -1, column
);
420 vf610_nfc_ecc_mode(nfc
, ECC_BYPASS
);
423 case NAND_CMD_ERASE1
:
424 vf610_nfc_transfer_size(nfc
, 0);
425 vf610_nfc_send_commands(nfc
, command
,
426 NAND_CMD_ERASE2
, ERASE_CMD_CODE
);
427 vf610_nfc_addr_cycle(nfc
, column
, page
);
430 case NAND_CMD_READID
:
431 nfc
->alt_buf
= ALT_BUF_ID
;
433 vf610_nfc_transfer_size(nfc
, 0);
434 vf610_nfc_send_command(nfc
, command
, READ_ID_CMD_CODE
);
435 vf610_nfc_addr_cycle(nfc
, -1, column
);
438 case NAND_CMD_STATUS
:
439 nfc
->alt_buf
= ALT_BUF_STAT
;
440 vf610_nfc_transfer_size(nfc
, 0);
441 vf610_nfc_send_command(nfc
, command
, STATUS_READ_CMD_CODE
);
449 nfc
->use_hw_ecc
= false;
453 static void vf610_nfc_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
455 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
456 uint c
= nfc
->buf_offset
;
458 /* Alternate buffers are only supported through read_byte */
459 WARN_ON(nfc
->alt_buf
);
461 vf610_nfc_memcpy(buf
, nfc
->regs
+ NFC_MAIN_AREA(0) + c
, len
);
463 nfc
->buf_offset
+= len
;
466 static void vf610_nfc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
469 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
470 uint c
= nfc
->buf_offset
;
473 l
= min_t(uint
, len
, mtd
->writesize
+ mtd
->oobsize
- c
);
474 vf610_nfc_memcpy(nfc
->regs
+ NFC_MAIN_AREA(0) + c
, buf
, l
);
477 nfc
->buf_offset
+= l
;
480 static uint8_t vf610_nfc_read_byte(struct mtd_info
*mtd
)
482 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
484 uint c
= nfc
->buf_offset
;
486 switch (nfc
->alt_buf
) {
488 tmp
= vf610_nfc_get_id(nfc
, c
);
491 tmp
= vf610_nfc_get_status(nfc
);
493 #ifdef __LITTLE_ENDIAN
495 /* Reverse byte since the controller uses big endianness */
496 c
= nfc
->buf_offset
^ 0x3;
500 tmp
= *((u8
*)(nfc
->regs
+ NFC_MAIN_AREA(0) + c
));
507 static u16
vf610_nfc_read_word(struct mtd_info
*mtd
)
511 vf610_nfc_read_buf(mtd
, (u_char
*)&tmp
, sizeof(tmp
));
515 /* If not provided, upper layers apply a fixed delay. */
516 static int vf610_nfc_dev_ready(struct mtd_info
*mtd
)
518 /* NFC handles R/B internally; always ready. */
523 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
525 static void vf610_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
527 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
528 u32 tmp
= vf610_nfc_read(nfc
, NFC_ROW_ADDR
);
530 /* Vybrid only (MPC5125 would have full RB and four CS) */
531 if (nfc
->variant
!= NFC_VFC610
)
534 tmp
&= ~(ROW_ADDR_CHIP_SEL_RB_MASK
| ROW_ADDR_CHIP_SEL_MASK
);
537 tmp
|= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT
;
538 tmp
|= BIT(chip
) << ROW_ADDR_CHIP_SEL_SHIFT
;
541 vf610_nfc_write(nfc
, NFC_ROW_ADDR
, tmp
);
544 /* Count the number of 0's in buff up to max_bits */
545 static inline int count_written_bits(uint8_t *buff
, int size
, int max_bits
)
547 uint32_t *buff32
= (uint32_t *)buff
;
548 int k
, written_bits
= 0;
550 for (k
= 0; k
< (size
/ 4); k
++) {
551 written_bits
+= hweight32(~buff32
[k
]);
552 if (unlikely(written_bits
> max_bits
))
559 static inline int vf610_nfc_correct_data(struct mtd_info
*mtd
, uint8_t *dat
,
560 uint8_t *oob
, int page
)
562 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
563 u32 ecc_status_off
= NFC_MAIN_AREA(0) + ECC_SRAM_ADDR
+ ECC_STATUS
;
566 int flips_threshold
= nfc
->chip
.ecc
.strength
/ 2;
568 ecc_status
= vf610_nfc_read(nfc
, ecc_status_off
) & 0xff;
569 ecc_count
= ecc_status
& ECC_STATUS_ERR_COUNT
;
571 if (!(ecc_status
& ECC_STATUS_MASK
))
574 /* Read OOB without ECC unit enabled */
575 vf610_nfc_command(mtd
, NAND_CMD_READOOB
, 0, page
);
576 vf610_nfc_read_buf(mtd
, oob
, mtd
->oobsize
);
579 * On an erased page, bit count (including OOB) should be zero or
580 * at least less then half of the ECC strength.
582 return nand_check_erased_ecc_chunk(dat
, nfc
->chip
.ecc
.size
, oob
,
583 mtd
->oobsize
, NULL
, 0,
587 static int vf610_nfc_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
588 uint8_t *buf
, int oob_required
, int page
)
590 int eccsize
= chip
->ecc
.size
;
593 vf610_nfc_read_buf(mtd
, buf
, eccsize
);
595 vf610_nfc_read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
597 stat
= vf610_nfc_correct_data(mtd
, buf
, chip
->oob_poi
, page
);
600 mtd
->ecc_stats
.failed
++;
603 mtd
->ecc_stats
.corrected
+= stat
;
608 static int vf610_nfc_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
609 const uint8_t *buf
, int oob_required
, int page
)
611 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
613 vf610_nfc_write_buf(mtd
, buf
, mtd
->writesize
);
615 vf610_nfc_write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
617 /* Always write whole page including OOB due to HW ECC */
618 nfc
->use_hw_ecc
= true;
619 nfc
->write_sz
= mtd
->writesize
+ mtd
->oobsize
;
624 static const struct of_device_id vf610_nfc_dt_ids
[] = {
625 { .compatible
= "fsl,vf610-nfc", .data
= (void *)NFC_VFC610
},
628 MODULE_DEVICE_TABLE(of
, vf610_nfc_dt_ids
);
630 static void vf610_nfc_preinit_controller(struct vf610_nfc
*nfc
)
632 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_16BIT
);
633 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_ADDR_AUTO_INCR_BIT
);
634 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_BUFNO_AUTO_INCR_BIT
);
635 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_BOOT_MODE_BIT
);
636 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_DMA_REQ_BIT
);
637 vf610_nfc_set(nfc
, NFC_FLASH_CONFIG
, CONFIG_FAST_FLASH_BIT
);
639 /* Disable virtual pages, only one elementary transfer unit */
640 vf610_nfc_set_field(nfc
, NFC_FLASH_CONFIG
, CONFIG_PAGE_CNT_MASK
,
641 CONFIG_PAGE_CNT_SHIFT
, 1);
644 static void vf610_nfc_init_controller(struct vf610_nfc
*nfc
)
646 if (nfc
->chip
.options
& NAND_BUSWIDTH_16
)
647 vf610_nfc_set(nfc
, NFC_FLASH_CONFIG
, CONFIG_16BIT
);
649 vf610_nfc_clear(nfc
, NFC_FLASH_CONFIG
, CONFIG_16BIT
);
651 if (nfc
->chip
.ecc
.mode
== NAND_ECC_HW
) {
652 /* Set ECC status offset in SRAM */
653 vf610_nfc_set_field(nfc
, NFC_FLASH_CONFIG
,
654 CONFIG_ECC_SRAM_ADDR_MASK
,
655 CONFIG_ECC_SRAM_ADDR_SHIFT
,
658 /* Enable ECC status in SRAM */
659 vf610_nfc_set(nfc
, NFC_FLASH_CONFIG
, CONFIG_ECC_SRAM_REQ_BIT
);
663 static int vf610_nfc_probe(struct platform_device
*pdev
)
665 struct vf610_nfc
*nfc
;
666 struct resource
*res
;
667 struct mtd_info
*mtd
;
668 struct nand_chip
*chip
;
669 struct device_node
*child
;
670 const struct of_device_id
*of_id
;
674 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(*nfc
), GFP_KERNEL
);
678 nfc
->dev
= &pdev
->dev
;
680 mtd
= nand_to_mtd(chip
);
682 mtd
->owner
= THIS_MODULE
;
683 mtd
->dev
.parent
= nfc
->dev
;
684 mtd
->name
= DRV_NAME
;
686 irq
= platform_get_irq(pdev
, 0);
690 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
691 nfc
->regs
= devm_ioremap_resource(nfc
->dev
, res
);
692 if (IS_ERR(nfc
->regs
))
693 return PTR_ERR(nfc
->regs
);
695 nfc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
696 if (IS_ERR(nfc
->clk
))
697 return PTR_ERR(nfc
->clk
);
699 err
= clk_prepare_enable(nfc
->clk
);
701 dev_err(nfc
->dev
, "Unable to enable clock!\n");
705 of_id
= of_match_device(vf610_nfc_dt_ids
, &pdev
->dev
);
706 nfc
->variant
= (enum vf610_nfc_variant
)of_id
->data
;
708 for_each_available_child_of_node(nfc
->dev
->of_node
, child
) {
709 if (of_device_is_compatible(child
, "fsl,vf610-nfc-nandcs")) {
711 if (nand_get_flash_node(chip
)) {
713 "Only one NAND chip supported!\n");
718 nand_set_flash_node(chip
, child
);
722 if (!nand_get_flash_node(chip
)) {
723 dev_err(nfc
->dev
, "NAND chip sub-node missing!\n");
728 chip
->dev_ready
= vf610_nfc_dev_ready
;
729 chip
->cmdfunc
= vf610_nfc_command
;
730 chip
->read_byte
= vf610_nfc_read_byte
;
731 chip
->read_word
= vf610_nfc_read_word
;
732 chip
->read_buf
= vf610_nfc_read_buf
;
733 chip
->write_buf
= vf610_nfc_write_buf
;
734 chip
->select_chip
= vf610_nfc_select_chip
;
736 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
738 init_completion(&nfc
->cmd_done
);
740 err
= devm_request_irq(nfc
->dev
, irq
, vf610_nfc_irq
, 0, DRV_NAME
, mtd
);
742 dev_err(nfc
->dev
, "Error requesting IRQ!\n");
746 vf610_nfc_preinit_controller(nfc
);
748 /* first scan to find the device and get the page size */
749 if (nand_scan_ident(mtd
, 1, NULL
)) {
754 vf610_nfc_init_controller(nfc
);
756 /* Bad block options. */
757 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
)
758 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
760 /* Single buffer only, max 256 OOB minus ECC status */
761 if (mtd
->writesize
+ mtd
->oobsize
> PAGE_2K
+ OOB_MAX
- 8) {
762 dev_err(nfc
->dev
, "Unsupported flash page size\n");
767 if (chip
->ecc
.mode
== NAND_ECC_HW
) {
768 if (mtd
->writesize
!= PAGE_2K
&& mtd
->oobsize
< 64) {
769 dev_err(nfc
->dev
, "Unsupported flash with hwecc\n");
774 if (chip
->ecc
.size
!= mtd
->writesize
) {
775 dev_err(nfc
->dev
, "Step size needs to be page size\n");
780 /* Only 64 byte ECC layouts known */
781 if (mtd
->oobsize
> 64)
784 if (chip
->ecc
.strength
== 32) {
785 nfc
->ecc_mode
= ECC_60_BYTE
;
786 chip
->ecc
.bytes
= 60;
787 chip
->ecc
.layout
= &vf610_nfc_ecc60
;
788 } else if (chip
->ecc
.strength
== 24) {
789 nfc
->ecc_mode
= ECC_45_BYTE
;
790 chip
->ecc
.bytes
= 45;
791 chip
->ecc
.layout
= &vf610_nfc_ecc45
;
793 dev_err(nfc
->dev
, "Unsupported ECC strength\n");
798 chip
->ecc
.read_page
= vf610_nfc_read_page
;
799 chip
->ecc
.write_page
= vf610_nfc_write_page
;
801 chip
->ecc
.size
= PAGE_2K
;
804 /* second phase scan */
805 if (nand_scan_tail(mtd
)) {
810 platform_set_drvdata(pdev
, mtd
);
812 /* Register device in MTD */
813 return mtd_device_register(mtd
, NULL
, 0);
816 of_node_put(nand_get_flash_node(chip
));
818 clk_disable_unprepare(nfc
->clk
);
822 static int vf610_nfc_remove(struct platform_device
*pdev
)
824 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
825 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
828 clk_disable_unprepare(nfc
->clk
);
832 #ifdef CONFIG_PM_SLEEP
833 static int vf610_nfc_suspend(struct device
*dev
)
835 struct mtd_info
*mtd
= dev_get_drvdata(dev
);
836 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
838 clk_disable_unprepare(nfc
->clk
);
842 static int vf610_nfc_resume(struct device
*dev
)
844 struct mtd_info
*mtd
= dev_get_drvdata(dev
);
845 struct vf610_nfc
*nfc
= mtd_to_nfc(mtd
);
847 pinctrl_pm_select_default_state(dev
);
849 clk_prepare_enable(nfc
->clk
);
851 vf610_nfc_preinit_controller(nfc
);
852 vf610_nfc_init_controller(nfc
);
857 static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops
, vf610_nfc_suspend
, vf610_nfc_resume
);
859 static struct platform_driver vf610_nfc_driver
= {
862 .of_match_table
= vf610_nfc_dt_ids
,
863 .pm
= &vf610_nfc_pm_ops
,
865 .probe
= vf610_nfc_probe
,
866 .remove
= vf610_nfc_remove
,
869 module_platform_driver(vf610_nfc_driver
);
871 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
872 MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
873 MODULE_LICENSE("GPL");