drivers/mtd/spi-nor/atmel-quadspi.c

   1 /*
   2  * Driver for Atmel QSPI Controller
   3  *
   4  * Copyright (C) 2015 Atmel Corporation
   5  *
   6  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/clk.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/mtd/spi-nor.h>
  33 #include <linux/platform_data/atmel.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/io.h>
  37 #include <linux/gpio.h>
  38 #include <linux/pinctrl/consumer.h>
  39
  40 /* QSPI register offsets */
  41 #define QSPI_CR      0x0000  /* Control Register */
  42 #define QSPI_MR      0x0004  /* Mode Register */
  43 #define QSPI_RD      0x0008  /* Receive Data Register */
  44 #define QSPI_TD      0x000c  /* Transmit Data Register */
  45 #define QSPI_SR      0x0010  /* Status Register */
  46 #define QSPI_IER     0x0014  /* Interrupt Enable Register */
  47 #define QSPI_IDR     0x0018  /* Interrupt Disable Register */
  48 #define QSPI_IMR     0x001c  /* Interrupt Mask Register */
  49 #define QSPI_SCR     0x0020  /* Serial Clock Register */
  50
  51 #define QSPI_IAR     0x0030  /* Instruction Address Register */
  52 #define QSPI_ICR     0x0034  /* Instruction Code Register */
  53 #define QSPI_IFR     0x0038  /* Instruction Frame Register */
  54
  55 #define QSPI_SMR     0x0040  /* Scrambling Mode Register */
  56 #define QSPI_SKR     0x0044  /* Scrambling Key Register */
  57
  58 #define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
  59 #define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
  60
  61 #define QSPI_VERSION 0x00FC  /* Version Register */
  62
  63
  64 /* Bitfields in QSPI_CR (Control Register) */
  65 #define QSPI_CR_QSPIEN                  BIT(0)
  66 #define QSPI_CR_QSPIDIS                 BIT(1)
  67 #define QSPI_CR_SWRST                   BIT(7)
  68 #define QSPI_CR_LASTXFER                BIT(24)
  69
  70 /* Bitfields in QSPI_MR (Mode Register) */
  71 #define QSPI_MR_SSM                     BIT(0)
  72 #define QSPI_MR_LLB                     BIT(1)
  73 #define QSPI_MR_WDRBT                   BIT(2)
  74 #define QSPI_MR_SMRM                    BIT(3)
  75 #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
  76 #define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
  77 #define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
  78 #define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
  79 #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
  80 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  81 #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
  82 #define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  83 #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
  84 #define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
  85
  86 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
  87 #define QSPI_SR_RDRF                    BIT(0)
  88 #define QSPI_SR_TDRE                    BIT(1)
  89 #define QSPI_SR_TXEMPTY                 BIT(2)
  90 #define QSPI_SR_OVRES                   BIT(3)
  91 #define QSPI_SR_CSR                     BIT(8)
  92 #define QSPI_SR_CSS                     BIT(9)
  93 #define QSPI_SR_INSTRE                  BIT(10)
  94 #define QSPI_SR_QSPIENS                 BIT(24)
  95
  96 #define QSPI_SR_CMD_COMPLETED   (QSPI_SR_INSTRE | QSPI_SR_CSR)
  97
  98 /* Bitfields in QSPI_SCR (Serial Clock Register) */
  99 #define QSPI_SCR_CPOL                   BIT(0)
 100 #define QSPI_SCR_CPHA                   BIT(1)
 101 #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
 102 #define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
 103 #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
 104 #define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
 105
 106 /* Bitfields in QSPI_ICR (Instruction Code Register) */
 107 #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
 108 #define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
 109 #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
 110 #define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
 111
 112 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
 113 #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
 114 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
 115 #define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
 116 #define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
 117 #define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
 118 #define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
 119 #define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
 120 #define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
 121 #define QSPI_IFR_INSTEN                 BIT(4)
 122 #define QSPI_IFR_ADDREN                 BIT(5)
 123 #define QSPI_IFR_OPTEN                  BIT(6)
 124 #define QSPI_IFR_DATAEN                 BIT(7)
 125 #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
 126 #define QSPI_IFR_OPTL_1BIT              (0 << 8)
 127 #define QSPI_IFR_OPTL_2BIT              (1 << 8)
 128 #define QSPI_IFR_OPTL_4BIT              (2 << 8)
 129 #define QSPI_IFR_OPTL_8BIT              (3 << 8)
 130 #define QSPI_IFR_ADDRL                  BIT(10)
 131 #define QSPI_IFR_TFRTYP_MASK            GENMASK(13, 12)
 132 #define QSPI_IFR_TFRTYP_TRSFR_READ      (0 << 12)
 133 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM  (1 << 12)
 134 #define QSPI_IFR_TFRTYP_TRSFR_WRITE     (2 << 12)
 135 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
 136 #define QSPI_IFR_CRM                    BIT(14)
 137 #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
 138 #define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
 139
 140 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
 141 #define QSPI_SMR_SCREN                  BIT(0)
 142 #define QSPI_SMR_RVDIS                  BIT(1)
 143
 144 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
 145 #define QSPI_WPMR_WPEN                  BIT(0)
 146 #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
 147 #define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
 148
 149 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
 150 #define QSPI_WPSR_WPVS                  BIT(0)
 151 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
 152 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 153
 154
 155 struct atmel_qspi {
 156         void __iomem            *regs;
 157         void __iomem            *mem;
 158         struct clk              *clk;
 159         struct platform_device  *pdev;
 160         u32                     pending;
 161
 162         struct spi_nor          nor;
 163         u32                     clk_rate;
 164         struct completion       cmd_completion;
 165 };
 166
 167 struct atmel_qspi_command {
 168         union {
 169                 struct {
 170                         u32     instruction:1;
 171                         u32     address:3;
 172                         u32     mode:1;
 173                         u32     dummy:1;
 174                         u32     data:1;
 175                         u32     reserved:25;
 176                 }               bits;
 177                 u32     word;
 178         }       enable;
 179         u8      instruction;
 180         u8      mode;
 181         u8      num_mode_cycles;
 182         u8      num_dummy_cycles;
 183         u32     address;
 184
 185         size_t          buf_len;
 186         const void      *tx_buf;
 187         void            *rx_buf;
 188 };
 189
 190 /* Register access functions */
 191 static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
 192 {
 193         return readl_relaxed(aq->regs + reg);
 194 }
 195
 196 static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
 197 {
 198         writel_relaxed(value, aq->regs + reg);
 199 }
 200
 201 static int atmel_qspi_run_transfer(struct atmel_qspi *aq,
 202                                    const struct atmel_qspi_command *cmd)
 203 {
 204         void __iomem *ahb_mem;
 205
 206         /* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */
 207         ahb_mem = aq->mem;
 208         if (cmd->enable.bits.address)
 209                 ahb_mem += cmd->address;
 210         if (cmd->tx_buf)
 211                 _memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len);
 212         else
 213                 _memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len);
 214
 215         return 0;
 216 }
 217
 218 #ifdef DEBUG
 219 static void atmel_qspi_debug_command(struct atmel_qspi *aq,
 220                                      const struct atmel_qspi_command *cmd,
 221                                      u32 ifr)
 222 {
 223         u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
 224         size_t len = 0;
 225         int i;
 226
 227         if (cmd->enable.bits.instruction)
 228                 cmd_buf[len++] = cmd->instruction;
 229
 230         for (i = cmd->enable.bits.address-1; i >= 0; --i)
 231                 cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff;
 232
 233         if (cmd->enable.bits.mode)
 234                 cmd_buf[len++] = cmd->mode;
 235
 236         if (cmd->enable.bits.dummy) {
 237                 int num = cmd->num_dummy_cycles;
 238
 239                 switch (ifr & QSPI_IFR_WIDTH_MASK) {
 240                 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
 241                 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
 242                 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
 243                         num >>= 3;
 244                         break;
 245                 case QSPI_IFR_WIDTH_DUAL_IO:
 246                 case QSPI_IFR_WIDTH_DUAL_CMD:
 247                         num >>= 2;
 248                         break;
 249                 case QSPI_IFR_WIDTH_QUAD_IO:
 250                 case QSPI_IFR_WIDTH_QUAD_CMD:
 251                         num >>= 1;
 252                         break;
 253                 default:
 254                         return;
 255                 }
 256
 257                 for (i = 0; i < num; ++i)
 258                         cmd_buf[len++] = 0;
 259         }
 260
 261         /* Dump the SPI command */
 262         print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE,
 263                        32, 1, cmd_buf, len, false);
 264
 265 #ifdef VERBOSE_DEBUG
 266         /* If verbose debug is enabled, also dump the TX data */
 267         if (cmd->enable.bits.data && cmd->tx_buf)
 268                 print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE,
 269                                32, 1, cmd->tx_buf, cmd->buf_len, false);
 270 #endif
 271 }
 272 #else
 273 #define atmel_qspi_debug_command(aq, cmd, ifr)
 274 #endif
 275
 276 static int atmel_qspi_run_command(struct atmel_qspi *aq,
 277                                   const struct atmel_qspi_command *cmd,
 278                                   u32 ifr_tfrtyp, u32 ifr_width)
 279 {
 280         u32 iar, icr, ifr, sr;
 281         int err = 0;
 282
 283         iar = 0;
 284         icr = 0;
 285         ifr = ifr_tfrtyp | ifr_width;
 286
 287         /* Compute instruction parameters */
 288         if (cmd->enable.bits.instruction) {
 289                 icr |= QSPI_ICR_INST(cmd->instruction);
 290                 ifr |= QSPI_IFR_INSTEN;
 291         }
 292
 293         /* Compute address parameters */
 294         switch (cmd->enable.bits.address) {
 295         case 4:
 296                 ifr |= QSPI_IFR_ADDRL;
 297                 /* fall through to the 24bit (3 byte) address case. */
 298         case 3:
 299                 iar = (cmd->enable.bits.data) ? 0 : cmd->address;
 300                 ifr |= QSPI_IFR_ADDREN;
 301                 break;
 302         case 0:
 303                 break;
 304         default:
 305                 return -EINVAL;
 306         }
 307
 308         /* Compute option parameters */
 309         if (cmd->enable.bits.mode && cmd->num_mode_cycles) {
 310                 u32 mode_cycle_bits, mode_bits;
 311
 312                 icr |= QSPI_ICR_OPT(cmd->mode);
 313                 ifr |= QSPI_IFR_OPTEN;
 314
 315                 switch (ifr & QSPI_IFR_WIDTH_MASK) {
 316                 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
 317                 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
 318                 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
 319                         mode_cycle_bits = 1;
 320                         break;
 321                 case QSPI_IFR_WIDTH_DUAL_IO:
 322                 case QSPI_IFR_WIDTH_DUAL_CMD:
 323                         mode_cycle_bits = 2;
 324                         break;
 325                 case QSPI_IFR_WIDTH_QUAD_IO:
 326                 case QSPI_IFR_WIDTH_QUAD_CMD:
 327                         mode_cycle_bits = 4;
 328                         break;
 329                 default:
 330                         return -EINVAL;
 331                 }
 332
 333                 mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
 334                 switch (mode_bits) {
 335                 case 1:
 336                         ifr |= QSPI_IFR_OPTL_1BIT;
 337                         break;
 338
 339                 case 2:
 340                         ifr |= QSPI_IFR_OPTL_2BIT;
 341                         break;
 342
 343                 case 4:
 344                         ifr |= QSPI_IFR_OPTL_4BIT;
 345                         break;
 346
 347                 case 8:
 348                         ifr |= QSPI_IFR_OPTL_8BIT;
 349                         break;
 350
 351                 default:
 352                         return -EINVAL;
 353                 }
 354         }
 355
 356         /* Set number of dummy cycles */
 357         if (cmd->enable.bits.dummy)
 358                 ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
 359
 360         /* Set data enable */
 361         if (cmd->enable.bits.data) {
 362                 ifr |= QSPI_IFR_DATAEN;
 363
 364                 /* Special case for Continuous Read Mode */
 365                 if (!cmd->tx_buf && !cmd->rx_buf)
 366                         ifr |= QSPI_IFR_CRM;
 367         }
 368
 369         /* Clear pending interrupts */
 370         (void)qspi_readl(aq, QSPI_SR);
 371
 372         /* Set QSPI Instruction Frame registers */
 373         atmel_qspi_debug_command(aq, cmd, ifr);
 374         qspi_writel(aq, QSPI_IAR, iar);
 375         qspi_writel(aq, QSPI_ICR, icr);
 376         qspi_writel(aq, QSPI_IFR, ifr);
 377
 378         /* Skip to the final steps if there is no data */
 379         if (!cmd->enable.bits.data)
 380                 goto no_data;
 381
 382         /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
 383         (void)qspi_readl(aq, QSPI_IFR);
 384
 385         /* Stop here for continuous read */
 386         if (!cmd->tx_buf && !cmd->rx_buf)
 387                 return 0;
 388         /* Send/Receive data */
 389         err = atmel_qspi_run_transfer(aq, cmd);
 390
 391         /* Release the chip-select */
 392         qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
 393
 394         if (err)
 395                 return err;
 396
 397 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
 398         /*
 399          * If verbose debug is enabled, also dump the RX data in addition to
 400          * the SPI command previously dumped by atmel_qspi_debug_command()
 401          */
 402         if (cmd->rx_buf)
 403                 print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE,
 404                                32, 1, cmd->rx_buf, cmd->buf_len, false);
 405 #endif
 406 no_data:
 407         /* Poll INSTRuction End status */
 408         sr = qspi_readl(aq, QSPI_SR);
 409         if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 410                 return err;
 411
 412         /* Wait for INSTRuction End interrupt */
 413         reinit_completion(&aq->cmd_completion);
 414         aq->pending = sr & QSPI_SR_CMD_COMPLETED;
 415         qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
 416         if (!wait_for_completion_timeout(&aq->cmd_completion,
 417                                          msecs_to_jiffies(1000)))
 418                 err = -ETIMEDOUT;
 419         qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
 420
 421         return err;
 422 }
 423
 424 static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
 425                                u8 *buf, int len)
 426 {
 427         struct atmel_qspi *aq = nor->priv;
 428         struct atmel_qspi_command cmd;
 429
 430         memset(&cmd, 0, sizeof(cmd));
 431         cmd.enable.bits.instruction = 1;
 432         cmd.enable.bits.data = 1;
 433         cmd.instruction = opcode;
 434         cmd.rx_buf = buf;
 435         cmd.buf_len = len;
 436         return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
 437                                       QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
 438 }
 439
 440 static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
 441                                 u8 *buf, int len)
 442 {
 443         struct atmel_qspi *aq = nor->priv;
 444         struct atmel_qspi_command cmd;
 445
 446         memset(&cmd, 0, sizeof(cmd));
 447         cmd.enable.bits.instruction = 1;
 448         cmd.enable.bits.data = (buf != NULL && len > 0);
 449         cmd.instruction = opcode;
 450         cmd.tx_buf = buf;
 451         cmd.buf_len = len;
 452         return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
 453                                       QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
 454 }
 455
 456 static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
 457                                 const u_char *write_buf)
 458 {
 459         struct atmel_qspi *aq = nor->priv;
 460         struct atmel_qspi_command cmd;
 461         ssize_t ret;
 462
 463         memset(&cmd, 0, sizeof(cmd));
 464         cmd.enable.bits.instruction = 1;
 465         cmd.enable.bits.address = nor->addr_width;
 466         cmd.enable.bits.data = 1;
 467         cmd.instruction = nor->program_opcode;
 468         cmd.address = (u32)to;
 469         cmd.tx_buf = write_buf;
 470         cmd.buf_len = len;
 471         ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
 472                                      QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
 473         return (ret < 0) ? ret : len;
 474 }
 475
 476 static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
 477 {
 478         struct atmel_qspi *aq = nor->priv;
 479         struct atmel_qspi_command cmd;
 480
 481         memset(&cmd, 0, sizeof(cmd));
 482         cmd.enable.bits.instruction = 1;
 483         cmd.enable.bits.address = nor->addr_width;
 484         cmd.instruction = nor->erase_opcode;
 485         cmd.address = (u32)offs;
 486         return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
 487                                       QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
 488 }
 489
 490 static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
 491                                u_char *read_buf)
 492 {
 493         struct atmel_qspi *aq = nor->priv;
 494         struct atmel_qspi_command cmd;
 495         u8 num_mode_cycles, num_dummy_cycles;
 496         u32 ifr_width;
 497         ssize_t ret;
 498
 499         switch (nor->flash_read) {
 500         case SPI_NOR_NORMAL:
 501         case SPI_NOR_FAST:
 502                 ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
 503                 break;
 504
 505         case SPI_NOR_DUAL:
 506                 ifr_width = QSPI_IFR_WIDTH_DUAL_OUTPUT;
 507                 break;
 508
 509         case SPI_NOR_QUAD:
 510                 ifr_width = QSPI_IFR_WIDTH_QUAD_OUTPUT;
 511                 break;
 512
 513         default:
 514                 return -EINVAL;
 515         }
 516
 517         if (nor->read_dummy >= 2) {
 518                 num_mode_cycles = 2;
 519                 num_dummy_cycles = nor->read_dummy - 2;
 520         } else {
 521                 num_mode_cycles = nor->read_dummy;
 522                 num_dummy_cycles = 0;
 523         }
 524
 525         memset(&cmd, 0, sizeof(cmd));
 526         cmd.enable.bits.instruction = 1;
 527         cmd.enable.bits.address = nor->addr_width;
 528         cmd.enable.bits.mode = (num_mode_cycles > 0);
 529         cmd.enable.bits.dummy = (num_dummy_cycles > 0);
 530         cmd.enable.bits.data = 1;
 531         cmd.instruction = nor->read_opcode;
 532         cmd.address = (u32)from;
 533         cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */
 534         cmd.num_mode_cycles = num_mode_cycles;
 535         cmd.num_dummy_cycles = num_dummy_cycles;
 536         cmd.rx_buf = read_buf;
 537         cmd.buf_len = len;
 538         ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
 539                                      ifr_width);
 540         return (ret < 0) ? ret : len;
 541 }
 542
 543 static int atmel_qspi_init(struct atmel_qspi *aq)
 544 {
 545         unsigned long src_rate;
 546         u32 mr, scr, scbr;
 547
 548         /* Reset the QSPI controller */
 549         qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
 550
 551         /* Set the QSPI controller in Serial Memory Mode */
 552         mr = QSPI_MR_NBBITS(8) | QSPI_MR_SSM;
 553         qspi_writel(aq, QSPI_MR, mr);
 554
 555         src_rate = clk_get_rate(aq->clk);
 556         if (!src_rate)
 557                 return -EINVAL;
 558
 559         /* Compute the QSPI baudrate */
 560         scbr = DIV_ROUND_UP(src_rate, aq->clk_rate);
 561         if (scbr > 0)
 562                 scbr--;
 563         scr = QSPI_SCR_SCBR(scbr);
 564         qspi_writel(aq, QSPI_SCR, scr);
 565
 566         /* Enable the QSPI controller */
 567         qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
 568
 569         return 0;
 570 }
 571
 572 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
 573 {
 574         struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
 575         u32 status, mask, pending;
 576
 577         status = qspi_readl(aq, QSPI_SR);
 578         mask = qspi_readl(aq, QSPI_IMR);
 579         pending = status & mask;
 580
 581         if (!pending)
 582                 return IRQ_NONE;
 583
 584         aq->pending |= pending;
 585         if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 586                 complete(&aq->cmd_completion);
 587
 588         return IRQ_HANDLED;
 589 }
 590
 591 static int atmel_qspi_probe(struct platform_device *pdev)
 592 {
 593         struct device_node *child, *np = pdev->dev.of_node;
 594         struct atmel_qspi *aq;
 595         struct resource *res;
 596         struct spi_nor *nor;
 597         struct mtd_info *mtd;
 598         int irq, err = 0;
 599
 600         if (of_get_child_count(np) != 1)
 601                 return -ENODEV;
 602         child = of_get_next_child(np, NULL);
 603
 604         aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
 605         if (!aq) {
 606                 err = -ENOMEM;
 607                 goto exit;
 608         }
 609
 610         platform_set_drvdata(pdev, aq);
 611         init_completion(&aq->cmd_completion);
 612         aq->pdev = pdev;
 613
 614         /* Map the registers */
 615         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 616         aq->regs = devm_ioremap_resource(&pdev->dev, res);
 617         if (IS_ERR(aq->regs)) {
 618                 dev_err(&pdev->dev, "missing registers\n");
 619                 err = PTR_ERR(aq->regs);
 620                 goto exit;
 621         }
 622
 623         /* Map the AHB memory */
 624         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
 625         aq->mem = devm_ioremap_resource(&pdev->dev, res);
 626         if (IS_ERR(aq->mem)) {
 627                 dev_err(&pdev->dev, "missing AHB memory\n");
 628                 err = PTR_ERR(aq->mem);
 629                 goto exit;
 630         }
 631
 632         /* Get the peripheral clock */
 633         aq->clk = devm_clk_get(&pdev->dev, NULL);
 634         if (IS_ERR(aq->clk)) {
 635                 dev_err(&pdev->dev, "missing peripheral clock\n");
 636                 err = PTR_ERR(aq->clk);
 637                 goto exit;
 638         }
 639
 640         /* Enable the peripheral clock */
 641         err = clk_prepare_enable(aq->clk);
 642         if (err) {
 643                 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
 644                 goto exit;
 645         }
 646
 647         /* Request the IRQ */
 648         irq = platform_get_irq(pdev, 0);
 649         if (irq < 0) {
 650                 dev_err(&pdev->dev, "missing IRQ\n");
 651                 err = irq;
 652                 goto disable_clk;
 653         }
 654         err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
 655                                0, dev_name(&pdev->dev), aq);
 656         if (err)
 657                 goto disable_clk;
 658
 659         /* Setup the spi-nor */
 660         nor = &aq->nor;
 661         mtd = &nor->mtd;
 662
 663         nor->dev = &pdev->dev;
 664         spi_nor_set_flash_node(nor, child);
 665         nor->priv = aq;
 666         mtd->priv = nor;
 667
 668         nor->read_reg = atmel_qspi_read_reg;
 669         nor->write_reg = atmel_qspi_write_reg;
 670         nor->read = atmel_qspi_read;
 671         nor->write = atmel_qspi_write;
 672         nor->erase = atmel_qspi_erase;
 673
 674         err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
 675         if (err < 0)
 676                 goto disable_clk;
 677
 678         err = atmel_qspi_init(aq);
 679         if (err)
 680                 goto disable_clk;
 681
 682         err = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
 683         if (err)
 684                 goto disable_clk;
 685
 686         err = mtd_device_register(mtd, NULL, 0);
 687         if (err)
 688                 goto disable_clk;
 689
 690         of_node_put(child);
 691
 692         return 0;
 693
 694 disable_clk:
 695         clk_disable_unprepare(aq->clk);
 696 exit:
 697         of_node_put(child);
 698
 699         return err;
 700 }
 701
 702 static int atmel_qspi_remove(struct platform_device *pdev)
 703 {
 704         struct atmel_qspi *aq = platform_get_drvdata(pdev);
 705
 706         mtd_device_unregister(&aq->nor.mtd);
 707         qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
 708         clk_disable_unprepare(aq->clk);
 709         return 0;
 710 }
 711
 712
 713 static const struct of_device_id atmel_qspi_dt_ids[] = {
 714         { .compatible = "atmel,sama5d2-qspi" },
 715         { /* sentinel */ }
 716 };
 717
 718 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
 719
 720 static struct platform_driver atmel_qspi_driver = {
 721         .driver = {
 722                 .name   = "atmel_qspi",
 723                 .of_match_table = atmel_qspi_dt_ids,
 724         },
 725         .probe          = atmel_qspi_probe,
 726         .remove         = atmel_qspi_remove,
 727 };
 728 module_platform_driver(atmel_qspi_driver);
 729
 730 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
 731 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
 732 MODULE_LICENSE("GPL v2");