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mtd: fsl-quadspi: fix printk() format warning for size_t
[deliverable/linux.git] / drivers / mtd / spi-nor / fsl-quadspi.c
1 /*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
31
32 /* Controller needs driver to swap endian */
33 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
34 /* Controller needs 4x internal clock */
35 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
36 /*
37 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
38 * trigger data transfer even though extern data will not transferred.
39 */
40 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
41 /* Controller cannot wake up from wait mode, TKT245618 */
42 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
43
44 /* The registers */
45 #define QUADSPI_MCR 0x00
46 #define QUADSPI_MCR_RESERVED_SHIFT 16
47 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
48 #define QUADSPI_MCR_MDIS_SHIFT 14
49 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
50 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
51 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
52 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
53 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
54 #define QUADSPI_MCR_DDR_EN_SHIFT 7
55 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
56 #define QUADSPI_MCR_END_CFG_SHIFT 2
57 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
58 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
59 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
60 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
61 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
62
63 #define QUADSPI_IPCR 0x08
64 #define QUADSPI_IPCR_SEQID_SHIFT 24
65 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
66
67 #define QUADSPI_BUF0CR 0x10
68 #define QUADSPI_BUF1CR 0x14
69 #define QUADSPI_BUF2CR 0x18
70 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
71
72 #define QUADSPI_BUF3CR 0x1c
73 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
74 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
75 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
76 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
77
78 #define QUADSPI_BFGENCR 0x20
79 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
80 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
81 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
82 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
83
84 #define QUADSPI_BUF0IND 0x30
85 #define QUADSPI_BUF1IND 0x34
86 #define QUADSPI_BUF2IND 0x38
87 #define QUADSPI_SFAR 0x100
88
89 #define QUADSPI_SMPR 0x108
90 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
91 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
92 #define QUADSPI_SMPR_FSDLY_SHIFT 6
93 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
94 #define QUADSPI_SMPR_FSPHS_SHIFT 5
95 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
96 #define QUADSPI_SMPR_HSENA_SHIFT 0
97 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
98
99 #define QUADSPI_RBSR 0x10c
100 #define QUADSPI_RBSR_RDBFL_SHIFT 8
101 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
102
103 #define QUADSPI_RBCT 0x110
104 #define QUADSPI_RBCT_WMRK_MASK 0x1F
105 #define QUADSPI_RBCT_RXBRD_SHIFT 8
106 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
107
108 #define QUADSPI_TBSR 0x150
109 #define QUADSPI_TBDR 0x154
110 #define QUADSPI_SR 0x15c
111 #define QUADSPI_SR_IP_ACC_SHIFT 1
112 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
113 #define QUADSPI_SR_AHB_ACC_SHIFT 2
114 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
115
116 #define QUADSPI_FR 0x160
117 #define QUADSPI_FR_TFF_MASK 0x1
118
119 #define QUADSPI_SFA1AD 0x180
120 #define QUADSPI_SFA2AD 0x184
121 #define QUADSPI_SFB1AD 0x188
122 #define QUADSPI_SFB2AD 0x18c
123 #define QUADSPI_RBDR 0x200
124
125 #define QUADSPI_LUTKEY 0x300
126 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
127
128 #define QUADSPI_LCKCR 0x304
129 #define QUADSPI_LCKER_LOCK 0x1
130 #define QUADSPI_LCKER_UNLOCK 0x2
131
132 #define QUADSPI_RSER 0x164
133 #define QUADSPI_RSER_TFIE (0x1 << 0)
134
135 #define QUADSPI_LUT_BASE 0x310
136
137 /*
138 * The definition of the LUT register shows below:
139 *
140 * ---------------------------------------------------
141 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
142 * ---------------------------------------------------
143 */
144 #define OPRND0_SHIFT 0
145 #define PAD0_SHIFT 8
146 #define INSTR0_SHIFT 10
147 #define OPRND1_SHIFT 16
148
149 /* Instruction set for the LUT register. */
150 #define LUT_STOP 0
151 #define LUT_CMD 1
152 #define LUT_ADDR 2
153 #define LUT_DUMMY 3
154 #define LUT_MODE 4
155 #define LUT_MODE2 5
156 #define LUT_MODE4 6
157 #define LUT_READ 7
158 #define LUT_WRITE 8
159 #define LUT_JMP_ON_CS 9
160 #define LUT_ADDR_DDR 10
161 #define LUT_MODE_DDR 11
162 #define LUT_MODE2_DDR 12
163 #define LUT_MODE4_DDR 13
164 #define LUT_READ_DDR 14
165 #define LUT_WRITE_DDR 15
166 #define LUT_DATA_LEARN 16
167
168 /*
169 * The PAD definitions for LUT register.
170 *
171 * The pad stands for the lines number of IO[0:3].
172 * For example, the Quad read need four IO lines, so you should
173 * set LUT_PAD4 which means we use four IO lines.
174 */
175 #define LUT_PAD1 0
176 #define LUT_PAD2 1
177 #define LUT_PAD4 2
178
179 /* Oprands for the LUT register. */
180 #define ADDR24BIT 0x18
181 #define ADDR32BIT 0x20
182
183 /* Macros for constructing the LUT register. */
184 #define LUT0(ins, pad, opr) \
185 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
186 ((LUT_##ins) << INSTR0_SHIFT))
187
188 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
189
190 /* other macros for LUT register. */
191 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
192 #define QUADSPI_LUT_NUM 64
193
194 /* SEQID -- we can have 16 seqids at most. */
195 #define SEQID_QUAD_READ 0
196 #define SEQID_WREN 1
197 #define SEQID_WRDI 2
198 #define SEQID_RDSR 3
199 #define SEQID_SE 4
200 #define SEQID_CHIP_ERASE 5
201 #define SEQID_PP 6
202 #define SEQID_RDID 7
203 #define SEQID_WRSR 8
204 #define SEQID_RDCR 9
205 #define SEQID_EN4B 10
206 #define SEQID_BRWR 11
207
208 #define QUADSPI_MIN_IOMAP SZ_4M
209
210 enum fsl_qspi_devtype {
211 FSL_QUADSPI_VYBRID,
212 FSL_QUADSPI_IMX6SX,
213 FSL_QUADSPI_IMX7D,
214 FSL_QUADSPI_IMX6UL,
215 };
216
217 struct fsl_qspi_devtype_data {
218 enum fsl_qspi_devtype devtype;
219 int rxfifo;
220 int txfifo;
221 int ahb_buf_size;
222 int driver_data;
223 };
224
225 static struct fsl_qspi_devtype_data vybrid_data = {
226 .devtype = FSL_QUADSPI_VYBRID,
227 .rxfifo = 128,
228 .txfifo = 64,
229 .ahb_buf_size = 1024,
230 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
231 };
232
233 static struct fsl_qspi_devtype_data imx6sx_data = {
234 .devtype = FSL_QUADSPI_IMX6SX,
235 .rxfifo = 128,
236 .txfifo = 512,
237 .ahb_buf_size = 1024,
238 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
239 | QUADSPI_QUIRK_TKT245618,
240 };
241
242 static struct fsl_qspi_devtype_data imx7d_data = {
243 .devtype = FSL_QUADSPI_IMX7D,
244 .rxfifo = 512,
245 .txfifo = 512,
246 .ahb_buf_size = 1024,
247 .driver_data = QUADSPI_QUIRK_TKT253890
248 | QUADSPI_QUIRK_4X_INT_CLK,
249 };
250
251 static struct fsl_qspi_devtype_data imx6ul_data = {
252 .devtype = FSL_QUADSPI_IMX6UL,
253 .rxfifo = 128,
254 .txfifo = 512,
255 .ahb_buf_size = 1024,
256 .driver_data = QUADSPI_QUIRK_TKT253890
257 | QUADSPI_QUIRK_4X_INT_CLK,
258 };
259
260 #define FSL_QSPI_MAX_CHIP 4
261 struct fsl_qspi {
262 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
263 void __iomem *iobase;
264 void __iomem *ahb_addr;
265 u32 memmap_phy;
266 u32 memmap_offs;
267 u32 memmap_len;
268 struct clk *clk, *clk_en;
269 struct device *dev;
270 struct completion c;
271 struct fsl_qspi_devtype_data *devtype_data;
272 u32 nor_size;
273 u32 nor_num;
274 u32 clk_rate;
275 unsigned int chip_base_addr; /* We may support two chips. */
276 bool has_second_chip;
277 struct mutex lock;
278 struct pm_qos_request pm_qos_req;
279 };
280
281 static inline int needs_swap_endian(struct fsl_qspi *q)
282 {
283 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
284 }
285
286 static inline int needs_4x_clock(struct fsl_qspi *q)
287 {
288 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
289 }
290
291 static inline int needs_fill_txfifo(struct fsl_qspi *q)
292 {
293 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
294 }
295
296 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
297 {
298 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
299 }
300
301 /*
302 * An IC bug makes us to re-arrange the 32-bit data.
303 * The following chips, such as IMX6SLX, have fixed this bug.
304 */
305 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
306 {
307 return needs_swap_endian(q) ? __swab32(a) : a;
308 }
309
310 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
311 {
312 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
313 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
314 }
315
316 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
317 {
318 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
319 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
320 }
321
322 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
323 {
324 struct fsl_qspi *q = dev_id;
325 u32 reg;
326
327 /* clear interrupt */
328 reg = readl(q->iobase + QUADSPI_FR);
329 writel(reg, q->iobase + QUADSPI_FR);
330
331 if (reg & QUADSPI_FR_TFF_MASK)
332 complete(&q->c);
333
334 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
335 return IRQ_HANDLED;
336 }
337
338 static void fsl_qspi_init_lut(struct fsl_qspi *q)
339 {
340 void __iomem *base = q->iobase;
341 int rxfifo = q->devtype_data->rxfifo;
342 u32 lut_base;
343 u8 cmd, addrlen, dummy;
344 int i;
345
346 fsl_qspi_unlock_lut(q);
347
348 /* Clear all the LUT table */
349 for (i = 0; i < QUADSPI_LUT_NUM; i++)
350 writel(0, base + QUADSPI_LUT_BASE + i * 4);
351
352 /* Quad Read */
353 lut_base = SEQID_QUAD_READ * 4;
354
355 if (q->nor_size <= SZ_16M) {
356 cmd = SPINOR_OP_READ_1_1_4;
357 addrlen = ADDR24BIT;
358 dummy = 8;
359 } else {
360 /* use the 4-byte address */
361 cmd = SPINOR_OP_READ_1_1_4;
362 addrlen = ADDR32BIT;
363 dummy = 8;
364 }
365
366 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
367 base + QUADSPI_LUT(lut_base));
368 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
369 base + QUADSPI_LUT(lut_base + 1));
370
371 /* Write enable */
372 lut_base = SEQID_WREN * 4;
373 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
374
375 /* Page Program */
376 lut_base = SEQID_PP * 4;
377
378 if (q->nor_size <= SZ_16M) {
379 cmd = SPINOR_OP_PP;
380 addrlen = ADDR24BIT;
381 } else {
382 /* use the 4-byte address */
383 cmd = SPINOR_OP_PP;
384 addrlen = ADDR32BIT;
385 }
386
387 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
388 base + QUADSPI_LUT(lut_base));
389 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
390
391 /* Read Status */
392 lut_base = SEQID_RDSR * 4;
393 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
394 base + QUADSPI_LUT(lut_base));
395
396 /* Erase a sector */
397 lut_base = SEQID_SE * 4;
398
399 cmd = q->nor[0].erase_opcode;
400 addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
401
402 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
403 base + QUADSPI_LUT(lut_base));
404
405 /* Erase the whole chip */
406 lut_base = SEQID_CHIP_ERASE * 4;
407 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
408 base + QUADSPI_LUT(lut_base));
409
410 /* READ ID */
411 lut_base = SEQID_RDID * 4;
412 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
413 base + QUADSPI_LUT(lut_base));
414
415 /* Write Register */
416 lut_base = SEQID_WRSR * 4;
417 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
418 base + QUADSPI_LUT(lut_base));
419
420 /* Read Configuration Register */
421 lut_base = SEQID_RDCR * 4;
422 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
423 base + QUADSPI_LUT(lut_base));
424
425 /* Write disable */
426 lut_base = SEQID_WRDI * 4;
427 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
428
429 /* Enter 4 Byte Mode (Micron) */
430 lut_base = SEQID_EN4B * 4;
431 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
432
433 /* Enter 4 Byte Mode (Spansion) */
434 lut_base = SEQID_BRWR * 4;
435 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
436
437 fsl_qspi_lock_lut(q);
438 }
439
440 /* Get the SEQID for the command */
441 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
442 {
443 switch (cmd) {
444 case SPINOR_OP_READ_1_1_4:
445 return SEQID_QUAD_READ;
446 case SPINOR_OP_WREN:
447 return SEQID_WREN;
448 case SPINOR_OP_WRDI:
449 return SEQID_WRDI;
450 case SPINOR_OP_RDSR:
451 return SEQID_RDSR;
452 case SPINOR_OP_SE:
453 return SEQID_SE;
454 case SPINOR_OP_CHIP_ERASE:
455 return SEQID_CHIP_ERASE;
456 case SPINOR_OP_PP:
457 return SEQID_PP;
458 case SPINOR_OP_RDID:
459 return SEQID_RDID;
460 case SPINOR_OP_WRSR:
461 return SEQID_WRSR;
462 case SPINOR_OP_RDCR:
463 return SEQID_RDCR;
464 case SPINOR_OP_EN4B:
465 return SEQID_EN4B;
466 case SPINOR_OP_BRWR:
467 return SEQID_BRWR;
468 default:
469 if (cmd == q->nor[0].erase_opcode)
470 return SEQID_SE;
471 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
472 break;
473 }
474 return -EINVAL;
475 }
476
477 static int
478 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
479 {
480 void __iomem *base = q->iobase;
481 int seqid;
482 u32 reg, reg2;
483 int err;
484
485 init_completion(&q->c);
486 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
487 q->chip_base_addr, addr, len, cmd);
488
489 /* save the reg */
490 reg = readl(base + QUADSPI_MCR);
491
492 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
493 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
494 base + QUADSPI_RBCT);
495 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
496
497 do {
498 reg2 = readl(base + QUADSPI_SR);
499 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
500 udelay(1);
501 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
502 continue;
503 }
504 break;
505 } while (1);
506
507 /* trigger the LUT now */
508 seqid = fsl_qspi_get_seqid(q, cmd);
509 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
510
511 /* Wait for the interrupt. */
512 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
513 dev_err(q->dev,
514 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
515 cmd, addr, readl(base + QUADSPI_FR),
516 readl(base + QUADSPI_SR));
517 err = -ETIMEDOUT;
518 } else {
519 err = 0;
520 }
521
522 /* restore the MCR */
523 writel(reg, base + QUADSPI_MCR);
524
525 return err;
526 }
527
528 /* Read out the data from the QUADSPI_RBDR buffer registers. */
529 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
530 {
531 u32 tmp;
532 int i = 0;
533
534 while (len > 0) {
535 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
536 tmp = fsl_qspi_endian_xchg(q, tmp);
537 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
538 q->chip_base_addr, tmp);
539
540 if (len >= 4) {
541 *((u32 *)rxbuf) = tmp;
542 rxbuf += 4;
543 } else {
544 memcpy(rxbuf, &tmp, len);
545 break;
546 }
547
548 len -= 4;
549 i++;
550 }
551 }
552
553 /*
554 * If we have changed the content of the flash by writing or erasing,
555 * we need to invalidate the AHB buffer. If we do not do so, we may read out
556 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
557 * domain at the same time.
558 */
559 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
560 {
561 u32 reg;
562
563 reg = readl(q->iobase + QUADSPI_MCR);
564 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
565 writel(reg, q->iobase + QUADSPI_MCR);
566
567 /*
568 * The minimum delay : 1 AHB + 2 SFCK clocks.
569 * Delay 1 us is enough.
570 */
571 udelay(1);
572
573 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
574 writel(reg, q->iobase + QUADSPI_MCR);
575 }
576
577 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
578 u8 opcode, unsigned int to, u32 *txbuf,
579 unsigned count, size_t *retlen)
580 {
581 int ret, i, j;
582 u32 tmp;
583
584 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
585 q->chip_base_addr, to, count);
586
587 /* clear the TX FIFO. */
588 tmp = readl(q->iobase + QUADSPI_MCR);
589 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
590
591 /* fill the TX data to the FIFO */
592 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
593 tmp = fsl_qspi_endian_xchg(q, *txbuf);
594 writel(tmp, q->iobase + QUADSPI_TBDR);
595 txbuf++;
596 }
597
598 /* fill the TXFIFO upto 16 bytes for i.MX7d */
599 if (needs_fill_txfifo(q))
600 for (; i < 4; i++)
601 writel(tmp, q->iobase + QUADSPI_TBDR);
602
603 /* Trigger it */
604 ret = fsl_qspi_runcmd(q, opcode, to, count);
605
606 if (ret == 0 && retlen)
607 *retlen += count;
608
609 return ret;
610 }
611
612 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
613 {
614 int nor_size = q->nor_size;
615 void __iomem *base = q->iobase;
616
617 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
618 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
619 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
620 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
621 }
622
623 /*
624 * There are two different ways to read out the data from the flash:
625 * the "IP Command Read" and the "AHB Command Read".
626 *
627 * The IC guy suggests we use the "AHB Command Read" which is faster
628 * then the "IP Command Read". (What's more is that there is a bug in
629 * the "IP Command Read" in the Vybrid.)
630 *
631 * After we set up the registers for the "AHB Command Read", we can use
632 * the memcpy to read the data directly. A "missed" access to the buffer
633 * causes the controller to clear the buffer, and use the sequence pointed
634 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
635 */
636 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
637 {
638 void __iomem *base = q->iobase;
639 int seqid;
640
641 /* AHB configuration for access buffer 0/1/2 .*/
642 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
643 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
644 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
645 /*
646 * Set ADATSZ with the maximum AHB buffer size to improve the
647 * read performance.
648 */
649 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
650 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
651
652 /* We only use the buffer3 */
653 writel(0, base + QUADSPI_BUF0IND);
654 writel(0, base + QUADSPI_BUF1IND);
655 writel(0, base + QUADSPI_BUF2IND);
656
657 /* Set the default lut sequence for AHB Read. */
658 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
659 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
660 q->iobase + QUADSPI_BFGENCR);
661 }
662
663 /* This function was used to prepare and enable QSPI clock */
664 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
665 {
666 int ret;
667
668 ret = clk_prepare_enable(q->clk_en);
669 if (ret)
670 return ret;
671
672 ret = clk_prepare_enable(q->clk);
673 if (ret) {
674 clk_disable_unprepare(q->clk_en);
675 return ret;
676 }
677
678 if (needs_wakeup_wait_mode(q))
679 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
680
681 return 0;
682 }
683
684 /* This function was used to disable and unprepare QSPI clock */
685 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
686 {
687 if (needs_wakeup_wait_mode(q))
688 pm_qos_remove_request(&q->pm_qos_req);
689
690 clk_disable_unprepare(q->clk);
691 clk_disable_unprepare(q->clk_en);
692
693 }
694
695 /* We use this function to do some basic init for spi_nor_scan(). */
696 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
697 {
698 void __iomem *base = q->iobase;
699 u32 reg;
700 int ret;
701
702 /* disable and unprepare clock to avoid glitch pass to controller */
703 fsl_qspi_clk_disable_unprep(q);
704
705 /* the default frequency, we will change it in the future. */
706 ret = clk_set_rate(q->clk, 66000000);
707 if (ret)
708 return ret;
709
710 ret = fsl_qspi_clk_prep_enable(q);
711 if (ret)
712 return ret;
713
714 /* Reset the module */
715 writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
716 base + QUADSPI_MCR);
717 udelay(1);
718
719 /* Init the LUT table. */
720 fsl_qspi_init_lut(q);
721
722 /* Disable the module */
723 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
724 base + QUADSPI_MCR);
725
726 reg = readl(base + QUADSPI_SMPR);
727 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
728 | QUADSPI_SMPR_FSPHS_MASK
729 | QUADSPI_SMPR_HSENA_MASK
730 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
731
732 /* Enable the module */
733 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
734 base + QUADSPI_MCR);
735
736 /* clear all interrupt status */
737 writel(0xffffffff, q->iobase + QUADSPI_FR);
738
739 /* enable the interrupt */
740 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
741
742 return 0;
743 }
744
745 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
746 {
747 unsigned long rate = q->clk_rate;
748 int ret;
749
750 if (needs_4x_clock(q))
751 rate *= 4;
752
753 /* disable and unprepare clock to avoid glitch pass to controller */
754 fsl_qspi_clk_disable_unprep(q);
755
756 ret = clk_set_rate(q->clk, rate);
757 if (ret)
758 return ret;
759
760 ret = fsl_qspi_clk_prep_enable(q);
761 if (ret)
762 return ret;
763
764 /* Init the LUT table again. */
765 fsl_qspi_init_lut(q);
766
767 /* Init for AHB read */
768 fsl_qspi_init_abh_read(q);
769
770 return 0;
771 }
772
773 static const struct of_device_id fsl_qspi_dt_ids[] = {
774 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
775 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
776 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
777 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
778 { /* sentinel */ }
779 };
780 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
781
782 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
783 {
784 q->chip_base_addr = q->nor_size * (nor - q->nor);
785 }
786
787 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
788 {
789 int ret;
790 struct fsl_qspi *q = nor->priv;
791
792 ret = fsl_qspi_runcmd(q, opcode, 0, len);
793 if (ret)
794 return ret;
795
796 fsl_qspi_read_data(q, len, buf);
797 return 0;
798 }
799
800 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
801 {
802 struct fsl_qspi *q = nor->priv;
803 int ret;
804
805 if (!buf) {
806 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
807 if (ret)
808 return ret;
809
810 if (opcode == SPINOR_OP_CHIP_ERASE)
811 fsl_qspi_invalid(q);
812
813 } else if (len > 0) {
814 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
815 (u32 *)buf, len, NULL);
816 } else {
817 dev_err(q->dev, "invalid cmd %d\n", opcode);
818 ret = -EINVAL;
819 }
820
821 return ret;
822 }
823
824 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
825 size_t len, size_t *retlen, const u_char *buf)
826 {
827 struct fsl_qspi *q = nor->priv;
828
829 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
830 (u32 *)buf, len, retlen);
831
832 /* invalid the data in the AHB buffer. */
833 fsl_qspi_invalid(q);
834 }
835
836 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
837 size_t len, size_t *retlen, u_char *buf)
838 {
839 struct fsl_qspi *q = nor->priv;
840 u8 cmd = nor->read_opcode;
841
842 /* if necessary,ioremap buffer before AHB read, */
843 if (!q->ahb_addr) {
844 q->memmap_offs = q->chip_base_addr + from;
845 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
846
847 q->ahb_addr = ioremap_nocache(
848 q->memmap_phy + q->memmap_offs,
849 q->memmap_len);
850 if (!q->ahb_addr) {
851 dev_err(q->dev, "ioremap failed\n");
852 return -ENOMEM;
853 }
854 /* ioremap if the data requested is out of range */
855 } else if (q->chip_base_addr + from < q->memmap_offs
856 || q->chip_base_addr + from + len >
857 q->memmap_offs + q->memmap_len) {
858 iounmap(q->ahb_addr);
859
860 q->memmap_offs = q->chip_base_addr + from;
861 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
862 q->ahb_addr = ioremap_nocache(
863 q->memmap_phy + q->memmap_offs,
864 q->memmap_len);
865 if (!q->ahb_addr) {
866 dev_err(q->dev, "ioremap failed\n");
867 return -ENOMEM;
868 }
869 }
870
871 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
872 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
873 len);
874
875 /* Read out the data directly from the AHB buffer.*/
876 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
877 len);
878
879 *retlen += len;
880 return 0;
881 }
882
883 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
884 {
885 struct fsl_qspi *q = nor->priv;
886 int ret;
887
888 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
889 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
890
891 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
892 if (ret)
893 return ret;
894
895 fsl_qspi_invalid(q);
896 return 0;
897 }
898
899 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
900 {
901 struct fsl_qspi *q = nor->priv;
902 int ret;
903
904 mutex_lock(&q->lock);
905
906 ret = fsl_qspi_clk_prep_enable(q);
907 if (ret)
908 goto err_mutex;
909
910 fsl_qspi_set_base_addr(q, nor);
911 return 0;
912
913 err_mutex:
914 mutex_unlock(&q->lock);
915 return ret;
916 }
917
918 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
919 {
920 struct fsl_qspi *q = nor->priv;
921
922 fsl_qspi_clk_disable_unprep(q);
923 mutex_unlock(&q->lock);
924 }
925
926 static int fsl_qspi_probe(struct platform_device *pdev)
927 {
928 struct device_node *np = pdev->dev.of_node;
929 struct mtd_part_parser_data ppdata;
930 struct device *dev = &pdev->dev;
931 struct fsl_qspi *q;
932 struct resource *res;
933 struct spi_nor *nor;
934 struct mtd_info *mtd;
935 int ret, i = 0;
936 const struct of_device_id *of_id =
937 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
938
939 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
940 if (!q)
941 return -ENOMEM;
942
943 q->nor_num = of_get_child_count(dev->of_node);
944 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
945 return -ENODEV;
946
947 q->dev = dev;
948 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
949 platform_set_drvdata(pdev, q);
950
951 /* find the resources */
952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
953 q->iobase = devm_ioremap_resource(dev, res);
954 if (IS_ERR(q->iobase))
955 return PTR_ERR(q->iobase);
956
957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
958 "QuadSPI-memory");
959 if (!devm_request_mem_region(dev, res->start, resource_size(res),
960 res->name)) {
961 dev_err(dev, "can't request region for resource %pR\n", res);
962 return -EBUSY;
963 }
964
965 q->memmap_phy = res->start;
966
967 /* find the clocks */
968 q->clk_en = devm_clk_get(dev, "qspi_en");
969 if (IS_ERR(q->clk_en))
970 return PTR_ERR(q->clk_en);
971
972 q->clk = devm_clk_get(dev, "qspi");
973 if (IS_ERR(q->clk))
974 return PTR_ERR(q->clk);
975
976 ret = fsl_qspi_clk_prep_enable(q);
977 if (ret) {
978 dev_err(dev, "can not enable the clock\n");
979 goto clk_failed;
980 }
981
982 /* find the irq */
983 ret = platform_get_irq(pdev, 0);
984 if (ret < 0) {
985 dev_err(dev, "failed to get the irq: %d\n", ret);
986 goto irq_failed;
987 }
988
989 ret = devm_request_irq(dev, ret,
990 fsl_qspi_irq_handler, 0, pdev->name, q);
991 if (ret) {
992 dev_err(dev, "failed to request irq: %d\n", ret);
993 goto irq_failed;
994 }
995
996 ret = fsl_qspi_nor_setup(q);
997 if (ret)
998 goto irq_failed;
999
1000 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1001 q->has_second_chip = true;
1002
1003 mutex_init(&q->lock);
1004
1005 /* iterate the subnodes. */
1006 for_each_available_child_of_node(dev->of_node, np) {
1007 /* skip the holes */
1008 if (!q->has_second_chip)
1009 i *= 2;
1010
1011 nor = &q->nor[i];
1012 mtd = &nor->mtd;
1013
1014 nor->dev = dev;
1015 nor->flash_node = np;
1016 nor->priv = q;
1017
1018 /* fill the hooks */
1019 nor->read_reg = fsl_qspi_read_reg;
1020 nor->write_reg = fsl_qspi_write_reg;
1021 nor->read = fsl_qspi_read;
1022 nor->write = fsl_qspi_write;
1023 nor->erase = fsl_qspi_erase;
1024
1025 nor->prepare = fsl_qspi_prep;
1026 nor->unprepare = fsl_qspi_unprep;
1027
1028 ret = of_property_read_u32(np, "spi-max-frequency",
1029 &q->clk_rate);
1030 if (ret < 0)
1031 goto mutex_failed;
1032
1033 /* set the chip address for READID */
1034 fsl_qspi_set_base_addr(q, nor);
1035
1036 ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
1037 if (ret)
1038 goto mutex_failed;
1039
1040 ppdata.of_node = np;
1041 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1042 if (ret)
1043 goto mutex_failed;
1044
1045 /* Set the correct NOR size now. */
1046 if (q->nor_size == 0) {
1047 q->nor_size = mtd->size;
1048
1049 /* Map the SPI NOR to accessiable address */
1050 fsl_qspi_set_map_addr(q);
1051 }
1052
1053 /*
1054 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1055 * may writes 265 bytes per time. The write is working in the
1056 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1057 * size.
1058 *
1059 * So shrink the spi_nor->page_size if it is larger then the
1060 * TX FIFO.
1061 */
1062 if (nor->page_size > q->devtype_data->txfifo)
1063 nor->page_size = q->devtype_data->txfifo;
1064
1065 i++;
1066 }
1067
1068 /* finish the rest init. */
1069 ret = fsl_qspi_nor_setup_last(q);
1070 if (ret)
1071 goto last_init_failed;
1072
1073 fsl_qspi_clk_disable_unprep(q);
1074 return 0;
1075
1076 last_init_failed:
1077 for (i = 0; i < q->nor_num; i++) {
1078 /* skip the holes */
1079 if (!q->has_second_chip)
1080 i *= 2;
1081 mtd_device_unregister(&q->nor[i].mtd);
1082 }
1083 mutex_failed:
1084 mutex_destroy(&q->lock);
1085 irq_failed:
1086 fsl_qspi_clk_disable_unprep(q);
1087 clk_failed:
1088 dev_err(dev, "Freescale QuadSPI probe failed\n");
1089 return ret;
1090 }
1091
1092 static int fsl_qspi_remove(struct platform_device *pdev)
1093 {
1094 struct fsl_qspi *q = platform_get_drvdata(pdev);
1095 int i;
1096
1097 for (i = 0; i < q->nor_num; i++) {
1098 /* skip the holes */
1099 if (!q->has_second_chip)
1100 i *= 2;
1101 mtd_device_unregister(&q->nor[i].mtd);
1102 }
1103
1104 /* disable the hardware */
1105 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1106 writel(0x0, q->iobase + QUADSPI_RSER);
1107
1108 mutex_destroy(&q->lock);
1109
1110 if (q->ahb_addr)
1111 iounmap(q->ahb_addr);
1112
1113 return 0;
1114 }
1115
1116 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1117 {
1118 return 0;
1119 }
1120
1121 static int fsl_qspi_resume(struct platform_device *pdev)
1122 {
1123 int ret;
1124 struct fsl_qspi *q = platform_get_drvdata(pdev);
1125
1126 ret = fsl_qspi_clk_prep_enable(q);
1127 if (ret)
1128 return ret;
1129
1130 fsl_qspi_nor_setup(q);
1131 fsl_qspi_set_map_addr(q);
1132 fsl_qspi_nor_setup_last(q);
1133
1134 fsl_qspi_clk_disable_unprep(q);
1135
1136 return 0;
1137 }
1138
1139 static struct platform_driver fsl_qspi_driver = {
1140 .driver = {
1141 .name = "fsl-quadspi",
1142 .bus = &platform_bus_type,
1143 .of_match_table = fsl_qspi_dt_ids,
1144 },
1145 .probe = fsl_qspi_probe,
1146 .remove = fsl_qspi_remove,
1147 .suspend = fsl_qspi_suspend,
1148 .resume = fsl_qspi_resume,
1149 };
1150 module_platform_driver(fsl_qspi_driver);
1151
1152 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1153 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1154 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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