2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Bayi Cheng <bayi.cheng@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
20 #include <linux/iopoll.h>
21 #include <linux/ioport.h>
22 #include <linux/math64.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/mtd/spi-nor.h>
34 #define MTK_NOR_CMD_REG 0x00
35 #define MTK_NOR_CNT_REG 0x04
36 #define MTK_NOR_RDSR_REG 0x08
37 #define MTK_NOR_RDATA_REG 0x0c
38 #define MTK_NOR_RADR0_REG 0x10
39 #define MTK_NOR_RADR1_REG 0x14
40 #define MTK_NOR_RADR2_REG 0x18
41 #define MTK_NOR_WDATA_REG 0x1c
42 #define MTK_NOR_PRGDATA0_REG 0x20
43 #define MTK_NOR_PRGDATA1_REG 0x24
44 #define MTK_NOR_PRGDATA2_REG 0x28
45 #define MTK_NOR_PRGDATA3_REG 0x2c
46 #define MTK_NOR_PRGDATA4_REG 0x30
47 #define MTK_NOR_PRGDATA5_REG 0x34
48 #define MTK_NOR_SHREG0_REG 0x38
49 #define MTK_NOR_SHREG1_REG 0x3c
50 #define MTK_NOR_SHREG2_REG 0x40
51 #define MTK_NOR_SHREG3_REG 0x44
52 #define MTK_NOR_SHREG4_REG 0x48
53 #define MTK_NOR_SHREG5_REG 0x4c
54 #define MTK_NOR_SHREG6_REG 0x50
55 #define MTK_NOR_SHREG7_REG 0x54
56 #define MTK_NOR_SHREG8_REG 0x58
57 #define MTK_NOR_SHREG9_REG 0x5c
58 #define MTK_NOR_CFG1_REG 0x60
59 #define MTK_NOR_CFG2_REG 0x64
60 #define MTK_NOR_CFG3_REG 0x68
61 #define MTK_NOR_STATUS0_REG 0x70
62 #define MTK_NOR_STATUS1_REG 0x74
63 #define MTK_NOR_STATUS2_REG 0x78
64 #define MTK_NOR_STATUS3_REG 0x7c
65 #define MTK_NOR_FLHCFG_REG 0x84
66 #define MTK_NOR_TIME_REG 0x94
67 #define MTK_NOR_PP_DATA_REG 0x98
68 #define MTK_NOR_PREBUF_STUS_REG 0x9c
69 #define MTK_NOR_DELSEL0_REG 0xa0
70 #define MTK_NOR_DELSEL1_REG 0xa4
71 #define MTK_NOR_INTRSTUS_REG 0xa8
72 #define MTK_NOR_INTREN_REG 0xac
73 #define MTK_NOR_CHKSUM_CTL_REG 0xb8
74 #define MTK_NOR_CHKSUM_REG 0xbc
75 #define MTK_NOR_CMD2_REG 0xc0
76 #define MTK_NOR_WRPROT_REG 0xc4
77 #define MTK_NOR_RADR3_REG 0xc8
78 #define MTK_NOR_DUAL_REG 0xcc
79 #define MTK_NOR_DELSEL2_REG 0xd0
80 #define MTK_NOR_DELSEL3_REG 0xd4
81 #define MTK_NOR_DELSEL4_REG 0xd8
83 /* commands for mtk nor controller */
84 #define MTK_NOR_READ_CMD 0x0
85 #define MTK_NOR_RDSR_CMD 0x2
86 #define MTK_NOR_PRG_CMD 0x4
87 #define MTK_NOR_WR_CMD 0x10
88 #define MTK_NOR_PIO_WR_CMD 0x90
89 #define MTK_NOR_WRSR_CMD 0x20
90 #define MTK_NOR_PIO_READ_CMD 0x81
91 #define MTK_NOR_WR_BUF_ENABLE 0x1
92 #define MTK_NOR_WR_BUF_DISABLE 0x0
93 #define MTK_NOR_ENABLE_SF_CMD 0x30
94 #define MTK_NOR_DUAD_ADDR_EN 0x8
95 #define MTK_NOR_QUAD_READ_EN 0x4
96 #define MTK_NOR_DUAL_ADDR_EN 0x2
97 #define MTK_NOR_DUAL_READ_EN 0x1
98 #define MTK_NOR_DUAL_DISABLE 0x0
99 #define MTK_NOR_FAST_READ 0x1
101 #define SFLASH_WRBUF_SIZE 128
103 /* Can shift up to 48 bits (6 bytes) of TX/RX */
104 #define MTK_NOR_MAX_RX_TX_SHIFT 6
105 /* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
106 #define MTK_NOR_MAX_SHIFT 7
108 /* Helpers for accessing the program data / shift data registers */
109 #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
110 #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
115 void __iomem
*base
; /* nor flash base address */
120 static void mt8173_nor_set_read_mode(struct mt8173_nor
*mt8173_nor
)
122 struct spi_nor
*nor
= &mt8173_nor
->nor
;
124 switch (nor
->flash_read
) {
126 writeb(nor
->read_opcode
, mt8173_nor
->base
+
127 MTK_NOR_PRGDATA3_REG
);
128 writeb(MTK_NOR_FAST_READ
, mt8173_nor
->base
+
132 writeb(nor
->read_opcode
, mt8173_nor
->base
+
133 MTK_NOR_PRGDATA3_REG
);
134 writeb(MTK_NOR_DUAL_READ_EN
, mt8173_nor
->base
+
138 writeb(nor
->read_opcode
, mt8173_nor
->base
+
139 MTK_NOR_PRGDATA4_REG
);
140 writeb(MTK_NOR_QUAD_READ_EN
, mt8173_nor
->base
+
144 writeb(MTK_NOR_DUAL_DISABLE
, mt8173_nor
->base
+
150 static int mt8173_nor_execute_cmd(struct mt8173_nor
*mt8173_nor
, u8 cmdval
)
153 u8 val
= cmdval
& 0x1f;
155 writeb(cmdval
, mt8173_nor
->base
+ MTK_NOR_CMD_REG
);
156 return readl_poll_timeout(mt8173_nor
->base
+ MTK_NOR_CMD_REG
, reg
,
157 !(reg
& val
), 100, 10000);
160 static int mt8173_nor_do_tx_rx(struct mt8173_nor
*mt8173_nor
, u8 op
,
161 u8
*tx
, int txlen
, u8
*rx
, int rxlen
)
163 int len
= 1 + txlen
+ rxlen
;
166 if (len
> MTK_NOR_MAX_SHIFT
)
169 writeb(len
* 8, mt8173_nor
->base
+ MTK_NOR_CNT_REG
);
171 /* start at PRGDATA5, go down to PRGDATA0 */
172 idx
= MTK_NOR_MAX_RX_TX_SHIFT
- 1;
175 writeb(op
, mt8173_nor
->base
+ MTK_NOR_PRG_REG(idx
));
178 /* program TX data */
179 for (i
= 0; i
< txlen
; i
++, idx
--)
180 writeb(tx
[i
], mt8173_nor
->base
+ MTK_NOR_PRG_REG(idx
));
182 /* clear out rest of TX registers */
184 writeb(0, mt8173_nor
->base
+ MTK_NOR_PRG_REG(idx
));
188 ret
= mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_PRG_CMD
);
192 /* restart at first RX byte */
195 /* read out RX data */
196 for (i
= 0; i
< rxlen
; i
++, idx
--)
197 rx
[i
] = readb(mt8173_nor
->base
+ MTK_NOR_SHREG(idx
));
202 /* Do a WRSR (Write Status Register) command */
203 static int mt8173_nor_wr_sr(struct mt8173_nor
*mt8173_nor
, u8 sr
)
205 writeb(sr
, mt8173_nor
->base
+ MTK_NOR_PRGDATA5_REG
);
206 writeb(8, mt8173_nor
->base
+ MTK_NOR_CNT_REG
);
207 return mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_WRSR_CMD
);
210 static int mt8173_nor_write_buffer_enable(struct mt8173_nor
*mt8173_nor
)
214 /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
215 * 0: pre-fetch buffer use for read
216 * 1: pre-fetch buffer use for page program
218 writel(MTK_NOR_WR_BUF_ENABLE
, mt8173_nor
->base
+ MTK_NOR_CFG2_REG
);
219 return readb_poll_timeout(mt8173_nor
->base
+ MTK_NOR_CFG2_REG
, reg
,
220 0x01 == (reg
& 0x01), 100, 10000);
223 static int mt8173_nor_write_buffer_disable(struct mt8173_nor
*mt8173_nor
)
227 writel(MTK_NOR_WR_BUF_DISABLE
, mt8173_nor
->base
+ MTK_NOR_CFG2_REG
);
228 return readb_poll_timeout(mt8173_nor
->base
+ MTK_NOR_CFG2_REG
, reg
,
229 MTK_NOR_WR_BUF_DISABLE
== (reg
& 0x1), 100,
233 static void mt8173_nor_set_addr(struct mt8173_nor
*mt8173_nor
, u32 addr
)
237 for (i
= 0; i
< 3; i
++) {
238 writeb(addr
& 0xff, mt8173_nor
->base
+ MTK_NOR_RADR0_REG
+ i
* 4);
241 /* Last register is non-contiguous */
242 writeb(addr
& 0xff, mt8173_nor
->base
+ MTK_NOR_RADR3_REG
);
245 static ssize_t
mt8173_nor_read(struct spi_nor
*nor
, loff_t from
, size_t length
,
249 int addr
= (int)from
;
250 u8
*buf
= (u8
*)buffer
;
251 struct mt8173_nor
*mt8173_nor
= nor
->priv
;
253 /* set mode for fast read mode ,dual mode or quad mode */
254 mt8173_nor_set_read_mode(mt8173_nor
);
255 mt8173_nor_set_addr(mt8173_nor
, addr
);
257 for (i
= 0; i
< length
; i
++) {
258 ret
= mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_PIO_READ_CMD
);
261 buf
[i
] = readb(mt8173_nor
->base
+ MTK_NOR_RDATA_REG
);
266 static int mt8173_nor_write_single_byte(struct mt8173_nor
*mt8173_nor
,
267 int addr
, int length
, u8
*data
)
271 mt8173_nor_set_addr(mt8173_nor
, addr
);
273 for (i
= 0; i
< length
; i
++) {
274 writeb(*data
++, mt8173_nor
->base
+ MTK_NOR_WDATA_REG
);
275 ret
= mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_PIO_WR_CMD
);
282 static int mt8173_nor_write_buffer(struct mt8173_nor
*mt8173_nor
, int addr
,
287 mt8173_nor_set_addr(mt8173_nor
, addr
);
290 for (i
= 0; i
< SFLASH_WRBUF_SIZE
; i
+= 4) {
291 data
= buf
[bufidx
+ 3]<<24 | buf
[bufidx
+ 2]<<16 |
292 buf
[bufidx
+ 1]<<8 | buf
[bufidx
];
294 writel(data
, mt8173_nor
->base
+ MTK_NOR_PP_DATA_REG
);
296 return mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_WR_CMD
);
299 static ssize_t
mt8173_nor_write(struct spi_nor
*nor
, loff_t to
, size_t len
,
303 struct mt8173_nor
*mt8173_nor
= nor
->priv
;
306 ret
= mt8173_nor_write_buffer_enable(mt8173_nor
);
308 dev_warn(mt8173_nor
->dev
, "write buffer enable failed!\n");
312 for (i
= 0; i
+ SFLASH_WRBUF_SIZE
<= len
; i
+= SFLASH_WRBUF_SIZE
) {
313 ret
= mt8173_nor_write_buffer(mt8173_nor
, to
, buf
);
315 dev_err(mt8173_nor
->dev
, "write buffer failed!\n");
318 to
+= SFLASH_WRBUF_SIZE
;
319 buf
+= SFLASH_WRBUF_SIZE
;
321 ret
= mt8173_nor_write_buffer_disable(mt8173_nor
);
323 dev_warn(mt8173_nor
->dev
, "write buffer disable failed!\n");
328 ret
= mt8173_nor_write_single_byte(mt8173_nor
, to
,
329 (int)(len
- i
), (u8
*)buf
);
331 dev_err(mt8173_nor
->dev
, "write single byte failed!\n");
339 static int mt8173_nor_read_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
)
342 struct mt8173_nor
*mt8173_nor
= nor
->priv
;
346 ret
= mt8173_nor_execute_cmd(mt8173_nor
, MTK_NOR_RDSR_CMD
);
350 *buf
= readb(mt8173_nor
->base
+ MTK_NOR_RDSR_REG
);
352 dev_err(mt8173_nor
->dev
, "len should be 1 for read status!\n");
355 ret
= mt8173_nor_do_tx_rx(mt8173_nor
, opcode
, NULL
, 0, buf
, len
);
361 static int mt8173_nor_write_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
,
365 struct mt8173_nor
*mt8173_nor
= nor
->priv
;
369 /* We only handle 1 byte */
370 ret
= mt8173_nor_wr_sr(mt8173_nor
, *buf
);
373 ret
= mt8173_nor_do_tx_rx(mt8173_nor
, opcode
, buf
, len
, NULL
, 0);
375 dev_warn(mt8173_nor
->dev
, "write reg failure!\n");
381 static int mtk_nor_init(struct mt8173_nor
*mt8173_nor
,
382 struct device_node
*flash_node
)
387 /* initialize controller to accept commands */
388 writel(MTK_NOR_ENABLE_SF_CMD
, mt8173_nor
->base
+ MTK_NOR_WRPROT_REG
);
390 nor
= &mt8173_nor
->nor
;
391 nor
->dev
= mt8173_nor
->dev
;
392 nor
->priv
= mt8173_nor
;
393 spi_nor_set_flash_node(nor
, flash_node
);
395 /* fill the hooks to spi nor */
396 nor
->read
= mt8173_nor_read
;
397 nor
->read_reg
= mt8173_nor_read_reg
;
398 nor
->write
= mt8173_nor_write
;
399 nor
->write_reg
= mt8173_nor_write_reg
;
400 nor
->mtd
.name
= "mtk_nor";
401 /* initialized with NULL */
402 ret
= spi_nor_scan(nor
, NULL
, SPI_NOR_DUAL
);
406 return mtd_device_register(&nor
->mtd
, NULL
, 0);
409 static int mtk_nor_drv_probe(struct platform_device
*pdev
)
411 struct device_node
*flash_np
;
412 struct resource
*res
;
414 struct mt8173_nor
*mt8173_nor
;
416 if (!pdev
->dev
.of_node
) {
417 dev_err(&pdev
->dev
, "No DT found\n");
421 mt8173_nor
= devm_kzalloc(&pdev
->dev
, sizeof(*mt8173_nor
), GFP_KERNEL
);
424 platform_set_drvdata(pdev
, mt8173_nor
);
426 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
427 mt8173_nor
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
428 if (IS_ERR(mt8173_nor
->base
))
429 return PTR_ERR(mt8173_nor
->base
);
431 mt8173_nor
->spi_clk
= devm_clk_get(&pdev
->dev
, "spi");
432 if (IS_ERR(mt8173_nor
->spi_clk
))
433 return PTR_ERR(mt8173_nor
->spi_clk
);
435 mt8173_nor
->nor_clk
= devm_clk_get(&pdev
->dev
, "sf");
436 if (IS_ERR(mt8173_nor
->nor_clk
))
437 return PTR_ERR(mt8173_nor
->nor_clk
);
439 mt8173_nor
->dev
= &pdev
->dev
;
440 ret
= clk_prepare_enable(mt8173_nor
->spi_clk
);
444 ret
= clk_prepare_enable(mt8173_nor
->nor_clk
);
446 clk_disable_unprepare(mt8173_nor
->spi_clk
);
449 /* only support one attached flash */
450 flash_np
= of_get_next_available_child(pdev
->dev
.of_node
, NULL
);
452 dev_err(&pdev
->dev
, "no SPI flash device to configure\n");
456 ret
= mtk_nor_init(mt8173_nor
, flash_np
);
460 clk_disable_unprepare(mt8173_nor
->spi_clk
);
461 clk_disable_unprepare(mt8173_nor
->nor_clk
);
466 static int mtk_nor_drv_remove(struct platform_device
*pdev
)
468 struct mt8173_nor
*mt8173_nor
= platform_get_drvdata(pdev
);
470 clk_disable_unprepare(mt8173_nor
->spi_clk
);
471 clk_disable_unprepare(mt8173_nor
->nor_clk
);
475 static const struct of_device_id mtk_nor_of_ids
[] = {
476 { .compatible
= "mediatek,mt8173-nor"},
479 MODULE_DEVICE_TABLE(of
, mtk_nor_of_ids
);
481 static struct platform_driver mtk_nor_driver
= {
482 .probe
= mtk_nor_drv_probe
,
483 .remove
= mtk_nor_drv_remove
,
486 .of_match_table
= mtk_nor_of_ids
,
490 module_platform_driver(mtk_nor_driver
);
491 MODULE_LICENSE("GPL v2");
492 MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");