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Revert "drm/i915: Use crtc_state->active in primary check_plane func"
[deliverable/linux.git] / drivers / mtd / spi-nor / spi-nor.c
1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
25
26 /* Define max times to check status register before we give up. */
27 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
28
29 #define SPI_NOR_MAX_ID_LEN 6
30
31 struct flash_info {
32 /*
33 * This array stores the ID bytes.
34 * The first three bytes are the JEDIC ID.
35 * JEDEC ID zero means "no ID" (mostly older chips).
36 */
37 u8 id[SPI_NOR_MAX_ID_LEN];
38 u8 id_len;
39
40 /* The size listed here is what works with SPINOR_OP_SE, which isn't
41 * necessarily called a "sector" by the vendor.
42 */
43 unsigned sector_size;
44 u16 n_sectors;
45
46 u16 page_size;
47 u16 addr_width;
48
49 u16 flags;
50 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
51 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
52 #define SST_WRITE 0x04 /* use SST byte programming */
53 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
54 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
55 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
56 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
57 #define USE_FSR 0x80 /* use flag status register */
58 };
59
60 #define JEDEC_MFR(info) ((info)->id[0])
61
62 static const struct spi_device_id *spi_nor_match_id(const char *name);
63
64 /*
65 * Read the status register, returning its value in the location
66 * Return the status register value.
67 * Returns negative if error occurred.
68 */
69 static int read_sr(struct spi_nor *nor)
70 {
71 int ret;
72 u8 val;
73
74 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
75 if (ret < 0) {
76 pr_err("error %d reading SR\n", (int) ret);
77 return ret;
78 }
79
80 return val;
81 }
82
83 /*
84 * Read the flag status register, returning its value in the location
85 * Return the status register value.
86 * Returns negative if error occurred.
87 */
88 static int read_fsr(struct spi_nor *nor)
89 {
90 int ret;
91 u8 val;
92
93 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
94 if (ret < 0) {
95 pr_err("error %d reading FSR\n", ret);
96 return ret;
97 }
98
99 return val;
100 }
101
102 /*
103 * Read configuration register, returning its value in the
104 * location. Return the configuration register value.
105 * Returns negative if error occured.
106 */
107 static int read_cr(struct spi_nor *nor)
108 {
109 int ret;
110 u8 val;
111
112 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
113 if (ret < 0) {
114 dev_err(nor->dev, "error %d reading CR\n", ret);
115 return ret;
116 }
117
118 return val;
119 }
120
121 /*
122 * Dummy Cycle calculation for different type of read.
123 * It can be used to support more commands with
124 * different dummy cycle requirements.
125 */
126 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
127 {
128 switch (nor->flash_read) {
129 case SPI_NOR_FAST:
130 case SPI_NOR_DUAL:
131 case SPI_NOR_QUAD:
132 return 8;
133 case SPI_NOR_NORMAL:
134 return 0;
135 }
136 return 0;
137 }
138
139 /*
140 * Write status register 1 byte
141 * Returns negative if error occurred.
142 */
143 static inline int write_sr(struct spi_nor *nor, u8 val)
144 {
145 nor->cmd_buf[0] = val;
146 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
147 }
148
149 /*
150 * Set write enable latch with Write Enable command.
151 * Returns negative if error occurred.
152 */
153 static inline int write_enable(struct spi_nor *nor)
154 {
155 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
156 }
157
158 /*
159 * Send write disble instruction to the chip.
160 */
161 static inline int write_disable(struct spi_nor *nor)
162 {
163 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
164 }
165
166 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
167 {
168 return mtd->priv;
169 }
170
171 /* Enable/disable 4-byte addressing mode. */
172 static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
173 int enable)
174 {
175 int status;
176 bool need_wren = false;
177 u8 cmd;
178
179 switch (JEDEC_MFR(info)) {
180 case CFI_MFR_ST: /* Micron, actually */
181 /* Some Micron need WREN command; all will accept it */
182 need_wren = true;
183 case CFI_MFR_MACRONIX:
184 case 0xEF /* winbond */:
185 if (need_wren)
186 write_enable(nor);
187
188 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
189 status = nor->write_reg(nor, cmd, NULL, 0, 0);
190 if (need_wren)
191 write_disable(nor);
192
193 return status;
194 default:
195 /* Spansion style */
196 nor->cmd_buf[0] = enable << 7;
197 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
198 }
199 }
200 static inline int spi_nor_sr_ready(struct spi_nor *nor)
201 {
202 int sr = read_sr(nor);
203 if (sr < 0)
204 return sr;
205 else
206 return !(sr & SR_WIP);
207 }
208
209 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
210 {
211 int fsr = read_fsr(nor);
212 if (fsr < 0)
213 return fsr;
214 else
215 return fsr & FSR_READY;
216 }
217
218 static int spi_nor_ready(struct spi_nor *nor)
219 {
220 int sr, fsr;
221 sr = spi_nor_sr_ready(nor);
222 if (sr < 0)
223 return sr;
224 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
225 if (fsr < 0)
226 return fsr;
227 return sr && fsr;
228 }
229
230 /*
231 * Service routine to read status register until ready, or timeout occurs.
232 * Returns non-zero if error.
233 */
234 static int spi_nor_wait_till_ready(struct spi_nor *nor)
235 {
236 unsigned long deadline;
237 int timeout = 0, ret;
238
239 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
240
241 while (!timeout) {
242 if (time_after_eq(jiffies, deadline))
243 timeout = 1;
244
245 ret = spi_nor_ready(nor);
246 if (ret < 0)
247 return ret;
248 if (ret)
249 return 0;
250
251 cond_resched();
252 }
253
254 dev_err(nor->dev, "flash operation timed out\n");
255
256 return -ETIMEDOUT;
257 }
258
259 /*
260 * Erase the whole flash memory
261 *
262 * Returns 0 if successful, non-zero otherwise.
263 */
264 static int erase_chip(struct spi_nor *nor)
265 {
266 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
267
268 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
269 }
270
271 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
272 {
273 int ret = 0;
274
275 mutex_lock(&nor->lock);
276
277 if (nor->prepare) {
278 ret = nor->prepare(nor, ops);
279 if (ret) {
280 dev_err(nor->dev, "failed in the preparation.\n");
281 mutex_unlock(&nor->lock);
282 return ret;
283 }
284 }
285 return ret;
286 }
287
288 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
289 {
290 if (nor->unprepare)
291 nor->unprepare(nor, ops);
292 mutex_unlock(&nor->lock);
293 }
294
295 /*
296 * Erase an address range on the nor chip. The address range may extend
297 * one or more erase sectors. Return an error is there is a problem erasing.
298 */
299 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
300 {
301 struct spi_nor *nor = mtd_to_spi_nor(mtd);
302 u32 addr, len;
303 uint32_t rem;
304 int ret;
305
306 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
307 (long long)instr->len);
308
309 div_u64_rem(instr->len, mtd->erasesize, &rem);
310 if (rem)
311 return -EINVAL;
312
313 addr = instr->addr;
314 len = instr->len;
315
316 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
317 if (ret)
318 return ret;
319
320 /* whole-chip erase? */
321 if (len == mtd->size) {
322 write_enable(nor);
323
324 if (erase_chip(nor)) {
325 ret = -EIO;
326 goto erase_err;
327 }
328
329 ret = spi_nor_wait_till_ready(nor);
330 if (ret)
331 goto erase_err;
332
333 /* REVISIT in some cases we could speed up erasing large regions
334 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
335 * to use "small sector erase", but that's not always optimal.
336 */
337
338 /* "sector"-at-a-time erase */
339 } else {
340 while (len) {
341 write_enable(nor);
342
343 if (nor->erase(nor, addr)) {
344 ret = -EIO;
345 goto erase_err;
346 }
347
348 addr += mtd->erasesize;
349 len -= mtd->erasesize;
350
351 ret = spi_nor_wait_till_ready(nor);
352 if (ret)
353 goto erase_err;
354 }
355 }
356
357 write_disable(nor);
358
359 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
360
361 instr->state = MTD_ERASE_DONE;
362 mtd_erase_callback(instr);
363
364 return ret;
365
366 erase_err:
367 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
368 instr->state = MTD_ERASE_FAILED;
369 return ret;
370 }
371
372 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
373 {
374 struct mtd_info *mtd = nor->mtd;
375 uint32_t offset = ofs;
376 uint8_t status_old, status_new;
377 int ret = 0;
378
379 status_old = read_sr(nor);
380
381 if (offset < mtd->size - (mtd->size / 2))
382 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
383 else if (offset < mtd->size - (mtd->size / 4))
384 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
385 else if (offset < mtd->size - (mtd->size / 8))
386 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
387 else if (offset < mtd->size - (mtd->size / 16))
388 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
389 else if (offset < mtd->size - (mtd->size / 32))
390 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
391 else if (offset < mtd->size - (mtd->size / 64))
392 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
393 else
394 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
395
396 /* Only modify protection if it will not unlock other areas */
397 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
398 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
399 write_enable(nor);
400 ret = write_sr(nor, status_new);
401 }
402
403 return ret;
404 }
405
406 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
407 {
408 struct mtd_info *mtd = nor->mtd;
409 uint32_t offset = ofs;
410 uint8_t status_old, status_new;
411 int ret = 0;
412
413 status_old = read_sr(nor);
414
415 if (offset+len > mtd->size - (mtd->size / 64))
416 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
417 else if (offset+len > mtd->size - (mtd->size / 32))
418 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
419 else if (offset+len > mtd->size - (mtd->size / 16))
420 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
421 else if (offset+len > mtd->size - (mtd->size / 8))
422 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
423 else if (offset+len > mtd->size - (mtd->size / 4))
424 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
425 else if (offset+len > mtd->size - (mtd->size / 2))
426 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
427 else
428 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
429
430 /* Only modify protection if it will not lock other areas */
431 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
432 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
433 write_enable(nor);
434 ret = write_sr(nor, status_new);
435 }
436
437 return ret;
438 }
439
440 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
441 {
442 struct spi_nor *nor = mtd_to_spi_nor(mtd);
443 int ret;
444
445 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
446 if (ret)
447 return ret;
448
449 ret = nor->flash_lock(nor, ofs, len);
450
451 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
452 return ret;
453 }
454
455 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
456 {
457 struct spi_nor *nor = mtd_to_spi_nor(mtd);
458 int ret;
459
460 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
461 if (ret)
462 return ret;
463
464 ret = nor->flash_unlock(nor, ofs, len);
465
466 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
467 return ret;
468 }
469
470 /* Used when the "_ext_id" is two bytes at most */
471 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
472 ((kernel_ulong_t)&(struct flash_info) { \
473 .id = { \
474 ((_jedec_id) >> 16) & 0xff, \
475 ((_jedec_id) >> 8) & 0xff, \
476 (_jedec_id) & 0xff, \
477 ((_ext_id) >> 8) & 0xff, \
478 (_ext_id) & 0xff, \
479 }, \
480 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
481 .sector_size = (_sector_size), \
482 .n_sectors = (_n_sectors), \
483 .page_size = 256, \
484 .flags = (_flags), \
485 })
486
487 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
488 ((kernel_ulong_t)&(struct flash_info) { \
489 .id = { \
490 ((_jedec_id) >> 16) & 0xff, \
491 ((_jedec_id) >> 8) & 0xff, \
492 (_jedec_id) & 0xff, \
493 ((_ext_id) >> 16) & 0xff, \
494 ((_ext_id) >> 8) & 0xff, \
495 (_ext_id) & 0xff, \
496 }, \
497 .id_len = 6, \
498 .sector_size = (_sector_size), \
499 .n_sectors = (_n_sectors), \
500 .page_size = 256, \
501 .flags = (_flags), \
502 })
503
504 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
505 ((kernel_ulong_t)&(struct flash_info) { \
506 .sector_size = (_sector_size), \
507 .n_sectors = (_n_sectors), \
508 .page_size = (_page_size), \
509 .addr_width = (_addr_width), \
510 .flags = (_flags), \
511 })
512
513 /* NOTE: double check command sets and memory organization when you add
514 * more nor chips. This current list focusses on newer chips, which
515 * have been converging on command sets which including JEDEC ID.
516 *
517 * All newly added entries should describe *hardware* and should use SECT_4K
518 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
519 * scenarios excluding small sectors there is config option that can be
520 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
521 * For historical (and compatibility) reasons (before we got above config) some
522 * old entries may be missing 4K flag.
523 */
524 static const struct spi_device_id spi_nor_ids[] = {
525 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
526 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
527 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
528
529 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
530 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
531 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
532
533 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
534 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
535 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
536 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
537
538 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
539
540 /* EON -- en25xxx */
541 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
542 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
543 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
544 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
545 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
546 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
547 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
548 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
549
550 /* ESMT */
551 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
552
553 /* Everspin */
554 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
555 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
556
557 /* Fujitsu */
558 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
559
560 /* GigaDevice */
561 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
562 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
563 { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
564
565 /* Intel/Numonyx -- xxxs33b */
566 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
567 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
568 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
569
570 /* ISSI */
571 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
572
573 /* Macronix */
574 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
575 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
576 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
577 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
578 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
579 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
580 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
581 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
582 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
583 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
584 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
585 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
586 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
587 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
588 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
589
590 /* Micron */
591 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
592 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
593 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
594 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
595 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
596 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
597 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
598 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
599
600 /* PMC */
601 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
602 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
603 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
604
605 /* Spansion -- single (large) sector size only, at least
606 * for the chips listed here (without boot sectors).
607 */
608 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
609 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
610 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
611 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
612 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
613 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
614 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
615 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
616 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
617 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
618 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
619 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
620 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
621 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
622 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
623 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
624 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
625 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
626 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
627 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
628 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
629
630 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
631 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
632 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
633 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
634 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
635 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
636 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
637 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
638 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
639 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
640 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
641
642 /* ST Microelectronics -- newer production may have feature updates */
643 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
644 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
645 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
646 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
647 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
648 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
649 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
650 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
651 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
652
653 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
654 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
655 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
656 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
657 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
658 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
659 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
660 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
661 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
662
663 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
664 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
665 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
666
667 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
668 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
669 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
670
671 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
672 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
673 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
674 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
675 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
676 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
677
678 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
679 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
680 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
681 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
682 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
683 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
684 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
685 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
686 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
687 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
688 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
689 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
690 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
691 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
692 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
693 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
694 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
695
696 /* Catalyst / On Semiconductor -- non-JEDEC */
697 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
698 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
699 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
700 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
701 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
702 { },
703 };
704
705 static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
706 {
707 int tmp;
708 u8 id[SPI_NOR_MAX_ID_LEN];
709 struct flash_info *info;
710
711 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
712 if (tmp < 0) {
713 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
714 return ERR_PTR(tmp);
715 }
716
717 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
718 info = (void *)spi_nor_ids[tmp].driver_data;
719 if (info->id_len) {
720 if (!memcmp(info->id, id, info->id_len))
721 return &spi_nor_ids[tmp];
722 }
723 }
724 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
725 id[0], id[1], id[2]);
726 return ERR_PTR(-ENODEV);
727 }
728
729 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
730 size_t *retlen, u_char *buf)
731 {
732 struct spi_nor *nor = mtd_to_spi_nor(mtd);
733 int ret;
734
735 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
736
737 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
738 if (ret)
739 return ret;
740
741 ret = nor->read(nor, from, len, retlen, buf);
742
743 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
744 return ret;
745 }
746
747 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
748 size_t *retlen, const u_char *buf)
749 {
750 struct spi_nor *nor = mtd_to_spi_nor(mtd);
751 size_t actual;
752 int ret;
753
754 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
755
756 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
757 if (ret)
758 return ret;
759
760 write_enable(nor);
761
762 nor->sst_write_second = false;
763
764 actual = to % 2;
765 /* Start write from odd address. */
766 if (actual) {
767 nor->program_opcode = SPINOR_OP_BP;
768
769 /* write one byte. */
770 nor->write(nor, to, 1, retlen, buf);
771 ret = spi_nor_wait_till_ready(nor);
772 if (ret)
773 goto time_out;
774 }
775 to += actual;
776
777 /* Write out most of the data here. */
778 for (; actual < len - 1; actual += 2) {
779 nor->program_opcode = SPINOR_OP_AAI_WP;
780
781 /* write two bytes. */
782 nor->write(nor, to, 2, retlen, buf + actual);
783 ret = spi_nor_wait_till_ready(nor);
784 if (ret)
785 goto time_out;
786 to += 2;
787 nor->sst_write_second = true;
788 }
789 nor->sst_write_second = false;
790
791 write_disable(nor);
792 ret = spi_nor_wait_till_ready(nor);
793 if (ret)
794 goto time_out;
795
796 /* Write out trailing byte if it exists. */
797 if (actual != len) {
798 write_enable(nor);
799
800 nor->program_opcode = SPINOR_OP_BP;
801 nor->write(nor, to, 1, retlen, buf + actual);
802
803 ret = spi_nor_wait_till_ready(nor);
804 if (ret)
805 goto time_out;
806 write_disable(nor);
807 }
808 time_out:
809 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
810 return ret;
811 }
812
813 /*
814 * Write an address range to the nor chip. Data must be written in
815 * FLASH_PAGESIZE chunks. The address range may be any size provided
816 * it is within the physical boundaries.
817 */
818 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
819 size_t *retlen, const u_char *buf)
820 {
821 struct spi_nor *nor = mtd_to_spi_nor(mtd);
822 u32 page_offset, page_size, i;
823 int ret;
824
825 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
826
827 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
828 if (ret)
829 return ret;
830
831 write_enable(nor);
832
833 page_offset = to & (nor->page_size - 1);
834
835 /* do all the bytes fit onto one page? */
836 if (page_offset + len <= nor->page_size) {
837 nor->write(nor, to, len, retlen, buf);
838 } else {
839 /* the size of data remaining on the first page */
840 page_size = nor->page_size - page_offset;
841 nor->write(nor, to, page_size, retlen, buf);
842
843 /* write everything in nor->page_size chunks */
844 for (i = page_size; i < len; i += page_size) {
845 page_size = len - i;
846 if (page_size > nor->page_size)
847 page_size = nor->page_size;
848
849 ret = spi_nor_wait_till_ready(nor);
850 if (ret)
851 goto write_err;
852
853 write_enable(nor);
854
855 nor->write(nor, to + i, page_size, retlen, buf + i);
856 }
857 }
858
859 ret = spi_nor_wait_till_ready(nor);
860 write_err:
861 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
862 return ret;
863 }
864
865 static int macronix_quad_enable(struct spi_nor *nor)
866 {
867 int ret, val;
868
869 val = read_sr(nor);
870 write_enable(nor);
871
872 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
873 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
874
875 if (spi_nor_wait_till_ready(nor))
876 return 1;
877
878 ret = read_sr(nor);
879 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
880 dev_err(nor->dev, "Macronix Quad bit not set\n");
881 return -EINVAL;
882 }
883
884 return 0;
885 }
886
887 /*
888 * Write status Register and configuration register with 2 bytes
889 * The first byte will be written to the status register, while the
890 * second byte will be written to the configuration register.
891 * Return negative if error occured.
892 */
893 static int write_sr_cr(struct spi_nor *nor, u16 val)
894 {
895 nor->cmd_buf[0] = val & 0xff;
896 nor->cmd_buf[1] = (val >> 8);
897
898 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
899 }
900
901 static int spansion_quad_enable(struct spi_nor *nor)
902 {
903 int ret;
904 int quad_en = CR_QUAD_EN_SPAN << 8;
905
906 write_enable(nor);
907
908 ret = write_sr_cr(nor, quad_en);
909 if (ret < 0) {
910 dev_err(nor->dev,
911 "error while writing configuration register\n");
912 return -EINVAL;
913 }
914
915 /* read back and check it */
916 ret = read_cr(nor);
917 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
918 dev_err(nor->dev, "Spansion Quad bit not set\n");
919 return -EINVAL;
920 }
921
922 return 0;
923 }
924
925 static int micron_quad_enable(struct spi_nor *nor)
926 {
927 int ret;
928 u8 val;
929
930 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
931 if (ret < 0) {
932 dev_err(nor->dev, "error %d reading EVCR\n", ret);
933 return ret;
934 }
935
936 write_enable(nor);
937
938 /* set EVCR, enable quad I/O */
939 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
940 ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
941 if (ret < 0) {
942 dev_err(nor->dev, "error while writing EVCR register\n");
943 return ret;
944 }
945
946 ret = spi_nor_wait_till_ready(nor);
947 if (ret)
948 return ret;
949
950 /* read EVCR and check it */
951 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
952 if (ret < 0) {
953 dev_err(nor->dev, "error %d reading EVCR\n", ret);
954 return ret;
955 }
956 if (val & EVCR_QUAD_EN_MICRON) {
957 dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
958 return -EINVAL;
959 }
960
961 return 0;
962 }
963
964 static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
965 {
966 int status;
967
968 switch (JEDEC_MFR(info)) {
969 case CFI_MFR_MACRONIX:
970 status = macronix_quad_enable(nor);
971 if (status) {
972 dev_err(nor->dev, "Macronix quad-read not enabled\n");
973 return -EINVAL;
974 }
975 return status;
976 case CFI_MFR_ST:
977 status = micron_quad_enable(nor);
978 if (status) {
979 dev_err(nor->dev, "Micron quad-read not enabled\n");
980 return -EINVAL;
981 }
982 return status;
983 default:
984 status = spansion_quad_enable(nor);
985 if (status) {
986 dev_err(nor->dev, "Spansion quad-read not enabled\n");
987 return -EINVAL;
988 }
989 return status;
990 }
991 }
992
993 static int spi_nor_check(struct spi_nor *nor)
994 {
995 if (!nor->dev || !nor->read || !nor->write ||
996 !nor->read_reg || !nor->write_reg || !nor->erase) {
997 pr_err("spi-nor: please fill all the necessary fields!\n");
998 return -EINVAL;
999 }
1000
1001 return 0;
1002 }
1003
1004 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1005 {
1006 const struct spi_device_id *id = NULL;
1007 struct flash_info *info;
1008 struct device *dev = nor->dev;
1009 struct mtd_info *mtd = nor->mtd;
1010 struct device_node *np = dev->of_node;
1011 int ret;
1012 int i;
1013
1014 ret = spi_nor_check(nor);
1015 if (ret)
1016 return ret;
1017
1018 /* Try to auto-detect if chip name wasn't specified */
1019 if (!name)
1020 id = spi_nor_read_id(nor);
1021 else
1022 id = spi_nor_match_id(name);
1023 if (IS_ERR_OR_NULL(id))
1024 return -ENOENT;
1025
1026 info = (void *)id->driver_data;
1027
1028 /*
1029 * If caller has specified name of flash model that can normally be
1030 * detected using JEDEC, let's verify it.
1031 */
1032 if (name && info->id_len) {
1033 const struct spi_device_id *jid;
1034
1035 jid = spi_nor_read_id(nor);
1036 if (IS_ERR(jid)) {
1037 return PTR_ERR(jid);
1038 } else if (jid != id) {
1039 /*
1040 * JEDEC knows better, so overwrite platform ID. We
1041 * can't trust partitions any longer, but we'll let
1042 * mtd apply them anyway, since some partitions may be
1043 * marked read-only, and we don't want to lose that
1044 * information, even if it's not 100% accurate.
1045 */
1046 dev_warn(dev, "found %s, expected %s\n",
1047 jid->name, id->name);
1048 id = jid;
1049 info = (void *)jid->driver_data;
1050 }
1051 }
1052
1053 mutex_init(&nor->lock);
1054
1055 /*
1056 * Atmel, SST and Intel/Numonyx serial nor tend to power
1057 * up with the software protection bits set
1058 */
1059
1060 if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
1061 JEDEC_MFR(info) == CFI_MFR_INTEL ||
1062 JEDEC_MFR(info) == CFI_MFR_SST) {
1063 write_enable(nor);
1064 write_sr(nor, 0);
1065 }
1066
1067 if (!mtd->name)
1068 mtd->name = dev_name(dev);
1069 mtd->type = MTD_NORFLASH;
1070 mtd->writesize = 1;
1071 mtd->flags = MTD_CAP_NORFLASH;
1072 mtd->size = info->sector_size * info->n_sectors;
1073 mtd->_erase = spi_nor_erase;
1074 mtd->_read = spi_nor_read;
1075
1076 /* nor protection support for STmicro chips */
1077 if (JEDEC_MFR(info) == CFI_MFR_ST) {
1078 nor->flash_lock = stm_lock;
1079 nor->flash_unlock = stm_unlock;
1080 }
1081
1082 if (nor->flash_lock && nor->flash_unlock) {
1083 mtd->_lock = spi_nor_lock;
1084 mtd->_unlock = spi_nor_unlock;
1085 }
1086
1087 /* sst nor chips use AAI word program */
1088 if (info->flags & SST_WRITE)
1089 mtd->_write = sst_write;
1090 else
1091 mtd->_write = spi_nor_write;
1092
1093 if (info->flags & USE_FSR)
1094 nor->flags |= SNOR_F_USE_FSR;
1095
1096 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1097 /* prefer "small sector" erase if possible */
1098 if (info->flags & SECT_4K) {
1099 nor->erase_opcode = SPINOR_OP_BE_4K;
1100 mtd->erasesize = 4096;
1101 } else if (info->flags & SECT_4K_PMC) {
1102 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1103 mtd->erasesize = 4096;
1104 } else
1105 #endif
1106 {
1107 nor->erase_opcode = SPINOR_OP_SE;
1108 mtd->erasesize = info->sector_size;
1109 }
1110
1111 if (info->flags & SPI_NOR_NO_ERASE)
1112 mtd->flags |= MTD_NO_ERASE;
1113
1114 mtd->dev.parent = dev;
1115 nor->page_size = info->page_size;
1116 mtd->writebufsize = nor->page_size;
1117
1118 if (np) {
1119 /* If we were instantiated by DT, use it */
1120 if (of_property_read_bool(np, "m25p,fast-read"))
1121 nor->flash_read = SPI_NOR_FAST;
1122 else
1123 nor->flash_read = SPI_NOR_NORMAL;
1124 } else {
1125 /* If we weren't instantiated by DT, default to fast-read */
1126 nor->flash_read = SPI_NOR_FAST;
1127 }
1128
1129 /* Some devices cannot do fast-read, no matter what DT tells us */
1130 if (info->flags & SPI_NOR_NO_FR)
1131 nor->flash_read = SPI_NOR_NORMAL;
1132
1133 /* Quad/Dual-read mode takes precedence over fast/normal */
1134 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1135 ret = set_quad_mode(nor, info);
1136 if (ret) {
1137 dev_err(dev, "quad mode not supported\n");
1138 return ret;
1139 }
1140 nor->flash_read = SPI_NOR_QUAD;
1141 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1142 nor->flash_read = SPI_NOR_DUAL;
1143 }
1144
1145 /* Default commands */
1146 switch (nor->flash_read) {
1147 case SPI_NOR_QUAD:
1148 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1149 break;
1150 case SPI_NOR_DUAL:
1151 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1152 break;
1153 case SPI_NOR_FAST:
1154 nor->read_opcode = SPINOR_OP_READ_FAST;
1155 break;
1156 case SPI_NOR_NORMAL:
1157 nor->read_opcode = SPINOR_OP_READ;
1158 break;
1159 default:
1160 dev_err(dev, "No Read opcode defined\n");
1161 return -EINVAL;
1162 }
1163
1164 nor->program_opcode = SPINOR_OP_PP;
1165
1166 if (info->addr_width)
1167 nor->addr_width = info->addr_width;
1168 else if (mtd->size > 0x1000000) {
1169 /* enable 4-byte addressing if the device exceeds 16MiB */
1170 nor->addr_width = 4;
1171 if (JEDEC_MFR(info) == CFI_MFR_AMD) {
1172 /* Dedicated 4-byte command set */
1173 switch (nor->flash_read) {
1174 case SPI_NOR_QUAD:
1175 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1176 break;
1177 case SPI_NOR_DUAL:
1178 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1179 break;
1180 case SPI_NOR_FAST:
1181 nor->read_opcode = SPINOR_OP_READ4_FAST;
1182 break;
1183 case SPI_NOR_NORMAL:
1184 nor->read_opcode = SPINOR_OP_READ4;
1185 break;
1186 }
1187 nor->program_opcode = SPINOR_OP_PP_4B;
1188 /* No small sector erase for 4-byte command set */
1189 nor->erase_opcode = SPINOR_OP_SE_4B;
1190 mtd->erasesize = info->sector_size;
1191 } else
1192 set_4byte(nor, info, 1);
1193 } else {
1194 nor->addr_width = 3;
1195 }
1196
1197 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1198
1199 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1200 (long long)mtd->size >> 10);
1201
1202 dev_dbg(dev,
1203 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1204 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1205 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1206 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1207
1208 if (mtd->numeraseregions)
1209 for (i = 0; i < mtd->numeraseregions; i++)
1210 dev_dbg(dev,
1211 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1212 ".erasesize = 0x%.8x (%uKiB), "
1213 ".numblocks = %d }\n",
1214 i, (long long)mtd->eraseregions[i].offset,
1215 mtd->eraseregions[i].erasesize,
1216 mtd->eraseregions[i].erasesize / 1024,
1217 mtd->eraseregions[i].numblocks);
1218 return 0;
1219 }
1220 EXPORT_SYMBOL_GPL(spi_nor_scan);
1221
1222 static const struct spi_device_id *spi_nor_match_id(const char *name)
1223 {
1224 const struct spi_device_id *id = spi_nor_ids;
1225
1226 while (id->name[0]) {
1227 if (!strcmp(name, id->name))
1228 return id;
1229 id++;
1230 }
1231 return NULL;
1232 }
1233
1234 MODULE_LICENSE("GPL");
1235 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1236 MODULE_AUTHOR("Mike Lavender");
1237 MODULE_DESCRIPTION("framework for SPI NOR");
Linux kernel - Deliverables
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