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iwlwifi: handle shared memory Rx index access
[deliverable/linux.git] / drivers / net / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define DRV_NAME "8139cp"
50 #define DRV_VERSION "1.3"
51 #define DRV_RELDATE "Mar 22, 2004"
52
53
54 #include <linux/module.h>
55 #include <linux/moduleparam.h>
56 #include <linux/kernel.h>
57 #include <linux/compiler.h>
58 #include <linux/netdevice.h>
59 #include <linux/etherdevice.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
68 #include <linux/in.h>
69 #include <linux/ip.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
73 #include <asm/io.h>
74 #include <asm/irq.h>
75 #include <asm/uaccess.h>
76
77 /* VLAN tagging feature enable/disable */
78 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79 #define CP_VLAN_TAG_USED 1
80 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
82 #else
83 #define CP_VLAN_TAG_USED 0
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86 #endif
87
88 /* These identify the driver base version and may not be removed. */
89 static char version[] =
90 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_LICENSE("GPL");
96
97 static int debug = -1;
98 module_param(debug, int, 0);
99 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103 static int multicast_filter_limit = 32;
104 module_param(multicast_filter_limit, int, 0);
105 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107 #define PFX DRV_NAME ": "
108
109 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114 #define CP_REGS_SIZE (0xff + 1)
115 #define CP_REGS_VER 1 /* version 1 */
116 #define CP_RX_RING_SIZE 64
117 #define CP_TX_RING_SIZE 64
118 #define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124 #define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130 #define RX_OFFSET 2
131 #define CP_INTERNAL_PHY 32
132
133 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define TX_TIMEOUT (6*HZ)
141
142 /* hardware minimum and maximum for a single frame's data payload */
143 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144 #define CP_MAX_MTU 4096
145
146 enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299 };
300
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305 struct cp_desc {
306 __le32 opts1;
307 __le32 opts2;
308 __le64 addr;
309 };
310
311 struct cp_dma_stats {
312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
325 } __attribute__((packed));
326
327 struct cp_extra_stats {
328 unsigned long rx_frags;
329 };
330
331 struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
337 struct napi_struct napi;
338
339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
343 struct cp_extra_stats cp_stats;
344
345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
347 struct cp_desc *rx_ring;
348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
352 struct cp_desc *tx_ring;
353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
357
358 #if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360 #endif
361 dma_addr_t ring_dma;
362
363 struct mii_if_info mii_if;
364 };
365
366 #define cpr8(reg) readb(cp->regs + (reg))
367 #define cpr16(reg) readw(cp->regs + (reg))
368 #define cpr32(reg) readl(cp->regs + (reg))
369 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
370 #define cpw16(reg,val) writew((val), cp->regs + (reg))
371 #define cpw32(reg,val) writel((val), cp->regs + (reg))
372 #define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376 #define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380 #define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386 static void __cp_set_rx_mode (struct net_device *dev);
387 static void cp_tx (struct cp_private *cp);
388 static void cp_clean_rings (struct cp_private *cp);
389 #ifdef CONFIG_NET_POLL_CONTROLLER
390 static void cp_poll_controller(struct net_device *dev);
391 #endif
392 static int cp_get_eeprom_len(struct net_device *dev);
393 static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395 static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
397
398 static struct pci_device_id cp_pci_tbl[] = {
399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
401 { },
402 };
403 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405 static struct {
406 const char str[ETH_GSTRING_LEN];
407 } ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422 };
423
424
425 #if CP_VLAN_TAG_USED
426 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427 {
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
437
438 cpw16(CpCmd, cp->cpcmd);
439 spin_unlock_irqrestore(&cp->lock, flags);
440 }
441 #endif /* CP_VLAN_TAG_USED */
442
443 static inline void cp_set_rxbufsize (struct cp_private *cp)
444 {
445 unsigned int mtu = cp->dev->mtu;
446
447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452 }
453
454 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456 {
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
461 cp->dev->last_rx = jiffies;
462
463 #if CP_VLAN_TAG_USED
464 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
465 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
466 swab16(le32_to_cpu(desc->opts2) & 0xffff));
467 } else
468 #endif
469 netif_receive_skb(skb);
470 }
471
472 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
473 u32 status, u32 len)
474 {
475 if (netif_msg_rx_err (cp))
476 printk (KERN_DEBUG
477 "%s: rx err, slot %d status 0x%x len %d\n",
478 cp->dev->name, rx_tail, status, len);
479 cp->dev->stats.rx_errors++;
480 if (status & RxErrFrame)
481 cp->dev->stats.rx_frame_errors++;
482 if (status & RxErrCRC)
483 cp->dev->stats.rx_crc_errors++;
484 if ((status & RxErrRunt) || (status & RxErrLong))
485 cp->dev->stats.rx_length_errors++;
486 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
487 cp->dev->stats.rx_length_errors++;
488 if (status & RxErrFIFO)
489 cp->dev->stats.rx_fifo_errors++;
490 }
491
492 static inline unsigned int cp_rx_csum_ok (u32 status)
493 {
494 unsigned int protocol = (status >> 16) & 0x3;
495
496 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
497 return 1;
498 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
499 return 1;
500 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
501 return 1;
502 return 0;
503 }
504
505 static int cp_rx_poll(struct napi_struct *napi, int budget)
506 {
507 struct cp_private *cp = container_of(napi, struct cp_private, napi);
508 struct net_device *dev = cp->dev;
509 unsigned int rx_tail = cp->rx_tail;
510 int rx;
511
512 rx_status_loop:
513 rx = 0;
514 cpw16(IntrStatus, cp_rx_intr_mask);
515
516 while (1) {
517 u32 status, len;
518 dma_addr_t mapping;
519 struct sk_buff *skb, *new_skb;
520 struct cp_desc *desc;
521 unsigned buflen;
522
523 skb = cp->rx_skb[rx_tail];
524 BUG_ON(!skb);
525
526 desc = &cp->rx_ring[rx_tail];
527 status = le32_to_cpu(desc->opts1);
528 if (status & DescOwn)
529 break;
530
531 len = (status & 0x1fff) - 4;
532 mapping = le64_to_cpu(desc->addr);
533
534 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
535 /* we don't support incoming fragmented frames.
536 * instead, we attempt to ensure that the
537 * pre-allocated RX skbs are properly sized such
538 * that RX fragments are never encountered
539 */
540 cp_rx_err_acct(cp, rx_tail, status, len);
541 dev->stats.rx_dropped++;
542 cp->cp_stats.rx_frags++;
543 goto rx_next;
544 }
545
546 if (status & (RxError | RxErrFIFO)) {
547 cp_rx_err_acct(cp, rx_tail, status, len);
548 goto rx_next;
549 }
550
551 if (netif_msg_rx_status(cp))
552 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
553 dev->name, rx_tail, status, len);
554
555 buflen = cp->rx_buf_sz + RX_OFFSET;
556 new_skb = dev_alloc_skb (buflen);
557 if (!new_skb) {
558 dev->stats.rx_dropped++;
559 goto rx_next;
560 }
561
562 skb_reserve(new_skb, RX_OFFSET);
563
564 dma_unmap_single(&cp->pdev->dev, mapping,
565 buflen, PCI_DMA_FROMDEVICE);
566
567 /* Handle checksum offloading for incoming packets. */
568 if (cp_rx_csum_ok(status))
569 skb->ip_summed = CHECKSUM_UNNECESSARY;
570 else
571 skb->ip_summed = CHECKSUM_NONE;
572
573 skb_put(skb, len);
574
575 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
576 PCI_DMA_FROMDEVICE);
577 cp->rx_skb[rx_tail] = new_skb;
578
579 cp_rx_skb(cp, skb, desc);
580 rx++;
581
582 rx_next:
583 cp->rx_ring[rx_tail].opts2 = 0;
584 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
585 if (rx_tail == (CP_RX_RING_SIZE - 1))
586 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
587 cp->rx_buf_sz);
588 else
589 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
590 rx_tail = NEXT_RX(rx_tail);
591
592 if (rx >= budget)
593 break;
594 }
595
596 cp->rx_tail = rx_tail;
597
598 /* if we did not reach work limit, then we're done with
599 * this round of polling
600 */
601 if (rx < budget) {
602 unsigned long flags;
603
604 if (cpr16(IntrStatus) & cp_rx_intr_mask)
605 goto rx_status_loop;
606
607 spin_lock_irqsave(&cp->lock, flags);
608 cpw16_f(IntrMask, cp_intr_mask);
609 __netif_rx_complete(dev, napi);
610 spin_unlock_irqrestore(&cp->lock, flags);
611 }
612
613 return rx;
614 }
615
616 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
617 {
618 struct net_device *dev = dev_instance;
619 struct cp_private *cp;
620 u16 status;
621
622 if (unlikely(dev == NULL))
623 return IRQ_NONE;
624 cp = netdev_priv(dev);
625
626 status = cpr16(IntrStatus);
627 if (!status || (status == 0xFFFF))
628 return IRQ_NONE;
629
630 if (netif_msg_intr(cp))
631 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
632 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
633
634 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
635
636 spin_lock(&cp->lock);
637
638 /* close possible race's with dev_close */
639 if (unlikely(!netif_running(dev))) {
640 cpw16(IntrMask, 0);
641 spin_unlock(&cp->lock);
642 return IRQ_HANDLED;
643 }
644
645 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
646 if (netif_rx_schedule_prep(dev, &cp->napi)) {
647 cpw16_f(IntrMask, cp_norx_intr_mask);
648 __netif_rx_schedule(dev, &cp->napi);
649 }
650
651 if (status & (TxOK | TxErr | TxEmpty | SWInt))
652 cp_tx(cp);
653 if (status & LinkChg)
654 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
655
656 spin_unlock(&cp->lock);
657
658 if (status & PciErr) {
659 u16 pci_status;
660
661 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
662 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
663 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
664 dev->name, status, pci_status);
665
666 /* TODO: reset hardware */
667 }
668
669 return IRQ_HANDLED;
670 }
671
672 #ifdef CONFIG_NET_POLL_CONTROLLER
673 /*
674 * Polling receive - used by netconsole and other diagnostic tools
675 * to allow network i/o with interrupts disabled.
676 */
677 static void cp_poll_controller(struct net_device *dev)
678 {
679 disable_irq(dev->irq);
680 cp_interrupt(dev->irq, dev);
681 enable_irq(dev->irq);
682 }
683 #endif
684
685 static void cp_tx (struct cp_private *cp)
686 {
687 unsigned tx_head = cp->tx_head;
688 unsigned tx_tail = cp->tx_tail;
689
690 while (tx_tail != tx_head) {
691 struct cp_desc *txd = cp->tx_ring + tx_tail;
692 struct sk_buff *skb;
693 u32 status;
694
695 rmb();
696 status = le32_to_cpu(txd->opts1);
697 if (status & DescOwn)
698 break;
699
700 skb = cp->tx_skb[tx_tail];
701 BUG_ON(!skb);
702
703 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
704 le32_to_cpu(txd->opts1) & 0xffff,
705 PCI_DMA_TODEVICE);
706
707 if (status & LastFrag) {
708 if (status & (TxError | TxFIFOUnder)) {
709 if (netif_msg_tx_err(cp))
710 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
711 cp->dev->name, status);
712 cp->dev->stats.tx_errors++;
713 if (status & TxOWC)
714 cp->dev->stats.tx_window_errors++;
715 if (status & TxMaxCol)
716 cp->dev->stats.tx_aborted_errors++;
717 if (status & TxLinkFail)
718 cp->dev->stats.tx_carrier_errors++;
719 if (status & TxFIFOUnder)
720 cp->dev->stats.tx_fifo_errors++;
721 } else {
722 cp->dev->stats.collisions +=
723 ((status >> TxColCntShift) & TxColCntMask);
724 cp->dev->stats.tx_packets++;
725 cp->dev->stats.tx_bytes += skb->len;
726 if (netif_msg_tx_done(cp))
727 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
728 }
729 dev_kfree_skb_irq(skb);
730 }
731
732 cp->tx_skb[tx_tail] = NULL;
733
734 tx_tail = NEXT_TX(tx_tail);
735 }
736
737 cp->tx_tail = tx_tail;
738
739 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
740 netif_wake_queue(cp->dev);
741 }
742
743 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
744 {
745 struct cp_private *cp = netdev_priv(dev);
746 unsigned entry;
747 u32 eor, flags;
748 unsigned long intr_flags;
749 #if CP_VLAN_TAG_USED
750 u32 vlan_tag = 0;
751 #endif
752 int mss = 0;
753
754 spin_lock_irqsave(&cp->lock, intr_flags);
755
756 /* This is a hard error, log it. */
757 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
758 netif_stop_queue(dev);
759 spin_unlock_irqrestore(&cp->lock, intr_flags);
760 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
761 dev->name);
762 return 1;
763 }
764
765 #if CP_VLAN_TAG_USED
766 if (cp->vlgrp && vlan_tx_tag_present(skb))
767 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
768 #endif
769
770 entry = cp->tx_head;
771 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
772 if (dev->features & NETIF_F_TSO)
773 mss = skb_shinfo(skb)->gso_size;
774
775 if (skb_shinfo(skb)->nr_frags == 0) {
776 struct cp_desc *txd = &cp->tx_ring[entry];
777 u32 len;
778 dma_addr_t mapping;
779
780 len = skb->len;
781 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
782 CP_VLAN_TX_TAG(txd, vlan_tag);
783 txd->addr = cpu_to_le64(mapping);
784 wmb();
785
786 flags = eor | len | DescOwn | FirstFrag | LastFrag;
787
788 if (mss)
789 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
790 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
791 const struct iphdr *ip = ip_hdr(skb);
792 if (ip->protocol == IPPROTO_TCP)
793 flags |= IPCS | TCPCS;
794 else if (ip->protocol == IPPROTO_UDP)
795 flags |= IPCS | UDPCS;
796 else
797 WARN_ON(1); /* we need a WARN() */
798 }
799
800 txd->opts1 = cpu_to_le32(flags);
801 wmb();
802
803 cp->tx_skb[entry] = skb;
804 entry = NEXT_TX(entry);
805 } else {
806 struct cp_desc *txd;
807 u32 first_len, first_eor;
808 dma_addr_t first_mapping;
809 int frag, first_entry = entry;
810 const struct iphdr *ip = ip_hdr(skb);
811
812 /* We must give this initial chunk to the device last.
813 * Otherwise we could race with the device.
814 */
815 first_eor = eor;
816 first_len = skb_headlen(skb);
817 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
818 first_len, PCI_DMA_TODEVICE);
819 cp->tx_skb[entry] = skb;
820 entry = NEXT_TX(entry);
821
822 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
823 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
824 u32 len;
825 u32 ctrl;
826 dma_addr_t mapping;
827
828 len = this_frag->size;
829 mapping = dma_map_single(&cp->pdev->dev,
830 ((void *) page_address(this_frag->page) +
831 this_frag->page_offset),
832 len, PCI_DMA_TODEVICE);
833 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
834
835 ctrl = eor | len | DescOwn;
836
837 if (mss)
838 ctrl |= LargeSend |
839 ((mss & MSSMask) << MSSShift);
840 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
841 if (ip->protocol == IPPROTO_TCP)
842 ctrl |= IPCS | TCPCS;
843 else if (ip->protocol == IPPROTO_UDP)
844 ctrl |= IPCS | UDPCS;
845 else
846 BUG();
847 }
848
849 if (frag == skb_shinfo(skb)->nr_frags - 1)
850 ctrl |= LastFrag;
851
852 txd = &cp->tx_ring[entry];
853 CP_VLAN_TX_TAG(txd, vlan_tag);
854 txd->addr = cpu_to_le64(mapping);
855 wmb();
856
857 txd->opts1 = cpu_to_le32(ctrl);
858 wmb();
859
860 cp->tx_skb[entry] = skb;
861 entry = NEXT_TX(entry);
862 }
863
864 txd = &cp->tx_ring[first_entry];
865 CP_VLAN_TX_TAG(txd, vlan_tag);
866 txd->addr = cpu_to_le64(first_mapping);
867 wmb();
868
869 if (skb->ip_summed == CHECKSUM_PARTIAL) {
870 if (ip->protocol == IPPROTO_TCP)
871 txd->opts1 = cpu_to_le32(first_eor | first_len |
872 FirstFrag | DescOwn |
873 IPCS | TCPCS);
874 else if (ip->protocol == IPPROTO_UDP)
875 txd->opts1 = cpu_to_le32(first_eor | first_len |
876 FirstFrag | DescOwn |
877 IPCS | UDPCS);
878 else
879 BUG();
880 } else
881 txd->opts1 = cpu_to_le32(first_eor | first_len |
882 FirstFrag | DescOwn);
883 wmb();
884 }
885 cp->tx_head = entry;
886 if (netif_msg_tx_queued(cp))
887 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
888 dev->name, entry, skb->len);
889 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
890 netif_stop_queue(dev);
891
892 spin_unlock_irqrestore(&cp->lock, intr_flags);
893
894 cpw8(TxPoll, NormalTxPoll);
895 dev->trans_start = jiffies;
896
897 return 0;
898 }
899
900 /* Set or clear the multicast filter for this adaptor.
901 This routine is not state sensitive and need not be SMP locked. */
902
903 static void __cp_set_rx_mode (struct net_device *dev)
904 {
905 struct cp_private *cp = netdev_priv(dev);
906 u32 mc_filter[2]; /* Multicast hash filter */
907 int i, rx_mode;
908 u32 tmp;
909
910 /* Note: do not reorder, GCC is clever about common statements. */
911 if (dev->flags & IFF_PROMISC) {
912 /* Unconditionally log net taps. */
913 rx_mode =
914 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
915 AcceptAllPhys;
916 mc_filter[1] = mc_filter[0] = 0xffffffff;
917 } else if ((dev->mc_count > multicast_filter_limit)
918 || (dev->flags & IFF_ALLMULTI)) {
919 /* Too many to filter perfectly -- accept all multicasts. */
920 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
921 mc_filter[1] = mc_filter[0] = 0xffffffff;
922 } else {
923 struct dev_mc_list *mclist;
924 rx_mode = AcceptBroadcast | AcceptMyPhys;
925 mc_filter[1] = mc_filter[0] = 0;
926 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
927 i++, mclist = mclist->next) {
928 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
929
930 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
931 rx_mode |= AcceptMulticast;
932 }
933 }
934
935 /* We can safely update without stopping the chip. */
936 tmp = cp_rx_config | rx_mode;
937 if (cp->rx_config != tmp) {
938 cpw32_f (RxConfig, tmp);
939 cp->rx_config = tmp;
940 }
941 cpw32_f (MAR0 + 0, mc_filter[0]);
942 cpw32_f (MAR0 + 4, mc_filter[1]);
943 }
944
945 static void cp_set_rx_mode (struct net_device *dev)
946 {
947 unsigned long flags;
948 struct cp_private *cp = netdev_priv(dev);
949
950 spin_lock_irqsave (&cp->lock, flags);
951 __cp_set_rx_mode(dev);
952 spin_unlock_irqrestore (&cp->lock, flags);
953 }
954
955 static void __cp_get_stats(struct cp_private *cp)
956 {
957 /* only lower 24 bits valid; write any value to clear */
958 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
959 cpw32 (RxMissed, 0);
960 }
961
962 static struct net_device_stats *cp_get_stats(struct net_device *dev)
963 {
964 struct cp_private *cp = netdev_priv(dev);
965 unsigned long flags;
966
967 /* The chip only need report frame silently dropped. */
968 spin_lock_irqsave(&cp->lock, flags);
969 if (netif_running(dev) && netif_device_present(dev))
970 __cp_get_stats(cp);
971 spin_unlock_irqrestore(&cp->lock, flags);
972
973 return &dev->stats;
974 }
975
976 static void cp_stop_hw (struct cp_private *cp)
977 {
978 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
979 cpw16_f(IntrMask, 0);
980 cpw8(Cmd, 0);
981 cpw16_f(CpCmd, 0);
982 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
983
984 cp->rx_tail = 0;
985 cp->tx_head = cp->tx_tail = 0;
986 }
987
988 static void cp_reset_hw (struct cp_private *cp)
989 {
990 unsigned work = 1000;
991
992 cpw8(Cmd, CmdReset);
993
994 while (work--) {
995 if (!(cpr8(Cmd) & CmdReset))
996 return;
997
998 schedule_timeout_uninterruptible(10);
999 }
1000
1001 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1002 }
1003
1004 static inline void cp_start_hw (struct cp_private *cp)
1005 {
1006 cpw16(CpCmd, cp->cpcmd);
1007 cpw8(Cmd, RxOn | TxOn);
1008 }
1009
1010 static void cp_init_hw (struct cp_private *cp)
1011 {
1012 struct net_device *dev = cp->dev;
1013 dma_addr_t ring_dma;
1014
1015 cp_reset_hw(cp);
1016
1017 cpw8_f (Cfg9346, Cfg9346_Unlock);
1018
1019 /* Restore our idea of the MAC address. */
1020 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1021 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1022
1023 cp_start_hw(cp);
1024 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1025
1026 __cp_set_rx_mode(dev);
1027 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1028
1029 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1030 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1031 cpw8(Config3, PARMEnable);
1032 cp->wol_enabled = 0;
1033
1034 cpw8(Config5, cpr8(Config5) & PMEStatus);
1035
1036 cpw32_f(HiTxRingAddr, 0);
1037 cpw32_f(HiTxRingAddr + 4, 0);
1038
1039 ring_dma = cp->ring_dma;
1040 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1041 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1042
1043 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1044 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1045 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1046
1047 cpw16(MultiIntr, 0);
1048
1049 cpw16_f(IntrMask, cp_intr_mask);
1050
1051 cpw8_f(Cfg9346, Cfg9346_Lock);
1052 }
1053
1054 static int cp_refill_rx (struct cp_private *cp)
1055 {
1056 unsigned i;
1057
1058 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1059 struct sk_buff *skb;
1060 dma_addr_t mapping;
1061
1062 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1063 if (!skb)
1064 goto err_out;
1065
1066 skb_reserve(skb, RX_OFFSET);
1067
1068 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1069 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1070 cp->rx_skb[i] = skb;
1071
1072 cp->rx_ring[i].opts2 = 0;
1073 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1074 if (i == (CP_RX_RING_SIZE - 1))
1075 cp->rx_ring[i].opts1 =
1076 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1077 else
1078 cp->rx_ring[i].opts1 =
1079 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1080 }
1081
1082 return 0;
1083
1084 err_out:
1085 cp_clean_rings(cp);
1086 return -ENOMEM;
1087 }
1088
1089 static void cp_init_rings_index (struct cp_private *cp)
1090 {
1091 cp->rx_tail = 0;
1092 cp->tx_head = cp->tx_tail = 0;
1093 }
1094
1095 static int cp_init_rings (struct cp_private *cp)
1096 {
1097 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1098 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1099
1100 cp_init_rings_index(cp);
1101
1102 return cp_refill_rx (cp);
1103 }
1104
1105 static int cp_alloc_rings (struct cp_private *cp)
1106 {
1107 void *mem;
1108
1109 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1110 &cp->ring_dma, GFP_KERNEL);
1111 if (!mem)
1112 return -ENOMEM;
1113
1114 cp->rx_ring = mem;
1115 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1116
1117 return cp_init_rings(cp);
1118 }
1119
1120 static void cp_clean_rings (struct cp_private *cp)
1121 {
1122 struct cp_desc *desc;
1123 unsigned i;
1124
1125 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1126 if (cp->rx_skb[i]) {
1127 desc = cp->rx_ring + i;
1128 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1129 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1130 dev_kfree_skb(cp->rx_skb[i]);
1131 }
1132 }
1133
1134 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1135 if (cp->tx_skb[i]) {
1136 struct sk_buff *skb = cp->tx_skb[i];
1137
1138 desc = cp->tx_ring + i;
1139 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1140 le32_to_cpu(desc->opts1) & 0xffff,
1141 PCI_DMA_TODEVICE);
1142 if (le32_to_cpu(desc->opts1) & LastFrag)
1143 dev_kfree_skb(skb);
1144 cp->dev->stats.tx_dropped++;
1145 }
1146 }
1147
1148 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1149 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1150
1151 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1152 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1153 }
1154
1155 static void cp_free_rings (struct cp_private *cp)
1156 {
1157 cp_clean_rings(cp);
1158 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1159 cp->ring_dma);
1160 cp->rx_ring = NULL;
1161 cp->tx_ring = NULL;
1162 }
1163
1164 static int cp_open (struct net_device *dev)
1165 {
1166 struct cp_private *cp = netdev_priv(dev);
1167 int rc;
1168
1169 if (netif_msg_ifup(cp))
1170 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1171
1172 rc = cp_alloc_rings(cp);
1173 if (rc)
1174 return rc;
1175
1176 napi_enable(&cp->napi);
1177
1178 cp_init_hw(cp);
1179
1180 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1181 if (rc)
1182 goto err_out_hw;
1183
1184 netif_carrier_off(dev);
1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1186 netif_start_queue(dev);
1187
1188 return 0;
1189
1190 err_out_hw:
1191 napi_disable(&cp->napi);
1192 cp_stop_hw(cp);
1193 cp_free_rings(cp);
1194 return rc;
1195 }
1196
1197 static int cp_close (struct net_device *dev)
1198 {
1199 struct cp_private *cp = netdev_priv(dev);
1200 unsigned long flags;
1201
1202 napi_disable(&cp->napi);
1203
1204 if (netif_msg_ifdown(cp))
1205 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1206
1207 spin_lock_irqsave(&cp->lock, flags);
1208
1209 netif_stop_queue(dev);
1210 netif_carrier_off(dev);
1211
1212 cp_stop_hw(cp);
1213
1214 spin_unlock_irqrestore(&cp->lock, flags);
1215
1216 synchronize_irq(dev->irq);
1217 free_irq(dev->irq, dev);
1218
1219 cp_free_rings(cp);
1220 return 0;
1221 }
1222
1223 static void cp_tx_timeout(struct net_device *dev)
1224 {
1225 struct cp_private *cp = netdev_priv(dev);
1226 unsigned long flags;
1227 int rc;
1228
1229 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1230 dev->name, cpr8(Cmd), cpr16(CpCmd),
1231 cpr16(IntrStatus), cpr16(IntrMask));
1232
1233 spin_lock_irqsave(&cp->lock, flags);
1234
1235 cp_stop_hw(cp);
1236 cp_clean_rings(cp);
1237 rc = cp_init_rings(cp);
1238 cp_start_hw(cp);
1239
1240 netif_wake_queue(dev);
1241
1242 spin_unlock_irqrestore(&cp->lock, flags);
1243
1244 return;
1245 }
1246
1247 #ifdef BROKEN
1248 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1249 {
1250 struct cp_private *cp = netdev_priv(dev);
1251 int rc;
1252 unsigned long flags;
1253
1254 /* check for invalid MTU, according to hardware limits */
1255 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1256 return -EINVAL;
1257
1258 /* if network interface not up, no need for complexity */
1259 if (!netif_running(dev)) {
1260 dev->mtu = new_mtu;
1261 cp_set_rxbufsize(cp); /* set new rx buf size */
1262 return 0;
1263 }
1264
1265 spin_lock_irqsave(&cp->lock, flags);
1266
1267 cp_stop_hw(cp); /* stop h/w and free rings */
1268 cp_clean_rings(cp);
1269
1270 dev->mtu = new_mtu;
1271 cp_set_rxbufsize(cp); /* set new rx buf size */
1272
1273 rc = cp_init_rings(cp); /* realloc and restart h/w */
1274 cp_start_hw(cp);
1275
1276 spin_unlock_irqrestore(&cp->lock, flags);
1277
1278 return rc;
1279 }
1280 #endif /* BROKEN */
1281
1282 static const char mii_2_8139_map[8] = {
1283 BasicModeCtrl,
1284 BasicModeStatus,
1285 0,
1286 0,
1287 NWayAdvert,
1288 NWayLPAR,
1289 NWayExpansion,
1290 0
1291 };
1292
1293 static int mdio_read(struct net_device *dev, int phy_id, int location)
1294 {
1295 struct cp_private *cp = netdev_priv(dev);
1296
1297 return location < 8 && mii_2_8139_map[location] ?
1298 readw(cp->regs + mii_2_8139_map[location]) : 0;
1299 }
1300
1301
1302 static void mdio_write(struct net_device *dev, int phy_id, int location,
1303 int value)
1304 {
1305 struct cp_private *cp = netdev_priv(dev);
1306
1307 if (location == 0) {
1308 cpw8(Cfg9346, Cfg9346_Unlock);
1309 cpw16(BasicModeCtrl, value);
1310 cpw8(Cfg9346, Cfg9346_Lock);
1311 } else if (location < 8 && mii_2_8139_map[location])
1312 cpw16(mii_2_8139_map[location], value);
1313 }
1314
1315 /* Set the ethtool Wake-on-LAN settings */
1316 static int netdev_set_wol (struct cp_private *cp,
1317 const struct ethtool_wolinfo *wol)
1318 {
1319 u8 options;
1320
1321 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1322 /* If WOL is being disabled, no need for complexity */
1323 if (wol->wolopts) {
1324 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1325 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1326 }
1327
1328 cpw8 (Cfg9346, Cfg9346_Unlock);
1329 cpw8 (Config3, options);
1330 cpw8 (Cfg9346, Cfg9346_Lock);
1331
1332 options = 0; /* Paranoia setting */
1333 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1334 /* If WOL is being disabled, no need for complexity */
1335 if (wol->wolopts) {
1336 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1337 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1338 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1339 }
1340
1341 cpw8 (Config5, options);
1342
1343 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1344
1345 return 0;
1346 }
1347
1348 /* Get the ethtool Wake-on-LAN settings */
1349 static void netdev_get_wol (struct cp_private *cp,
1350 struct ethtool_wolinfo *wol)
1351 {
1352 u8 options;
1353
1354 wol->wolopts = 0; /* Start from scratch */
1355 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1356 WAKE_MCAST | WAKE_UCAST;
1357 /* We don't need to go on if WOL is disabled */
1358 if (!cp->wol_enabled) return;
1359
1360 options = cpr8 (Config3);
1361 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1362 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1363
1364 options = 0; /* Paranoia setting */
1365 options = cpr8 (Config5);
1366 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1367 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1368 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1369 }
1370
1371 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1372 {
1373 struct cp_private *cp = netdev_priv(dev);
1374
1375 strcpy (info->driver, DRV_NAME);
1376 strcpy (info->version, DRV_VERSION);
1377 strcpy (info->bus_info, pci_name(cp->pdev));
1378 }
1379
1380 static int cp_get_regs_len(struct net_device *dev)
1381 {
1382 return CP_REGS_SIZE;
1383 }
1384
1385 static int cp_get_sset_count (struct net_device *dev, int sset)
1386 {
1387 switch (sset) {
1388 case ETH_SS_STATS:
1389 return CP_NUM_STATS;
1390 default:
1391 return -EOPNOTSUPP;
1392 }
1393 }
1394
1395 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1396 {
1397 struct cp_private *cp = netdev_priv(dev);
1398 int rc;
1399 unsigned long flags;
1400
1401 spin_lock_irqsave(&cp->lock, flags);
1402 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1403 spin_unlock_irqrestore(&cp->lock, flags);
1404
1405 return rc;
1406 }
1407
1408 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1409 {
1410 struct cp_private *cp = netdev_priv(dev);
1411 int rc;
1412 unsigned long flags;
1413
1414 spin_lock_irqsave(&cp->lock, flags);
1415 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1416 spin_unlock_irqrestore(&cp->lock, flags);
1417
1418 return rc;
1419 }
1420
1421 static int cp_nway_reset(struct net_device *dev)
1422 {
1423 struct cp_private *cp = netdev_priv(dev);
1424 return mii_nway_restart(&cp->mii_if);
1425 }
1426
1427 static u32 cp_get_msglevel(struct net_device *dev)
1428 {
1429 struct cp_private *cp = netdev_priv(dev);
1430 return cp->msg_enable;
1431 }
1432
1433 static void cp_set_msglevel(struct net_device *dev, u32 value)
1434 {
1435 struct cp_private *cp = netdev_priv(dev);
1436 cp->msg_enable = value;
1437 }
1438
1439 static u32 cp_get_rx_csum(struct net_device *dev)
1440 {
1441 struct cp_private *cp = netdev_priv(dev);
1442 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1443 }
1444
1445 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1446 {
1447 struct cp_private *cp = netdev_priv(dev);
1448 u16 cmd = cp->cpcmd, newcmd;
1449
1450 newcmd = cmd;
1451
1452 if (data)
1453 newcmd |= RxChkSum;
1454 else
1455 newcmd &= ~RxChkSum;
1456
1457 if (newcmd != cmd) {
1458 unsigned long flags;
1459
1460 spin_lock_irqsave(&cp->lock, flags);
1461 cp->cpcmd = newcmd;
1462 cpw16_f(CpCmd, newcmd);
1463 spin_unlock_irqrestore(&cp->lock, flags);
1464 }
1465
1466 return 0;
1467 }
1468
1469 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1470 void *p)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474
1475 if (regs->len < CP_REGS_SIZE)
1476 return /* -EINVAL */;
1477
1478 regs->version = CP_REGS_VER;
1479
1480 spin_lock_irqsave(&cp->lock, flags);
1481 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1482 spin_unlock_irqrestore(&cp->lock, flags);
1483 }
1484
1485 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1486 {
1487 struct cp_private *cp = netdev_priv(dev);
1488 unsigned long flags;
1489
1490 spin_lock_irqsave (&cp->lock, flags);
1491 netdev_get_wol (cp, wol);
1492 spin_unlock_irqrestore (&cp->lock, flags);
1493 }
1494
1495 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1496 {
1497 struct cp_private *cp = netdev_priv(dev);
1498 unsigned long flags;
1499 int rc;
1500
1501 spin_lock_irqsave (&cp->lock, flags);
1502 rc = netdev_set_wol (cp, wol);
1503 spin_unlock_irqrestore (&cp->lock, flags);
1504
1505 return rc;
1506 }
1507
1508 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1509 {
1510 switch (stringset) {
1511 case ETH_SS_STATS:
1512 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1513 break;
1514 default:
1515 BUG();
1516 break;
1517 }
1518 }
1519
1520 static void cp_get_ethtool_stats (struct net_device *dev,
1521 struct ethtool_stats *estats, u64 *tmp_stats)
1522 {
1523 struct cp_private *cp = netdev_priv(dev);
1524 struct cp_dma_stats *nic_stats;
1525 dma_addr_t dma;
1526 int i;
1527
1528 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1529 &dma, GFP_KERNEL);
1530 if (!nic_stats)
1531 return;
1532
1533 /* begin NIC statistics dump */
1534 cpw32(StatsAddr + 4, (u64)dma >> 32);
1535 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1536 cpr32(StatsAddr);
1537
1538 for (i = 0; i < 1000; i++) {
1539 if ((cpr32(StatsAddr) & DumpStats) == 0)
1540 break;
1541 udelay(10);
1542 }
1543 cpw32(StatsAddr, 0);
1544 cpw32(StatsAddr + 4, 0);
1545 cpr32(StatsAddr);
1546
1547 i = 0;
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1555 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1556 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1557 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1558 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1559 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1560 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1561 tmp_stats[i++] = cp->cp_stats.rx_frags;
1562 BUG_ON(i != CP_NUM_STATS);
1563
1564 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1565 }
1566
1567 static const struct ethtool_ops cp_ethtool_ops = {
1568 .get_drvinfo = cp_get_drvinfo,
1569 .get_regs_len = cp_get_regs_len,
1570 .get_sset_count = cp_get_sset_count,
1571 .get_settings = cp_get_settings,
1572 .set_settings = cp_set_settings,
1573 .nway_reset = cp_nway_reset,
1574 .get_link = ethtool_op_get_link,
1575 .get_msglevel = cp_get_msglevel,
1576 .set_msglevel = cp_set_msglevel,
1577 .get_rx_csum = cp_get_rx_csum,
1578 .set_rx_csum = cp_set_rx_csum,
1579 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1580 .set_sg = ethtool_op_set_sg,
1581 .set_tso = ethtool_op_set_tso,
1582 .get_regs = cp_get_regs,
1583 .get_wol = cp_get_wol,
1584 .set_wol = cp_set_wol,
1585 .get_strings = cp_get_strings,
1586 .get_ethtool_stats = cp_get_ethtool_stats,
1587 .get_eeprom_len = cp_get_eeprom_len,
1588 .get_eeprom = cp_get_eeprom,
1589 .set_eeprom = cp_set_eeprom,
1590 };
1591
1592 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1593 {
1594 struct cp_private *cp = netdev_priv(dev);
1595 int rc;
1596 unsigned long flags;
1597
1598 if (!netif_running(dev))
1599 return -EINVAL;
1600
1601 spin_lock_irqsave(&cp->lock, flags);
1602 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1603 spin_unlock_irqrestore(&cp->lock, flags);
1604 return rc;
1605 }
1606
1607 /* Serial EEPROM section. */
1608
1609 /* EEPROM_Ctrl bits. */
1610 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1611 #define EE_CS 0x08 /* EEPROM chip select. */
1612 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1613 #define EE_WRITE_0 0x00
1614 #define EE_WRITE_1 0x02
1615 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1616 #define EE_ENB (0x80 | EE_CS)
1617
1618 /* Delay between EEPROM clock transitions.
1619 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1620 */
1621
1622 #define eeprom_delay() readl(ee_addr)
1623
1624 /* The EEPROM commands include the alway-set leading bit. */
1625 #define EE_EXTEND_CMD (4)
1626 #define EE_WRITE_CMD (5)
1627 #define EE_READ_CMD (6)
1628 #define EE_ERASE_CMD (7)
1629
1630 #define EE_EWDS_ADDR (0)
1631 #define EE_WRAL_ADDR (1)
1632 #define EE_ERAL_ADDR (2)
1633 #define EE_EWEN_ADDR (3)
1634
1635 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1636
1637 static void eeprom_cmd_start(void __iomem *ee_addr)
1638 {
1639 writeb (EE_ENB & ~EE_CS, ee_addr);
1640 writeb (EE_ENB, ee_addr);
1641 eeprom_delay ();
1642 }
1643
1644 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1645 {
1646 int i;
1647
1648 /* Shift the command bits out. */
1649 for (i = cmd_len - 1; i >= 0; i--) {
1650 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1651 writeb (EE_ENB | dataval, ee_addr);
1652 eeprom_delay ();
1653 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1654 eeprom_delay ();
1655 }
1656 writeb (EE_ENB, ee_addr);
1657 eeprom_delay ();
1658 }
1659
1660 static void eeprom_cmd_end(void __iomem *ee_addr)
1661 {
1662 writeb (~EE_CS, ee_addr);
1663 eeprom_delay ();
1664 }
1665
1666 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1667 int addr_len)
1668 {
1669 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1670
1671 eeprom_cmd_start(ee_addr);
1672 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1673 eeprom_cmd_end(ee_addr);
1674 }
1675
1676 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1677 {
1678 int i;
1679 u16 retval = 0;
1680 void __iomem *ee_addr = ioaddr + Cfg9346;
1681 int read_cmd = location | (EE_READ_CMD << addr_len);
1682
1683 eeprom_cmd_start(ee_addr);
1684 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1685
1686 for (i = 16; i > 0; i--) {
1687 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1688 eeprom_delay ();
1689 retval =
1690 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1691 0);
1692 writeb (EE_ENB, ee_addr);
1693 eeprom_delay ();
1694 }
1695
1696 eeprom_cmd_end(ee_addr);
1697
1698 return retval;
1699 }
1700
1701 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1702 int addr_len)
1703 {
1704 int i;
1705 void __iomem *ee_addr = ioaddr + Cfg9346;
1706 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1707
1708 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1709
1710 eeprom_cmd_start(ee_addr);
1711 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1712 eeprom_cmd(ee_addr, val, 16);
1713 eeprom_cmd_end(ee_addr);
1714
1715 eeprom_cmd_start(ee_addr);
1716 for (i = 0; i < 20000; i++)
1717 if (readb(ee_addr) & EE_DATA_READ)
1718 break;
1719 eeprom_cmd_end(ee_addr);
1720
1721 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1722 }
1723
1724 static int cp_get_eeprom_len(struct net_device *dev)
1725 {
1726 struct cp_private *cp = netdev_priv(dev);
1727 int size;
1728
1729 spin_lock_irq(&cp->lock);
1730 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1731 spin_unlock_irq(&cp->lock);
1732
1733 return size;
1734 }
1735
1736 static int cp_get_eeprom(struct net_device *dev,
1737 struct ethtool_eeprom *eeprom, u8 *data)
1738 {
1739 struct cp_private *cp = netdev_priv(dev);
1740 unsigned int addr_len;
1741 u16 val;
1742 u32 offset = eeprom->offset >> 1;
1743 u32 len = eeprom->len;
1744 u32 i = 0;
1745
1746 eeprom->magic = CP_EEPROM_MAGIC;
1747
1748 spin_lock_irq(&cp->lock);
1749
1750 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1751
1752 if (eeprom->offset & 1) {
1753 val = read_eeprom(cp->regs, offset, addr_len);
1754 data[i++] = (u8)(val >> 8);
1755 offset++;
1756 }
1757
1758 while (i < len - 1) {
1759 val = read_eeprom(cp->regs, offset, addr_len);
1760 data[i++] = (u8)val;
1761 data[i++] = (u8)(val >> 8);
1762 offset++;
1763 }
1764
1765 if (i < len) {
1766 val = read_eeprom(cp->regs, offset, addr_len);
1767 data[i] = (u8)val;
1768 }
1769
1770 spin_unlock_irq(&cp->lock);
1771 return 0;
1772 }
1773
1774 static int cp_set_eeprom(struct net_device *dev,
1775 struct ethtool_eeprom *eeprom, u8 *data)
1776 {
1777 struct cp_private *cp = netdev_priv(dev);
1778 unsigned int addr_len;
1779 u16 val;
1780 u32 offset = eeprom->offset >> 1;
1781 u32 len = eeprom->len;
1782 u32 i = 0;
1783
1784 if (eeprom->magic != CP_EEPROM_MAGIC)
1785 return -EINVAL;
1786
1787 spin_lock_irq(&cp->lock);
1788
1789 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1790
1791 if (eeprom->offset & 1) {
1792 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1793 val |= (u16)data[i++] << 8;
1794 write_eeprom(cp->regs, offset, val, addr_len);
1795 offset++;
1796 }
1797
1798 while (i < len - 1) {
1799 val = (u16)data[i++];
1800 val |= (u16)data[i++] << 8;
1801 write_eeprom(cp->regs, offset, val, addr_len);
1802 offset++;
1803 }
1804
1805 if (i < len) {
1806 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1807 val |= (u16)data[i];
1808 write_eeprom(cp->regs, offset, val, addr_len);
1809 }
1810
1811 spin_unlock_irq(&cp->lock);
1812 return 0;
1813 }
1814
1815 /* Put the board into D3cold state and wait for WakeUp signal */
1816 static void cp_set_d3_state (struct cp_private *cp)
1817 {
1818 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1819 pci_set_power_state (cp->pdev, PCI_D3hot);
1820 }
1821
1822 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1823 {
1824 struct net_device *dev;
1825 struct cp_private *cp;
1826 int rc;
1827 void __iomem *regs;
1828 resource_size_t pciaddr;
1829 unsigned int addr_len, i, pci_using_dac;
1830 DECLARE_MAC_BUF(mac);
1831
1832 #ifndef MODULE
1833 static int version_printed;
1834 if (version_printed++ == 0)
1835 printk("%s", version);
1836 #endif
1837
1838 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1839 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1840 dev_err(&pdev->dev,
1841 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1842 pdev->vendor, pdev->device, pdev->revision);
1843 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1844 return -ENODEV;
1845 }
1846
1847 dev = alloc_etherdev(sizeof(struct cp_private));
1848 if (!dev)
1849 return -ENOMEM;
1850 SET_NETDEV_DEV(dev, &pdev->dev);
1851
1852 cp = netdev_priv(dev);
1853 cp->pdev = pdev;
1854 cp->dev = dev;
1855 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1856 spin_lock_init (&cp->lock);
1857 cp->mii_if.dev = dev;
1858 cp->mii_if.mdio_read = mdio_read;
1859 cp->mii_if.mdio_write = mdio_write;
1860 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1861 cp->mii_if.phy_id_mask = 0x1f;
1862 cp->mii_if.reg_num_mask = 0x1f;
1863 cp_set_rxbufsize(cp);
1864
1865 rc = pci_enable_device(pdev);
1866 if (rc)
1867 goto err_out_free;
1868
1869 rc = pci_set_mwi(pdev);
1870 if (rc)
1871 goto err_out_disable;
1872
1873 rc = pci_request_regions(pdev, DRV_NAME);
1874 if (rc)
1875 goto err_out_mwi;
1876
1877 pciaddr = pci_resource_start(pdev, 1);
1878 if (!pciaddr) {
1879 rc = -EIO;
1880 dev_err(&pdev->dev, "no MMIO resource\n");
1881 goto err_out_res;
1882 }
1883 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1884 rc = -EIO;
1885 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1886 (unsigned long long)pci_resource_len(pdev, 1));
1887 goto err_out_res;
1888 }
1889
1890 /* Configure DMA attributes. */
1891 if ((sizeof(dma_addr_t) > 4) &&
1892 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1893 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1894 pci_using_dac = 1;
1895 } else {
1896 pci_using_dac = 0;
1897
1898 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1899 if (rc) {
1900 dev_err(&pdev->dev,
1901 "No usable DMA configuration, aborting.\n");
1902 goto err_out_res;
1903 }
1904 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1905 if (rc) {
1906 dev_err(&pdev->dev,
1907 "No usable consistent DMA configuration, "
1908 "aborting.\n");
1909 goto err_out_res;
1910 }
1911 }
1912
1913 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1914 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1915
1916 regs = ioremap(pciaddr, CP_REGS_SIZE);
1917 if (!regs) {
1918 rc = -EIO;
1919 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1920 (unsigned long long)pci_resource_len(pdev, 1),
1921 (unsigned long long)pciaddr);
1922 goto err_out_res;
1923 }
1924 dev->base_addr = (unsigned long) regs;
1925 cp->regs = regs;
1926
1927 cp_stop_hw(cp);
1928
1929 /* read MAC address from EEPROM */
1930 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1931 for (i = 0; i < 3; i++)
1932 ((__le16 *) (dev->dev_addr))[i] =
1933 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1934 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1935
1936 dev->open = cp_open;
1937 dev->stop = cp_close;
1938 dev->set_multicast_list = cp_set_rx_mode;
1939 dev->hard_start_xmit = cp_start_xmit;
1940 dev->get_stats = cp_get_stats;
1941 dev->do_ioctl = cp_ioctl;
1942 #ifdef CONFIG_NET_POLL_CONTROLLER
1943 dev->poll_controller = cp_poll_controller;
1944 #endif
1945 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1946 #ifdef BROKEN
1947 dev->change_mtu = cp_change_mtu;
1948 #endif
1949 dev->ethtool_ops = &cp_ethtool_ops;
1950 dev->tx_timeout = cp_tx_timeout;
1951 dev->watchdog_timeo = TX_TIMEOUT;
1952
1953 #if CP_VLAN_TAG_USED
1954 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1955 dev->vlan_rx_register = cp_vlan_rx_register;
1956 #endif
1957
1958 if (pci_using_dac)
1959 dev->features |= NETIF_F_HIGHDMA;
1960
1961 #if 0 /* disabled by default until verified */
1962 dev->features |= NETIF_F_TSO;
1963 #endif
1964
1965 dev->irq = pdev->irq;
1966
1967 rc = register_netdev(dev);
1968 if (rc)
1969 goto err_out_iomap;
1970
1971 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1972 "%s, IRQ %d\n",
1973 dev->name,
1974 dev->base_addr,
1975 print_mac(mac, dev->dev_addr),
1976 dev->irq);
1977
1978 pci_set_drvdata(pdev, dev);
1979
1980 /* enable busmastering and memory-write-invalidate */
1981 pci_set_master(pdev);
1982
1983 if (cp->wol_enabled)
1984 cp_set_d3_state (cp);
1985
1986 return 0;
1987
1988 err_out_iomap:
1989 iounmap(regs);
1990 err_out_res:
1991 pci_release_regions(pdev);
1992 err_out_mwi:
1993 pci_clear_mwi(pdev);
1994 err_out_disable:
1995 pci_disable_device(pdev);
1996 err_out_free:
1997 free_netdev(dev);
1998 return rc;
1999 }
2000
2001 static void cp_remove_one (struct pci_dev *pdev)
2002 {
2003 struct net_device *dev = pci_get_drvdata(pdev);
2004 struct cp_private *cp = netdev_priv(dev);
2005
2006 unregister_netdev(dev);
2007 iounmap(cp->regs);
2008 if (cp->wol_enabled)
2009 pci_set_power_state (pdev, PCI_D0);
2010 pci_release_regions(pdev);
2011 pci_clear_mwi(pdev);
2012 pci_disable_device(pdev);
2013 pci_set_drvdata(pdev, NULL);
2014 free_netdev(dev);
2015 }
2016
2017 #ifdef CONFIG_PM
2018 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2019 {
2020 struct net_device *dev = pci_get_drvdata(pdev);
2021 struct cp_private *cp = netdev_priv(dev);
2022 unsigned long flags;
2023
2024 if (!netif_running(dev))
2025 return 0;
2026
2027 netif_device_detach (dev);
2028 netif_stop_queue (dev);
2029
2030 spin_lock_irqsave (&cp->lock, flags);
2031
2032 /* Disable Rx and Tx */
2033 cpw16 (IntrMask, 0);
2034 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2035
2036 spin_unlock_irqrestore (&cp->lock, flags);
2037
2038 pci_save_state(pdev);
2039 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2040 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2041
2042 return 0;
2043 }
2044
2045 static int cp_resume (struct pci_dev *pdev)
2046 {
2047 struct net_device *dev = pci_get_drvdata (pdev);
2048 struct cp_private *cp = netdev_priv(dev);
2049 unsigned long flags;
2050
2051 if (!netif_running(dev))
2052 return 0;
2053
2054 netif_device_attach (dev);
2055
2056 pci_set_power_state(pdev, PCI_D0);
2057 pci_restore_state(pdev);
2058 pci_enable_wake(pdev, PCI_D0, 0);
2059
2060 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2061 cp_init_rings_index (cp);
2062 cp_init_hw (cp);
2063 netif_start_queue (dev);
2064
2065 spin_lock_irqsave (&cp->lock, flags);
2066
2067 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2068
2069 spin_unlock_irqrestore (&cp->lock, flags);
2070
2071 return 0;
2072 }
2073 #endif /* CONFIG_PM */
2074
2075 static struct pci_driver cp_driver = {
2076 .name = DRV_NAME,
2077 .id_table = cp_pci_tbl,
2078 .probe = cp_init_one,
2079 .remove = cp_remove_one,
2080 #ifdef CONFIG_PM
2081 .resume = cp_resume,
2082 .suspend = cp_suspend,
2083 #endif
2084 };
2085
2086 static int __init cp_init (void)
2087 {
2088 #ifdef MODULE
2089 printk("%s", version);
2090 #endif
2091 return pci_register_driver(&cp_driver);
2092 }
2093
2094 static void __exit cp_exit (void)
2095 {
2096 pci_unregister_driver (&cp_driver);
2097 }
2098
2099 module_init(cp_init);
2100 module_exit(cp_exit);
Linux kernel - Deliverables
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