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[PATCH] Updated ipw2200 to compile with ieee80211 abg_ture to abg_true change
[deliverable/linux.git] / drivers / net / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/if_vlan.h>
69 #include <linux/crc32.h>
70 #include <linux/in.h>
71 #include <linux/ip.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/cache.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/uaccess.h>
78
79 /* VLAN tagging feature enable/disable */
80 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81 #define CP_VLAN_TAG_USED 1
82 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #else
85 #define CP_VLAN_TAG_USED 0
86 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88 #endif
89
90 /* These identify the driver base version and may not be removed. */
91 static char version[] =
92 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96 MODULE_VERSION(DRV_VERSION);
97 MODULE_LICENSE("GPL");
98
99 static int debug = -1;
100 module_param(debug, int, 0);
101 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105 static int multicast_filter_limit = 32;
106 module_param(multicast_filter_limit, int, 0);
107 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109 #define PFX DRV_NAME ": "
110
111 #ifndef TRUE
112 #define FALSE 0
113 #define TRUE (!FALSE)
114 #endif
115
116 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
117 NETIF_MSG_PROBE | \
118 NETIF_MSG_LINK)
119 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
120 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
121 #define CP_REGS_SIZE (0xff + 1)
122 #define CP_REGS_VER 1 /* version 1 */
123 #define CP_RX_RING_SIZE 64
124 #define CP_TX_RING_SIZE 64
125 #define CP_RING_BYTES \
126 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
127 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 CP_STATS_SIZE)
129 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
130 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
131 #define TX_BUFFS_AVAIL(CP) \
132 (((CP)->tx_tail <= (CP)->tx_head) ? \
133 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
134 (CP)->tx_tail - (CP)->tx_head - 1)
135
136 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define RX_OFFSET 2
138 #define CP_INTERNAL_PHY 32
139
140 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
141 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
142 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
143 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
144 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145
146 /* Time in jiffies before concluding the transmitter is hung. */
147 #define TX_TIMEOUT (6*HZ)
148
149 /* hardware minimum and maximum for a single frame's data payload */
150 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
151 #define CP_MAX_MTU 4096
152
153 enum {
154 /* NIC register offsets */
155 MAC0 = 0x00, /* Ethernet hardware address. */
156 MAR0 = 0x08, /* Multicast filter. */
157 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
158 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
159 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
160 Cmd = 0x37, /* Command register */
161 IntrMask = 0x3C, /* Interrupt mask */
162 IntrStatus = 0x3E, /* Interrupt status */
163 TxConfig = 0x40, /* Tx configuration */
164 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
165 RxConfig = 0x44, /* Rx configuration */
166 RxMissed = 0x4C, /* 24 bits valid, write clears */
167 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
168 Config1 = 0x52, /* Config1 */
169 Config3 = 0x59, /* Config3 */
170 Config4 = 0x5A, /* Config4 */
171 MultiIntr = 0x5C, /* Multiple interrupt select */
172 BasicModeCtrl = 0x62, /* MII BMCR */
173 BasicModeStatus = 0x64, /* MII BMSR */
174 NWayAdvert = 0x66, /* MII ADVERTISE */
175 NWayLPAR = 0x68, /* MII LPA */
176 NWayExpansion = 0x6A, /* MII Expansion */
177 Config5 = 0xD8, /* Config5 */
178 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
179 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
180 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
181 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
182 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
183 TxThresh = 0xEC, /* Early Tx threshold */
184 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
185 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186
187 /* Tx and Rx status descriptors */
188 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
189 RingEnd = (1 << 30), /* End of descriptor ring */
190 FirstFrag = (1 << 29), /* First segment of a packet */
191 LastFrag = (1 << 28), /* Final segment of a packet */
192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
195 TxError = (1 << 23), /* Tx error summary */
196 RxError = (1 << 20), /* Rx error summary */
197 IPCS = (1 << 18), /* Calculate IP checksum */
198 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
199 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
200 TxVlanTag = (1 << 17), /* Add VLAN tag */
201 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
202 IPFail = (1 << 15), /* IP checksum failed */
203 UDPFail = (1 << 14), /* UDP/IP checksum failed */
204 TCPFail = (1 << 13), /* TCP/IP checksum failed */
205 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
206 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
207 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 RxProtoTCP = 1,
209 RxProtoUDP = 2,
210 RxProtoIP = 3,
211 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
212 TxOWC = (1 << 22), /* Tx Out-of-window collision */
213 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
214 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
215 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
216 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
217 RxErrFrame = (1 << 27), /* Rx frame alignment error */
218 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
219 RxErrCRC = (1 << 18), /* Rx CRC error */
220 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
221 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
222 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223
224 /* StatsAddr register */
225 DumpStats = (1 << 3), /* Begin stats dump */
226
227 /* RxConfig register */
228 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
229 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
230 AcceptErr = 0x20, /* Accept packets with CRC errors */
231 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
232 AcceptBroadcast = 0x08, /* Accept broadcast packets */
233 AcceptMulticast = 0x04, /* Accept multicast packets */
234 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
235 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236
237 /* IntrMask / IntrStatus registers */
238 PciErr = (1 << 15), /* System error on the PCI bus */
239 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
240 LenChg = (1 << 13), /* Cable length change */
241 SWInt = (1 << 8), /* Software-requested interrupt */
242 TxEmpty = (1 << 7), /* No Tx descriptors available */
243 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
244 LinkChg = (1 << 5), /* Packet underrun, or link change */
245 RxEmpty = (1 << 4), /* No Rx descriptors available */
246 TxErr = (1 << 3), /* Tx error */
247 TxOK = (1 << 2), /* Tx packet sent */
248 RxErr = (1 << 1), /* Rx error */
249 RxOK = (1 << 0), /* Rx packet received */
250 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
251 but hardware likes to raise it */
252
253 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
254 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
255 RxErr | RxOK | IntrResvd,
256
257 /* C mode command register */
258 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
259 RxOn = (1 << 3), /* Rx mode enable */
260 TxOn = (1 << 2), /* Tx mode enable */
261
262 /* C+ mode command register */
263 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
264 RxChkSum = (1 << 5), /* Rx checksum offload enable */
265 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
266 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
267 CpRxOn = (1 << 1), /* Rx mode enable */
268 CpTxOn = (1 << 0), /* Tx mode enable */
269
270 /* Cfg9436 EEPROM control register */
271 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
272 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273
274 /* TxConfig register */
275 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /* Early Tx Threshold register */
279 TxThreshMask = 0x3f, /* Mask bits 5-0 */
280 TxThreshMax = 2048, /* Max early Tx threshold */
281
282 /* Config1 register */
283 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
284 LWACT = (1 << 4), /* LWAKE active mode */
285 PMEnable = (1 << 0), /* Enable various PM features of chip */
286
287 /* Config3 register */
288 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
292 /* Config4 register */
293 LWPTN = (1 << 1), /* LWAKE Pattern */
294 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295
296 /* Config5 register */
297 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
298 MWF = (1 << 5), /* Accept Multicast wakeup frame */
299 UWF = (1 << 4), /* Accept Unicast wakeup frame */
300 LANWake = (1 << 1), /* Enable LANWake signal */
301 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302
303 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
304 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
305 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
306 };
307
308 static const unsigned int cp_rx_config =
309 (RX_FIFO_THRESH << RxCfgFIFOShift) |
310 (RX_DMA_BURST << RxCfgDMAShift);
311
312 struct cp_desc {
313 u32 opts1;
314 u32 opts2;
315 u64 addr;
316 };
317
318 struct ring_info {
319 struct sk_buff *skb;
320 dma_addr_t mapping;
321 u32 len;
322 };
323
324 struct cp_dma_stats {
325 u64 tx_ok;
326 u64 rx_ok;
327 u64 tx_err;
328 u32 rx_err;
329 u16 rx_fifo;
330 u16 frame_align;
331 u32 tx_ok_1col;
332 u32 tx_ok_mcol;
333 u64 rx_ok_phys;
334 u64 rx_ok_bcast;
335 u32 rx_ok_mcast;
336 u16 tx_abort;
337 u16 tx_underrun;
338 } __attribute__((packed));
339
340 struct cp_extra_stats {
341 unsigned long rx_frags;
342 };
343
344 struct cp_private {
345 void __iomem *regs;
346 struct net_device *dev;
347 spinlock_t lock;
348 u32 msg_enable;
349
350 struct pci_dev *pdev;
351 u32 rx_config;
352 u16 cpcmd;
353
354 struct net_device_stats net_stats;
355 struct cp_extra_stats cp_stats;
356 struct cp_dma_stats *nic_stats;
357 dma_addr_t nic_stats_dma;
358
359 unsigned rx_tail ____cacheline_aligned;
360 struct cp_desc *rx_ring;
361 struct ring_info rx_skb[CP_RX_RING_SIZE];
362 unsigned rx_buf_sz;
363
364 unsigned tx_head ____cacheline_aligned;
365 unsigned tx_tail;
366
367 struct cp_desc *tx_ring;
368 struct ring_info tx_skb[CP_TX_RING_SIZE];
369 dma_addr_t ring_dma;
370
371 #if CP_VLAN_TAG_USED
372 struct vlan_group *vlgrp;
373 #endif
374
375 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
376
377 struct mii_if_info mii_if;
378 };
379
380 #define cpr8(reg) readb(cp->regs + (reg))
381 #define cpr16(reg) readw(cp->regs + (reg))
382 #define cpr32(reg) readl(cp->regs + (reg))
383 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
384 #define cpw16(reg,val) writew((val), cp->regs + (reg))
385 #define cpw32(reg,val) writel((val), cp->regs + (reg))
386 #define cpw8_f(reg,val) do { \
387 writeb((val), cp->regs + (reg)); \
388 readb(cp->regs + (reg)); \
389 } while (0)
390 #define cpw16_f(reg,val) do { \
391 writew((val), cp->regs + (reg)); \
392 readw(cp->regs + (reg)); \
393 } while (0)
394 #define cpw32_f(reg,val) do { \
395 writel((val), cp->regs + (reg)); \
396 readl(cp->regs + (reg)); \
397 } while (0)
398
399
400 static void __cp_set_rx_mode (struct net_device *dev);
401 static void cp_tx (struct cp_private *cp);
402 static void cp_clean_rings (struct cp_private *cp);
403 #ifdef CONFIG_NET_POLL_CONTROLLER
404 static void cp_poll_controller(struct net_device *dev);
405 #endif
406
407 static struct pci_device_id cp_pci_tbl[] = {
408 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
410 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
412 { },
413 };
414 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
415
416 static struct {
417 const char str[ETH_GSTRING_LEN];
418 } ethtool_stats_keys[] = {
419 { "tx_ok" },
420 { "rx_ok" },
421 { "tx_err" },
422 { "rx_err" },
423 { "rx_fifo" },
424 { "frame_align" },
425 { "tx_ok_1col" },
426 { "tx_ok_mcol" },
427 { "rx_ok_phys" },
428 { "rx_ok_bcast" },
429 { "rx_ok_mcast" },
430 { "tx_abort" },
431 { "tx_underrun" },
432 { "rx_frags" },
433 };
434
435
436 #if CP_VLAN_TAG_USED
437 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
438 {
439 struct cp_private *cp = netdev_priv(dev);
440 unsigned long flags;
441
442 spin_lock_irqsave(&cp->lock, flags);
443 cp->vlgrp = grp;
444 cp->cpcmd |= RxVlanOn;
445 cpw16(CpCmd, cp->cpcmd);
446 spin_unlock_irqrestore(&cp->lock, flags);
447 }
448
449 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
450 {
451 struct cp_private *cp = netdev_priv(dev);
452 unsigned long flags;
453
454 spin_lock_irqsave(&cp->lock, flags);
455 cp->cpcmd &= ~RxVlanOn;
456 cpw16(CpCmd, cp->cpcmd);
457 if (cp->vlgrp)
458 cp->vlgrp->vlan_devices[vid] = NULL;
459 spin_unlock_irqrestore(&cp->lock, flags);
460 }
461 #endif /* CP_VLAN_TAG_USED */
462
463 static inline void cp_set_rxbufsize (struct cp_private *cp)
464 {
465 unsigned int mtu = cp->dev->mtu;
466
467 if (mtu > ETH_DATA_LEN)
468 /* MTU + ethernet header + FCS + optional VLAN tag */
469 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
470 else
471 cp->rx_buf_sz = PKT_BUF_SZ;
472 }
473
474 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
475 struct cp_desc *desc)
476 {
477 skb->protocol = eth_type_trans (skb, cp->dev);
478
479 cp->net_stats.rx_packets++;
480 cp->net_stats.rx_bytes += skb->len;
481 cp->dev->last_rx = jiffies;
482
483 #if CP_VLAN_TAG_USED
484 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
485 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
486 be16_to_cpu(desc->opts2 & 0xffff));
487 } else
488 #endif
489 netif_receive_skb(skb);
490 }
491
492 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
493 u32 status, u32 len)
494 {
495 if (netif_msg_rx_err (cp))
496 printk (KERN_DEBUG
497 "%s: rx err, slot %d status 0x%x len %d\n",
498 cp->dev->name, rx_tail, status, len);
499 cp->net_stats.rx_errors++;
500 if (status & RxErrFrame)
501 cp->net_stats.rx_frame_errors++;
502 if (status & RxErrCRC)
503 cp->net_stats.rx_crc_errors++;
504 if ((status & RxErrRunt) || (status & RxErrLong))
505 cp->net_stats.rx_length_errors++;
506 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
507 cp->net_stats.rx_length_errors++;
508 if (status & RxErrFIFO)
509 cp->net_stats.rx_fifo_errors++;
510 }
511
512 static inline unsigned int cp_rx_csum_ok (u32 status)
513 {
514 unsigned int protocol = (status >> 16) & 0x3;
515
516 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
517 return 1;
518 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
519 return 1;
520 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
521 return 1;
522 return 0;
523 }
524
525 static int cp_rx_poll (struct net_device *dev, int *budget)
526 {
527 struct cp_private *cp = netdev_priv(dev);
528 unsigned rx_tail = cp->rx_tail;
529 unsigned rx_work = dev->quota;
530 unsigned rx;
531
532 rx_status_loop:
533 rx = 0;
534 cpw16(IntrStatus, cp_rx_intr_mask);
535
536 while (1) {
537 u32 status, len;
538 dma_addr_t mapping;
539 struct sk_buff *skb, *new_skb;
540 struct cp_desc *desc;
541 unsigned buflen;
542
543 skb = cp->rx_skb[rx_tail].skb;
544 if (!skb)
545 BUG();
546
547 desc = &cp->rx_ring[rx_tail];
548 status = le32_to_cpu(desc->opts1);
549 if (status & DescOwn)
550 break;
551
552 len = (status & 0x1fff) - 4;
553 mapping = cp->rx_skb[rx_tail].mapping;
554
555 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
556 /* we don't support incoming fragmented frames.
557 * instead, we attempt to ensure that the
558 * pre-allocated RX skbs are properly sized such
559 * that RX fragments are never encountered
560 */
561 cp_rx_err_acct(cp, rx_tail, status, len);
562 cp->net_stats.rx_dropped++;
563 cp->cp_stats.rx_frags++;
564 goto rx_next;
565 }
566
567 if (status & (RxError | RxErrFIFO)) {
568 cp_rx_err_acct(cp, rx_tail, status, len);
569 goto rx_next;
570 }
571
572 if (netif_msg_rx_status(cp))
573 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
574 cp->dev->name, rx_tail, status, len);
575
576 buflen = cp->rx_buf_sz + RX_OFFSET;
577 new_skb = dev_alloc_skb (buflen);
578 if (!new_skb) {
579 cp->net_stats.rx_dropped++;
580 goto rx_next;
581 }
582
583 skb_reserve(new_skb, RX_OFFSET);
584 new_skb->dev = cp->dev;
585
586 pci_unmap_single(cp->pdev, mapping,
587 buflen, PCI_DMA_FROMDEVICE);
588
589 /* Handle checksum offloading for incoming packets. */
590 if (cp_rx_csum_ok(status))
591 skb->ip_summed = CHECKSUM_UNNECESSARY;
592 else
593 skb->ip_summed = CHECKSUM_NONE;
594
595 skb_put(skb, len);
596
597 mapping =
598 cp->rx_skb[rx_tail].mapping =
599 pci_map_single(cp->pdev, new_skb->data,
600 buflen, PCI_DMA_FROMDEVICE);
601 cp->rx_skb[rx_tail].skb = new_skb;
602
603 cp_rx_skb(cp, skb, desc);
604 rx++;
605
606 rx_next:
607 cp->rx_ring[rx_tail].opts2 = 0;
608 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
609 if (rx_tail == (CP_RX_RING_SIZE - 1))
610 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
611 cp->rx_buf_sz);
612 else
613 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
614 rx_tail = NEXT_RX(rx_tail);
615
616 if (!rx_work--)
617 break;
618 }
619
620 cp->rx_tail = rx_tail;
621
622 dev->quota -= rx;
623 *budget -= rx;
624
625 /* if we did not reach work limit, then we're done with
626 * this round of polling
627 */
628 if (rx_work) {
629 if (cpr16(IntrStatus) & cp_rx_intr_mask)
630 goto rx_status_loop;
631
632 local_irq_disable();
633 cpw16_f(IntrMask, cp_intr_mask);
634 __netif_rx_complete(dev);
635 local_irq_enable();
636
637 return 0; /* done */
638 }
639
640 return 1; /* not done */
641 }
642
643 static irqreturn_t
644 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
645 {
646 struct net_device *dev = dev_instance;
647 struct cp_private *cp;
648 u16 status;
649
650 if (unlikely(dev == NULL))
651 return IRQ_NONE;
652 cp = netdev_priv(dev);
653
654 status = cpr16(IntrStatus);
655 if (!status || (status == 0xFFFF))
656 return IRQ_NONE;
657
658 if (netif_msg_intr(cp))
659 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
660 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
661
662 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
663
664 spin_lock(&cp->lock);
665
666 /* close possible race's with dev_close */
667 if (unlikely(!netif_running(dev))) {
668 cpw16(IntrMask, 0);
669 spin_unlock(&cp->lock);
670 return IRQ_HANDLED;
671 }
672
673 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
674 if (netif_rx_schedule_prep(dev)) {
675 cpw16_f(IntrMask, cp_norx_intr_mask);
676 __netif_rx_schedule(dev);
677 }
678
679 if (status & (TxOK | TxErr | TxEmpty | SWInt))
680 cp_tx(cp);
681 if (status & LinkChg)
682 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
683
684 spin_unlock(&cp->lock);
685
686 if (status & PciErr) {
687 u16 pci_status;
688
689 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
690 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
691 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
692 dev->name, status, pci_status);
693
694 /* TODO: reset hardware */
695 }
696
697 return IRQ_HANDLED;
698 }
699
700 #ifdef CONFIG_NET_POLL_CONTROLLER
701 /*
702 * Polling receive - used by netconsole and other diagnostic tools
703 * to allow network i/o with interrupts disabled.
704 */
705 static void cp_poll_controller(struct net_device *dev)
706 {
707 disable_irq(dev->irq);
708 cp_interrupt(dev->irq, dev, NULL);
709 enable_irq(dev->irq);
710 }
711 #endif
712
713 static void cp_tx (struct cp_private *cp)
714 {
715 unsigned tx_head = cp->tx_head;
716 unsigned tx_tail = cp->tx_tail;
717
718 while (tx_tail != tx_head) {
719 struct sk_buff *skb;
720 u32 status;
721
722 rmb();
723 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
724 if (status & DescOwn)
725 break;
726
727 skb = cp->tx_skb[tx_tail].skb;
728 if (!skb)
729 BUG();
730
731 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
732 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
733
734 if (status & LastFrag) {
735 if (status & (TxError | TxFIFOUnder)) {
736 if (netif_msg_tx_err(cp))
737 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
738 cp->dev->name, status);
739 cp->net_stats.tx_errors++;
740 if (status & TxOWC)
741 cp->net_stats.tx_window_errors++;
742 if (status & TxMaxCol)
743 cp->net_stats.tx_aborted_errors++;
744 if (status & TxLinkFail)
745 cp->net_stats.tx_carrier_errors++;
746 if (status & TxFIFOUnder)
747 cp->net_stats.tx_fifo_errors++;
748 } else {
749 cp->net_stats.collisions +=
750 ((status >> TxColCntShift) & TxColCntMask);
751 cp->net_stats.tx_packets++;
752 cp->net_stats.tx_bytes += skb->len;
753 if (netif_msg_tx_done(cp))
754 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
755 }
756 dev_kfree_skb_irq(skb);
757 }
758
759 cp->tx_skb[tx_tail].skb = NULL;
760
761 tx_tail = NEXT_TX(tx_tail);
762 }
763
764 cp->tx_tail = tx_tail;
765
766 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
767 netif_wake_queue(cp->dev);
768 }
769
770 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
771 {
772 struct cp_private *cp = netdev_priv(dev);
773 unsigned entry;
774 u32 eor, flags;
775 #if CP_VLAN_TAG_USED
776 u32 vlan_tag = 0;
777 #endif
778 int mss = 0;
779
780 spin_lock_irq(&cp->lock);
781
782 /* This is a hard error, log it. */
783 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
784 netif_stop_queue(dev);
785 spin_unlock_irq(&cp->lock);
786 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
787 dev->name);
788 return 1;
789 }
790
791 #if CP_VLAN_TAG_USED
792 if (cp->vlgrp && vlan_tx_tag_present(skb))
793 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
794 #endif
795
796 entry = cp->tx_head;
797 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
798 if (dev->features & NETIF_F_TSO)
799 mss = skb_shinfo(skb)->tso_size;
800
801 if (skb_shinfo(skb)->nr_frags == 0) {
802 struct cp_desc *txd = &cp->tx_ring[entry];
803 u32 len;
804 dma_addr_t mapping;
805
806 len = skb->len;
807 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
808 CP_VLAN_TX_TAG(txd, vlan_tag);
809 txd->addr = cpu_to_le64(mapping);
810 wmb();
811
812 flags = eor | len | DescOwn | FirstFrag | LastFrag;
813
814 if (mss)
815 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
816 else if (skb->ip_summed == CHECKSUM_HW) {
817 const struct iphdr *ip = skb->nh.iph;
818 if (ip->protocol == IPPROTO_TCP)
819 flags |= IPCS | TCPCS;
820 else if (ip->protocol == IPPROTO_UDP)
821 flags |= IPCS | UDPCS;
822 else
823 WARN_ON(1); /* we need a WARN() */
824 }
825
826 txd->opts1 = cpu_to_le32(flags);
827 wmb();
828
829 cp->tx_skb[entry].skb = skb;
830 cp->tx_skb[entry].mapping = mapping;
831 cp->tx_skb[entry].len = len;
832 entry = NEXT_TX(entry);
833 } else {
834 struct cp_desc *txd;
835 u32 first_len, first_eor;
836 dma_addr_t first_mapping;
837 int frag, first_entry = entry;
838 const struct iphdr *ip = skb->nh.iph;
839
840 /* We must give this initial chunk to the device last.
841 * Otherwise we could race with the device.
842 */
843 first_eor = eor;
844 first_len = skb_headlen(skb);
845 first_mapping = pci_map_single(cp->pdev, skb->data,
846 first_len, PCI_DMA_TODEVICE);
847 cp->tx_skb[entry].skb = skb;
848 cp->tx_skb[entry].mapping = first_mapping;
849 cp->tx_skb[entry].len = first_len;
850 entry = NEXT_TX(entry);
851
852 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
853 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
854 u32 len;
855 u32 ctrl;
856 dma_addr_t mapping;
857
858 len = this_frag->size;
859 mapping = pci_map_single(cp->pdev,
860 ((void *) page_address(this_frag->page) +
861 this_frag->page_offset),
862 len, PCI_DMA_TODEVICE);
863 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
864
865 ctrl = eor | len | DescOwn;
866
867 if (mss)
868 ctrl |= LargeSend |
869 ((mss & MSSMask) << MSSShift);
870 else if (skb->ip_summed == CHECKSUM_HW) {
871 if (ip->protocol == IPPROTO_TCP)
872 ctrl |= IPCS | TCPCS;
873 else if (ip->protocol == IPPROTO_UDP)
874 ctrl |= IPCS | UDPCS;
875 else
876 BUG();
877 }
878
879 if (frag == skb_shinfo(skb)->nr_frags - 1)
880 ctrl |= LastFrag;
881
882 txd = &cp->tx_ring[entry];
883 CP_VLAN_TX_TAG(txd, vlan_tag);
884 txd->addr = cpu_to_le64(mapping);
885 wmb();
886
887 txd->opts1 = cpu_to_le32(ctrl);
888 wmb();
889
890 cp->tx_skb[entry].skb = skb;
891 cp->tx_skb[entry].mapping = mapping;
892 cp->tx_skb[entry].len = len;
893 entry = NEXT_TX(entry);
894 }
895
896 txd = &cp->tx_ring[first_entry];
897 CP_VLAN_TX_TAG(txd, vlan_tag);
898 txd->addr = cpu_to_le64(first_mapping);
899 wmb();
900
901 if (skb->ip_summed == CHECKSUM_HW) {
902 if (ip->protocol == IPPROTO_TCP)
903 txd->opts1 = cpu_to_le32(first_eor | first_len |
904 FirstFrag | DescOwn |
905 IPCS | TCPCS);
906 else if (ip->protocol == IPPROTO_UDP)
907 txd->opts1 = cpu_to_le32(first_eor | first_len |
908 FirstFrag | DescOwn |
909 IPCS | UDPCS);
910 else
911 BUG();
912 } else
913 txd->opts1 = cpu_to_le32(first_eor | first_len |
914 FirstFrag | DescOwn);
915 wmb();
916 }
917 cp->tx_head = entry;
918 if (netif_msg_tx_queued(cp))
919 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
920 dev->name, entry, skb->len);
921 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
922 netif_stop_queue(dev);
923
924 spin_unlock_irq(&cp->lock);
925
926 cpw8(TxPoll, NormalTxPoll);
927 dev->trans_start = jiffies;
928
929 return 0;
930 }
931
932 /* Set or clear the multicast filter for this adaptor.
933 This routine is not state sensitive and need not be SMP locked. */
934
935 static void __cp_set_rx_mode (struct net_device *dev)
936 {
937 struct cp_private *cp = netdev_priv(dev);
938 u32 mc_filter[2]; /* Multicast hash filter */
939 int i, rx_mode;
940 u32 tmp;
941
942 /* Note: do not reorder, GCC is clever about common statements. */
943 if (dev->flags & IFF_PROMISC) {
944 /* Unconditionally log net taps. */
945 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
946 dev->name);
947 rx_mode =
948 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
949 AcceptAllPhys;
950 mc_filter[1] = mc_filter[0] = 0xffffffff;
951 } else if ((dev->mc_count > multicast_filter_limit)
952 || (dev->flags & IFF_ALLMULTI)) {
953 /* Too many to filter perfectly -- accept all multicasts. */
954 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
955 mc_filter[1] = mc_filter[0] = 0xffffffff;
956 } else {
957 struct dev_mc_list *mclist;
958 rx_mode = AcceptBroadcast | AcceptMyPhys;
959 mc_filter[1] = mc_filter[0] = 0;
960 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
961 i++, mclist = mclist->next) {
962 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
963
964 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
965 rx_mode |= AcceptMulticast;
966 }
967 }
968
969 /* We can safely update without stopping the chip. */
970 tmp = cp_rx_config | rx_mode;
971 if (cp->rx_config != tmp) {
972 cpw32_f (RxConfig, tmp);
973 cp->rx_config = tmp;
974 }
975 cpw32_f (MAR0 + 0, mc_filter[0]);
976 cpw32_f (MAR0 + 4, mc_filter[1]);
977 }
978
979 static void cp_set_rx_mode (struct net_device *dev)
980 {
981 unsigned long flags;
982 struct cp_private *cp = netdev_priv(dev);
983
984 spin_lock_irqsave (&cp->lock, flags);
985 __cp_set_rx_mode(dev);
986 spin_unlock_irqrestore (&cp->lock, flags);
987 }
988
989 static void __cp_get_stats(struct cp_private *cp)
990 {
991 /* only lower 24 bits valid; write any value to clear */
992 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
993 cpw32 (RxMissed, 0);
994 }
995
996 static struct net_device_stats *cp_get_stats(struct net_device *dev)
997 {
998 struct cp_private *cp = netdev_priv(dev);
999 unsigned long flags;
1000
1001 /* The chip only need report frame silently dropped. */
1002 spin_lock_irqsave(&cp->lock, flags);
1003 if (netif_running(dev) && netif_device_present(dev))
1004 __cp_get_stats(cp);
1005 spin_unlock_irqrestore(&cp->lock, flags);
1006
1007 return &cp->net_stats;
1008 }
1009
1010 static void cp_stop_hw (struct cp_private *cp)
1011 {
1012 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1013 cpw16_f(IntrMask, 0);
1014 cpw8(Cmd, 0);
1015 cpw16_f(CpCmd, 0);
1016 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1017
1018 cp->rx_tail = 0;
1019 cp->tx_head = cp->tx_tail = 0;
1020 }
1021
1022 static void cp_reset_hw (struct cp_private *cp)
1023 {
1024 unsigned work = 1000;
1025
1026 cpw8(Cmd, CmdReset);
1027
1028 while (work--) {
1029 if (!(cpr8(Cmd) & CmdReset))
1030 return;
1031
1032 schedule_timeout_uninterruptible(10);
1033 }
1034
1035 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1036 }
1037
1038 static inline void cp_start_hw (struct cp_private *cp)
1039 {
1040 cpw16(CpCmd, cp->cpcmd);
1041 cpw8(Cmd, RxOn | TxOn);
1042 }
1043
1044 static void cp_init_hw (struct cp_private *cp)
1045 {
1046 struct net_device *dev = cp->dev;
1047 dma_addr_t ring_dma;
1048
1049 cp_reset_hw(cp);
1050
1051 cpw8_f (Cfg9346, Cfg9346_Unlock);
1052
1053 /* Restore our idea of the MAC address. */
1054 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1055 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1056
1057 cp_start_hw(cp);
1058 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1059
1060 __cp_set_rx_mode(dev);
1061 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1062
1063 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1064 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1065 cpw8(Config3, PARMEnable);
1066 cp->wol_enabled = 0;
1067
1068 cpw8(Config5, cpr8(Config5) & PMEStatus);
1069
1070 cpw32_f(HiTxRingAddr, 0);
1071 cpw32_f(HiTxRingAddr + 4, 0);
1072
1073 ring_dma = cp->ring_dma;
1074 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1075 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1076
1077 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1078 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1079 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1080
1081 cpw16(MultiIntr, 0);
1082
1083 cpw16_f(IntrMask, cp_intr_mask);
1084
1085 cpw8_f(Cfg9346, Cfg9346_Lock);
1086 }
1087
1088 static int cp_refill_rx (struct cp_private *cp)
1089 {
1090 unsigned i;
1091
1092 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1093 struct sk_buff *skb;
1094
1095 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1096 if (!skb)
1097 goto err_out;
1098
1099 skb->dev = cp->dev;
1100 skb_reserve(skb, RX_OFFSET);
1101
1102 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1103 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1104 cp->rx_skb[i].skb = skb;
1105
1106 cp->rx_ring[i].opts2 = 0;
1107 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1108 if (i == (CP_RX_RING_SIZE - 1))
1109 cp->rx_ring[i].opts1 =
1110 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1111 else
1112 cp->rx_ring[i].opts1 =
1113 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1114 }
1115
1116 return 0;
1117
1118 err_out:
1119 cp_clean_rings(cp);
1120 return -ENOMEM;
1121 }
1122
1123 static int cp_init_rings (struct cp_private *cp)
1124 {
1125 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1126 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1127
1128 cp->rx_tail = 0;
1129 cp->tx_head = cp->tx_tail = 0;
1130
1131 return cp_refill_rx (cp);
1132 }
1133
1134 static int cp_alloc_rings (struct cp_private *cp)
1135 {
1136 void *mem;
1137
1138 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1139 if (!mem)
1140 return -ENOMEM;
1141
1142 cp->rx_ring = mem;
1143 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1144
1145 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1146 cp->nic_stats = mem;
1147 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1148
1149 return cp_init_rings(cp);
1150 }
1151
1152 static void cp_clean_rings (struct cp_private *cp)
1153 {
1154 unsigned i;
1155
1156 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1157 if (cp->rx_skb[i].skb) {
1158 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1159 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1160 dev_kfree_skb(cp->rx_skb[i].skb);
1161 }
1162 }
1163
1164 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1165 if (cp->tx_skb[i].skb) {
1166 struct sk_buff *skb = cp->tx_skb[i].skb;
1167
1168 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1169 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1170 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1171 dev_kfree_skb(skb);
1172 cp->net_stats.tx_dropped++;
1173 }
1174 }
1175
1176 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1177 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1178
1179 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1180 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1181 }
1182
1183 static void cp_free_rings (struct cp_private *cp)
1184 {
1185 cp_clean_rings(cp);
1186 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1187 cp->rx_ring = NULL;
1188 cp->tx_ring = NULL;
1189 cp->nic_stats = NULL;
1190 }
1191
1192 static int cp_open (struct net_device *dev)
1193 {
1194 struct cp_private *cp = netdev_priv(dev);
1195 int rc;
1196
1197 if (netif_msg_ifup(cp))
1198 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1199
1200 rc = cp_alloc_rings(cp);
1201 if (rc)
1202 return rc;
1203
1204 cp_init_hw(cp);
1205
1206 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1207 if (rc)
1208 goto err_out_hw;
1209
1210 netif_carrier_off(dev);
1211 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1212 netif_start_queue(dev);
1213
1214 return 0;
1215
1216 err_out_hw:
1217 cp_stop_hw(cp);
1218 cp_free_rings(cp);
1219 return rc;
1220 }
1221
1222 static int cp_close (struct net_device *dev)
1223 {
1224 struct cp_private *cp = netdev_priv(dev);
1225 unsigned long flags;
1226
1227 if (netif_msg_ifdown(cp))
1228 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1229
1230 spin_lock_irqsave(&cp->lock, flags);
1231
1232 netif_stop_queue(dev);
1233 netif_carrier_off(dev);
1234
1235 cp_stop_hw(cp);
1236
1237 spin_unlock_irqrestore(&cp->lock, flags);
1238
1239 synchronize_irq(dev->irq);
1240 free_irq(dev->irq, dev);
1241
1242 cp_free_rings(cp);
1243 return 0;
1244 }
1245
1246 #ifdef BROKEN
1247 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1248 {
1249 struct cp_private *cp = netdev_priv(dev);
1250 int rc;
1251 unsigned long flags;
1252
1253 /* check for invalid MTU, according to hardware limits */
1254 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1255 return -EINVAL;
1256
1257 /* if network interface not up, no need for complexity */
1258 if (!netif_running(dev)) {
1259 dev->mtu = new_mtu;
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1261 return 0;
1262 }
1263
1264 spin_lock_irqsave(&cp->lock, flags);
1265
1266 cp_stop_hw(cp); /* stop h/w and free rings */
1267 cp_clean_rings(cp);
1268
1269 dev->mtu = new_mtu;
1270 cp_set_rxbufsize(cp); /* set new rx buf size */
1271
1272 rc = cp_init_rings(cp); /* realloc and restart h/w */
1273 cp_start_hw(cp);
1274
1275 spin_unlock_irqrestore(&cp->lock, flags);
1276
1277 return rc;
1278 }
1279 #endif /* BROKEN */
1280
1281 static char mii_2_8139_map[8] = {
1282 BasicModeCtrl,
1283 BasicModeStatus,
1284 0,
1285 0,
1286 NWayAdvert,
1287 NWayLPAR,
1288 NWayExpansion,
1289 0
1290 };
1291
1292 static int mdio_read(struct net_device *dev, int phy_id, int location)
1293 {
1294 struct cp_private *cp = netdev_priv(dev);
1295
1296 return location < 8 && mii_2_8139_map[location] ?
1297 readw(cp->regs + mii_2_8139_map[location]) : 0;
1298 }
1299
1300
1301 static void mdio_write(struct net_device *dev, int phy_id, int location,
1302 int value)
1303 {
1304 struct cp_private *cp = netdev_priv(dev);
1305
1306 if (location == 0) {
1307 cpw8(Cfg9346, Cfg9346_Unlock);
1308 cpw16(BasicModeCtrl, value);
1309 cpw8(Cfg9346, Cfg9346_Lock);
1310 } else if (location < 8 && mii_2_8139_map[location])
1311 cpw16(mii_2_8139_map[location], value);
1312 }
1313
1314 /* Set the ethtool Wake-on-LAN settings */
1315 static int netdev_set_wol (struct cp_private *cp,
1316 const struct ethtool_wolinfo *wol)
1317 {
1318 u8 options;
1319
1320 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1321 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts) {
1323 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1324 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1325 }
1326
1327 cpw8 (Cfg9346, Cfg9346_Unlock);
1328 cpw8 (Config3, options);
1329 cpw8 (Cfg9346, Cfg9346_Lock);
1330
1331 options = 0; /* Paranoia setting */
1332 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1333 /* If WOL is being disabled, no need for complexity */
1334 if (wol->wolopts) {
1335 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1336 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1337 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1338 }
1339
1340 cpw8 (Config5, options);
1341
1342 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1343
1344 return 0;
1345 }
1346
1347 /* Get the ethtool Wake-on-LAN settings */
1348 static void netdev_get_wol (struct cp_private *cp,
1349 struct ethtool_wolinfo *wol)
1350 {
1351 u8 options;
1352
1353 wol->wolopts = 0; /* Start from scratch */
1354 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1355 WAKE_MCAST | WAKE_UCAST;
1356 /* We don't need to go on if WOL is disabled */
1357 if (!cp->wol_enabled) return;
1358
1359 options = cpr8 (Config3);
1360 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1361 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1362
1363 options = 0; /* Paranoia setting */
1364 options = cpr8 (Config5);
1365 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1366 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1367 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1368 }
1369
1370 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1371 {
1372 struct cp_private *cp = netdev_priv(dev);
1373
1374 strcpy (info->driver, DRV_NAME);
1375 strcpy (info->version, DRV_VERSION);
1376 strcpy (info->bus_info, pci_name(cp->pdev));
1377 }
1378
1379 static int cp_get_regs_len(struct net_device *dev)
1380 {
1381 return CP_REGS_SIZE;
1382 }
1383
1384 static int cp_get_stats_count (struct net_device *dev)
1385 {
1386 return CP_NUM_STATS;
1387 }
1388
1389 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1390 {
1391 struct cp_private *cp = netdev_priv(dev);
1392 int rc;
1393 unsigned long flags;
1394
1395 spin_lock_irqsave(&cp->lock, flags);
1396 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1397 spin_unlock_irqrestore(&cp->lock, flags);
1398
1399 return rc;
1400 }
1401
1402 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1403 {
1404 struct cp_private *cp = netdev_priv(dev);
1405 int rc;
1406 unsigned long flags;
1407
1408 spin_lock_irqsave(&cp->lock, flags);
1409 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1410 spin_unlock_irqrestore(&cp->lock, flags);
1411
1412 return rc;
1413 }
1414
1415 static int cp_nway_reset(struct net_device *dev)
1416 {
1417 struct cp_private *cp = netdev_priv(dev);
1418 return mii_nway_restart(&cp->mii_if);
1419 }
1420
1421 static u32 cp_get_msglevel(struct net_device *dev)
1422 {
1423 struct cp_private *cp = netdev_priv(dev);
1424 return cp->msg_enable;
1425 }
1426
1427 static void cp_set_msglevel(struct net_device *dev, u32 value)
1428 {
1429 struct cp_private *cp = netdev_priv(dev);
1430 cp->msg_enable = value;
1431 }
1432
1433 static u32 cp_get_rx_csum(struct net_device *dev)
1434 {
1435 struct cp_private *cp = netdev_priv(dev);
1436 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1437 }
1438
1439 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1440 {
1441 struct cp_private *cp = netdev_priv(dev);
1442 u16 cmd = cp->cpcmd, newcmd;
1443
1444 newcmd = cmd;
1445
1446 if (data)
1447 newcmd |= RxChkSum;
1448 else
1449 newcmd &= ~RxChkSum;
1450
1451 if (newcmd != cmd) {
1452 unsigned long flags;
1453
1454 spin_lock_irqsave(&cp->lock, flags);
1455 cp->cpcmd = newcmd;
1456 cpw16_f(CpCmd, newcmd);
1457 spin_unlock_irqrestore(&cp->lock, flags);
1458 }
1459
1460 return 0;
1461 }
1462
1463 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1464 void *p)
1465 {
1466 struct cp_private *cp = netdev_priv(dev);
1467 unsigned long flags;
1468
1469 if (regs->len < CP_REGS_SIZE)
1470 return /* -EINVAL */;
1471
1472 regs->version = CP_REGS_VER;
1473
1474 spin_lock_irqsave(&cp->lock, flags);
1475 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1476 spin_unlock_irqrestore(&cp->lock, flags);
1477 }
1478
1479 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1480 {
1481 struct cp_private *cp = netdev_priv(dev);
1482 unsigned long flags;
1483
1484 spin_lock_irqsave (&cp->lock, flags);
1485 netdev_get_wol (cp, wol);
1486 spin_unlock_irqrestore (&cp->lock, flags);
1487 }
1488
1489 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1490 {
1491 struct cp_private *cp = netdev_priv(dev);
1492 unsigned long flags;
1493 int rc;
1494
1495 spin_lock_irqsave (&cp->lock, flags);
1496 rc = netdev_set_wol (cp, wol);
1497 spin_unlock_irqrestore (&cp->lock, flags);
1498
1499 return rc;
1500 }
1501
1502 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1503 {
1504 switch (stringset) {
1505 case ETH_SS_STATS:
1506 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1507 break;
1508 default:
1509 BUG();
1510 break;
1511 }
1512 }
1513
1514 static void cp_get_ethtool_stats (struct net_device *dev,
1515 struct ethtool_stats *estats, u64 *tmp_stats)
1516 {
1517 struct cp_private *cp = netdev_priv(dev);
1518 int i;
1519
1520 memset(cp->nic_stats, 0, sizeof(struct cp_dma_stats));
1521
1522 /* begin NIC statistics dump */
1523 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1524 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1525 cpr32(StatsAddr);
1526
1527 for (i = 0; i < 1000; i++) {
1528 if ((cpr32(StatsAddr) & DumpStats) == 0)
1529 break;
1530 udelay(10);
1531 }
1532 cpw32(StatsAddr, 0);
1533 cpw32(StatsAddr + 4, 0);
1534
1535 i = 0;
1536 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1537 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1538 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1539 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1540 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1541 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1542 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1543 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1544 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1545 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1546 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1547 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1548 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1549 tmp_stats[i++] = cp->cp_stats.rx_frags;
1550 if (i != CP_NUM_STATS)
1551 BUG();
1552 }
1553
1554 static struct ethtool_ops cp_ethtool_ops = {
1555 .get_drvinfo = cp_get_drvinfo,
1556 .get_regs_len = cp_get_regs_len,
1557 .get_stats_count = cp_get_stats_count,
1558 .get_settings = cp_get_settings,
1559 .set_settings = cp_set_settings,
1560 .nway_reset = cp_nway_reset,
1561 .get_link = ethtool_op_get_link,
1562 .get_msglevel = cp_get_msglevel,
1563 .set_msglevel = cp_set_msglevel,
1564 .get_rx_csum = cp_get_rx_csum,
1565 .set_rx_csum = cp_set_rx_csum,
1566 .get_tx_csum = ethtool_op_get_tx_csum,
1567 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1568 .get_sg = ethtool_op_get_sg,
1569 .set_sg = ethtool_op_set_sg,
1570 .get_tso = ethtool_op_get_tso,
1571 .set_tso = ethtool_op_set_tso,
1572 .get_regs = cp_get_regs,
1573 .get_wol = cp_get_wol,
1574 .set_wol = cp_set_wol,
1575 .get_strings = cp_get_strings,
1576 .get_ethtool_stats = cp_get_ethtool_stats,
1577 .get_perm_addr = ethtool_op_get_perm_addr,
1578 };
1579
1580 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1581 {
1582 struct cp_private *cp = netdev_priv(dev);
1583 int rc;
1584 unsigned long flags;
1585
1586 if (!netif_running(dev))
1587 return -EINVAL;
1588
1589 spin_lock_irqsave(&cp->lock, flags);
1590 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1591 spin_unlock_irqrestore(&cp->lock, flags);
1592 return rc;
1593 }
1594
1595 /* Serial EEPROM section. */
1596
1597 /* EEPROM_Ctrl bits. */
1598 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1599 #define EE_CS 0x08 /* EEPROM chip select. */
1600 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1601 #define EE_WRITE_0 0x00
1602 #define EE_WRITE_1 0x02
1603 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1604 #define EE_ENB (0x80 | EE_CS)
1605
1606 /* Delay between EEPROM clock transitions.
1607 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1608 */
1609
1610 #define eeprom_delay() readl(ee_addr)
1611
1612 /* The EEPROM commands include the alway-set leading bit. */
1613 #define EE_WRITE_CMD (5)
1614 #define EE_READ_CMD (6)
1615 #define EE_ERASE_CMD (7)
1616
1617 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1618 {
1619 int i;
1620 unsigned retval = 0;
1621 void __iomem *ee_addr = ioaddr + Cfg9346;
1622 int read_cmd = location | (EE_READ_CMD << addr_len);
1623
1624 writeb (EE_ENB & ~EE_CS, ee_addr);
1625 writeb (EE_ENB, ee_addr);
1626 eeprom_delay ();
1627
1628 /* Shift the read command bits out. */
1629 for (i = 4 + addr_len; i >= 0; i--) {
1630 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1631 writeb (EE_ENB | dataval, ee_addr);
1632 eeprom_delay ();
1633 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1634 eeprom_delay ();
1635 }
1636 writeb (EE_ENB, ee_addr);
1637 eeprom_delay ();
1638
1639 for (i = 16; i > 0; i--) {
1640 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1641 eeprom_delay ();
1642 retval =
1643 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1644 0);
1645 writeb (EE_ENB, ee_addr);
1646 eeprom_delay ();
1647 }
1648
1649 /* Terminate the EEPROM access. */
1650 writeb (~EE_CS, ee_addr);
1651 eeprom_delay ();
1652
1653 return retval;
1654 }
1655
1656 /* Put the board into D3cold state and wait for WakeUp signal */
1657 static void cp_set_d3_state (struct cp_private *cp)
1658 {
1659 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1660 pci_set_power_state (cp->pdev, PCI_D3hot);
1661 }
1662
1663 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1664 {
1665 struct net_device *dev;
1666 struct cp_private *cp;
1667 int rc;
1668 void __iomem *regs;
1669 long pciaddr;
1670 unsigned int addr_len, i, pci_using_dac;
1671 u8 pci_rev;
1672
1673 #ifndef MODULE
1674 static int version_printed;
1675 if (version_printed++ == 0)
1676 printk("%s", version);
1677 #endif
1678
1679 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1680
1681 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1682 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1683 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1684 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1685 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1686 return -ENODEV;
1687 }
1688
1689 dev = alloc_etherdev(sizeof(struct cp_private));
1690 if (!dev)
1691 return -ENOMEM;
1692 SET_MODULE_OWNER(dev);
1693 SET_NETDEV_DEV(dev, &pdev->dev);
1694
1695 cp = netdev_priv(dev);
1696 cp->pdev = pdev;
1697 cp->dev = dev;
1698 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1699 spin_lock_init (&cp->lock);
1700 cp->mii_if.dev = dev;
1701 cp->mii_if.mdio_read = mdio_read;
1702 cp->mii_if.mdio_write = mdio_write;
1703 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1704 cp->mii_if.phy_id_mask = 0x1f;
1705 cp->mii_if.reg_num_mask = 0x1f;
1706 cp_set_rxbufsize(cp);
1707
1708 rc = pci_enable_device(pdev);
1709 if (rc)
1710 goto err_out_free;
1711
1712 rc = pci_set_mwi(pdev);
1713 if (rc)
1714 goto err_out_disable;
1715
1716 rc = pci_request_regions(pdev, DRV_NAME);
1717 if (rc)
1718 goto err_out_mwi;
1719
1720 pciaddr = pci_resource_start(pdev, 1);
1721 if (!pciaddr) {
1722 rc = -EIO;
1723 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1724 pci_name(pdev));
1725 goto err_out_res;
1726 }
1727 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1728 rc = -EIO;
1729 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1730 pci_resource_len(pdev, 1), pci_name(pdev));
1731 goto err_out_res;
1732 }
1733
1734 /* Configure DMA attributes. */
1735 if ((sizeof(dma_addr_t) > 4) &&
1736 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1737 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1738 pci_using_dac = 1;
1739 } else {
1740 pci_using_dac = 0;
1741
1742 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1743 if (rc) {
1744 printk(KERN_ERR PFX "No usable DMA configuration, "
1745 "aborting.\n");
1746 goto err_out_res;
1747 }
1748 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1749 if (rc) {
1750 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1751 "aborting.\n");
1752 goto err_out_res;
1753 }
1754 }
1755
1756 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1757 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1758
1759 regs = ioremap(pciaddr, CP_REGS_SIZE);
1760 if (!regs) {
1761 rc = -EIO;
1762 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1763 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1764 goto err_out_res;
1765 }
1766 dev->base_addr = (unsigned long) regs;
1767 cp->regs = regs;
1768
1769 cp_stop_hw(cp);
1770
1771 /* read MAC address from EEPROM */
1772 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1773 for (i = 0; i < 3; i++)
1774 ((u16 *) (dev->dev_addr))[i] =
1775 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1776 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1777
1778 dev->open = cp_open;
1779 dev->stop = cp_close;
1780 dev->set_multicast_list = cp_set_rx_mode;
1781 dev->hard_start_xmit = cp_start_xmit;
1782 dev->get_stats = cp_get_stats;
1783 dev->do_ioctl = cp_ioctl;
1784 dev->poll = cp_rx_poll;
1785 #ifdef CONFIG_NET_POLL_CONTROLLER
1786 dev->poll_controller = cp_poll_controller;
1787 #endif
1788 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1789 #ifdef BROKEN
1790 dev->change_mtu = cp_change_mtu;
1791 #endif
1792 dev->ethtool_ops = &cp_ethtool_ops;
1793 #if 0
1794 dev->tx_timeout = cp_tx_timeout;
1795 dev->watchdog_timeo = TX_TIMEOUT;
1796 #endif
1797
1798 #if CP_VLAN_TAG_USED
1799 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1800 dev->vlan_rx_register = cp_vlan_rx_register;
1801 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1802 #endif
1803
1804 if (pci_using_dac)
1805 dev->features |= NETIF_F_HIGHDMA;
1806
1807 #if 0 /* disabled by default until verified */
1808 dev->features |= NETIF_F_TSO;
1809 #endif
1810
1811 dev->irq = pdev->irq;
1812
1813 rc = register_netdev(dev);
1814 if (rc)
1815 goto err_out_iomap;
1816
1817 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1818 "%02x:%02x:%02x:%02x:%02x:%02x, "
1819 "IRQ %d\n",
1820 dev->name,
1821 dev->base_addr,
1822 dev->dev_addr[0], dev->dev_addr[1],
1823 dev->dev_addr[2], dev->dev_addr[3],
1824 dev->dev_addr[4], dev->dev_addr[5],
1825 dev->irq);
1826
1827 pci_set_drvdata(pdev, dev);
1828
1829 /* enable busmastering and memory-write-invalidate */
1830 pci_set_master(pdev);
1831
1832 if (cp->wol_enabled) cp_set_d3_state (cp);
1833
1834 return 0;
1835
1836 err_out_iomap:
1837 iounmap(regs);
1838 err_out_res:
1839 pci_release_regions(pdev);
1840 err_out_mwi:
1841 pci_clear_mwi(pdev);
1842 err_out_disable:
1843 pci_disable_device(pdev);
1844 err_out_free:
1845 free_netdev(dev);
1846 return rc;
1847 }
1848
1849 static void cp_remove_one (struct pci_dev *pdev)
1850 {
1851 struct net_device *dev = pci_get_drvdata(pdev);
1852 struct cp_private *cp = netdev_priv(dev);
1853
1854 if (!dev)
1855 BUG();
1856 unregister_netdev(dev);
1857 iounmap(cp->regs);
1858 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1859 pci_release_regions(pdev);
1860 pci_clear_mwi(pdev);
1861 pci_disable_device(pdev);
1862 pci_set_drvdata(pdev, NULL);
1863 free_netdev(dev);
1864 }
1865
1866 #ifdef CONFIG_PM
1867 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1868 {
1869 struct net_device *dev;
1870 struct cp_private *cp;
1871 unsigned long flags;
1872
1873 dev = pci_get_drvdata (pdev);
1874 cp = netdev_priv(dev);
1875
1876 if (!dev || !netif_running (dev)) return 0;
1877
1878 netif_device_detach (dev);
1879 netif_stop_queue (dev);
1880
1881 spin_lock_irqsave (&cp->lock, flags);
1882
1883 /* Disable Rx and Tx */
1884 cpw16 (IntrMask, 0);
1885 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1886
1887 spin_unlock_irqrestore (&cp->lock, flags);
1888
1889 if (cp->pdev && cp->wol_enabled) {
1890 pci_save_state (cp->pdev);
1891 cp_set_d3_state (cp);
1892 }
1893
1894 return 0;
1895 }
1896
1897 static int cp_resume (struct pci_dev *pdev)
1898 {
1899 struct net_device *dev;
1900 struct cp_private *cp;
1901 unsigned long flags;
1902
1903 dev = pci_get_drvdata (pdev);
1904 cp = netdev_priv(dev);
1905
1906 netif_device_attach (dev);
1907
1908 if (cp->pdev && cp->wol_enabled) {
1909 pci_set_power_state (cp->pdev, PCI_D0);
1910 pci_restore_state (cp->pdev);
1911 }
1912
1913 cp_init_hw (cp);
1914 netif_start_queue (dev);
1915
1916 spin_lock_irqsave (&cp->lock, flags);
1917
1918 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
1919
1920 spin_unlock_irqrestore (&cp->lock, flags);
1921
1922 return 0;
1923 }
1924 #endif /* CONFIG_PM */
1925
1926 static struct pci_driver cp_driver = {
1927 .name = DRV_NAME,
1928 .id_table = cp_pci_tbl,
1929 .probe = cp_init_one,
1930 .remove = cp_remove_one,
1931 #ifdef CONFIG_PM
1932 .resume = cp_resume,
1933 .suspend = cp_suspend,
1934 #endif
1935 };
1936
1937 static int __init cp_init (void)
1938 {
1939 #ifdef MODULE
1940 printk("%s", version);
1941 #endif
1942 return pci_module_init (&cp_driver);
1943 }
1944
1945 static void __exit cp_exit (void)
1946 {
1947 pci_unregister_driver (&cp_driver);
1948 }
1949
1950 module_init(cp_init);
1951 module_exit(cp_exit);
Linux kernel - Deliverables
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