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Merge /spare/repo/linux-2.6/
[deliverable/linux.git] / drivers / net / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/if_vlan.h>
69 #include <linux/crc32.h>
70 #include <linux/in.h>
71 #include <linux/ip.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/cache.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/uaccess.h>
78
79 /* VLAN tagging feature enable/disable */
80 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81 #define CP_VLAN_TAG_USED 1
82 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #else
85 #define CP_VLAN_TAG_USED 0
86 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88 #endif
89
90 /* These identify the driver base version and may not be removed. */
91 static char version[] =
92 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96 MODULE_VERSION(DRV_VERSION);
97 MODULE_LICENSE("GPL");
98
99 static int debug = -1;
100 module_param(debug, int, 0);
101 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105 static int multicast_filter_limit = 32;
106 module_param(multicast_filter_limit, int, 0);
107 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109 #define PFX DRV_NAME ": "
110
111 #ifndef TRUE
112 #define FALSE 0
113 #define TRUE (!FALSE)
114 #endif
115
116 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
117 NETIF_MSG_PROBE | \
118 NETIF_MSG_LINK)
119 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
120 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
121 #define CP_REGS_SIZE (0xff + 1)
122 #define CP_REGS_VER 1 /* version 1 */
123 #define CP_RX_RING_SIZE 64
124 #define CP_TX_RING_SIZE 64
125 #define CP_RING_BYTES \
126 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
127 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 CP_STATS_SIZE)
129 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
130 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
131 #define TX_BUFFS_AVAIL(CP) \
132 (((CP)->tx_tail <= (CP)->tx_head) ? \
133 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
134 (CP)->tx_tail - (CP)->tx_head - 1)
135
136 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define RX_OFFSET 2
138 #define CP_INTERNAL_PHY 32
139
140 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
141 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
142 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
143 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
144 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145
146 /* Time in jiffies before concluding the transmitter is hung. */
147 #define TX_TIMEOUT (6*HZ)
148
149 /* hardware minimum and maximum for a single frame's data payload */
150 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
151 #define CP_MAX_MTU 4096
152
153 enum {
154 /* NIC register offsets */
155 MAC0 = 0x00, /* Ethernet hardware address. */
156 MAR0 = 0x08, /* Multicast filter. */
157 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
158 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
159 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
160 Cmd = 0x37, /* Command register */
161 IntrMask = 0x3C, /* Interrupt mask */
162 IntrStatus = 0x3E, /* Interrupt status */
163 TxConfig = 0x40, /* Tx configuration */
164 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
165 RxConfig = 0x44, /* Rx configuration */
166 RxMissed = 0x4C, /* 24 bits valid, write clears */
167 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
168 Config1 = 0x52, /* Config1 */
169 Config3 = 0x59, /* Config3 */
170 Config4 = 0x5A, /* Config4 */
171 MultiIntr = 0x5C, /* Multiple interrupt select */
172 BasicModeCtrl = 0x62, /* MII BMCR */
173 BasicModeStatus = 0x64, /* MII BMSR */
174 NWayAdvert = 0x66, /* MII ADVERTISE */
175 NWayLPAR = 0x68, /* MII LPA */
176 NWayExpansion = 0x6A, /* MII Expansion */
177 Config5 = 0xD8, /* Config5 */
178 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
179 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
180 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
181 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
182 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
183 TxThresh = 0xEC, /* Early Tx threshold */
184 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
185 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186
187 /* Tx and Rx status descriptors */
188 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
189 RingEnd = (1 << 30), /* End of descriptor ring */
190 FirstFrag = (1 << 29), /* First segment of a packet */
191 LastFrag = (1 << 28), /* Final segment of a packet */
192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
195 TxError = (1 << 23), /* Tx error summary */
196 RxError = (1 << 20), /* Rx error summary */
197 IPCS = (1 << 18), /* Calculate IP checksum */
198 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
199 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
200 TxVlanTag = (1 << 17), /* Add VLAN tag */
201 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
202 IPFail = (1 << 15), /* IP checksum failed */
203 UDPFail = (1 << 14), /* UDP/IP checksum failed */
204 TCPFail = (1 << 13), /* TCP/IP checksum failed */
205 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
206 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
207 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 RxProtoTCP = 1,
209 RxProtoUDP = 2,
210 RxProtoIP = 3,
211 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
212 TxOWC = (1 << 22), /* Tx Out-of-window collision */
213 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
214 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
215 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
216 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
217 RxErrFrame = (1 << 27), /* Rx frame alignment error */
218 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
219 RxErrCRC = (1 << 18), /* Rx CRC error */
220 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
221 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
222 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223
224 /* StatsAddr register */
225 DumpStats = (1 << 3), /* Begin stats dump */
226
227 /* RxConfig register */
228 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
229 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
230 AcceptErr = 0x20, /* Accept packets with CRC errors */
231 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
232 AcceptBroadcast = 0x08, /* Accept broadcast packets */
233 AcceptMulticast = 0x04, /* Accept multicast packets */
234 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
235 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236
237 /* IntrMask / IntrStatus registers */
238 PciErr = (1 << 15), /* System error on the PCI bus */
239 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
240 LenChg = (1 << 13), /* Cable length change */
241 SWInt = (1 << 8), /* Software-requested interrupt */
242 TxEmpty = (1 << 7), /* No Tx descriptors available */
243 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
244 LinkChg = (1 << 5), /* Packet underrun, or link change */
245 RxEmpty = (1 << 4), /* No Rx descriptors available */
246 TxErr = (1 << 3), /* Tx error */
247 TxOK = (1 << 2), /* Tx packet sent */
248 RxErr = (1 << 1), /* Rx error */
249 RxOK = (1 << 0), /* Rx packet received */
250 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
251 but hardware likes to raise it */
252
253 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
254 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
255 RxErr | RxOK | IntrResvd,
256
257 /* C mode command register */
258 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
259 RxOn = (1 << 3), /* Rx mode enable */
260 TxOn = (1 << 2), /* Tx mode enable */
261
262 /* C+ mode command register */
263 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
264 RxChkSum = (1 << 5), /* Rx checksum offload enable */
265 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
266 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
267 CpRxOn = (1 << 1), /* Rx mode enable */
268 CpTxOn = (1 << 0), /* Tx mode enable */
269
270 /* Cfg9436 EEPROM control register */
271 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
272 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273
274 /* TxConfig register */
275 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /* Early Tx Threshold register */
279 TxThreshMask = 0x3f, /* Mask bits 5-0 */
280 TxThreshMax = 2048, /* Max early Tx threshold */
281
282 /* Config1 register */
283 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
284 LWACT = (1 << 4), /* LWAKE active mode */
285 PMEnable = (1 << 0), /* Enable various PM features of chip */
286
287 /* Config3 register */
288 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
292 /* Config4 register */
293 LWPTN = (1 << 1), /* LWAKE Pattern */
294 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295
296 /* Config5 register */
297 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
298 MWF = (1 << 5), /* Accept Multicast wakeup frame */
299 UWF = (1 << 4), /* Accept Unicast wakeup frame */
300 LANWake = (1 << 1), /* Enable LANWake signal */
301 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302
303 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
304 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
305 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
306 };
307
308 static const unsigned int cp_rx_config =
309 (RX_FIFO_THRESH << RxCfgFIFOShift) |
310 (RX_DMA_BURST << RxCfgDMAShift);
311
312 struct cp_desc {
313 u32 opts1;
314 u32 opts2;
315 u64 addr;
316 };
317
318 struct ring_info {
319 struct sk_buff *skb;
320 dma_addr_t mapping;
321 u32 len;
322 };
323
324 struct cp_dma_stats {
325 u64 tx_ok;
326 u64 rx_ok;
327 u64 tx_err;
328 u32 rx_err;
329 u16 rx_fifo;
330 u16 frame_align;
331 u32 tx_ok_1col;
332 u32 tx_ok_mcol;
333 u64 rx_ok_phys;
334 u64 rx_ok_bcast;
335 u32 rx_ok_mcast;
336 u16 tx_abort;
337 u16 tx_underrun;
338 } __attribute__((packed));
339
340 struct cp_extra_stats {
341 unsigned long rx_frags;
342 };
343
344 struct cp_private {
345 void __iomem *regs;
346 struct net_device *dev;
347 spinlock_t lock;
348 u32 msg_enable;
349
350 struct pci_dev *pdev;
351 u32 rx_config;
352 u16 cpcmd;
353
354 struct net_device_stats net_stats;
355 struct cp_extra_stats cp_stats;
356
357 unsigned rx_tail ____cacheline_aligned;
358 struct cp_desc *rx_ring;
359 struct ring_info rx_skb[CP_RX_RING_SIZE];
360 unsigned rx_buf_sz;
361
362 unsigned tx_head ____cacheline_aligned;
363 unsigned tx_tail;
364
365 struct cp_desc *tx_ring;
366 struct ring_info tx_skb[CP_TX_RING_SIZE];
367 dma_addr_t ring_dma;
368
369 #if CP_VLAN_TAG_USED
370 struct vlan_group *vlgrp;
371 #endif
372
373 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374
375 struct mii_if_info mii_if;
376 };
377
378 #define cpr8(reg) readb(cp->regs + (reg))
379 #define cpr16(reg) readw(cp->regs + (reg))
380 #define cpr32(reg) readl(cp->regs + (reg))
381 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
382 #define cpw16(reg,val) writew((val), cp->regs + (reg))
383 #define cpw32(reg,val) writel((val), cp->regs + (reg))
384 #define cpw8_f(reg,val) do { \
385 writeb((val), cp->regs + (reg)); \
386 readb(cp->regs + (reg)); \
387 } while (0)
388 #define cpw16_f(reg,val) do { \
389 writew((val), cp->regs + (reg)); \
390 readw(cp->regs + (reg)); \
391 } while (0)
392 #define cpw32_f(reg,val) do { \
393 writel((val), cp->regs + (reg)); \
394 readl(cp->regs + (reg)); \
395 } while (0)
396
397
398 static void __cp_set_rx_mode (struct net_device *dev);
399 static void cp_tx (struct cp_private *cp);
400 static void cp_clean_rings (struct cp_private *cp);
401 #ifdef CONFIG_NET_POLL_CONTROLLER
402 static void cp_poll_controller(struct net_device *dev);
403 #endif
404
405 static struct pci_device_id cp_pci_tbl[] = {
406 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
410 { },
411 };
412 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
413
414 static struct {
415 const char str[ETH_GSTRING_LEN];
416 } ethtool_stats_keys[] = {
417 { "tx_ok" },
418 { "rx_ok" },
419 { "tx_err" },
420 { "rx_err" },
421 { "rx_fifo" },
422 { "frame_align" },
423 { "tx_ok_1col" },
424 { "tx_ok_mcol" },
425 { "rx_ok_phys" },
426 { "rx_ok_bcast" },
427 { "rx_ok_mcast" },
428 { "tx_abort" },
429 { "tx_underrun" },
430 { "rx_frags" },
431 };
432
433
434 #if CP_VLAN_TAG_USED
435 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
436 {
437 struct cp_private *cp = netdev_priv(dev);
438 unsigned long flags;
439
440 spin_lock_irqsave(&cp->lock, flags);
441 cp->vlgrp = grp;
442 cp->cpcmd |= RxVlanOn;
443 cpw16(CpCmd, cp->cpcmd);
444 spin_unlock_irqrestore(&cp->lock, flags);
445 }
446
447 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
448 {
449 struct cp_private *cp = netdev_priv(dev);
450 unsigned long flags;
451
452 spin_lock_irqsave(&cp->lock, flags);
453 cp->cpcmd &= ~RxVlanOn;
454 cpw16(CpCmd, cp->cpcmd);
455 if (cp->vlgrp)
456 cp->vlgrp->vlan_devices[vid] = NULL;
457 spin_unlock_irqrestore(&cp->lock, flags);
458 }
459 #endif /* CP_VLAN_TAG_USED */
460
461 static inline void cp_set_rxbufsize (struct cp_private *cp)
462 {
463 unsigned int mtu = cp->dev->mtu;
464
465 if (mtu > ETH_DATA_LEN)
466 /* MTU + ethernet header + FCS + optional VLAN tag */
467 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
468 else
469 cp->rx_buf_sz = PKT_BUF_SZ;
470 }
471
472 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
473 struct cp_desc *desc)
474 {
475 skb->protocol = eth_type_trans (skb, cp->dev);
476
477 cp->net_stats.rx_packets++;
478 cp->net_stats.rx_bytes += skb->len;
479 cp->dev->last_rx = jiffies;
480
481 #if CP_VLAN_TAG_USED
482 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
483 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
484 be16_to_cpu(desc->opts2 & 0xffff));
485 } else
486 #endif
487 netif_receive_skb(skb);
488 }
489
490 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
491 u32 status, u32 len)
492 {
493 if (netif_msg_rx_err (cp))
494 printk (KERN_DEBUG
495 "%s: rx err, slot %d status 0x%x len %d\n",
496 cp->dev->name, rx_tail, status, len);
497 cp->net_stats.rx_errors++;
498 if (status & RxErrFrame)
499 cp->net_stats.rx_frame_errors++;
500 if (status & RxErrCRC)
501 cp->net_stats.rx_crc_errors++;
502 if ((status & RxErrRunt) || (status & RxErrLong))
503 cp->net_stats.rx_length_errors++;
504 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
505 cp->net_stats.rx_length_errors++;
506 if (status & RxErrFIFO)
507 cp->net_stats.rx_fifo_errors++;
508 }
509
510 static inline unsigned int cp_rx_csum_ok (u32 status)
511 {
512 unsigned int protocol = (status >> 16) & 0x3;
513
514 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
515 return 1;
516 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
517 return 1;
518 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 return 1;
520 return 0;
521 }
522
523 static int cp_rx_poll (struct net_device *dev, int *budget)
524 {
525 struct cp_private *cp = netdev_priv(dev);
526 unsigned rx_tail = cp->rx_tail;
527 unsigned rx_work = dev->quota;
528 unsigned rx;
529
530 rx_status_loop:
531 rx = 0;
532 cpw16(IntrStatus, cp_rx_intr_mask);
533
534 while (1) {
535 u32 status, len;
536 dma_addr_t mapping;
537 struct sk_buff *skb, *new_skb;
538 struct cp_desc *desc;
539 unsigned buflen;
540
541 skb = cp->rx_skb[rx_tail].skb;
542 if (!skb)
543 BUG();
544
545 desc = &cp->rx_ring[rx_tail];
546 status = le32_to_cpu(desc->opts1);
547 if (status & DescOwn)
548 break;
549
550 len = (status & 0x1fff) - 4;
551 mapping = cp->rx_skb[rx_tail].mapping;
552
553 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
554 /* we don't support incoming fragmented frames.
555 * instead, we attempt to ensure that the
556 * pre-allocated RX skbs are properly sized such
557 * that RX fragments are never encountered
558 */
559 cp_rx_err_acct(cp, rx_tail, status, len);
560 cp->net_stats.rx_dropped++;
561 cp->cp_stats.rx_frags++;
562 goto rx_next;
563 }
564
565 if (status & (RxError | RxErrFIFO)) {
566 cp_rx_err_acct(cp, rx_tail, status, len);
567 goto rx_next;
568 }
569
570 if (netif_msg_rx_status(cp))
571 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
572 cp->dev->name, rx_tail, status, len);
573
574 buflen = cp->rx_buf_sz + RX_OFFSET;
575 new_skb = dev_alloc_skb (buflen);
576 if (!new_skb) {
577 cp->net_stats.rx_dropped++;
578 goto rx_next;
579 }
580
581 skb_reserve(new_skb, RX_OFFSET);
582 new_skb->dev = cp->dev;
583
584 pci_unmap_single(cp->pdev, mapping,
585 buflen, PCI_DMA_FROMDEVICE);
586
587 /* Handle checksum offloading for incoming packets. */
588 if (cp_rx_csum_ok(status))
589 skb->ip_summed = CHECKSUM_UNNECESSARY;
590 else
591 skb->ip_summed = CHECKSUM_NONE;
592
593 skb_put(skb, len);
594
595 mapping =
596 cp->rx_skb[rx_tail].mapping =
597 pci_map_single(cp->pdev, new_skb->data,
598 buflen, PCI_DMA_FROMDEVICE);
599 cp->rx_skb[rx_tail].skb = new_skb;
600
601 cp_rx_skb(cp, skb, desc);
602 rx++;
603
604 rx_next:
605 cp->rx_ring[rx_tail].opts2 = 0;
606 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
607 if (rx_tail == (CP_RX_RING_SIZE - 1))
608 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
609 cp->rx_buf_sz);
610 else
611 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
612 rx_tail = NEXT_RX(rx_tail);
613
614 if (!rx_work--)
615 break;
616 }
617
618 cp->rx_tail = rx_tail;
619
620 dev->quota -= rx;
621 *budget -= rx;
622
623 /* if we did not reach work limit, then we're done with
624 * this round of polling
625 */
626 if (rx_work) {
627 if (cpr16(IntrStatus) & cp_rx_intr_mask)
628 goto rx_status_loop;
629
630 local_irq_disable();
631 cpw16_f(IntrMask, cp_intr_mask);
632 __netif_rx_complete(dev);
633 local_irq_enable();
634
635 return 0; /* done */
636 }
637
638 return 1; /* not done */
639 }
640
641 static irqreturn_t
642 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
643 {
644 struct net_device *dev = dev_instance;
645 struct cp_private *cp;
646 u16 status;
647
648 if (unlikely(dev == NULL))
649 return IRQ_NONE;
650 cp = netdev_priv(dev);
651
652 status = cpr16(IntrStatus);
653 if (!status || (status == 0xFFFF))
654 return IRQ_NONE;
655
656 if (netif_msg_intr(cp))
657 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
658 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
659
660 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
661
662 spin_lock(&cp->lock);
663
664 /* close possible race's with dev_close */
665 if (unlikely(!netif_running(dev))) {
666 cpw16(IntrMask, 0);
667 spin_unlock(&cp->lock);
668 return IRQ_HANDLED;
669 }
670
671 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
672 if (netif_rx_schedule_prep(dev)) {
673 cpw16_f(IntrMask, cp_norx_intr_mask);
674 __netif_rx_schedule(dev);
675 }
676
677 if (status & (TxOK | TxErr | TxEmpty | SWInt))
678 cp_tx(cp);
679 if (status & LinkChg)
680 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
681
682 spin_unlock(&cp->lock);
683
684 if (status & PciErr) {
685 u16 pci_status;
686
687 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
688 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
689 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
690 dev->name, status, pci_status);
691
692 /* TODO: reset hardware */
693 }
694
695 return IRQ_HANDLED;
696 }
697
698 #ifdef CONFIG_NET_POLL_CONTROLLER
699 /*
700 * Polling receive - used by netconsole and other diagnostic tools
701 * to allow network i/o with interrupts disabled.
702 */
703 static void cp_poll_controller(struct net_device *dev)
704 {
705 disable_irq(dev->irq);
706 cp_interrupt(dev->irq, dev, NULL);
707 enable_irq(dev->irq);
708 }
709 #endif
710
711 static void cp_tx (struct cp_private *cp)
712 {
713 unsigned tx_head = cp->tx_head;
714 unsigned tx_tail = cp->tx_tail;
715
716 while (tx_tail != tx_head) {
717 struct sk_buff *skb;
718 u32 status;
719
720 rmb();
721 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
722 if (status & DescOwn)
723 break;
724
725 skb = cp->tx_skb[tx_tail].skb;
726 if (!skb)
727 BUG();
728
729 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
730 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
731
732 if (status & LastFrag) {
733 if (status & (TxError | TxFIFOUnder)) {
734 if (netif_msg_tx_err(cp))
735 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
736 cp->dev->name, status);
737 cp->net_stats.tx_errors++;
738 if (status & TxOWC)
739 cp->net_stats.tx_window_errors++;
740 if (status & TxMaxCol)
741 cp->net_stats.tx_aborted_errors++;
742 if (status & TxLinkFail)
743 cp->net_stats.tx_carrier_errors++;
744 if (status & TxFIFOUnder)
745 cp->net_stats.tx_fifo_errors++;
746 } else {
747 cp->net_stats.collisions +=
748 ((status >> TxColCntShift) & TxColCntMask);
749 cp->net_stats.tx_packets++;
750 cp->net_stats.tx_bytes += skb->len;
751 if (netif_msg_tx_done(cp))
752 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
753 }
754 dev_kfree_skb_irq(skb);
755 }
756
757 cp->tx_skb[tx_tail].skb = NULL;
758
759 tx_tail = NEXT_TX(tx_tail);
760 }
761
762 cp->tx_tail = tx_tail;
763
764 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
765 netif_wake_queue(cp->dev);
766 }
767
768 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
769 {
770 struct cp_private *cp = netdev_priv(dev);
771 unsigned entry;
772 u32 eor, flags;
773 #if CP_VLAN_TAG_USED
774 u32 vlan_tag = 0;
775 #endif
776 int mss = 0;
777
778 spin_lock_irq(&cp->lock);
779
780 /* This is a hard error, log it. */
781 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
782 netif_stop_queue(dev);
783 spin_unlock_irq(&cp->lock);
784 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
785 dev->name);
786 return 1;
787 }
788
789 #if CP_VLAN_TAG_USED
790 if (cp->vlgrp && vlan_tx_tag_present(skb))
791 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
792 #endif
793
794 entry = cp->tx_head;
795 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
796 if (dev->features & NETIF_F_TSO)
797 mss = skb_shinfo(skb)->tso_size;
798
799 if (skb_shinfo(skb)->nr_frags == 0) {
800 struct cp_desc *txd = &cp->tx_ring[entry];
801 u32 len;
802 dma_addr_t mapping;
803
804 len = skb->len;
805 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
806 CP_VLAN_TX_TAG(txd, vlan_tag);
807 txd->addr = cpu_to_le64(mapping);
808 wmb();
809
810 flags = eor | len | DescOwn | FirstFrag | LastFrag;
811
812 if (mss)
813 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
814 else if (skb->ip_summed == CHECKSUM_HW) {
815 const struct iphdr *ip = skb->nh.iph;
816 if (ip->protocol == IPPROTO_TCP)
817 flags |= IPCS | TCPCS;
818 else if (ip->protocol == IPPROTO_UDP)
819 flags |= IPCS | UDPCS;
820 else
821 WARN_ON(1); /* we need a WARN() */
822 }
823
824 txd->opts1 = cpu_to_le32(flags);
825 wmb();
826
827 cp->tx_skb[entry].skb = skb;
828 cp->tx_skb[entry].mapping = mapping;
829 cp->tx_skb[entry].len = len;
830 entry = NEXT_TX(entry);
831 } else {
832 struct cp_desc *txd;
833 u32 first_len, first_eor;
834 dma_addr_t first_mapping;
835 int frag, first_entry = entry;
836 const struct iphdr *ip = skb->nh.iph;
837
838 /* We must give this initial chunk to the device last.
839 * Otherwise we could race with the device.
840 */
841 first_eor = eor;
842 first_len = skb_headlen(skb);
843 first_mapping = pci_map_single(cp->pdev, skb->data,
844 first_len, PCI_DMA_TODEVICE);
845 cp->tx_skb[entry].skb = skb;
846 cp->tx_skb[entry].mapping = first_mapping;
847 cp->tx_skb[entry].len = first_len;
848 entry = NEXT_TX(entry);
849
850 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
851 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
852 u32 len;
853 u32 ctrl;
854 dma_addr_t mapping;
855
856 len = this_frag->size;
857 mapping = pci_map_single(cp->pdev,
858 ((void *) page_address(this_frag->page) +
859 this_frag->page_offset),
860 len, PCI_DMA_TODEVICE);
861 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
862
863 ctrl = eor | len | DescOwn;
864
865 if (mss)
866 ctrl |= LargeSend |
867 ((mss & MSSMask) << MSSShift);
868 else if (skb->ip_summed == CHECKSUM_HW) {
869 if (ip->protocol == IPPROTO_TCP)
870 ctrl |= IPCS | TCPCS;
871 else if (ip->protocol == IPPROTO_UDP)
872 ctrl |= IPCS | UDPCS;
873 else
874 BUG();
875 }
876
877 if (frag == skb_shinfo(skb)->nr_frags - 1)
878 ctrl |= LastFrag;
879
880 txd = &cp->tx_ring[entry];
881 CP_VLAN_TX_TAG(txd, vlan_tag);
882 txd->addr = cpu_to_le64(mapping);
883 wmb();
884
885 txd->opts1 = cpu_to_le32(ctrl);
886 wmb();
887
888 cp->tx_skb[entry].skb = skb;
889 cp->tx_skb[entry].mapping = mapping;
890 cp->tx_skb[entry].len = len;
891 entry = NEXT_TX(entry);
892 }
893
894 txd = &cp->tx_ring[first_entry];
895 CP_VLAN_TX_TAG(txd, vlan_tag);
896 txd->addr = cpu_to_le64(first_mapping);
897 wmb();
898
899 if (skb->ip_summed == CHECKSUM_HW) {
900 if (ip->protocol == IPPROTO_TCP)
901 txd->opts1 = cpu_to_le32(first_eor | first_len |
902 FirstFrag | DescOwn |
903 IPCS | TCPCS);
904 else if (ip->protocol == IPPROTO_UDP)
905 txd->opts1 = cpu_to_le32(first_eor | first_len |
906 FirstFrag | DescOwn |
907 IPCS | UDPCS);
908 else
909 BUG();
910 } else
911 txd->opts1 = cpu_to_le32(first_eor | first_len |
912 FirstFrag | DescOwn);
913 wmb();
914 }
915 cp->tx_head = entry;
916 if (netif_msg_tx_queued(cp))
917 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
918 dev->name, entry, skb->len);
919 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
920 netif_stop_queue(dev);
921
922 spin_unlock_irq(&cp->lock);
923
924 cpw8(TxPoll, NormalTxPoll);
925 dev->trans_start = jiffies;
926
927 return 0;
928 }
929
930 /* Set or clear the multicast filter for this adaptor.
931 This routine is not state sensitive and need not be SMP locked. */
932
933 static void __cp_set_rx_mode (struct net_device *dev)
934 {
935 struct cp_private *cp = netdev_priv(dev);
936 u32 mc_filter[2]; /* Multicast hash filter */
937 int i, rx_mode;
938 u32 tmp;
939
940 /* Note: do not reorder, GCC is clever about common statements. */
941 if (dev->flags & IFF_PROMISC) {
942 /* Unconditionally log net taps. */
943 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
944 dev->name);
945 rx_mode =
946 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
947 AcceptAllPhys;
948 mc_filter[1] = mc_filter[0] = 0xffffffff;
949 } else if ((dev->mc_count > multicast_filter_limit)
950 || (dev->flags & IFF_ALLMULTI)) {
951 /* Too many to filter perfectly -- accept all multicasts. */
952 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
953 mc_filter[1] = mc_filter[0] = 0xffffffff;
954 } else {
955 struct dev_mc_list *mclist;
956 rx_mode = AcceptBroadcast | AcceptMyPhys;
957 mc_filter[1] = mc_filter[0] = 0;
958 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
959 i++, mclist = mclist->next) {
960 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
961
962 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
963 rx_mode |= AcceptMulticast;
964 }
965 }
966
967 /* We can safely update without stopping the chip. */
968 tmp = cp_rx_config | rx_mode;
969 if (cp->rx_config != tmp) {
970 cpw32_f (RxConfig, tmp);
971 cp->rx_config = tmp;
972 }
973 cpw32_f (MAR0 + 0, mc_filter[0]);
974 cpw32_f (MAR0 + 4, mc_filter[1]);
975 }
976
977 static void cp_set_rx_mode (struct net_device *dev)
978 {
979 unsigned long flags;
980 struct cp_private *cp = netdev_priv(dev);
981
982 spin_lock_irqsave (&cp->lock, flags);
983 __cp_set_rx_mode(dev);
984 spin_unlock_irqrestore (&cp->lock, flags);
985 }
986
987 static void __cp_get_stats(struct cp_private *cp)
988 {
989 /* only lower 24 bits valid; write any value to clear */
990 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
991 cpw32 (RxMissed, 0);
992 }
993
994 static struct net_device_stats *cp_get_stats(struct net_device *dev)
995 {
996 struct cp_private *cp = netdev_priv(dev);
997 unsigned long flags;
998
999 /* The chip only need report frame silently dropped. */
1000 spin_lock_irqsave(&cp->lock, flags);
1001 if (netif_running(dev) && netif_device_present(dev))
1002 __cp_get_stats(cp);
1003 spin_unlock_irqrestore(&cp->lock, flags);
1004
1005 return &cp->net_stats;
1006 }
1007
1008 static void cp_stop_hw (struct cp_private *cp)
1009 {
1010 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1011 cpw16_f(IntrMask, 0);
1012 cpw8(Cmd, 0);
1013 cpw16_f(CpCmd, 0);
1014 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1015
1016 cp->rx_tail = 0;
1017 cp->tx_head = cp->tx_tail = 0;
1018 }
1019
1020 static void cp_reset_hw (struct cp_private *cp)
1021 {
1022 unsigned work = 1000;
1023
1024 cpw8(Cmd, CmdReset);
1025
1026 while (work--) {
1027 if (!(cpr8(Cmd) & CmdReset))
1028 return;
1029
1030 schedule_timeout_uninterruptible(10);
1031 }
1032
1033 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1034 }
1035
1036 static inline void cp_start_hw (struct cp_private *cp)
1037 {
1038 cpw16(CpCmd, cp->cpcmd);
1039 cpw8(Cmd, RxOn | TxOn);
1040 }
1041
1042 static void cp_init_hw (struct cp_private *cp)
1043 {
1044 struct net_device *dev = cp->dev;
1045 dma_addr_t ring_dma;
1046
1047 cp_reset_hw(cp);
1048
1049 cpw8_f (Cfg9346, Cfg9346_Unlock);
1050
1051 /* Restore our idea of the MAC address. */
1052 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1053 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1054
1055 cp_start_hw(cp);
1056 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1057
1058 __cp_set_rx_mode(dev);
1059 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1060
1061 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1062 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1063 cpw8(Config3, PARMEnable);
1064 cp->wol_enabled = 0;
1065
1066 cpw8(Config5, cpr8(Config5) & PMEStatus);
1067
1068 cpw32_f(HiTxRingAddr, 0);
1069 cpw32_f(HiTxRingAddr + 4, 0);
1070
1071 ring_dma = cp->ring_dma;
1072 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1073 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1074
1075 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1076 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1077 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1078
1079 cpw16(MultiIntr, 0);
1080
1081 cpw16_f(IntrMask, cp_intr_mask);
1082
1083 cpw8_f(Cfg9346, Cfg9346_Lock);
1084 }
1085
1086 static int cp_refill_rx (struct cp_private *cp)
1087 {
1088 unsigned i;
1089
1090 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1091 struct sk_buff *skb;
1092
1093 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1094 if (!skb)
1095 goto err_out;
1096
1097 skb->dev = cp->dev;
1098 skb_reserve(skb, RX_OFFSET);
1099
1100 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1101 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1102 cp->rx_skb[i].skb = skb;
1103
1104 cp->rx_ring[i].opts2 = 0;
1105 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1106 if (i == (CP_RX_RING_SIZE - 1))
1107 cp->rx_ring[i].opts1 =
1108 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1109 else
1110 cp->rx_ring[i].opts1 =
1111 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1112 }
1113
1114 return 0;
1115
1116 err_out:
1117 cp_clean_rings(cp);
1118 return -ENOMEM;
1119 }
1120
1121 static int cp_init_rings (struct cp_private *cp)
1122 {
1123 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1124 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1125
1126 cp->rx_tail = 0;
1127 cp->tx_head = cp->tx_tail = 0;
1128
1129 return cp_refill_rx (cp);
1130 }
1131
1132 static int cp_alloc_rings (struct cp_private *cp)
1133 {
1134 void *mem;
1135
1136 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1137 if (!mem)
1138 return -ENOMEM;
1139
1140 cp->rx_ring = mem;
1141 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1142
1143 return cp_init_rings(cp);
1144 }
1145
1146 static void cp_clean_rings (struct cp_private *cp)
1147 {
1148 unsigned i;
1149
1150 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1151 if (cp->rx_skb[i].skb) {
1152 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1153 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1154 dev_kfree_skb(cp->rx_skb[i].skb);
1155 }
1156 }
1157
1158 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1159 if (cp->tx_skb[i].skb) {
1160 struct sk_buff *skb = cp->tx_skb[i].skb;
1161
1162 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1163 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1164 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1165 dev_kfree_skb(skb);
1166 cp->net_stats.tx_dropped++;
1167 }
1168 }
1169
1170 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1171 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1172
1173 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1174 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1175 }
1176
1177 static void cp_free_rings (struct cp_private *cp)
1178 {
1179 cp_clean_rings(cp);
1180 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1181 cp->rx_ring = NULL;
1182 cp->tx_ring = NULL;
1183 }
1184
1185 static int cp_open (struct net_device *dev)
1186 {
1187 struct cp_private *cp = netdev_priv(dev);
1188 int rc;
1189
1190 if (netif_msg_ifup(cp))
1191 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1192
1193 rc = cp_alloc_rings(cp);
1194 if (rc)
1195 return rc;
1196
1197 cp_init_hw(cp);
1198
1199 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1200 if (rc)
1201 goto err_out_hw;
1202
1203 netif_carrier_off(dev);
1204 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1205 netif_start_queue(dev);
1206
1207 return 0;
1208
1209 err_out_hw:
1210 cp_stop_hw(cp);
1211 cp_free_rings(cp);
1212 return rc;
1213 }
1214
1215 static int cp_close (struct net_device *dev)
1216 {
1217 struct cp_private *cp = netdev_priv(dev);
1218 unsigned long flags;
1219
1220 if (netif_msg_ifdown(cp))
1221 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1222
1223 spin_lock_irqsave(&cp->lock, flags);
1224
1225 netif_stop_queue(dev);
1226 netif_carrier_off(dev);
1227
1228 cp_stop_hw(cp);
1229
1230 spin_unlock_irqrestore(&cp->lock, flags);
1231
1232 synchronize_irq(dev->irq);
1233 free_irq(dev->irq, dev);
1234
1235 cp_free_rings(cp);
1236 return 0;
1237 }
1238
1239 #ifdef BROKEN
1240 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1241 {
1242 struct cp_private *cp = netdev_priv(dev);
1243 int rc;
1244 unsigned long flags;
1245
1246 /* check for invalid MTU, according to hardware limits */
1247 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1248 return -EINVAL;
1249
1250 /* if network interface not up, no need for complexity */
1251 if (!netif_running(dev)) {
1252 dev->mtu = new_mtu;
1253 cp_set_rxbufsize(cp); /* set new rx buf size */
1254 return 0;
1255 }
1256
1257 spin_lock_irqsave(&cp->lock, flags);
1258
1259 cp_stop_hw(cp); /* stop h/w and free rings */
1260 cp_clean_rings(cp);
1261
1262 dev->mtu = new_mtu;
1263 cp_set_rxbufsize(cp); /* set new rx buf size */
1264
1265 rc = cp_init_rings(cp); /* realloc and restart h/w */
1266 cp_start_hw(cp);
1267
1268 spin_unlock_irqrestore(&cp->lock, flags);
1269
1270 return rc;
1271 }
1272 #endif /* BROKEN */
1273
1274 static char mii_2_8139_map[8] = {
1275 BasicModeCtrl,
1276 BasicModeStatus,
1277 0,
1278 0,
1279 NWayAdvert,
1280 NWayLPAR,
1281 NWayExpansion,
1282 0
1283 };
1284
1285 static int mdio_read(struct net_device *dev, int phy_id, int location)
1286 {
1287 struct cp_private *cp = netdev_priv(dev);
1288
1289 return location < 8 && mii_2_8139_map[location] ?
1290 readw(cp->regs + mii_2_8139_map[location]) : 0;
1291 }
1292
1293
1294 static void mdio_write(struct net_device *dev, int phy_id, int location,
1295 int value)
1296 {
1297 struct cp_private *cp = netdev_priv(dev);
1298
1299 if (location == 0) {
1300 cpw8(Cfg9346, Cfg9346_Unlock);
1301 cpw16(BasicModeCtrl, value);
1302 cpw8(Cfg9346, Cfg9346_Lock);
1303 } else if (location < 8 && mii_2_8139_map[location])
1304 cpw16(mii_2_8139_map[location], value);
1305 }
1306
1307 /* Set the ethtool Wake-on-LAN settings */
1308 static int netdev_set_wol (struct cp_private *cp,
1309 const struct ethtool_wolinfo *wol)
1310 {
1311 u8 options;
1312
1313 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1314 /* If WOL is being disabled, no need for complexity */
1315 if (wol->wolopts) {
1316 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1317 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1318 }
1319
1320 cpw8 (Cfg9346, Cfg9346_Unlock);
1321 cpw8 (Config3, options);
1322 cpw8 (Cfg9346, Cfg9346_Lock);
1323
1324 options = 0; /* Paranoia setting */
1325 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1326 /* If WOL is being disabled, no need for complexity */
1327 if (wol->wolopts) {
1328 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1329 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1330 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1331 }
1332
1333 cpw8 (Config5, options);
1334
1335 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1336
1337 return 0;
1338 }
1339
1340 /* Get the ethtool Wake-on-LAN settings */
1341 static void netdev_get_wol (struct cp_private *cp,
1342 struct ethtool_wolinfo *wol)
1343 {
1344 u8 options;
1345
1346 wol->wolopts = 0; /* Start from scratch */
1347 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1348 WAKE_MCAST | WAKE_UCAST;
1349 /* We don't need to go on if WOL is disabled */
1350 if (!cp->wol_enabled) return;
1351
1352 options = cpr8 (Config3);
1353 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1354 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1355
1356 options = 0; /* Paranoia setting */
1357 options = cpr8 (Config5);
1358 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1359 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1360 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1361 }
1362
1363 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1364 {
1365 struct cp_private *cp = netdev_priv(dev);
1366
1367 strcpy (info->driver, DRV_NAME);
1368 strcpy (info->version, DRV_VERSION);
1369 strcpy (info->bus_info, pci_name(cp->pdev));
1370 }
1371
1372 static int cp_get_regs_len(struct net_device *dev)
1373 {
1374 return CP_REGS_SIZE;
1375 }
1376
1377 static int cp_get_stats_count (struct net_device *dev)
1378 {
1379 return CP_NUM_STATS;
1380 }
1381
1382 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1383 {
1384 struct cp_private *cp = netdev_priv(dev);
1385 int rc;
1386 unsigned long flags;
1387
1388 spin_lock_irqsave(&cp->lock, flags);
1389 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1390 spin_unlock_irqrestore(&cp->lock, flags);
1391
1392 return rc;
1393 }
1394
1395 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1396 {
1397 struct cp_private *cp = netdev_priv(dev);
1398 int rc;
1399 unsigned long flags;
1400
1401 spin_lock_irqsave(&cp->lock, flags);
1402 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1403 spin_unlock_irqrestore(&cp->lock, flags);
1404
1405 return rc;
1406 }
1407
1408 static int cp_nway_reset(struct net_device *dev)
1409 {
1410 struct cp_private *cp = netdev_priv(dev);
1411 return mii_nway_restart(&cp->mii_if);
1412 }
1413
1414 static u32 cp_get_msglevel(struct net_device *dev)
1415 {
1416 struct cp_private *cp = netdev_priv(dev);
1417 return cp->msg_enable;
1418 }
1419
1420 static void cp_set_msglevel(struct net_device *dev, u32 value)
1421 {
1422 struct cp_private *cp = netdev_priv(dev);
1423 cp->msg_enable = value;
1424 }
1425
1426 static u32 cp_get_rx_csum(struct net_device *dev)
1427 {
1428 struct cp_private *cp = netdev_priv(dev);
1429 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1430 }
1431
1432 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1433 {
1434 struct cp_private *cp = netdev_priv(dev);
1435 u16 cmd = cp->cpcmd, newcmd;
1436
1437 newcmd = cmd;
1438
1439 if (data)
1440 newcmd |= RxChkSum;
1441 else
1442 newcmd &= ~RxChkSum;
1443
1444 if (newcmd != cmd) {
1445 unsigned long flags;
1446
1447 spin_lock_irqsave(&cp->lock, flags);
1448 cp->cpcmd = newcmd;
1449 cpw16_f(CpCmd, newcmd);
1450 spin_unlock_irqrestore(&cp->lock, flags);
1451 }
1452
1453 return 0;
1454 }
1455
1456 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1457 void *p)
1458 {
1459 struct cp_private *cp = netdev_priv(dev);
1460 unsigned long flags;
1461
1462 if (regs->len < CP_REGS_SIZE)
1463 return /* -EINVAL */;
1464
1465 regs->version = CP_REGS_VER;
1466
1467 spin_lock_irqsave(&cp->lock, flags);
1468 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1469 spin_unlock_irqrestore(&cp->lock, flags);
1470 }
1471
1472 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1473 {
1474 struct cp_private *cp = netdev_priv(dev);
1475 unsigned long flags;
1476
1477 spin_lock_irqsave (&cp->lock, flags);
1478 netdev_get_wol (cp, wol);
1479 spin_unlock_irqrestore (&cp->lock, flags);
1480 }
1481
1482 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1483 {
1484 struct cp_private *cp = netdev_priv(dev);
1485 unsigned long flags;
1486 int rc;
1487
1488 spin_lock_irqsave (&cp->lock, flags);
1489 rc = netdev_set_wol (cp, wol);
1490 spin_unlock_irqrestore (&cp->lock, flags);
1491
1492 return rc;
1493 }
1494
1495 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1496 {
1497 switch (stringset) {
1498 case ETH_SS_STATS:
1499 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1500 break;
1501 default:
1502 BUG();
1503 break;
1504 }
1505 }
1506
1507 static void cp_get_ethtool_stats (struct net_device *dev,
1508 struct ethtool_stats *estats, u64 *tmp_stats)
1509 {
1510 struct cp_private *cp = netdev_priv(dev);
1511 struct cp_dma_stats *nic_stats;
1512 dma_addr_t dma;
1513 int i;
1514
1515 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1516 if (!nic_stats)
1517 return;
1518
1519 /* begin NIC statistics dump */
1520 cpw32(StatsAddr + 4, (u64)dma >> 32);
1521 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1522 cpr32(StatsAddr);
1523
1524 for (i = 0; i < 1000; i++) {
1525 if ((cpr32(StatsAddr) & DumpStats) == 0)
1526 break;
1527 udelay(10);
1528 }
1529 cpw32(StatsAddr, 0);
1530 cpw32(StatsAddr + 4, 0);
1531 cpr32(StatsAddr);
1532
1533 i = 0;
1534 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1535 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1536 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1537 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1538 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1539 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1540 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1541 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1543 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1544 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1545 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1546 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1547 tmp_stats[i++] = cp->cp_stats.rx_frags;
1548 if (i != CP_NUM_STATS)
1549 BUG();
1550
1551 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1552 }
1553
1554 static struct ethtool_ops cp_ethtool_ops = {
1555 .get_drvinfo = cp_get_drvinfo,
1556 .get_regs_len = cp_get_regs_len,
1557 .get_stats_count = cp_get_stats_count,
1558 .get_settings = cp_get_settings,
1559 .set_settings = cp_set_settings,
1560 .nway_reset = cp_nway_reset,
1561 .get_link = ethtool_op_get_link,
1562 .get_msglevel = cp_get_msglevel,
1563 .set_msglevel = cp_set_msglevel,
1564 .get_rx_csum = cp_get_rx_csum,
1565 .set_rx_csum = cp_set_rx_csum,
1566 .get_tx_csum = ethtool_op_get_tx_csum,
1567 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1568 .get_sg = ethtool_op_get_sg,
1569 .set_sg = ethtool_op_set_sg,
1570 .get_tso = ethtool_op_get_tso,
1571 .set_tso = ethtool_op_set_tso,
1572 .get_regs = cp_get_regs,
1573 .get_wol = cp_get_wol,
1574 .set_wol = cp_set_wol,
1575 .get_strings = cp_get_strings,
1576 .get_ethtool_stats = cp_get_ethtool_stats,
1577 .get_perm_addr = ethtool_op_get_perm_addr,
1578 };
1579
1580 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1581 {
1582 struct cp_private *cp = netdev_priv(dev);
1583 int rc;
1584 unsigned long flags;
1585
1586 if (!netif_running(dev))
1587 return -EINVAL;
1588
1589 spin_lock_irqsave(&cp->lock, flags);
1590 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1591 spin_unlock_irqrestore(&cp->lock, flags);
1592 return rc;
1593 }
1594
1595 /* Serial EEPROM section. */
1596
1597 /* EEPROM_Ctrl bits. */
1598 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1599 #define EE_CS 0x08 /* EEPROM chip select. */
1600 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1601 #define EE_WRITE_0 0x00
1602 #define EE_WRITE_1 0x02
1603 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1604 #define EE_ENB (0x80 | EE_CS)
1605
1606 /* Delay between EEPROM clock transitions.
1607 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1608 */
1609
1610 #define eeprom_delay() readl(ee_addr)
1611
1612 /* The EEPROM commands include the alway-set leading bit. */
1613 #define EE_WRITE_CMD (5)
1614 #define EE_READ_CMD (6)
1615 #define EE_ERASE_CMD (7)
1616
1617 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1618 {
1619 int i;
1620 unsigned retval = 0;
1621 void __iomem *ee_addr = ioaddr + Cfg9346;
1622 int read_cmd = location | (EE_READ_CMD << addr_len);
1623
1624 writeb (EE_ENB & ~EE_CS, ee_addr);
1625 writeb (EE_ENB, ee_addr);
1626 eeprom_delay ();
1627
1628 /* Shift the read command bits out. */
1629 for (i = 4 + addr_len; i >= 0; i--) {
1630 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1631 writeb (EE_ENB | dataval, ee_addr);
1632 eeprom_delay ();
1633 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1634 eeprom_delay ();
1635 }
1636 writeb (EE_ENB, ee_addr);
1637 eeprom_delay ();
1638
1639 for (i = 16; i > 0; i--) {
1640 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1641 eeprom_delay ();
1642 retval =
1643 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1644 0);
1645 writeb (EE_ENB, ee_addr);
1646 eeprom_delay ();
1647 }
1648
1649 /* Terminate the EEPROM access. */
1650 writeb (~EE_CS, ee_addr);
1651 eeprom_delay ();
1652
1653 return retval;
1654 }
1655
1656 /* Put the board into D3cold state and wait for WakeUp signal */
1657 static void cp_set_d3_state (struct cp_private *cp)
1658 {
1659 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1660 pci_set_power_state (cp->pdev, PCI_D3hot);
1661 }
1662
1663 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1664 {
1665 struct net_device *dev;
1666 struct cp_private *cp;
1667 int rc;
1668 void __iomem *regs;
1669 long pciaddr;
1670 unsigned int addr_len, i, pci_using_dac;
1671 u8 pci_rev;
1672
1673 #ifndef MODULE
1674 static int version_printed;
1675 if (version_printed++ == 0)
1676 printk("%s", version);
1677 #endif
1678
1679 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1680
1681 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1682 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1683 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1684 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1685 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1686 return -ENODEV;
1687 }
1688
1689 dev = alloc_etherdev(sizeof(struct cp_private));
1690 if (!dev)
1691 return -ENOMEM;
1692 SET_MODULE_OWNER(dev);
1693 SET_NETDEV_DEV(dev, &pdev->dev);
1694
1695 cp = netdev_priv(dev);
1696 cp->pdev = pdev;
1697 cp->dev = dev;
1698 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1699 spin_lock_init (&cp->lock);
1700 cp->mii_if.dev = dev;
1701 cp->mii_if.mdio_read = mdio_read;
1702 cp->mii_if.mdio_write = mdio_write;
1703 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1704 cp->mii_if.phy_id_mask = 0x1f;
1705 cp->mii_if.reg_num_mask = 0x1f;
1706 cp_set_rxbufsize(cp);
1707
1708 rc = pci_enable_device(pdev);
1709 if (rc)
1710 goto err_out_free;
1711
1712 rc = pci_set_mwi(pdev);
1713 if (rc)
1714 goto err_out_disable;
1715
1716 rc = pci_request_regions(pdev, DRV_NAME);
1717 if (rc)
1718 goto err_out_mwi;
1719
1720 pciaddr = pci_resource_start(pdev, 1);
1721 if (!pciaddr) {
1722 rc = -EIO;
1723 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1724 pci_name(pdev));
1725 goto err_out_res;
1726 }
1727 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1728 rc = -EIO;
1729 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1730 pci_resource_len(pdev, 1), pci_name(pdev));
1731 goto err_out_res;
1732 }
1733
1734 /* Configure DMA attributes. */
1735 if ((sizeof(dma_addr_t) > 4) &&
1736 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1737 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1738 pci_using_dac = 1;
1739 } else {
1740 pci_using_dac = 0;
1741
1742 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1743 if (rc) {
1744 printk(KERN_ERR PFX "No usable DMA configuration, "
1745 "aborting.\n");
1746 goto err_out_res;
1747 }
1748 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1749 if (rc) {
1750 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1751 "aborting.\n");
1752 goto err_out_res;
1753 }
1754 }
1755
1756 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1757 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1758
1759 regs = ioremap(pciaddr, CP_REGS_SIZE);
1760 if (!regs) {
1761 rc = -EIO;
1762 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1763 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1764 goto err_out_res;
1765 }
1766 dev->base_addr = (unsigned long) regs;
1767 cp->regs = regs;
1768
1769 cp_stop_hw(cp);
1770
1771 /* read MAC address from EEPROM */
1772 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1773 for (i = 0; i < 3; i++)
1774 ((u16 *) (dev->dev_addr))[i] =
1775 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1776 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1777
1778 dev->open = cp_open;
1779 dev->stop = cp_close;
1780 dev->set_multicast_list = cp_set_rx_mode;
1781 dev->hard_start_xmit = cp_start_xmit;
1782 dev->get_stats = cp_get_stats;
1783 dev->do_ioctl = cp_ioctl;
1784 dev->poll = cp_rx_poll;
1785 #ifdef CONFIG_NET_POLL_CONTROLLER
1786 dev->poll_controller = cp_poll_controller;
1787 #endif
1788 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1789 #ifdef BROKEN
1790 dev->change_mtu = cp_change_mtu;
1791 #endif
1792 dev->ethtool_ops = &cp_ethtool_ops;
1793 #if 0
1794 dev->tx_timeout = cp_tx_timeout;
1795 dev->watchdog_timeo = TX_TIMEOUT;
1796 #endif
1797
1798 #if CP_VLAN_TAG_USED
1799 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1800 dev->vlan_rx_register = cp_vlan_rx_register;
1801 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1802 #endif
1803
1804 if (pci_using_dac)
1805 dev->features |= NETIF_F_HIGHDMA;
1806
1807 #if 0 /* disabled by default until verified */
1808 dev->features |= NETIF_F_TSO;
1809 #endif
1810
1811 dev->irq = pdev->irq;
1812
1813 rc = register_netdev(dev);
1814 if (rc)
1815 goto err_out_iomap;
1816
1817 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1818 "%02x:%02x:%02x:%02x:%02x:%02x, "
1819 "IRQ %d\n",
1820 dev->name,
1821 dev->base_addr,
1822 dev->dev_addr[0], dev->dev_addr[1],
1823 dev->dev_addr[2], dev->dev_addr[3],
1824 dev->dev_addr[4], dev->dev_addr[5],
1825 dev->irq);
1826
1827 pci_set_drvdata(pdev, dev);
1828
1829 /* enable busmastering and memory-write-invalidate */
1830 pci_set_master(pdev);
1831
1832 if (cp->wol_enabled) cp_set_d3_state (cp);
1833
1834 return 0;
1835
1836 err_out_iomap:
1837 iounmap(regs);
1838 err_out_res:
1839 pci_release_regions(pdev);
1840 err_out_mwi:
1841 pci_clear_mwi(pdev);
1842 err_out_disable:
1843 pci_disable_device(pdev);
1844 err_out_free:
1845 free_netdev(dev);
1846 return rc;
1847 }
1848
1849 static void cp_remove_one (struct pci_dev *pdev)
1850 {
1851 struct net_device *dev = pci_get_drvdata(pdev);
1852 struct cp_private *cp = netdev_priv(dev);
1853
1854 if (!dev)
1855 BUG();
1856 unregister_netdev(dev);
1857 iounmap(cp->regs);
1858 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1859 pci_release_regions(pdev);
1860 pci_clear_mwi(pdev);
1861 pci_disable_device(pdev);
1862 pci_set_drvdata(pdev, NULL);
1863 free_netdev(dev);
1864 }
1865
1866 #ifdef CONFIG_PM
1867 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1868 {
1869 struct net_device *dev;
1870 struct cp_private *cp;
1871 unsigned long flags;
1872
1873 dev = pci_get_drvdata (pdev);
1874 cp = netdev_priv(dev);
1875
1876 if (!dev || !netif_running (dev)) return 0;
1877
1878 netif_device_detach (dev);
1879 netif_stop_queue (dev);
1880
1881 spin_lock_irqsave (&cp->lock, flags);
1882
1883 /* Disable Rx and Tx */
1884 cpw16 (IntrMask, 0);
1885 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1886
1887 spin_unlock_irqrestore (&cp->lock, flags);
1888
1889 if (cp->pdev && cp->wol_enabled) {
1890 pci_save_state (cp->pdev);
1891 cp_set_d3_state (cp);
1892 }
1893
1894 return 0;
1895 }
1896
1897 static int cp_resume (struct pci_dev *pdev)
1898 {
1899 struct net_device *dev;
1900 struct cp_private *cp;
1901 unsigned long flags;
1902
1903 dev = pci_get_drvdata (pdev);
1904 cp = netdev_priv(dev);
1905
1906 netif_device_attach (dev);
1907
1908 if (cp->pdev && cp->wol_enabled) {
1909 pci_set_power_state (cp->pdev, PCI_D0);
1910 pci_restore_state (cp->pdev);
1911 }
1912
1913 cp_init_hw (cp);
1914 netif_start_queue (dev);
1915
1916 spin_lock_irqsave (&cp->lock, flags);
1917
1918 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
1919
1920 spin_unlock_irqrestore (&cp->lock, flags);
1921
1922 return 0;
1923 }
1924 #endif /* CONFIG_PM */
1925
1926 static struct pci_driver cp_driver = {
1927 .name = DRV_NAME,
1928 .id_table = cp_pci_tbl,
1929 .probe = cp_init_one,
1930 .remove = cp_remove_one,
1931 #ifdef CONFIG_PM
1932 .resume = cp_resume,
1933 .suspend = cp_suspend,
1934 #endif
1935 };
1936
1937 static int __init cp_init (void)
1938 {
1939 #ifdef MODULE
1940 printk("%s", version);
1941 #endif
1942 return pci_module_init (&cp_driver);
1943 }
1944
1945 static void __exit cp_exit (void)
1946 {
1947 pci_unregister_driver (&cp_driver);
1948 }
1949
1950 module_init(cp_init);
1951 module_exit(cp_exit);
Linux kernel - Deliverables
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