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[netdrvr] Use dev_printk() when ethernet interface isn't available
[deliverable/linux.git] / drivers / net / 8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct net_device_stats stats;
577 unsigned char *rx_ring;
578 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t rx_ring_dma;
585 dma_addr_t tx_bufs_dma;
586 signed char phys[4]; /* MII device addresses. */
587 char twistie, twist_row, twist_col; /* Twister tune state. */
588 unsigned int watchdog_fired : 1;
589 unsigned int default_port : 4; /* Last dev->if_port value. */
590 unsigned int have_thread : 1;
591 spinlock_t lock;
592 spinlock_t rx_lock;
593 chip_t chipset;
594 u32 rx_config;
595 struct rtl_extra_stats xstats;
596
597 struct work_struct thread;
598
599 struct mii_if_info mii;
600 unsigned int regs_len;
601 unsigned long fifo_copy_timeout;
602 };
603
604 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
605 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
606 MODULE_LICENSE("GPL");
607 MODULE_VERSION(DRV_VERSION);
608
609 module_param(multicast_filter_limit, int, 0);
610 module_param_array(media, int, NULL, 0);
611 module_param_array(full_duplex, int, NULL, 0);
612 module_param(debug, int, 0);
613 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
614 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
615 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
616 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
617
618 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
619 static int rtl8139_open (struct net_device *dev);
620 static int mdio_read (struct net_device *dev, int phy_id, int location);
621 static void mdio_write (struct net_device *dev, int phy_id, int location,
622 int val);
623 static void rtl8139_start_thread(struct rtl8139_private *tp);
624 static void rtl8139_tx_timeout (struct net_device *dev);
625 static void rtl8139_init_ring (struct net_device *dev);
626 static int rtl8139_start_xmit (struct sk_buff *skb,
627 struct net_device *dev);
628 static int rtl8139_poll(struct net_device *dev, int *budget);
629 #ifdef CONFIG_NET_POLL_CONTROLLER
630 static void rtl8139_poll_controller(struct net_device *dev);
631 #endif
632 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
633 struct pt_regs *regs);
634 static int rtl8139_close (struct net_device *dev);
635 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
636 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
637 static void rtl8139_set_rx_mode (struct net_device *dev);
638 static void __set_rx_mode (struct net_device *dev);
639 static void rtl8139_hw_start (struct net_device *dev);
640 static void rtl8139_thread (void *_data);
641 static void rtl8139_tx_timeout_task(void *_data);
642 static struct ethtool_ops rtl8139_ethtool_ops;
643
644 /* write MMIO register, with flush */
645 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
646 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
647 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
648 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
649
650
651 #define MMIO_FLUSH_AUDIT_COMPLETE 1
652 #if MMIO_FLUSH_AUDIT_COMPLETE
653
654 /* write MMIO register */
655 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
656 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
657 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
658
659 #else
660
661 /* write MMIO register, then flush */
662 #define RTL_W8 RTL_W8_F
663 #define RTL_W16 RTL_W16_F
664 #define RTL_W32 RTL_W32_F
665
666 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
667
668 /* read MMIO register */
669 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
670 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
671 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
672
673
674 static const u16 rtl8139_intr_mask =
675 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
676 TxErr | TxOK | RxErr | RxOK;
677
678 static const u16 rtl8139_norx_intr_mask =
679 PCIErr | PCSTimeout | RxUnderrun |
680 TxErr | TxOK | RxErr ;
681
682 #if RX_BUF_IDX == 0
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv8K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 1
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv16K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 2
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv32K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #elif RX_BUF_IDX == 3
698 static const unsigned int rtl8139_rx_config =
699 RxCfgRcv64K |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702 #else
703 #error "Invalid configuration for 8139_RXBUF_IDX"
704 #endif
705
706 static const unsigned int rtl8139_tx_config =
707 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
708
709 static void __rtl8139_cleanup_dev (struct net_device *dev)
710 {
711 struct rtl8139_private *tp = netdev_priv(dev);
712 struct pci_dev *pdev;
713
714 assert (dev != NULL);
715 assert (tp->pci_dev != NULL);
716 pdev = tp->pci_dev;
717
718 #ifdef USE_IO_OPS
719 if (tp->mmio_addr)
720 ioport_unmap (tp->mmio_addr);
721 #else
722 if (tp->mmio_addr)
723 pci_iounmap (pdev, tp->mmio_addr);
724 #endif /* USE_IO_OPS */
725
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
728
729 free_netdev(dev);
730 pci_set_drvdata (pdev, NULL);
731 }
732
733
734 static void rtl8139_chip_reset (void __iomem *ioaddr)
735 {
736 int i;
737
738 /* Soft reset the chip. */
739 RTL_W8 (ChipCmd, CmdReset);
740
741 /* Check that the chip has finished the reset. */
742 for (i = 1000; i > 0; i--) {
743 barrier();
744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
745 break;
746 udelay (10);
747 }
748 }
749
750
751 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
752 struct net_device **dev_out)
753 {
754 void __iomem *ioaddr;
755 struct net_device *dev;
756 struct rtl8139_private *tp;
757 u8 tmp8;
758 int rc, disable_dev_on_err = 0;
759 unsigned int i;
760 unsigned long pio_start, pio_end, pio_flags, pio_len;
761 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
762 u32 version;
763
764 assert (pdev != NULL);
765
766 *dev_out = NULL;
767
768 /* dev and priv zeroed in alloc_etherdev */
769 dev = alloc_etherdev (sizeof (*tp));
770 if (dev == NULL) {
771 dev_printk (KERN_ERR, &pdev->dev,
772 "Unable to alloc new net device\n");
773 return -ENOMEM;
774 }
775 SET_MODULE_OWNER(dev);
776 SET_NETDEV_DEV(dev, &pdev->dev);
777
778 tp = netdev_priv(dev);
779 tp->pci_dev = pdev;
780
781 /* enable device (incl. PCI PM wakeup and hotplug setup) */
782 rc = pci_enable_device (pdev);
783 if (rc)
784 goto err_out;
785
786 pio_start = pci_resource_start (pdev, 0);
787 pio_end = pci_resource_end (pdev, 0);
788 pio_flags = pci_resource_flags (pdev, 0);
789 pio_len = pci_resource_len (pdev, 0);
790
791 mmio_start = pci_resource_start (pdev, 1);
792 mmio_end = pci_resource_end (pdev, 1);
793 mmio_flags = pci_resource_flags (pdev, 1);
794 mmio_len = pci_resource_len (pdev, 1);
795
796 /* set this immediately, we need to know before
797 * we talk to the chip directly */
798 DPRINTK("PIO region size == 0x%02X\n", pio_len);
799 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
800
801 #ifdef USE_IO_OPS
802 /* make sure PCI base addr 0 is PIO */
803 if (!(pio_flags & IORESOURCE_IO)) {
804 dev_printk (KERN_ERR, &pdev->dev,
805 "region #0 not a PIO resource, aborting\n");
806 rc = -ENODEV;
807 goto err_out;
808 }
809 /* check for weird/broken PCI region reporting */
810 if (pio_len < RTL_MIN_IO_SIZE) {
811 dev_printk (KERN_ERR, &pdev->dev,
812 "Invalid PCI I/O region size(s), aborting\n");
813 rc = -ENODEV;
814 goto err_out;
815 }
816 #else
817 /* make sure PCI base addr 1 is MMIO */
818 if (!(mmio_flags & IORESOURCE_MEM)) {
819 dev_printk (KERN_ERR, &pdev->dev,
820 "region #1 not an MMIO resource, aborting\n");
821 rc = -ENODEV;
822 goto err_out;
823 }
824 if (mmio_len < RTL_MIN_IO_SIZE) {
825 dev_printk (KERN_ERR, &pdev->dev,
826 "Invalid PCI mem region size(s), aborting\n");
827 rc = -ENODEV;
828 goto err_out;
829 }
830 #endif
831
832 rc = pci_request_regions (pdev, DRV_NAME);
833 if (rc)
834 goto err_out;
835 disable_dev_on_err = 1;
836
837 /* enable PCI bus-mastering */
838 pci_set_master (pdev);
839
840 #ifdef USE_IO_OPS
841 ioaddr = ioport_map(pio_start, pio_len);
842 if (!ioaddr) {
843 dev_printk (KERN_ERR, &pdev->dev, "cannot map PIO, aborting\n");
844 rc = -EIO;
845 goto err_out;
846 }
847 dev->base_addr = pio_start;
848 tp->mmio_addr = ioaddr;
849 tp->regs_len = pio_len;
850 #else
851 /* ioremap MMIO region */
852 ioaddr = pci_iomap(pdev, 1, 0);
853 if (ioaddr == NULL) {
854 dev_printk (KERN_ERR, &pdev->dev,
855 "cannot remap MMIO, aborting\n");
856 rc = -EIO;
857 goto err_out;
858 }
859 dev->base_addr = (long) ioaddr;
860 tp->mmio_addr = ioaddr;
861 tp->regs_len = mmio_len;
862 #endif /* USE_IO_OPS */
863
864 /* Bring old chips out of low-power mode. */
865 RTL_W8 (HltClk, 'R');
866
867 /* check for missing/broken hardware */
868 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
869 dev_printk (KERN_ERR, &pdev->dev,
870 "Chip not responding, ignoring board\n");
871 rc = -EIO;
872 goto err_out;
873 }
874
875 /* identify chip attached to board */
876 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
877 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
878 if (version == rtl_chip_info[i].version) {
879 tp->chipset = i;
880 goto match;
881 }
882
883 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
884 dev_printk (KERN_DEBUG, &pdev->dev,
885 "unknown chip version, assuming RTL-8139\n");
886 dev_printk (KERN_DEBUG, &pdev->dev,
887 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
888 tp->chipset = 0;
889
890 match:
891 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
892 version, i, rtl_chip_info[i].name);
893
894 if (tp->chipset >= CH_8139B) {
895 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
896 DPRINTK("PCI PM wakeup\n");
897 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
898 (tmp8 & LWAKE))
899 new_tmp8 &= ~LWAKE;
900 new_tmp8 |= Cfg1_PM_Enable;
901 if (new_tmp8 != tmp8) {
902 RTL_W8 (Cfg9346, Cfg9346_Unlock);
903 RTL_W8 (Config1, tmp8);
904 RTL_W8 (Cfg9346, Cfg9346_Lock);
905 }
906 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
907 tmp8 = RTL_R8 (Config4);
908 if (tmp8 & LWPTN) {
909 RTL_W8 (Cfg9346, Cfg9346_Unlock);
910 RTL_W8 (Config4, tmp8 & ~LWPTN);
911 RTL_W8 (Cfg9346, Cfg9346_Lock);
912 }
913 }
914 } else {
915 DPRINTK("Old chip wakeup\n");
916 tmp8 = RTL_R8 (Config1);
917 tmp8 &= ~(SLEEP | PWRDN);
918 RTL_W8 (Config1, tmp8);
919 }
920
921 rtl8139_chip_reset (ioaddr);
922
923 *dev_out = dev;
924 return 0;
925
926 err_out:
927 __rtl8139_cleanup_dev (dev);
928 if (disable_dev_on_err)
929 pci_disable_device (pdev);
930 return rc;
931 }
932
933
934 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
935 const struct pci_device_id *ent)
936 {
937 struct net_device *dev = NULL;
938 struct rtl8139_private *tp;
939 int i, addr_len, option;
940 void __iomem *ioaddr;
941 static int board_idx = -1;
942 u8 pci_rev;
943
944 assert (pdev != NULL);
945 assert (ent != NULL);
946
947 board_idx++;
948
949 /* when we're built into the kernel, the driver version message
950 * is only printed if at least one 8139 board has been found
951 */
952 #ifndef MODULE
953 {
954 static int printed_version;
955 if (!printed_version++)
956 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
957 }
958 #endif
959
960 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
961
962 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
963 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
964 dev_printk(KERN_INFO, &pdev->dev,
965 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
966 pdev->vendor, pdev->device, pci_rev);
967 dev_printk(KERN_INFO, &pdev->dev,
968 "Use the \"8139cp\" driver for improved performance and stability.\n");
969 }
970
971 i = rtl8139_init_board (pdev, &dev);
972 if (i < 0)
973 return i;
974
975 assert (dev != NULL);
976 tp = netdev_priv(dev);
977
978 ioaddr = tp->mmio_addr;
979 assert (ioaddr != NULL);
980
981 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
982 for (i = 0; i < 3; i++)
983 ((u16 *) (dev->dev_addr))[i] =
984 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
985 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
986
987 /* The Rtl8139-specific entries in the device structure. */
988 dev->open = rtl8139_open;
989 dev->hard_start_xmit = rtl8139_start_xmit;
990 dev->poll = rtl8139_poll;
991 dev->weight = 64;
992 dev->stop = rtl8139_close;
993 dev->get_stats = rtl8139_get_stats;
994 dev->set_multicast_list = rtl8139_set_rx_mode;
995 dev->do_ioctl = netdev_ioctl;
996 dev->ethtool_ops = &rtl8139_ethtool_ops;
997 dev->tx_timeout = rtl8139_tx_timeout;
998 dev->watchdog_timeo = TX_TIMEOUT;
999 #ifdef CONFIG_NET_POLL_CONTROLLER
1000 dev->poll_controller = rtl8139_poll_controller;
1001 #endif
1002
1003 /* note: the hardware is not capable of sg/csum/highdma, however
1004 * through the use of skb_copy_and_csum_dev we enable these
1005 * features
1006 */
1007 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1008
1009 dev->irq = pdev->irq;
1010
1011 /* tp zeroed and aligned in alloc_etherdev */
1012 tp = netdev_priv(dev);
1013
1014 /* note: tp->chipset set in rtl8139_init_board */
1015 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1016 tp->mmio_addr = ioaddr;
1017 tp->msg_enable =
1018 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1019 spin_lock_init (&tp->lock);
1020 spin_lock_init (&tp->rx_lock);
1021 INIT_WORK(&tp->thread, rtl8139_thread, dev);
1022 tp->mii.dev = dev;
1023 tp->mii.mdio_read = mdio_read;
1024 tp->mii.mdio_write = mdio_write;
1025 tp->mii.phy_id_mask = 0x3f;
1026 tp->mii.reg_num_mask = 0x1f;
1027
1028 /* dev is fully set up and ready to use now */
1029 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1030 i = register_netdev (dev);
1031 if (i) goto err_out;
1032
1033 pci_set_drvdata (pdev, dev);
1034
1035 printk (KERN_INFO "%s: %s at 0x%lx, "
1036 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1037 "IRQ %d\n",
1038 dev->name,
1039 board_info[ent->driver_data].name,
1040 dev->base_addr,
1041 dev->dev_addr[0], dev->dev_addr[1],
1042 dev->dev_addr[2], dev->dev_addr[3],
1043 dev->dev_addr[4], dev->dev_addr[5],
1044 dev->irq);
1045
1046 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1047 dev->name, rtl_chip_info[tp->chipset].name);
1048
1049 /* Find the connected MII xcvrs.
1050 Doing this in open() would allow detecting external xcvrs later, but
1051 takes too much time. */
1052 #ifdef CONFIG_8139TOO_8129
1053 if (tp->drv_flags & HAS_MII_XCVR) {
1054 int phy, phy_idx = 0;
1055 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1056 int mii_status = mdio_read(dev, phy, 1);
1057 if (mii_status != 0xffff && mii_status != 0x0000) {
1058 u16 advertising = mdio_read(dev, phy, 4);
1059 tp->phys[phy_idx++] = phy;
1060 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1061 "advertising %4.4x.\n",
1062 dev->name, phy, mii_status, advertising);
1063 }
1064 }
1065 if (phy_idx == 0) {
1066 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1067 "transceiver.\n",
1068 dev->name);
1069 tp->phys[0] = 32;
1070 }
1071 } else
1072 #endif
1073 tp->phys[0] = 32;
1074 tp->mii.phy_id = tp->phys[0];
1075
1076 /* The lower four bits are the media type. */
1077 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1078 if (option > 0) {
1079 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1080 tp->default_port = option & 0xFF;
1081 if (tp->default_port)
1082 tp->mii.force_media = 1;
1083 }
1084 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1085 tp->mii.full_duplex = full_duplex[board_idx];
1086 if (tp->mii.full_duplex) {
1087 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1088 /* Changing the MII-advertised media because might prevent
1089 re-connection. */
1090 tp->mii.force_media = 1;
1091 }
1092 if (tp->default_port) {
1093 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1094 (option & 0x20 ? 100 : 10),
1095 (option & 0x10 ? "full" : "half"));
1096 mdio_write(dev, tp->phys[0], 0,
1097 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1098 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1099 }
1100
1101 /* Put the chip into low-power mode. */
1102 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1103 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1104
1105 return 0;
1106
1107 err_out:
1108 __rtl8139_cleanup_dev (dev);
1109 pci_disable_device (pdev);
1110 return i;
1111 }
1112
1113
1114 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1115 {
1116 struct net_device *dev = pci_get_drvdata (pdev);
1117
1118 assert (dev != NULL);
1119
1120 unregister_netdev (dev);
1121
1122 __rtl8139_cleanup_dev (dev);
1123 pci_disable_device (pdev);
1124 }
1125
1126
1127 /* Serial EEPROM section. */
1128
1129 /* EEPROM_Ctrl bits. */
1130 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1131 #define EE_CS 0x08 /* EEPROM chip select. */
1132 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1133 #define EE_WRITE_0 0x00
1134 #define EE_WRITE_1 0x02
1135 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1136 #define EE_ENB (0x80 | EE_CS)
1137
1138 /* Delay between EEPROM clock transitions.
1139 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1140 */
1141
1142 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1143
1144 /* The EEPROM commands include the alway-set leading bit. */
1145 #define EE_WRITE_CMD (5)
1146 #define EE_READ_CMD (6)
1147 #define EE_ERASE_CMD (7)
1148
1149 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1150 {
1151 int i;
1152 unsigned retval = 0;
1153 int read_cmd = location | (EE_READ_CMD << addr_len);
1154
1155 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1156 RTL_W8 (Cfg9346, EE_ENB);
1157 eeprom_delay ();
1158
1159 /* Shift the read command bits out. */
1160 for (i = 4 + addr_len; i >= 0; i--) {
1161 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1162 RTL_W8 (Cfg9346, EE_ENB | dataval);
1163 eeprom_delay ();
1164 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1165 eeprom_delay ();
1166 }
1167 RTL_W8 (Cfg9346, EE_ENB);
1168 eeprom_delay ();
1169
1170 for (i = 16; i > 0; i--) {
1171 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1172 eeprom_delay ();
1173 retval =
1174 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1175 0);
1176 RTL_W8 (Cfg9346, EE_ENB);
1177 eeprom_delay ();
1178 }
1179
1180 /* Terminate the EEPROM access. */
1181 RTL_W8 (Cfg9346, ~EE_CS);
1182 eeprom_delay ();
1183
1184 return retval;
1185 }
1186
1187 /* MII serial management: mostly bogus for now. */
1188 /* Read and write the MII management registers using software-generated
1189 serial MDIO protocol.
1190 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1191 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1192 "overclocking" issues. */
1193 #define MDIO_DIR 0x80
1194 #define MDIO_DATA_OUT 0x04
1195 #define MDIO_DATA_IN 0x02
1196 #define MDIO_CLK 0x01
1197 #define MDIO_WRITE0 (MDIO_DIR)
1198 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1199
1200 #define mdio_delay() RTL_R8(Config4)
1201
1202
1203 static const char mii_2_8139_map[8] = {
1204 BasicModeCtrl,
1205 BasicModeStatus,
1206 0,
1207 0,
1208 NWayAdvert,
1209 NWayLPAR,
1210 NWayExpansion,
1211 0
1212 };
1213
1214
1215 #ifdef CONFIG_8139TOO_8129
1216 /* Syncronize the MII management interface by shifting 32 one bits out. */
1217 static void mdio_sync (void __iomem *ioaddr)
1218 {
1219 int i;
1220
1221 for (i = 32; i >= 0; i--) {
1222 RTL_W8 (Config4, MDIO_WRITE1);
1223 mdio_delay ();
1224 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1225 mdio_delay ();
1226 }
1227 }
1228 #endif
1229
1230 static int mdio_read (struct net_device *dev, int phy_id, int location)
1231 {
1232 struct rtl8139_private *tp = netdev_priv(dev);
1233 int retval = 0;
1234 #ifdef CONFIG_8139TOO_8129
1235 void __iomem *ioaddr = tp->mmio_addr;
1236 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1237 int i;
1238 #endif
1239
1240 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 return location < 8 && mii_2_8139_map[location] ?
1243 RTL_R16 (mii_2_8139_map[location]) : 0;
1244 }
1245
1246 #ifdef CONFIG_8139TOO_8129
1247 mdio_sync (ioaddr);
1248 /* Shift the read command bits out. */
1249 for (i = 15; i >= 0; i--) {
1250 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1251
1252 RTL_W8 (Config4, MDIO_DIR | dataval);
1253 mdio_delay ();
1254 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1255 mdio_delay ();
1256 }
1257
1258 /* Read the two transition, 16 data, and wire-idle bits. */
1259 for (i = 19; i > 0; i--) {
1260 RTL_W8 (Config4, 0);
1261 mdio_delay ();
1262 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1263 RTL_W8 (Config4, MDIO_CLK);
1264 mdio_delay ();
1265 }
1266 #endif
1267
1268 return (retval >> 1) & 0xffff;
1269 }
1270
1271
1272 static void mdio_write (struct net_device *dev, int phy_id, int location,
1273 int value)
1274 {
1275 struct rtl8139_private *tp = netdev_priv(dev);
1276 #ifdef CONFIG_8139TOO_8129
1277 void __iomem *ioaddr = tp->mmio_addr;
1278 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1279 int i;
1280 #endif
1281
1282 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1283 void __iomem *ioaddr = tp->mmio_addr;
1284 if (location == 0) {
1285 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1286 RTL_W16 (BasicModeCtrl, value);
1287 RTL_W8 (Cfg9346, Cfg9346_Lock);
1288 } else if (location < 8 && mii_2_8139_map[location])
1289 RTL_W16 (mii_2_8139_map[location], value);
1290 return;
1291 }
1292
1293 #ifdef CONFIG_8139TOO_8129
1294 mdio_sync (ioaddr);
1295
1296 /* Shift the command bits out. */
1297 for (i = 31; i >= 0; i--) {
1298 int dataval =
1299 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1300 RTL_W8 (Config4, dataval);
1301 mdio_delay ();
1302 RTL_W8 (Config4, dataval | MDIO_CLK);
1303 mdio_delay ();
1304 }
1305 /* Clear out extra bits. */
1306 for (i = 2; i > 0; i--) {
1307 RTL_W8 (Config4, 0);
1308 mdio_delay ();
1309 RTL_W8 (Config4, MDIO_CLK);
1310 mdio_delay ();
1311 }
1312 #endif
1313 }
1314
1315
1316 static int rtl8139_open (struct net_device *dev)
1317 {
1318 struct rtl8139_private *tp = netdev_priv(dev);
1319 int retval;
1320 void __iomem *ioaddr = tp->mmio_addr;
1321
1322 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1323 if (retval)
1324 return retval;
1325
1326 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1327 &tp->tx_bufs_dma);
1328 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1329 &tp->rx_ring_dma);
1330 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1331 free_irq(dev->irq, dev);
1332
1333 if (tp->tx_bufs)
1334 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1335 tp->tx_bufs, tp->tx_bufs_dma);
1336 if (tp->rx_ring)
1337 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1338 tp->rx_ring, tp->rx_ring_dma);
1339
1340 return -ENOMEM;
1341
1342 }
1343
1344 tp->mii.full_duplex = tp->mii.force_media;
1345 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1346
1347 rtl8139_init_ring (dev);
1348 rtl8139_hw_start (dev);
1349 netif_start_queue (dev);
1350
1351 if (netif_msg_ifup(tp))
1352 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1353 " GP Pins %2.2x %s-duplex.\n", dev->name,
1354 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1355 dev->irq, RTL_R8 (MediaStatus),
1356 tp->mii.full_duplex ? "full" : "half");
1357
1358 rtl8139_start_thread(tp);
1359
1360 return 0;
1361 }
1362
1363
1364 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1365 {
1366 struct rtl8139_private *tp = netdev_priv(dev);
1367
1368 if (tp->phys[0] >= 0) {
1369 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1370 }
1371 }
1372
1373 /* Start the hardware at open or resume. */
1374 static void rtl8139_hw_start (struct net_device *dev)
1375 {
1376 struct rtl8139_private *tp = netdev_priv(dev);
1377 void __iomem *ioaddr = tp->mmio_addr;
1378 u32 i;
1379 u8 tmp;
1380
1381 /* Bring old chips out of low-power mode. */
1382 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1383 RTL_W8 (HltClk, 'R');
1384
1385 rtl8139_chip_reset (ioaddr);
1386
1387 /* unlock Config[01234] and BMCR register writes */
1388 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1389 /* Restore our idea of the MAC address. */
1390 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1391 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1392
1393 /* Must enable Tx/Rx before setting transfer thresholds! */
1394 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1395
1396 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1397 RTL_W32 (RxConfig, tp->rx_config);
1398 RTL_W32 (TxConfig, rtl8139_tx_config);
1399
1400 tp->cur_rx = 0;
1401
1402 rtl_check_media (dev, 1);
1403
1404 if (tp->chipset >= CH_8139B) {
1405 /* Disable magic packet scanning, which is enabled
1406 * when PM is enabled in Config1. It can be reenabled
1407 * via ETHTOOL_SWOL if desired. */
1408 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1409 }
1410
1411 DPRINTK("init buffer addresses\n");
1412
1413 /* Lock Config[01234] and BMCR register writes */
1414 RTL_W8 (Cfg9346, Cfg9346_Lock);
1415
1416 /* init Rx ring buffer DMA address */
1417 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1418
1419 /* init Tx buffer DMA addresses */
1420 for (i = 0; i < NUM_TX_DESC; i++)
1421 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1422
1423 RTL_W32 (RxMissed, 0);
1424
1425 rtl8139_set_rx_mode (dev);
1426
1427 /* no early-rx interrupts */
1428 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1429
1430 /* make sure RxTx has started */
1431 tmp = RTL_R8 (ChipCmd);
1432 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1433 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1434
1435 /* Enable all known interrupts by setting the interrupt mask. */
1436 RTL_W16 (IntrMask, rtl8139_intr_mask);
1437 }
1438
1439
1440 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1441 static void rtl8139_init_ring (struct net_device *dev)
1442 {
1443 struct rtl8139_private *tp = netdev_priv(dev);
1444 int i;
1445
1446 tp->cur_rx = 0;
1447 tp->cur_tx = 0;
1448 tp->dirty_tx = 0;
1449
1450 for (i = 0; i < NUM_TX_DESC; i++)
1451 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1452 }
1453
1454
1455 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1456 static int next_tick = 3 * HZ;
1457
1458 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1459 static inline void rtl8139_tune_twister (struct net_device *dev,
1460 struct rtl8139_private *tp) {}
1461 #else
1462 enum TwisterParamVals {
1463 PARA78_default = 0x78fa8388,
1464 PARA7c_default = 0xcb38de43, /* param[0][3] */
1465 PARA7c_xxx = 0xcb38de43,
1466 };
1467
1468 static const unsigned long param[4][4] = {
1469 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1470 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1471 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1472 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1473 };
1474
1475 static void rtl8139_tune_twister (struct net_device *dev,
1476 struct rtl8139_private *tp)
1477 {
1478 int linkcase;
1479 void __iomem *ioaddr = tp->mmio_addr;
1480
1481 /* This is a complicated state machine to configure the "twister" for
1482 impedance/echos based on the cable length.
1483 All of this is magic and undocumented.
1484 */
1485 switch (tp->twistie) {
1486 case 1:
1487 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1488 /* We have link beat, let us tune the twister. */
1489 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1490 tp->twistie = 2; /* Change to state 2. */
1491 next_tick = HZ / 10;
1492 } else {
1493 /* Just put in some reasonable defaults for when beat returns. */
1494 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1495 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1496 RTL_W32 (PARA78, PARA78_default);
1497 RTL_W32 (PARA7c, PARA7c_default);
1498 tp->twistie = 0; /* Bail from future actions. */
1499 }
1500 break;
1501 case 2:
1502 /* Read how long it took to hear the echo. */
1503 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1504 if (linkcase == 0x7000)
1505 tp->twist_row = 3;
1506 else if (linkcase == 0x3000)
1507 tp->twist_row = 2;
1508 else if (linkcase == 0x1000)
1509 tp->twist_row = 1;
1510 else
1511 tp->twist_row = 0;
1512 tp->twist_col = 0;
1513 tp->twistie = 3; /* Change to state 2. */
1514 next_tick = HZ / 10;
1515 break;
1516 case 3:
1517 /* Put out four tuning parameters, one per 100msec. */
1518 if (tp->twist_col == 0)
1519 RTL_W16 (FIFOTMS, 0);
1520 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1521 [(int) tp->twist_col]);
1522 next_tick = HZ / 10;
1523 if (++tp->twist_col >= 4) {
1524 /* For short cables we are done.
1525 For long cables (row == 3) check for mistune. */
1526 tp->twistie =
1527 (tp->twist_row == 3) ? 4 : 0;
1528 }
1529 break;
1530 case 4:
1531 /* Special case for long cables: check for mistune. */
1532 if ((RTL_R16 (CSCR) &
1533 CSCR_LinkStatusBits) == 0x7000) {
1534 tp->twistie = 0;
1535 break;
1536 } else {
1537 RTL_W32 (PARA7c, 0xfb38de03);
1538 tp->twistie = 5;
1539 next_tick = HZ / 10;
1540 }
1541 break;
1542 case 5:
1543 /* Retune for shorter cable (column 2). */
1544 RTL_W32 (FIFOTMS, 0x20);
1545 RTL_W32 (PARA78, PARA78_default);
1546 RTL_W32 (PARA7c, PARA7c_default);
1547 RTL_W32 (FIFOTMS, 0x00);
1548 tp->twist_row = 2;
1549 tp->twist_col = 0;
1550 tp->twistie = 3;
1551 next_tick = HZ / 10;
1552 break;
1553
1554 default:
1555 /* do nothing */
1556 break;
1557 }
1558 }
1559 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1560
1561 static inline void rtl8139_thread_iter (struct net_device *dev,
1562 struct rtl8139_private *tp,
1563 void __iomem *ioaddr)
1564 {
1565 int mii_lpa;
1566
1567 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1568
1569 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1570 int duplex = (mii_lpa & LPA_100FULL)
1571 || (mii_lpa & 0x01C0) == 0x0040;
1572 if (tp->mii.full_duplex != duplex) {
1573 tp->mii.full_duplex = duplex;
1574
1575 if (mii_lpa) {
1576 printk (KERN_INFO
1577 "%s: Setting %s-duplex based on MII #%d link"
1578 " partner ability of %4.4x.\n",
1579 dev->name,
1580 tp->mii.full_duplex ? "full" : "half",
1581 tp->phys[0], mii_lpa);
1582 } else {
1583 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1584 dev->name);
1585 }
1586 #if 0
1587 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1588 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1589 RTL_W8 (Cfg9346, Cfg9346_Lock);
1590 #endif
1591 }
1592 }
1593
1594 next_tick = HZ * 60;
1595
1596 rtl8139_tune_twister (dev, tp);
1597
1598 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1599 dev->name, RTL_R16 (NWayLPAR));
1600 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1601 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1602 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1603 dev->name, RTL_R8 (Config0),
1604 RTL_R8 (Config1));
1605 }
1606
1607 static void rtl8139_thread (void *_data)
1608 {
1609 struct net_device *dev = _data;
1610 struct rtl8139_private *tp = netdev_priv(dev);
1611 unsigned long thr_delay = next_tick;
1612
1613 if (tp->watchdog_fired) {
1614 tp->watchdog_fired = 0;
1615 rtl8139_tx_timeout_task(_data);
1616 } else if (rtnl_trylock()) {
1617 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1618 rtnl_unlock ();
1619 } else {
1620 /* unlikely race. mitigate with fast poll. */
1621 thr_delay = HZ / 2;
1622 }
1623
1624 schedule_delayed_work(&tp->thread, thr_delay);
1625 }
1626
1627 static void rtl8139_start_thread(struct rtl8139_private *tp)
1628 {
1629 tp->twistie = 0;
1630 if (tp->chipset == CH_8139_K)
1631 tp->twistie = 1;
1632 else if (tp->drv_flags & HAS_LNK_CHNG)
1633 return;
1634
1635 tp->have_thread = 1;
1636
1637 schedule_delayed_work(&tp->thread, next_tick);
1638 }
1639
1640 static void rtl8139_stop_thread(struct rtl8139_private *tp)
1641 {
1642 if (tp->have_thread) {
1643 cancel_rearming_delayed_work(&tp->thread);
1644 tp->have_thread = 0;
1645 } else
1646 flush_scheduled_work();
1647 }
1648
1649 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1650 {
1651 tp->cur_tx = 0;
1652 tp->dirty_tx = 0;
1653
1654 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1655 }
1656
1657 static void rtl8139_tx_timeout_task (void *_data)
1658 {
1659 struct net_device *dev = _data;
1660 struct rtl8139_private *tp = netdev_priv(dev);
1661 void __iomem *ioaddr = tp->mmio_addr;
1662 int i;
1663 u8 tmp8;
1664
1665 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1666 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1667 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1668 /* Emit info to figure out what went wrong. */
1669 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1670 dev->name, tp->cur_tx, tp->dirty_tx);
1671 for (i = 0; i < NUM_TX_DESC; i++)
1672 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1673 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1674 i == tp->dirty_tx % NUM_TX_DESC ?
1675 " (queue head)" : "");
1676
1677 tp->xstats.tx_timeouts++;
1678
1679 /* disable Tx ASAP, if not already */
1680 tmp8 = RTL_R8 (ChipCmd);
1681 if (tmp8 & CmdTxEnb)
1682 RTL_W8 (ChipCmd, CmdRxEnb);
1683
1684 spin_lock_bh(&tp->rx_lock);
1685 /* Disable interrupts by clearing the interrupt mask. */
1686 RTL_W16 (IntrMask, 0x0000);
1687
1688 /* Stop a shared interrupt from scavenging while we are. */
1689 spin_lock_irq(&tp->lock);
1690 rtl8139_tx_clear (tp);
1691 spin_unlock_irq(&tp->lock);
1692
1693 /* ...and finally, reset everything */
1694 if (netif_running(dev)) {
1695 rtl8139_hw_start (dev);
1696 netif_wake_queue (dev);
1697 }
1698 spin_unlock_bh(&tp->rx_lock);
1699 }
1700
1701 static void rtl8139_tx_timeout (struct net_device *dev)
1702 {
1703 struct rtl8139_private *tp = netdev_priv(dev);
1704
1705 if (!tp->have_thread) {
1706 INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
1707 schedule_delayed_work(&tp->thread, next_tick);
1708 } else
1709 tp->watchdog_fired = 1;
1710
1711 }
1712
1713 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1714 {
1715 struct rtl8139_private *tp = netdev_priv(dev);
1716 void __iomem *ioaddr = tp->mmio_addr;
1717 unsigned int entry;
1718 unsigned int len = skb->len;
1719
1720 /* Calculate the next Tx descriptor entry. */
1721 entry = tp->cur_tx % NUM_TX_DESC;
1722
1723 /* Note: the chip doesn't have auto-pad! */
1724 if (likely(len < TX_BUF_SIZE)) {
1725 if (len < ETH_ZLEN)
1726 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1727 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1728 dev_kfree_skb(skb);
1729 } else {
1730 dev_kfree_skb(skb);
1731 tp->stats.tx_dropped++;
1732 return 0;
1733 }
1734
1735 spin_lock_irq(&tp->lock);
1736 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1737 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1738
1739 dev->trans_start = jiffies;
1740
1741 tp->cur_tx++;
1742 wmb();
1743
1744 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1745 netif_stop_queue (dev);
1746 spin_unlock_irq(&tp->lock);
1747
1748 if (netif_msg_tx_queued(tp))
1749 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1750 dev->name, len, entry);
1751
1752 return 0;
1753 }
1754
1755
1756 static void rtl8139_tx_interrupt (struct net_device *dev,
1757 struct rtl8139_private *tp,
1758 void __iomem *ioaddr)
1759 {
1760 unsigned long dirty_tx, tx_left;
1761
1762 assert (dev != NULL);
1763 assert (ioaddr != NULL);
1764
1765 dirty_tx = tp->dirty_tx;
1766 tx_left = tp->cur_tx - dirty_tx;
1767 while (tx_left > 0) {
1768 int entry = dirty_tx % NUM_TX_DESC;
1769 int txstatus;
1770
1771 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1772
1773 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1774 break; /* It still hasn't been Txed */
1775
1776 /* Note: TxCarrierLost is always asserted at 100mbps. */
1777 if (txstatus & (TxOutOfWindow | TxAborted)) {
1778 /* There was an major error, log it. */
1779 if (netif_msg_tx_err(tp))
1780 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1781 dev->name, txstatus);
1782 tp->stats.tx_errors++;
1783 if (txstatus & TxAborted) {
1784 tp->stats.tx_aborted_errors++;
1785 RTL_W32 (TxConfig, TxClearAbt);
1786 RTL_W16 (IntrStatus, TxErr);
1787 wmb();
1788 }
1789 if (txstatus & TxCarrierLost)
1790 tp->stats.tx_carrier_errors++;
1791 if (txstatus & TxOutOfWindow)
1792 tp->stats.tx_window_errors++;
1793 } else {
1794 if (txstatus & TxUnderrun) {
1795 /* Add 64 to the Tx FIFO threshold. */
1796 if (tp->tx_flag < 0x00300000)
1797 tp->tx_flag += 0x00020000;
1798 tp->stats.tx_fifo_errors++;
1799 }
1800 tp->stats.collisions += (txstatus >> 24) & 15;
1801 tp->stats.tx_bytes += txstatus & 0x7ff;
1802 tp->stats.tx_packets++;
1803 }
1804
1805 dirty_tx++;
1806 tx_left--;
1807 }
1808
1809 #ifndef RTL8139_NDEBUG
1810 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1811 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1812 dev->name, dirty_tx, tp->cur_tx);
1813 dirty_tx += NUM_TX_DESC;
1814 }
1815 #endif /* RTL8139_NDEBUG */
1816
1817 /* only wake the queue if we did work, and the queue is stopped */
1818 if (tp->dirty_tx != dirty_tx) {
1819 tp->dirty_tx = dirty_tx;
1820 mb();
1821 netif_wake_queue (dev);
1822 }
1823 }
1824
1825
1826 /* TODO: clean this up! Rx reset need not be this intensive */
1827 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1828 struct rtl8139_private *tp, void __iomem *ioaddr)
1829 {
1830 u8 tmp8;
1831 #ifdef CONFIG_8139_OLD_RX_RESET
1832 int tmp_work;
1833 #endif
1834
1835 if (netif_msg_rx_err (tp))
1836 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1837 dev->name, rx_status);
1838 tp->stats.rx_errors++;
1839 if (!(rx_status & RxStatusOK)) {
1840 if (rx_status & RxTooLong) {
1841 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1842 dev->name, rx_status);
1843 /* A.C.: The chip hangs here. */
1844 }
1845 if (rx_status & (RxBadSymbol | RxBadAlign))
1846 tp->stats.rx_frame_errors++;
1847 if (rx_status & (RxRunt | RxTooLong))
1848 tp->stats.rx_length_errors++;
1849 if (rx_status & RxCRCErr)
1850 tp->stats.rx_crc_errors++;
1851 } else {
1852 tp->xstats.rx_lost_in_ring++;
1853 }
1854
1855 #ifndef CONFIG_8139_OLD_RX_RESET
1856 tmp8 = RTL_R8 (ChipCmd);
1857 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1858 RTL_W8 (ChipCmd, tmp8);
1859 RTL_W32 (RxConfig, tp->rx_config);
1860 tp->cur_rx = 0;
1861 #else
1862 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1863
1864 /* disable receive */
1865 RTL_W8_F (ChipCmd, CmdTxEnb);
1866 tmp_work = 200;
1867 while (--tmp_work > 0) {
1868 udelay(1);
1869 tmp8 = RTL_R8 (ChipCmd);
1870 if (!(tmp8 & CmdRxEnb))
1871 break;
1872 }
1873 if (tmp_work <= 0)
1874 printk (KERN_WARNING PFX "rx stop wait too long\n");
1875 /* restart receive */
1876 tmp_work = 200;
1877 while (--tmp_work > 0) {
1878 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1879 udelay(1);
1880 tmp8 = RTL_R8 (ChipCmd);
1881 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1882 break;
1883 }
1884 if (tmp_work <= 0)
1885 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1886
1887 /* and reinitialize all rx related registers */
1888 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1889 /* Must enable Tx/Rx before setting transfer thresholds! */
1890 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1891
1892 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1893 RTL_W32 (RxConfig, tp->rx_config);
1894 tp->cur_rx = 0;
1895
1896 DPRINTK("init buffer addresses\n");
1897
1898 /* Lock Config[01234] and BMCR register writes */
1899 RTL_W8 (Cfg9346, Cfg9346_Lock);
1900
1901 /* init Rx ring buffer DMA address */
1902 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1903
1904 /* A.C.: Reset the multicast list. */
1905 __set_rx_mode (dev);
1906 #endif
1907 }
1908
1909 #if RX_BUF_IDX == 3
1910 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1911 u32 offset, unsigned int size)
1912 {
1913 u32 left = RX_BUF_LEN - offset;
1914
1915 if (size > left) {
1916 memcpy(skb->data, ring + offset, left);
1917 memcpy(skb->data+left, ring, size - left);
1918 } else
1919 memcpy(skb->data, ring + offset, size);
1920 }
1921 #endif
1922
1923 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1924 {
1925 void __iomem *ioaddr = tp->mmio_addr;
1926 u16 status;
1927
1928 status = RTL_R16 (IntrStatus) & RxAckBits;
1929
1930 /* Clear out errors and receive interrupts */
1931 if (likely(status != 0)) {
1932 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1933 tp->stats.rx_errors++;
1934 if (status & RxFIFOOver)
1935 tp->stats.rx_fifo_errors++;
1936 }
1937 RTL_W16_F (IntrStatus, RxAckBits);
1938 }
1939 }
1940
1941 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1942 int budget)
1943 {
1944 void __iomem *ioaddr = tp->mmio_addr;
1945 int received = 0;
1946 unsigned char *rx_ring = tp->rx_ring;
1947 unsigned int cur_rx = tp->cur_rx;
1948 unsigned int rx_size = 0;
1949
1950 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1951 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1952 RTL_R16 (RxBufAddr),
1953 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1954
1955 while (netif_running(dev) && received < budget
1956 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1957 u32 ring_offset = cur_rx % RX_BUF_LEN;
1958 u32 rx_status;
1959 unsigned int pkt_size;
1960 struct sk_buff *skb;
1961
1962 rmb();
1963
1964 /* read size+status of next frame from DMA ring buffer */
1965 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1966 rx_size = rx_status >> 16;
1967 pkt_size = rx_size - 4;
1968
1969 if (netif_msg_rx_status(tp))
1970 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1971 " cur %4.4x.\n", dev->name, rx_status,
1972 rx_size, cur_rx);
1973 #if RTL8139_DEBUG > 2
1974 {
1975 int i;
1976 DPRINTK ("%s: Frame contents ", dev->name);
1977 for (i = 0; i < 70; i++)
1978 printk (" %2.2x",
1979 rx_ring[ring_offset + i]);
1980 printk (".\n");
1981 }
1982 #endif
1983
1984 /* Packet copy from FIFO still in progress.
1985 * Theoretically, this should never happen
1986 * since EarlyRx is disabled.
1987 */
1988 if (unlikely(rx_size == 0xfff0)) {
1989 if (!tp->fifo_copy_timeout)
1990 tp->fifo_copy_timeout = jiffies + 2;
1991 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1992 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1993 rx_size = 0;
1994 goto no_early_rx;
1995 }
1996 if (netif_msg_intr(tp)) {
1997 printk(KERN_DEBUG "%s: fifo copy in progress.",
1998 dev->name);
1999 }
2000 tp->xstats.early_rx++;
2001 break;
2002 }
2003
2004 no_early_rx:
2005 tp->fifo_copy_timeout = 0;
2006
2007 /* If Rx err or invalid rx_size/rx_status received
2008 * (which happens if we get lost in the ring),
2009 * Rx process gets reset, so we abort any further
2010 * Rx processing.
2011 */
2012 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2013 (rx_size < 8) ||
2014 (!(rx_status & RxStatusOK)))) {
2015 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2016 received = -1;
2017 goto out;
2018 }
2019
2020 /* Malloc up new buffer, compatible with net-2e. */
2021 /* Omit the four octet CRC from the length. */
2022
2023 skb = dev_alloc_skb (pkt_size + 2);
2024 if (likely(skb)) {
2025 skb->dev = dev;
2026 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2027 #if RX_BUF_IDX == 3
2028 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2029 #else
2030 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2031 #endif
2032 skb_put (skb, pkt_size);
2033
2034 skb->protocol = eth_type_trans (skb, dev);
2035
2036 dev->last_rx = jiffies;
2037 tp->stats.rx_bytes += pkt_size;
2038 tp->stats.rx_packets++;
2039
2040 netif_receive_skb (skb);
2041 } else {
2042 if (net_ratelimit())
2043 printk (KERN_WARNING
2044 "%s: Memory squeeze, dropping packet.\n",
2045 dev->name);
2046 tp->stats.rx_dropped++;
2047 }
2048 received++;
2049
2050 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2051 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2052
2053 rtl8139_isr_ack(tp);
2054 }
2055
2056 if (unlikely(!received || rx_size == 0xfff0))
2057 rtl8139_isr_ack(tp);
2058
2059 #if RTL8139_DEBUG > 1
2060 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2061 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2062 RTL_R16 (RxBufAddr),
2063 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2064 #endif
2065
2066 tp->cur_rx = cur_rx;
2067
2068 /*
2069 * The receive buffer should be mostly empty.
2070 * Tell NAPI to reenable the Rx irq.
2071 */
2072 if (tp->fifo_copy_timeout)
2073 received = budget;
2074
2075 out:
2076 return received;
2077 }
2078
2079
2080 static void rtl8139_weird_interrupt (struct net_device *dev,
2081 struct rtl8139_private *tp,
2082 void __iomem *ioaddr,
2083 int status, int link_changed)
2084 {
2085 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2086 dev->name, status);
2087
2088 assert (dev != NULL);
2089 assert (tp != NULL);
2090 assert (ioaddr != NULL);
2091
2092 /* Update the error count. */
2093 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2094 RTL_W32 (RxMissed, 0);
2095
2096 if ((status & RxUnderrun) && link_changed &&
2097 (tp->drv_flags & HAS_LNK_CHNG)) {
2098 rtl_check_media(dev, 0);
2099 status &= ~RxUnderrun;
2100 }
2101
2102 if (status & (RxUnderrun | RxErr))
2103 tp->stats.rx_errors++;
2104
2105 if (status & PCSTimeout)
2106 tp->stats.rx_length_errors++;
2107 if (status & RxUnderrun)
2108 tp->stats.rx_fifo_errors++;
2109 if (status & PCIErr) {
2110 u16 pci_cmd_status;
2111 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2112 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2113
2114 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2115 dev->name, pci_cmd_status);
2116 }
2117 }
2118
2119 static int rtl8139_poll(struct net_device *dev, int *budget)
2120 {
2121 struct rtl8139_private *tp = netdev_priv(dev);
2122 void __iomem *ioaddr = tp->mmio_addr;
2123 int orig_budget = min(*budget, dev->quota);
2124 int done = 1;
2125
2126 spin_lock(&tp->rx_lock);
2127 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2128 int work_done;
2129
2130 work_done = rtl8139_rx(dev, tp, orig_budget);
2131 if (likely(work_done > 0)) {
2132 *budget -= work_done;
2133 dev->quota -= work_done;
2134 done = (work_done < orig_budget);
2135 }
2136 }
2137
2138 if (done) {
2139 /*
2140 * Order is important since data can get interrupted
2141 * again when we think we are done.
2142 */
2143 local_irq_disable();
2144 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2145 __netif_rx_complete(dev);
2146 local_irq_enable();
2147 }
2148 spin_unlock(&tp->rx_lock);
2149
2150 return !done;
2151 }
2152
2153 /* The interrupt handler does all of the Rx thread work and cleans up
2154 after the Tx thread. */
2155 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2156 struct pt_regs *regs)
2157 {
2158 struct net_device *dev = (struct net_device *) dev_instance;
2159 struct rtl8139_private *tp = netdev_priv(dev);
2160 void __iomem *ioaddr = tp->mmio_addr;
2161 u16 status, ackstat;
2162 int link_changed = 0; /* avoid bogus "uninit" warning */
2163 int handled = 0;
2164
2165 spin_lock (&tp->lock);
2166 status = RTL_R16 (IntrStatus);
2167
2168 /* shared irq? */
2169 if (unlikely((status & rtl8139_intr_mask) == 0))
2170 goto out;
2171
2172 handled = 1;
2173
2174 /* h/w no longer present (hotplug?) or major error, bail */
2175 if (unlikely(status == 0xFFFF))
2176 goto out;
2177
2178 /* close possible race's with dev_close */
2179 if (unlikely(!netif_running(dev))) {
2180 RTL_W16 (IntrMask, 0);
2181 goto out;
2182 }
2183
2184 /* Acknowledge all of the current interrupt sources ASAP, but
2185 an first get an additional status bit from CSCR. */
2186 if (unlikely(status & RxUnderrun))
2187 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2188
2189 ackstat = status & ~(RxAckBits | TxErr);
2190 if (ackstat)
2191 RTL_W16 (IntrStatus, ackstat);
2192
2193 /* Receive packets are processed by poll routine.
2194 If not running start it now. */
2195 if (status & RxAckBits){
2196 if (netif_rx_schedule_prep(dev)) {
2197 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2198 __netif_rx_schedule (dev);
2199 }
2200 }
2201
2202 /* Check uncommon events with one test. */
2203 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2204 rtl8139_weird_interrupt (dev, tp, ioaddr,
2205 status, link_changed);
2206
2207 if (status & (TxOK | TxErr)) {
2208 rtl8139_tx_interrupt (dev, tp, ioaddr);
2209 if (status & TxErr)
2210 RTL_W16 (IntrStatus, TxErr);
2211 }
2212 out:
2213 spin_unlock (&tp->lock);
2214
2215 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2216 dev->name, RTL_R16 (IntrStatus));
2217 return IRQ_RETVAL(handled);
2218 }
2219
2220 #ifdef CONFIG_NET_POLL_CONTROLLER
2221 /*
2222 * Polling receive - used by netconsole and other diagnostic tools
2223 * to allow network i/o with interrupts disabled.
2224 */
2225 static void rtl8139_poll_controller(struct net_device *dev)
2226 {
2227 disable_irq(dev->irq);
2228 rtl8139_interrupt(dev->irq, dev, NULL);
2229 enable_irq(dev->irq);
2230 }
2231 #endif
2232
2233 static int rtl8139_close (struct net_device *dev)
2234 {
2235 struct rtl8139_private *tp = netdev_priv(dev);
2236 void __iomem *ioaddr = tp->mmio_addr;
2237 unsigned long flags;
2238
2239 netif_stop_queue (dev);
2240
2241 rtl8139_stop_thread(tp);
2242
2243 if (netif_msg_ifdown(tp))
2244 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2245 dev->name, RTL_R16 (IntrStatus));
2246
2247 spin_lock_irqsave (&tp->lock, flags);
2248
2249 /* Stop the chip's Tx and Rx DMA processes. */
2250 RTL_W8 (ChipCmd, 0);
2251
2252 /* Disable interrupts by clearing the interrupt mask. */
2253 RTL_W16 (IntrMask, 0);
2254
2255 /* Update the error counts. */
2256 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2257 RTL_W32 (RxMissed, 0);
2258
2259 spin_unlock_irqrestore (&tp->lock, flags);
2260
2261 synchronize_irq (dev->irq); /* racy, but that's ok here */
2262 free_irq (dev->irq, dev);
2263
2264 rtl8139_tx_clear (tp);
2265
2266 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2267 tp->rx_ring, tp->rx_ring_dma);
2268 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2269 tp->tx_bufs, tp->tx_bufs_dma);
2270 tp->rx_ring = NULL;
2271 tp->tx_bufs = NULL;
2272
2273 /* Green! Put the chip in low-power mode. */
2274 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2275
2276 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2277 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2278
2279 return 0;
2280 }
2281
2282
2283 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2284 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2285 other threads or interrupts aren't messing with the 8139. */
2286 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2287 {
2288 struct rtl8139_private *np = netdev_priv(dev);
2289 void __iomem *ioaddr = np->mmio_addr;
2290
2291 spin_lock_irq(&np->lock);
2292 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2293 u8 cfg3 = RTL_R8 (Config3);
2294 u8 cfg5 = RTL_R8 (Config5);
2295
2296 wol->supported = WAKE_PHY | WAKE_MAGIC
2297 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2298
2299 wol->wolopts = 0;
2300 if (cfg3 & Cfg3_LinkUp)
2301 wol->wolopts |= WAKE_PHY;
2302 if (cfg3 & Cfg3_Magic)
2303 wol->wolopts |= WAKE_MAGIC;
2304 /* (KON)FIXME: See how netdev_set_wol() handles the
2305 following constants. */
2306 if (cfg5 & Cfg5_UWF)
2307 wol->wolopts |= WAKE_UCAST;
2308 if (cfg5 & Cfg5_MWF)
2309 wol->wolopts |= WAKE_MCAST;
2310 if (cfg5 & Cfg5_BWF)
2311 wol->wolopts |= WAKE_BCAST;
2312 }
2313 spin_unlock_irq(&np->lock);
2314 }
2315
2316
2317 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2318 that wol points to kernel memory and other threads or interrupts
2319 aren't messing with the 8139. */
2320 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2321 {
2322 struct rtl8139_private *np = netdev_priv(dev);
2323 void __iomem *ioaddr = np->mmio_addr;
2324 u32 support;
2325 u8 cfg3, cfg5;
2326
2327 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2328 ? (WAKE_PHY | WAKE_MAGIC
2329 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2330 : 0);
2331 if (wol->wolopts & ~support)
2332 return -EINVAL;
2333
2334 spin_lock_irq(&np->lock);
2335 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2336 if (wol->wolopts & WAKE_PHY)
2337 cfg3 |= Cfg3_LinkUp;
2338 if (wol->wolopts & WAKE_MAGIC)
2339 cfg3 |= Cfg3_Magic;
2340 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2341 RTL_W8 (Config3, cfg3);
2342 RTL_W8 (Cfg9346, Cfg9346_Lock);
2343
2344 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2345 /* (KON)FIXME: These are untested. We may have to set the
2346 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2347 documentation. */
2348 if (wol->wolopts & WAKE_UCAST)
2349 cfg5 |= Cfg5_UWF;
2350 if (wol->wolopts & WAKE_MCAST)
2351 cfg5 |= Cfg5_MWF;
2352 if (wol->wolopts & WAKE_BCAST)
2353 cfg5 |= Cfg5_BWF;
2354 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2355 spin_unlock_irq(&np->lock);
2356
2357 return 0;
2358 }
2359
2360 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2361 {
2362 struct rtl8139_private *np = netdev_priv(dev);
2363 strcpy(info->driver, DRV_NAME);
2364 strcpy(info->version, DRV_VERSION);
2365 strcpy(info->bus_info, pci_name(np->pci_dev));
2366 info->regdump_len = np->regs_len;
2367 }
2368
2369 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2370 {
2371 struct rtl8139_private *np = netdev_priv(dev);
2372 spin_lock_irq(&np->lock);
2373 mii_ethtool_gset(&np->mii, cmd);
2374 spin_unlock_irq(&np->lock);
2375 return 0;
2376 }
2377
2378 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2379 {
2380 struct rtl8139_private *np = netdev_priv(dev);
2381 int rc;
2382 spin_lock_irq(&np->lock);
2383 rc = mii_ethtool_sset(&np->mii, cmd);
2384 spin_unlock_irq(&np->lock);
2385 return rc;
2386 }
2387
2388 static int rtl8139_nway_reset(struct net_device *dev)
2389 {
2390 struct rtl8139_private *np = netdev_priv(dev);
2391 return mii_nway_restart(&np->mii);
2392 }
2393
2394 static u32 rtl8139_get_link(struct net_device *dev)
2395 {
2396 struct rtl8139_private *np = netdev_priv(dev);
2397 return mii_link_ok(&np->mii);
2398 }
2399
2400 static u32 rtl8139_get_msglevel(struct net_device *dev)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403 return np->msg_enable;
2404 }
2405
2406 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409 np->msg_enable = datum;
2410 }
2411
2412 /* TODO: we are too slack to do reg dumping for pio, for now */
2413 #ifdef CONFIG_8139TOO_PIO
2414 #define rtl8139_get_regs_len NULL
2415 #define rtl8139_get_regs NULL
2416 #else
2417 static int rtl8139_get_regs_len(struct net_device *dev)
2418 {
2419 struct rtl8139_private *np = netdev_priv(dev);
2420 return np->regs_len;
2421 }
2422
2423 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2424 {
2425 struct rtl8139_private *np = netdev_priv(dev);
2426
2427 regs->version = RTL_REGS_VER;
2428
2429 spin_lock_irq(&np->lock);
2430 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2431 spin_unlock_irq(&np->lock);
2432 }
2433 #endif /* CONFIG_8139TOO_MMIO */
2434
2435 static int rtl8139_get_stats_count(struct net_device *dev)
2436 {
2437 return RTL_NUM_STATS;
2438 }
2439
2440 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2441 {
2442 struct rtl8139_private *np = netdev_priv(dev);
2443
2444 data[0] = np->xstats.early_rx;
2445 data[1] = np->xstats.tx_buf_mapped;
2446 data[2] = np->xstats.tx_timeouts;
2447 data[3] = np->xstats.rx_lost_in_ring;
2448 }
2449
2450 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2451 {
2452 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2453 }
2454
2455 static struct ethtool_ops rtl8139_ethtool_ops = {
2456 .get_drvinfo = rtl8139_get_drvinfo,
2457 .get_settings = rtl8139_get_settings,
2458 .set_settings = rtl8139_set_settings,
2459 .get_regs_len = rtl8139_get_regs_len,
2460 .get_regs = rtl8139_get_regs,
2461 .nway_reset = rtl8139_nway_reset,
2462 .get_link = rtl8139_get_link,
2463 .get_msglevel = rtl8139_get_msglevel,
2464 .set_msglevel = rtl8139_set_msglevel,
2465 .get_wol = rtl8139_get_wol,
2466 .set_wol = rtl8139_set_wol,
2467 .get_strings = rtl8139_get_strings,
2468 .get_stats_count = rtl8139_get_stats_count,
2469 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2470 .get_perm_addr = ethtool_op_get_perm_addr,
2471 };
2472
2473 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2474 {
2475 struct rtl8139_private *np = netdev_priv(dev);
2476 int rc;
2477
2478 if (!netif_running(dev))
2479 return -EINVAL;
2480
2481 spin_lock_irq(&np->lock);
2482 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2483 spin_unlock_irq(&np->lock);
2484
2485 return rc;
2486 }
2487
2488
2489 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2490 {
2491 struct rtl8139_private *tp = netdev_priv(dev);
2492 void __iomem *ioaddr = tp->mmio_addr;
2493 unsigned long flags;
2494
2495 if (netif_running(dev)) {
2496 spin_lock_irqsave (&tp->lock, flags);
2497 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2498 RTL_W32 (RxMissed, 0);
2499 spin_unlock_irqrestore (&tp->lock, flags);
2500 }
2501
2502 return &tp->stats;
2503 }
2504
2505 /* Set or clear the multicast filter for this adaptor.
2506 This routine is not state sensitive and need not be SMP locked. */
2507
2508 static void __set_rx_mode (struct net_device *dev)
2509 {
2510 struct rtl8139_private *tp = netdev_priv(dev);
2511 void __iomem *ioaddr = tp->mmio_addr;
2512 u32 mc_filter[2]; /* Multicast hash filter */
2513 int i, rx_mode;
2514 u32 tmp;
2515
2516 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2517 dev->name, dev->flags, RTL_R32 (RxConfig));
2518
2519 /* Note: do not reorder, GCC is clever about common statements. */
2520 if (dev->flags & IFF_PROMISC) {
2521 /* Unconditionally log net taps. */
2522 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2523 dev->name);
2524 rx_mode =
2525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2526 AcceptAllPhys;
2527 mc_filter[1] = mc_filter[0] = 0xffffffff;
2528 } else if ((dev->mc_count > multicast_filter_limit)
2529 || (dev->flags & IFF_ALLMULTI)) {
2530 /* Too many to filter perfectly -- accept all multicasts. */
2531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2532 mc_filter[1] = mc_filter[0] = 0xffffffff;
2533 } else {
2534 struct dev_mc_list *mclist;
2535 rx_mode = AcceptBroadcast | AcceptMyPhys;
2536 mc_filter[1] = mc_filter[0] = 0;
2537 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2538 i++, mclist = mclist->next) {
2539 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2540
2541 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2542 rx_mode |= AcceptMulticast;
2543 }
2544 }
2545
2546 /* We can safely update without stopping the chip. */
2547 tmp = rtl8139_rx_config | rx_mode;
2548 if (tp->rx_config != tmp) {
2549 RTL_W32_F (RxConfig, tmp);
2550 tp->rx_config = tmp;
2551 }
2552 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2553 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2554 }
2555
2556 static void rtl8139_set_rx_mode (struct net_device *dev)
2557 {
2558 unsigned long flags;
2559 struct rtl8139_private *tp = netdev_priv(dev);
2560
2561 spin_lock_irqsave (&tp->lock, flags);
2562 __set_rx_mode(dev);
2563 spin_unlock_irqrestore (&tp->lock, flags);
2564 }
2565
2566 #ifdef CONFIG_PM
2567
2568 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2569 {
2570 struct net_device *dev = pci_get_drvdata (pdev);
2571 struct rtl8139_private *tp = netdev_priv(dev);
2572 void __iomem *ioaddr = tp->mmio_addr;
2573 unsigned long flags;
2574
2575 pci_save_state (pdev);
2576
2577 if (!netif_running (dev))
2578 return 0;
2579
2580 netif_device_detach (dev);
2581
2582 spin_lock_irqsave (&tp->lock, flags);
2583
2584 /* Disable interrupts, stop Tx and Rx. */
2585 RTL_W16 (IntrMask, 0);
2586 RTL_W8 (ChipCmd, 0);
2587
2588 /* Update the error counts. */
2589 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2590 RTL_W32 (RxMissed, 0);
2591
2592 spin_unlock_irqrestore (&tp->lock, flags);
2593
2594 pci_set_power_state (pdev, PCI_D3hot);
2595
2596 return 0;
2597 }
2598
2599
2600 static int rtl8139_resume (struct pci_dev *pdev)
2601 {
2602 struct net_device *dev = pci_get_drvdata (pdev);
2603
2604 pci_restore_state (pdev);
2605 if (!netif_running (dev))
2606 return 0;
2607 pci_set_power_state (pdev, PCI_D0);
2608 rtl8139_init_ring (dev);
2609 rtl8139_hw_start (dev);
2610 netif_device_attach (dev);
2611 return 0;
2612 }
2613
2614 #endif /* CONFIG_PM */
2615
2616
2617 static struct pci_driver rtl8139_pci_driver = {
2618 .name = DRV_NAME,
2619 .id_table = rtl8139_pci_tbl,
2620 .probe = rtl8139_init_one,
2621 .remove = __devexit_p(rtl8139_remove_one),
2622 #ifdef CONFIG_PM
2623 .suspend = rtl8139_suspend,
2624 .resume = rtl8139_resume,
2625 #endif /* CONFIG_PM */
2626 };
2627
2628
2629 static int __init rtl8139_init_module (void)
2630 {
2631 /* when we're a module, we always print a version message,
2632 * even if no 8139 board is found.
2633 */
2634 #ifdef MODULE
2635 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2636 #endif
2637
2638 return pci_module_init (&rtl8139_pci_driver);
2639 }
2640
2641
2642 static void __exit rtl8139_cleanup_module (void)
2643 {
2644 pci_unregister_driver (&rtl8139_pci_driver);
2645 }
2646
2647
2648 module_init(rtl8139_init_module);
2649 module_exit(rtl8139_cleanup_module);
Linux kernel - Deliverables
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