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iwlwifi: refactor tx byte count table usage
[deliverable/linux.git] / drivers / net / 8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 TimerInt = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct napi_struct napi;
578 struct net_device *dev;
579
580 unsigned char *rx_ring;
581 unsigned int cur_rx; /* RX buf index of next pkt */
582 dma_addr_t rx_ring_dma;
583
584 unsigned int tx_flag;
585 unsigned long cur_tx;
586 unsigned long dirty_tx;
587 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
588 unsigned char *tx_bufs; /* Tx bounce buffer region. */
589 dma_addr_t tx_bufs_dma;
590
591 signed char phys[4]; /* MII device addresses. */
592
593 /* Twister tune state. */
594 char twistie, twist_row, twist_col;
595
596 unsigned int watchdog_fired : 1;
597 unsigned int default_port : 4; /* Last dev->if_port value. */
598 unsigned int have_thread : 1;
599
600 spinlock_t lock;
601 spinlock_t rx_lock;
602
603 chip_t chipset;
604 u32 rx_config;
605 struct rtl_extra_stats xstats;
606
607 struct delayed_work thread;
608
609 struct mii_if_info mii;
610 unsigned int regs_len;
611 unsigned long fifo_copy_timeout;
612 };
613
614 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
615 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
616 MODULE_LICENSE("GPL");
617 MODULE_VERSION(DRV_VERSION);
618
619 module_param(use_io, int, 0);
620 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
621 module_param(multicast_filter_limit, int, 0);
622 module_param_array(media, int, NULL, 0);
623 module_param_array(full_duplex, int, NULL, 0);
624 module_param(debug, int, 0);
625 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
626 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
627 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
628 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
629
630 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
631 static int rtl8139_open (struct net_device *dev);
632 static int mdio_read (struct net_device *dev, int phy_id, int location);
633 static void mdio_write (struct net_device *dev, int phy_id, int location,
634 int val);
635 static void rtl8139_start_thread(struct rtl8139_private *tp);
636 static void rtl8139_tx_timeout (struct net_device *dev);
637 static void rtl8139_init_ring (struct net_device *dev);
638 static int rtl8139_start_xmit (struct sk_buff *skb,
639 struct net_device *dev);
640 #ifdef CONFIG_NET_POLL_CONTROLLER
641 static void rtl8139_poll_controller(struct net_device *dev);
642 #endif
643 static int rtl8139_poll(struct napi_struct *napi, int budget);
644 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
645 static int rtl8139_close (struct net_device *dev);
646 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
647 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
648 static void rtl8139_set_rx_mode (struct net_device *dev);
649 static void __set_rx_mode (struct net_device *dev);
650 static void rtl8139_hw_start (struct net_device *dev);
651 static void rtl8139_thread (struct work_struct *work);
652 static void rtl8139_tx_timeout_task(struct work_struct *work);
653 static const struct ethtool_ops rtl8139_ethtool_ops;
654
655 /* write MMIO register, with flush */
656 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
657 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
658 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
659 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
660
661 /* write MMIO register */
662 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
663 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
664 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
665
666 /* read MMIO register */
667 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
668 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
669 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
670
671
672 static const u16 rtl8139_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
674 TxErr | TxOK | RxErr | RxOK;
675
676 static const u16 rtl8139_norx_intr_mask =
677 PCIErr | PCSTimeout | RxUnderrun |
678 TxErr | TxOK | RxErr ;
679
680 #if RX_BUF_IDX == 0
681 static const unsigned int rtl8139_rx_config =
682 RxCfgRcv8K | RxNoWrap |
683 (RX_FIFO_THRESH << RxCfgFIFOShift) |
684 (RX_DMA_BURST << RxCfgDMAShift);
685 #elif RX_BUF_IDX == 1
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv16K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 2
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv32K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 3
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv64K |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #else
701 #error "Invalid configuration for 8139_RXBUF_IDX"
702 #endif
703
704 static const unsigned int rtl8139_tx_config =
705 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
706
707 static void __rtl8139_cleanup_dev (struct net_device *dev)
708 {
709 struct rtl8139_private *tp = netdev_priv(dev);
710 struct pci_dev *pdev;
711
712 assert (dev != NULL);
713 assert (tp->pci_dev != NULL);
714 pdev = tp->pci_dev;
715
716 if (tp->mmio_addr)
717 pci_iounmap (pdev, tp->mmio_addr);
718
719 /* it's ok to call this even if we have no regions to free */
720 pci_release_regions (pdev);
721
722 free_netdev(dev);
723 pci_set_drvdata (pdev, NULL);
724 }
725
726
727 static void rtl8139_chip_reset (void __iomem *ioaddr)
728 {
729 int i;
730
731 /* Soft reset the chip. */
732 RTL_W8 (ChipCmd, CmdReset);
733
734 /* Check that the chip has finished the reset. */
735 for (i = 1000; i > 0; i--) {
736 barrier();
737 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
738 break;
739 udelay (10);
740 }
741 }
742
743
744 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
745 struct net_device **dev_out)
746 {
747 void __iomem *ioaddr;
748 struct net_device *dev;
749 struct rtl8139_private *tp;
750 u8 tmp8;
751 int rc, disable_dev_on_err = 0;
752 unsigned int i;
753 unsigned long pio_start, pio_end, pio_flags, pio_len;
754 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
755 u32 version;
756
757 assert (pdev != NULL);
758
759 *dev_out = NULL;
760
761 /* dev and priv zeroed in alloc_etherdev */
762 dev = alloc_etherdev (sizeof (*tp));
763 if (dev == NULL) {
764 dev_err(&pdev->dev, "Unable to alloc new net device\n");
765 return -ENOMEM;
766 }
767 SET_NETDEV_DEV(dev, &pdev->dev);
768
769 tp = netdev_priv(dev);
770 tp->pci_dev = pdev;
771
772 /* enable device (incl. PCI PM wakeup and hotplug setup) */
773 rc = pci_enable_device (pdev);
774 if (rc)
775 goto err_out;
776
777 pio_start = pci_resource_start (pdev, 0);
778 pio_end = pci_resource_end (pdev, 0);
779 pio_flags = pci_resource_flags (pdev, 0);
780 pio_len = pci_resource_len (pdev, 0);
781
782 mmio_start = pci_resource_start (pdev, 1);
783 mmio_end = pci_resource_end (pdev, 1);
784 mmio_flags = pci_resource_flags (pdev, 1);
785 mmio_len = pci_resource_len (pdev, 1);
786
787 /* set this immediately, we need to know before
788 * we talk to the chip directly */
789 DPRINTK("PIO region size == 0x%02X\n", pio_len);
790 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
791
792 retry:
793 if (use_io) {
794 /* make sure PCI base addr 0 is PIO */
795 if (!(pio_flags & IORESOURCE_IO)) {
796 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
797 rc = -ENODEV;
798 goto err_out;
799 }
800 /* check for weird/broken PCI region reporting */
801 if (pio_len < RTL_MIN_IO_SIZE) {
802 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 } else {
807 /* make sure PCI base addr 1 is MMIO */
808 if (!(mmio_flags & IORESOURCE_MEM)) {
809 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
810 rc = -ENODEV;
811 goto err_out;
812 }
813 if (mmio_len < RTL_MIN_IO_SIZE) {
814 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
815 rc = -ENODEV;
816 goto err_out;
817 }
818 }
819
820 rc = pci_request_regions (pdev, DRV_NAME);
821 if (rc)
822 goto err_out;
823 disable_dev_on_err = 1;
824
825 /* enable PCI bus-mastering */
826 pci_set_master (pdev);
827
828 if (use_io) {
829 ioaddr = pci_iomap(pdev, 0, 0);
830 if (!ioaddr) {
831 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
832 rc = -EIO;
833 goto err_out;
834 }
835 dev->base_addr = pio_start;
836 tp->regs_len = pio_len;
837 } else {
838 /* ioremap MMIO region */
839 ioaddr = pci_iomap(pdev, 1, 0);
840 if (ioaddr == NULL) {
841 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
842 pci_release_regions(pdev);
843 use_io = 1;
844 goto retry;
845 }
846 dev->base_addr = (long) ioaddr;
847 tp->regs_len = mmio_len;
848 }
849 tp->mmio_addr = ioaddr;
850
851 /* Bring old chips out of low-power mode. */
852 RTL_W8 (HltClk, 'R');
853
854 /* check for missing/broken hardware */
855 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
856 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
857 rc = -EIO;
858 goto err_out;
859 }
860
861 /* identify chip attached to board */
862 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
863 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
864 if (version == rtl_chip_info[i].version) {
865 tp->chipset = i;
866 goto match;
867 }
868
869 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "unknown chip version, assuming RTL-8139\n");
872 dev_printk (KERN_DEBUG, &pdev->dev,
873 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
874 tp->chipset = 0;
875
876 match:
877 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
878 version, i, rtl_chip_info[i].name);
879
880 if (tp->chipset >= CH_8139B) {
881 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
882 DPRINTK("PCI PM wakeup\n");
883 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
884 (tmp8 & LWAKE))
885 new_tmp8 &= ~LWAKE;
886 new_tmp8 |= Cfg1_PM_Enable;
887 if (new_tmp8 != tmp8) {
888 RTL_W8 (Cfg9346, Cfg9346_Unlock);
889 RTL_W8 (Config1, tmp8);
890 RTL_W8 (Cfg9346, Cfg9346_Lock);
891 }
892 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
893 tmp8 = RTL_R8 (Config4);
894 if (tmp8 & LWPTN) {
895 RTL_W8 (Cfg9346, Cfg9346_Unlock);
896 RTL_W8 (Config4, tmp8 & ~LWPTN);
897 RTL_W8 (Cfg9346, Cfg9346_Lock);
898 }
899 }
900 } else {
901 DPRINTK("Old chip wakeup\n");
902 tmp8 = RTL_R8 (Config1);
903 tmp8 &= ~(SLEEP | PWRDN);
904 RTL_W8 (Config1, tmp8);
905 }
906
907 rtl8139_chip_reset (ioaddr);
908
909 *dev_out = dev;
910 return 0;
911
912 err_out:
913 __rtl8139_cleanup_dev (dev);
914 if (disable_dev_on_err)
915 pci_disable_device (pdev);
916 return rc;
917 }
918
919
920 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
921 const struct pci_device_id *ent)
922 {
923 struct net_device *dev = NULL;
924 struct rtl8139_private *tp;
925 int i, addr_len, option;
926 void __iomem *ioaddr;
927 static int board_idx = -1;
928
929 assert (pdev != NULL);
930 assert (ent != NULL);
931
932 board_idx++;
933
934 /* when we're built into the kernel, the driver version message
935 * is only printed if at least one 8139 board has been found
936 */
937 #ifndef MODULE
938 {
939 static int printed_version;
940 if (!printed_version++)
941 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
942 }
943 #endif
944
945 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
946 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
947 dev_info(&pdev->dev,
948 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
949 pdev->vendor, pdev->device, pdev->revision);
950 return -ENODEV;
951 }
952
953 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
954 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
955 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
956 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
957 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
958 use_io = 1;
959 }
960
961 i = rtl8139_init_board (pdev, &dev);
962 if (i < 0)
963 return i;
964
965 assert (dev != NULL);
966 tp = netdev_priv(dev);
967 tp->dev = dev;
968
969 ioaddr = tp->mmio_addr;
970 assert (ioaddr != NULL);
971
972 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
973 for (i = 0; i < 3; i++)
974 ((__le16 *) (dev->dev_addr))[i] =
975 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
976 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
977
978 /* The Rtl8139-specific entries in the device structure. */
979 dev->open = rtl8139_open;
980 dev->hard_start_xmit = rtl8139_start_xmit;
981 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
982 dev->stop = rtl8139_close;
983 dev->get_stats = rtl8139_get_stats;
984 dev->set_multicast_list = rtl8139_set_rx_mode;
985 dev->do_ioctl = netdev_ioctl;
986 dev->ethtool_ops = &rtl8139_ethtool_ops;
987 dev->tx_timeout = rtl8139_tx_timeout;
988 dev->watchdog_timeo = TX_TIMEOUT;
989 #ifdef CONFIG_NET_POLL_CONTROLLER
990 dev->poll_controller = rtl8139_poll_controller;
991 #endif
992
993 /* note: the hardware is not capable of sg/csum/highdma, however
994 * through the use of skb_copy_and_csum_dev we enable these
995 * features
996 */
997 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
998
999 dev->irq = pdev->irq;
1000
1001 /* tp zeroed and aligned in alloc_etherdev */
1002 tp = netdev_priv(dev);
1003
1004 /* note: tp->chipset set in rtl8139_init_board */
1005 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1006 tp->mmio_addr = ioaddr;
1007 tp->msg_enable =
1008 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1009 spin_lock_init (&tp->lock);
1010 spin_lock_init (&tp->rx_lock);
1011 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1012 tp->mii.dev = dev;
1013 tp->mii.mdio_read = mdio_read;
1014 tp->mii.mdio_write = mdio_write;
1015 tp->mii.phy_id_mask = 0x3f;
1016 tp->mii.reg_num_mask = 0x1f;
1017
1018 /* dev is fully set up and ready to use now */
1019 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1020 i = register_netdev (dev);
1021 if (i) goto err_out;
1022
1023 pci_set_drvdata (pdev, dev);
1024
1025 printk (KERN_INFO "%s: %s at 0x%lx, "
1026 "%pM, IRQ %d\n",
1027 dev->name,
1028 board_info[ent->driver_data].name,
1029 dev->base_addr,
1030 dev->dev_addr,
1031 dev->irq);
1032
1033 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1034 dev->name, rtl_chip_info[tp->chipset].name);
1035
1036 /* Find the connected MII xcvrs.
1037 Doing this in open() would allow detecting external xcvrs later, but
1038 takes too much time. */
1039 #ifdef CONFIG_8139TOO_8129
1040 if (tp->drv_flags & HAS_MII_XCVR) {
1041 int phy, phy_idx = 0;
1042 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1043 int mii_status = mdio_read(dev, phy, 1);
1044 if (mii_status != 0xffff && mii_status != 0x0000) {
1045 u16 advertising = mdio_read(dev, phy, 4);
1046 tp->phys[phy_idx++] = phy;
1047 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1048 "advertising %4.4x.\n",
1049 dev->name, phy, mii_status, advertising);
1050 }
1051 }
1052 if (phy_idx == 0) {
1053 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1054 "transceiver.\n",
1055 dev->name);
1056 tp->phys[0] = 32;
1057 }
1058 } else
1059 #endif
1060 tp->phys[0] = 32;
1061 tp->mii.phy_id = tp->phys[0];
1062
1063 /* The lower four bits are the media type. */
1064 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1065 if (option > 0) {
1066 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1067 tp->default_port = option & 0xFF;
1068 if (tp->default_port)
1069 tp->mii.force_media = 1;
1070 }
1071 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1072 tp->mii.full_duplex = full_duplex[board_idx];
1073 if (tp->mii.full_duplex) {
1074 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1075 /* Changing the MII-advertised media because might prevent
1076 re-connection. */
1077 tp->mii.force_media = 1;
1078 }
1079 if (tp->default_port) {
1080 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1081 (option & 0x20 ? 100 : 10),
1082 (option & 0x10 ? "full" : "half"));
1083 mdio_write(dev, tp->phys[0], 0,
1084 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1085 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1086 }
1087
1088 /* Put the chip into low-power mode. */
1089 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1090 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1091
1092 return 0;
1093
1094 err_out:
1095 __rtl8139_cleanup_dev (dev);
1096 pci_disable_device (pdev);
1097 return i;
1098 }
1099
1100
1101 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1102 {
1103 struct net_device *dev = pci_get_drvdata (pdev);
1104
1105 assert (dev != NULL);
1106
1107 flush_scheduled_work();
1108
1109 unregister_netdev (dev);
1110
1111 __rtl8139_cleanup_dev (dev);
1112 pci_disable_device (pdev);
1113 }
1114
1115
1116 /* Serial EEPROM section. */
1117
1118 /* EEPROM_Ctrl bits. */
1119 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1120 #define EE_CS 0x08 /* EEPROM chip select. */
1121 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1122 #define EE_WRITE_0 0x00
1123 #define EE_WRITE_1 0x02
1124 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1125 #define EE_ENB (0x80 | EE_CS)
1126
1127 /* Delay between EEPROM clock transitions.
1128 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1129 */
1130
1131 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1132
1133 /* The EEPROM commands include the alway-set leading bit. */
1134 #define EE_WRITE_CMD (5)
1135 #define EE_READ_CMD (6)
1136 #define EE_ERASE_CMD (7)
1137
1138 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1139 {
1140 int i;
1141 unsigned retval = 0;
1142 int read_cmd = location | (EE_READ_CMD << addr_len);
1143
1144 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1145 RTL_W8 (Cfg9346, EE_ENB);
1146 eeprom_delay ();
1147
1148 /* Shift the read command bits out. */
1149 for (i = 4 + addr_len; i >= 0; i--) {
1150 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1151 RTL_W8 (Cfg9346, EE_ENB | dataval);
1152 eeprom_delay ();
1153 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1154 eeprom_delay ();
1155 }
1156 RTL_W8 (Cfg9346, EE_ENB);
1157 eeprom_delay ();
1158
1159 for (i = 16; i > 0; i--) {
1160 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1161 eeprom_delay ();
1162 retval =
1163 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1164 0);
1165 RTL_W8 (Cfg9346, EE_ENB);
1166 eeprom_delay ();
1167 }
1168
1169 /* Terminate the EEPROM access. */
1170 RTL_W8 (Cfg9346, ~EE_CS);
1171 eeprom_delay ();
1172
1173 return retval;
1174 }
1175
1176 /* MII serial management: mostly bogus for now. */
1177 /* Read and write the MII management registers using software-generated
1178 serial MDIO protocol.
1179 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1180 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1181 "overclocking" issues. */
1182 #define MDIO_DIR 0x80
1183 #define MDIO_DATA_OUT 0x04
1184 #define MDIO_DATA_IN 0x02
1185 #define MDIO_CLK 0x01
1186 #define MDIO_WRITE0 (MDIO_DIR)
1187 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1188
1189 #define mdio_delay() RTL_R8(Config4)
1190
1191
1192 static const char mii_2_8139_map[8] = {
1193 BasicModeCtrl,
1194 BasicModeStatus,
1195 0,
1196 0,
1197 NWayAdvert,
1198 NWayLPAR,
1199 NWayExpansion,
1200 0
1201 };
1202
1203
1204 #ifdef CONFIG_8139TOO_8129
1205 /* Syncronize the MII management interface by shifting 32 one bits out. */
1206 static void mdio_sync (void __iomem *ioaddr)
1207 {
1208 int i;
1209
1210 for (i = 32; i >= 0; i--) {
1211 RTL_W8 (Config4, MDIO_WRITE1);
1212 mdio_delay ();
1213 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1214 mdio_delay ();
1215 }
1216 }
1217 #endif
1218
1219 static int mdio_read (struct net_device *dev, int phy_id, int location)
1220 {
1221 struct rtl8139_private *tp = netdev_priv(dev);
1222 int retval = 0;
1223 #ifdef CONFIG_8139TOO_8129
1224 void __iomem *ioaddr = tp->mmio_addr;
1225 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1226 int i;
1227 #endif
1228
1229 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1230 void __iomem *ioaddr = tp->mmio_addr;
1231 return location < 8 && mii_2_8139_map[location] ?
1232 RTL_R16 (mii_2_8139_map[location]) : 0;
1233 }
1234
1235 #ifdef CONFIG_8139TOO_8129
1236 mdio_sync (ioaddr);
1237 /* Shift the read command bits out. */
1238 for (i = 15; i >= 0; i--) {
1239 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1240
1241 RTL_W8 (Config4, MDIO_DIR | dataval);
1242 mdio_delay ();
1243 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1244 mdio_delay ();
1245 }
1246
1247 /* Read the two transition, 16 data, and wire-idle bits. */
1248 for (i = 19; i > 0; i--) {
1249 RTL_W8 (Config4, 0);
1250 mdio_delay ();
1251 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1252 RTL_W8 (Config4, MDIO_CLK);
1253 mdio_delay ();
1254 }
1255 #endif
1256
1257 return (retval >> 1) & 0xffff;
1258 }
1259
1260
1261 static void mdio_write (struct net_device *dev, int phy_id, int location,
1262 int value)
1263 {
1264 struct rtl8139_private *tp = netdev_priv(dev);
1265 #ifdef CONFIG_8139TOO_8129
1266 void __iomem *ioaddr = tp->mmio_addr;
1267 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1268 int i;
1269 #endif
1270
1271 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1272 void __iomem *ioaddr = tp->mmio_addr;
1273 if (location == 0) {
1274 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1275 RTL_W16 (BasicModeCtrl, value);
1276 RTL_W8 (Cfg9346, Cfg9346_Lock);
1277 } else if (location < 8 && mii_2_8139_map[location])
1278 RTL_W16 (mii_2_8139_map[location], value);
1279 return;
1280 }
1281
1282 #ifdef CONFIG_8139TOO_8129
1283 mdio_sync (ioaddr);
1284
1285 /* Shift the command bits out. */
1286 for (i = 31; i >= 0; i--) {
1287 int dataval =
1288 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1289 RTL_W8 (Config4, dataval);
1290 mdio_delay ();
1291 RTL_W8 (Config4, dataval | MDIO_CLK);
1292 mdio_delay ();
1293 }
1294 /* Clear out extra bits. */
1295 for (i = 2; i > 0; i--) {
1296 RTL_W8 (Config4, 0);
1297 mdio_delay ();
1298 RTL_W8 (Config4, MDIO_CLK);
1299 mdio_delay ();
1300 }
1301 #endif
1302 }
1303
1304
1305 static int rtl8139_open (struct net_device *dev)
1306 {
1307 struct rtl8139_private *tp = netdev_priv(dev);
1308 int retval;
1309 void __iomem *ioaddr = tp->mmio_addr;
1310
1311 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1312 if (retval)
1313 return retval;
1314
1315 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1316 &tp->tx_bufs_dma, GFP_KERNEL);
1317 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1318 &tp->rx_ring_dma, GFP_KERNEL);
1319 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1320 free_irq(dev->irq, dev);
1321
1322 if (tp->tx_bufs)
1323 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1324 tp->tx_bufs, tp->tx_bufs_dma);
1325 if (tp->rx_ring)
1326 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1327 tp->rx_ring, tp->rx_ring_dma);
1328
1329 return -ENOMEM;
1330
1331 }
1332
1333 napi_enable(&tp->napi);
1334
1335 tp->mii.full_duplex = tp->mii.force_media;
1336 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1337
1338 rtl8139_init_ring (dev);
1339 rtl8139_hw_start (dev);
1340 netif_start_queue (dev);
1341
1342 if (netif_msg_ifup(tp))
1343 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1344 " GP Pins %2.2x %s-duplex.\n", dev->name,
1345 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1346 dev->irq, RTL_R8 (MediaStatus),
1347 tp->mii.full_duplex ? "full" : "half");
1348
1349 rtl8139_start_thread(tp);
1350
1351 return 0;
1352 }
1353
1354
1355 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1356 {
1357 struct rtl8139_private *tp = netdev_priv(dev);
1358
1359 if (tp->phys[0] >= 0) {
1360 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1361 }
1362 }
1363
1364 /* Start the hardware at open or resume. */
1365 static void rtl8139_hw_start (struct net_device *dev)
1366 {
1367 struct rtl8139_private *tp = netdev_priv(dev);
1368 void __iomem *ioaddr = tp->mmio_addr;
1369 u32 i;
1370 u8 tmp;
1371
1372 /* Bring old chips out of low-power mode. */
1373 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1374 RTL_W8 (HltClk, 'R');
1375
1376 rtl8139_chip_reset (ioaddr);
1377
1378 /* unlock Config[01234] and BMCR register writes */
1379 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1380 /* Restore our idea of the MAC address. */
1381 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1382 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1383
1384 /* Must enable Tx/Rx before setting transfer thresholds! */
1385 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1386
1387 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1388 RTL_W32 (RxConfig, tp->rx_config);
1389 RTL_W32 (TxConfig, rtl8139_tx_config);
1390
1391 tp->cur_rx = 0;
1392
1393 rtl_check_media (dev, 1);
1394
1395 if (tp->chipset >= CH_8139B) {
1396 /* Disable magic packet scanning, which is enabled
1397 * when PM is enabled in Config1. It can be reenabled
1398 * via ETHTOOL_SWOL if desired. */
1399 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1400 }
1401
1402 DPRINTK("init buffer addresses\n");
1403
1404 /* Lock Config[01234] and BMCR register writes */
1405 RTL_W8 (Cfg9346, Cfg9346_Lock);
1406
1407 /* init Rx ring buffer DMA address */
1408 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1409
1410 /* init Tx buffer DMA addresses */
1411 for (i = 0; i < NUM_TX_DESC; i++)
1412 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1413
1414 RTL_W32 (RxMissed, 0);
1415
1416 rtl8139_set_rx_mode (dev);
1417
1418 /* no early-rx interrupts */
1419 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1420
1421 /* make sure RxTx has started */
1422 tmp = RTL_R8 (ChipCmd);
1423 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1424 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1425
1426 /* Enable all known interrupts by setting the interrupt mask. */
1427 RTL_W16 (IntrMask, rtl8139_intr_mask);
1428 }
1429
1430
1431 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1432 static void rtl8139_init_ring (struct net_device *dev)
1433 {
1434 struct rtl8139_private *tp = netdev_priv(dev);
1435 int i;
1436
1437 tp->cur_rx = 0;
1438 tp->cur_tx = 0;
1439 tp->dirty_tx = 0;
1440
1441 for (i = 0; i < NUM_TX_DESC; i++)
1442 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1443 }
1444
1445
1446 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1447 static int next_tick = 3 * HZ;
1448
1449 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1450 static inline void rtl8139_tune_twister (struct net_device *dev,
1451 struct rtl8139_private *tp) {}
1452 #else
1453 enum TwisterParamVals {
1454 PARA78_default = 0x78fa8388,
1455 PARA7c_default = 0xcb38de43, /* param[0][3] */
1456 PARA7c_xxx = 0xcb38de43,
1457 };
1458
1459 static const unsigned long param[4][4] = {
1460 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1461 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1462 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1463 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1464 };
1465
1466 static void rtl8139_tune_twister (struct net_device *dev,
1467 struct rtl8139_private *tp)
1468 {
1469 int linkcase;
1470 void __iomem *ioaddr = tp->mmio_addr;
1471
1472 /* This is a complicated state machine to configure the "twister" for
1473 impedance/echos based on the cable length.
1474 All of this is magic and undocumented.
1475 */
1476 switch (tp->twistie) {
1477 case 1:
1478 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1479 /* We have link beat, let us tune the twister. */
1480 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1481 tp->twistie = 2; /* Change to state 2. */
1482 next_tick = HZ / 10;
1483 } else {
1484 /* Just put in some reasonable defaults for when beat returns. */
1485 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1486 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1487 RTL_W32 (PARA78, PARA78_default);
1488 RTL_W32 (PARA7c, PARA7c_default);
1489 tp->twistie = 0; /* Bail from future actions. */
1490 }
1491 break;
1492 case 2:
1493 /* Read how long it took to hear the echo. */
1494 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1495 if (linkcase == 0x7000)
1496 tp->twist_row = 3;
1497 else if (linkcase == 0x3000)
1498 tp->twist_row = 2;
1499 else if (linkcase == 0x1000)
1500 tp->twist_row = 1;
1501 else
1502 tp->twist_row = 0;
1503 tp->twist_col = 0;
1504 tp->twistie = 3; /* Change to state 2. */
1505 next_tick = HZ / 10;
1506 break;
1507 case 3:
1508 /* Put out four tuning parameters, one per 100msec. */
1509 if (tp->twist_col == 0)
1510 RTL_W16 (FIFOTMS, 0);
1511 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1512 [(int) tp->twist_col]);
1513 next_tick = HZ / 10;
1514 if (++tp->twist_col >= 4) {
1515 /* For short cables we are done.
1516 For long cables (row == 3) check for mistune. */
1517 tp->twistie =
1518 (tp->twist_row == 3) ? 4 : 0;
1519 }
1520 break;
1521 case 4:
1522 /* Special case for long cables: check for mistune. */
1523 if ((RTL_R16 (CSCR) &
1524 CSCR_LinkStatusBits) == 0x7000) {
1525 tp->twistie = 0;
1526 break;
1527 } else {
1528 RTL_W32 (PARA7c, 0xfb38de03);
1529 tp->twistie = 5;
1530 next_tick = HZ / 10;
1531 }
1532 break;
1533 case 5:
1534 /* Retune for shorter cable (column 2). */
1535 RTL_W32 (FIFOTMS, 0x20);
1536 RTL_W32 (PARA78, PARA78_default);
1537 RTL_W32 (PARA7c, PARA7c_default);
1538 RTL_W32 (FIFOTMS, 0x00);
1539 tp->twist_row = 2;
1540 tp->twist_col = 0;
1541 tp->twistie = 3;
1542 next_tick = HZ / 10;
1543 break;
1544
1545 default:
1546 /* do nothing */
1547 break;
1548 }
1549 }
1550 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1551
1552 static inline void rtl8139_thread_iter (struct net_device *dev,
1553 struct rtl8139_private *tp,
1554 void __iomem *ioaddr)
1555 {
1556 int mii_lpa;
1557
1558 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1559
1560 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1561 int duplex = (mii_lpa & LPA_100FULL)
1562 || (mii_lpa & 0x01C0) == 0x0040;
1563 if (tp->mii.full_duplex != duplex) {
1564 tp->mii.full_duplex = duplex;
1565
1566 if (mii_lpa) {
1567 printk (KERN_INFO
1568 "%s: Setting %s-duplex based on MII #%d link"
1569 " partner ability of %4.4x.\n",
1570 dev->name,
1571 tp->mii.full_duplex ? "full" : "half",
1572 tp->phys[0], mii_lpa);
1573 } else {
1574 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1575 dev->name);
1576 }
1577 #if 0
1578 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1579 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1580 RTL_W8 (Cfg9346, Cfg9346_Lock);
1581 #endif
1582 }
1583 }
1584
1585 next_tick = HZ * 60;
1586
1587 rtl8139_tune_twister (dev, tp);
1588
1589 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1590 dev->name, RTL_R16 (NWayLPAR));
1591 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1592 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1593 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1594 dev->name, RTL_R8 (Config0),
1595 RTL_R8 (Config1));
1596 }
1597
1598 static void rtl8139_thread (struct work_struct *work)
1599 {
1600 struct rtl8139_private *tp =
1601 container_of(work, struct rtl8139_private, thread.work);
1602 struct net_device *dev = tp->mii.dev;
1603 unsigned long thr_delay = next_tick;
1604
1605 rtnl_lock();
1606
1607 if (!netif_running(dev))
1608 goto out_unlock;
1609
1610 if (tp->watchdog_fired) {
1611 tp->watchdog_fired = 0;
1612 rtl8139_tx_timeout_task(work);
1613 } else
1614 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1615
1616 if (tp->have_thread)
1617 schedule_delayed_work(&tp->thread, thr_delay);
1618 out_unlock:
1619 rtnl_unlock ();
1620 }
1621
1622 static void rtl8139_start_thread(struct rtl8139_private *tp)
1623 {
1624 tp->twistie = 0;
1625 if (tp->chipset == CH_8139_K)
1626 tp->twistie = 1;
1627 else if (tp->drv_flags & HAS_LNK_CHNG)
1628 return;
1629
1630 tp->have_thread = 1;
1631 tp->watchdog_fired = 0;
1632
1633 schedule_delayed_work(&tp->thread, next_tick);
1634 }
1635
1636 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1637 {
1638 tp->cur_tx = 0;
1639 tp->dirty_tx = 0;
1640
1641 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1642 }
1643
1644 static void rtl8139_tx_timeout_task (struct work_struct *work)
1645 {
1646 struct rtl8139_private *tp =
1647 container_of(work, struct rtl8139_private, thread.work);
1648 struct net_device *dev = tp->mii.dev;
1649 void __iomem *ioaddr = tp->mmio_addr;
1650 int i;
1651 u8 tmp8;
1652
1653 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1654 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1655 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1656 /* Emit info to figure out what went wrong. */
1657 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1658 dev->name, tp->cur_tx, tp->dirty_tx);
1659 for (i = 0; i < NUM_TX_DESC; i++)
1660 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1661 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1662 i == tp->dirty_tx % NUM_TX_DESC ?
1663 " (queue head)" : "");
1664
1665 tp->xstats.tx_timeouts++;
1666
1667 /* disable Tx ASAP, if not already */
1668 tmp8 = RTL_R8 (ChipCmd);
1669 if (tmp8 & CmdTxEnb)
1670 RTL_W8 (ChipCmd, CmdRxEnb);
1671
1672 spin_lock_bh(&tp->rx_lock);
1673 /* Disable interrupts by clearing the interrupt mask. */
1674 RTL_W16 (IntrMask, 0x0000);
1675
1676 /* Stop a shared interrupt from scavenging while we are. */
1677 spin_lock_irq(&tp->lock);
1678 rtl8139_tx_clear (tp);
1679 spin_unlock_irq(&tp->lock);
1680
1681 /* ...and finally, reset everything */
1682 if (netif_running(dev)) {
1683 rtl8139_hw_start (dev);
1684 netif_wake_queue (dev);
1685 }
1686 spin_unlock_bh(&tp->rx_lock);
1687 }
1688
1689 static void rtl8139_tx_timeout (struct net_device *dev)
1690 {
1691 struct rtl8139_private *tp = netdev_priv(dev);
1692
1693 tp->watchdog_fired = 1;
1694 if (!tp->have_thread) {
1695 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1696 schedule_delayed_work(&tp->thread, next_tick);
1697 }
1698 }
1699
1700 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1701 {
1702 struct rtl8139_private *tp = netdev_priv(dev);
1703 void __iomem *ioaddr = tp->mmio_addr;
1704 unsigned int entry;
1705 unsigned int len = skb->len;
1706 unsigned long flags;
1707
1708 /* Calculate the next Tx descriptor entry. */
1709 entry = tp->cur_tx % NUM_TX_DESC;
1710
1711 /* Note: the chip doesn't have auto-pad! */
1712 if (likely(len < TX_BUF_SIZE)) {
1713 if (len < ETH_ZLEN)
1714 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1715 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1716 dev_kfree_skb(skb);
1717 } else {
1718 dev_kfree_skb(skb);
1719 dev->stats.tx_dropped++;
1720 return 0;
1721 }
1722
1723 spin_lock_irqsave(&tp->lock, flags);
1724 /*
1725 * Writing to TxStatus triggers a DMA transfer of the data
1726 * copied to tp->tx_buf[entry] above. Use a memory barrier
1727 * to make sure that the device sees the updated data.
1728 */
1729 wmb();
1730 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1731 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1732
1733 dev->trans_start = jiffies;
1734
1735 tp->cur_tx++;
1736
1737 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1738 netif_stop_queue (dev);
1739 spin_unlock_irqrestore(&tp->lock, flags);
1740
1741 if (netif_msg_tx_queued(tp))
1742 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1743 dev->name, len, entry);
1744
1745 return 0;
1746 }
1747
1748
1749 static void rtl8139_tx_interrupt (struct net_device *dev,
1750 struct rtl8139_private *tp,
1751 void __iomem *ioaddr)
1752 {
1753 unsigned long dirty_tx, tx_left;
1754
1755 assert (dev != NULL);
1756 assert (ioaddr != NULL);
1757
1758 dirty_tx = tp->dirty_tx;
1759 tx_left = tp->cur_tx - dirty_tx;
1760 while (tx_left > 0) {
1761 int entry = dirty_tx % NUM_TX_DESC;
1762 int txstatus;
1763
1764 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1765
1766 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1767 break; /* It still hasn't been Txed */
1768
1769 /* Note: TxCarrierLost is always asserted at 100mbps. */
1770 if (txstatus & (TxOutOfWindow | TxAborted)) {
1771 /* There was an major error, log it. */
1772 if (netif_msg_tx_err(tp))
1773 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1774 dev->name, txstatus);
1775 dev->stats.tx_errors++;
1776 if (txstatus & TxAborted) {
1777 dev->stats.tx_aborted_errors++;
1778 RTL_W32 (TxConfig, TxClearAbt);
1779 RTL_W16 (IntrStatus, TxErr);
1780 wmb();
1781 }
1782 if (txstatus & TxCarrierLost)
1783 dev->stats.tx_carrier_errors++;
1784 if (txstatus & TxOutOfWindow)
1785 dev->stats.tx_window_errors++;
1786 } else {
1787 if (txstatus & TxUnderrun) {
1788 /* Add 64 to the Tx FIFO threshold. */
1789 if (tp->tx_flag < 0x00300000)
1790 tp->tx_flag += 0x00020000;
1791 dev->stats.tx_fifo_errors++;
1792 }
1793 dev->stats.collisions += (txstatus >> 24) & 15;
1794 dev->stats.tx_bytes += txstatus & 0x7ff;
1795 dev->stats.tx_packets++;
1796 }
1797
1798 dirty_tx++;
1799 tx_left--;
1800 }
1801
1802 #ifndef RTL8139_NDEBUG
1803 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1804 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1805 dev->name, dirty_tx, tp->cur_tx);
1806 dirty_tx += NUM_TX_DESC;
1807 }
1808 #endif /* RTL8139_NDEBUG */
1809
1810 /* only wake the queue if we did work, and the queue is stopped */
1811 if (tp->dirty_tx != dirty_tx) {
1812 tp->dirty_tx = dirty_tx;
1813 mb();
1814 netif_wake_queue (dev);
1815 }
1816 }
1817
1818
1819 /* TODO: clean this up! Rx reset need not be this intensive */
1820 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1821 struct rtl8139_private *tp, void __iomem *ioaddr)
1822 {
1823 u8 tmp8;
1824 #ifdef CONFIG_8139_OLD_RX_RESET
1825 int tmp_work;
1826 #endif
1827
1828 if (netif_msg_rx_err (tp))
1829 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1830 dev->name, rx_status);
1831 dev->stats.rx_errors++;
1832 if (!(rx_status & RxStatusOK)) {
1833 if (rx_status & RxTooLong) {
1834 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1835 dev->name, rx_status);
1836 /* A.C.: The chip hangs here. */
1837 }
1838 if (rx_status & (RxBadSymbol | RxBadAlign))
1839 dev->stats.rx_frame_errors++;
1840 if (rx_status & (RxRunt | RxTooLong))
1841 dev->stats.rx_length_errors++;
1842 if (rx_status & RxCRCErr)
1843 dev->stats.rx_crc_errors++;
1844 } else {
1845 tp->xstats.rx_lost_in_ring++;
1846 }
1847
1848 #ifndef CONFIG_8139_OLD_RX_RESET
1849 tmp8 = RTL_R8 (ChipCmd);
1850 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1851 RTL_W8 (ChipCmd, tmp8);
1852 RTL_W32 (RxConfig, tp->rx_config);
1853 tp->cur_rx = 0;
1854 #else
1855 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1856
1857 /* disable receive */
1858 RTL_W8_F (ChipCmd, CmdTxEnb);
1859 tmp_work = 200;
1860 while (--tmp_work > 0) {
1861 udelay(1);
1862 tmp8 = RTL_R8 (ChipCmd);
1863 if (!(tmp8 & CmdRxEnb))
1864 break;
1865 }
1866 if (tmp_work <= 0)
1867 printk (KERN_WARNING PFX "rx stop wait too long\n");
1868 /* restart receive */
1869 tmp_work = 200;
1870 while (--tmp_work > 0) {
1871 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1872 udelay(1);
1873 tmp8 = RTL_R8 (ChipCmd);
1874 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1875 break;
1876 }
1877 if (tmp_work <= 0)
1878 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1879
1880 /* and reinitialize all rx related registers */
1881 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1882 /* Must enable Tx/Rx before setting transfer thresholds! */
1883 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1884
1885 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1886 RTL_W32 (RxConfig, tp->rx_config);
1887 tp->cur_rx = 0;
1888
1889 DPRINTK("init buffer addresses\n");
1890
1891 /* Lock Config[01234] and BMCR register writes */
1892 RTL_W8 (Cfg9346, Cfg9346_Lock);
1893
1894 /* init Rx ring buffer DMA address */
1895 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1896
1897 /* A.C.: Reset the multicast list. */
1898 __set_rx_mode (dev);
1899 #endif
1900 }
1901
1902 #if RX_BUF_IDX == 3
1903 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1904 u32 offset, unsigned int size)
1905 {
1906 u32 left = RX_BUF_LEN - offset;
1907
1908 if (size > left) {
1909 skb_copy_to_linear_data(skb, ring + offset, left);
1910 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1911 } else
1912 skb_copy_to_linear_data(skb, ring + offset, size);
1913 }
1914 #endif
1915
1916 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1917 {
1918 void __iomem *ioaddr = tp->mmio_addr;
1919 u16 status;
1920
1921 status = RTL_R16 (IntrStatus) & RxAckBits;
1922
1923 /* Clear out errors and receive interrupts */
1924 if (likely(status != 0)) {
1925 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1926 tp->dev->stats.rx_errors++;
1927 if (status & RxFIFOOver)
1928 tp->dev->stats.rx_fifo_errors++;
1929 }
1930 RTL_W16_F (IntrStatus, RxAckBits);
1931 }
1932 }
1933
1934 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1935 int budget)
1936 {
1937 void __iomem *ioaddr = tp->mmio_addr;
1938 int received = 0;
1939 unsigned char *rx_ring = tp->rx_ring;
1940 unsigned int cur_rx = tp->cur_rx;
1941 unsigned int rx_size = 0;
1942
1943 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1944 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1945 RTL_R16 (RxBufAddr),
1946 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1947
1948 while (netif_running(dev) && received < budget
1949 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1950 u32 ring_offset = cur_rx % RX_BUF_LEN;
1951 u32 rx_status;
1952 unsigned int pkt_size;
1953 struct sk_buff *skb;
1954
1955 rmb();
1956
1957 /* read size+status of next frame from DMA ring buffer */
1958 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1959 rx_size = rx_status >> 16;
1960 pkt_size = rx_size - 4;
1961
1962 if (netif_msg_rx_status(tp))
1963 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1964 " cur %4.4x.\n", dev->name, rx_status,
1965 rx_size, cur_rx);
1966 #if RTL8139_DEBUG > 2
1967 {
1968 int i;
1969 DPRINTK ("%s: Frame contents ", dev->name);
1970 for (i = 0; i < 70; i++)
1971 printk (" %2.2x",
1972 rx_ring[ring_offset + i]);
1973 printk (".\n");
1974 }
1975 #endif
1976
1977 /* Packet copy from FIFO still in progress.
1978 * Theoretically, this should never happen
1979 * since EarlyRx is disabled.
1980 */
1981 if (unlikely(rx_size == 0xfff0)) {
1982 if (!tp->fifo_copy_timeout)
1983 tp->fifo_copy_timeout = jiffies + 2;
1984 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1985 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1986 rx_size = 0;
1987 goto no_early_rx;
1988 }
1989 if (netif_msg_intr(tp)) {
1990 printk(KERN_DEBUG "%s: fifo copy in progress.",
1991 dev->name);
1992 }
1993 tp->xstats.early_rx++;
1994 break;
1995 }
1996
1997 no_early_rx:
1998 tp->fifo_copy_timeout = 0;
1999
2000 /* If Rx err or invalid rx_size/rx_status received
2001 * (which happens if we get lost in the ring),
2002 * Rx process gets reset, so we abort any further
2003 * Rx processing.
2004 */
2005 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2006 (rx_size < 8) ||
2007 (!(rx_status & RxStatusOK)))) {
2008 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2009 received = -1;
2010 goto out;
2011 }
2012
2013 /* Malloc up new buffer, compatible with net-2e. */
2014 /* Omit the four octet CRC from the length. */
2015
2016 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2017 if (likely(skb)) {
2018 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2019 #if RX_BUF_IDX == 3
2020 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2021 #else
2022 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2023 #endif
2024 skb_put (skb, pkt_size);
2025
2026 skb->protocol = eth_type_trans (skb, dev);
2027
2028 dev->last_rx = jiffies;
2029 dev->stats.rx_bytes += pkt_size;
2030 dev->stats.rx_packets++;
2031
2032 netif_receive_skb (skb);
2033 } else {
2034 if (net_ratelimit())
2035 printk (KERN_WARNING
2036 "%s: Memory squeeze, dropping packet.\n",
2037 dev->name);
2038 dev->stats.rx_dropped++;
2039 }
2040 received++;
2041
2042 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2043 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2044
2045 rtl8139_isr_ack(tp);
2046 }
2047
2048 if (unlikely(!received || rx_size == 0xfff0))
2049 rtl8139_isr_ack(tp);
2050
2051 #if RTL8139_DEBUG > 1
2052 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2053 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2054 RTL_R16 (RxBufAddr),
2055 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2056 #endif
2057
2058 tp->cur_rx = cur_rx;
2059
2060 /*
2061 * The receive buffer should be mostly empty.
2062 * Tell NAPI to reenable the Rx irq.
2063 */
2064 if (tp->fifo_copy_timeout)
2065 received = budget;
2066
2067 out:
2068 return received;
2069 }
2070
2071
2072 static void rtl8139_weird_interrupt (struct net_device *dev,
2073 struct rtl8139_private *tp,
2074 void __iomem *ioaddr,
2075 int status, int link_changed)
2076 {
2077 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2078 dev->name, status);
2079
2080 assert (dev != NULL);
2081 assert (tp != NULL);
2082 assert (ioaddr != NULL);
2083
2084 /* Update the error count. */
2085 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2086 RTL_W32 (RxMissed, 0);
2087
2088 if ((status & RxUnderrun) && link_changed &&
2089 (tp->drv_flags & HAS_LNK_CHNG)) {
2090 rtl_check_media(dev, 0);
2091 status &= ~RxUnderrun;
2092 }
2093
2094 if (status & (RxUnderrun | RxErr))
2095 dev->stats.rx_errors++;
2096
2097 if (status & PCSTimeout)
2098 dev->stats.rx_length_errors++;
2099 if (status & RxUnderrun)
2100 dev->stats.rx_fifo_errors++;
2101 if (status & PCIErr) {
2102 u16 pci_cmd_status;
2103 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2104 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2105
2106 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2107 dev->name, pci_cmd_status);
2108 }
2109 }
2110
2111 static int rtl8139_poll(struct napi_struct *napi, int budget)
2112 {
2113 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2114 struct net_device *dev = tp->dev;
2115 void __iomem *ioaddr = tp->mmio_addr;
2116 int work_done;
2117
2118 spin_lock(&tp->rx_lock);
2119 work_done = 0;
2120 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2121 work_done += rtl8139_rx(dev, tp, budget);
2122
2123 if (work_done < budget) {
2124 unsigned long flags;
2125 /*
2126 * Order is important since data can get interrupted
2127 * again when we think we are done.
2128 */
2129 spin_lock_irqsave(&tp->lock, flags);
2130 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2131 __netif_rx_complete(dev, napi);
2132 spin_unlock_irqrestore(&tp->lock, flags);
2133 }
2134 spin_unlock(&tp->rx_lock);
2135
2136 return work_done;
2137 }
2138
2139 /* The interrupt handler does all of the Rx thread work and cleans up
2140 after the Tx thread. */
2141 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2142 {
2143 struct net_device *dev = (struct net_device *) dev_instance;
2144 struct rtl8139_private *tp = netdev_priv(dev);
2145 void __iomem *ioaddr = tp->mmio_addr;
2146 u16 status, ackstat;
2147 int link_changed = 0; /* avoid bogus "uninit" warning */
2148 int handled = 0;
2149
2150 spin_lock (&tp->lock);
2151 status = RTL_R16 (IntrStatus);
2152
2153 /* shared irq? */
2154 if (unlikely((status & rtl8139_intr_mask) == 0))
2155 goto out;
2156
2157 handled = 1;
2158
2159 /* h/w no longer present (hotplug?) or major error, bail */
2160 if (unlikely(status == 0xFFFF))
2161 goto out;
2162
2163 /* close possible race's with dev_close */
2164 if (unlikely(!netif_running(dev))) {
2165 RTL_W16 (IntrMask, 0);
2166 goto out;
2167 }
2168
2169 /* Acknowledge all of the current interrupt sources ASAP, but
2170 an first get an additional status bit from CSCR. */
2171 if (unlikely(status & RxUnderrun))
2172 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2173
2174 ackstat = status & ~(RxAckBits | TxErr);
2175 if (ackstat)
2176 RTL_W16 (IntrStatus, ackstat);
2177
2178 /* Receive packets are processed by poll routine.
2179 If not running start it now. */
2180 if (status & RxAckBits){
2181 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2182 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2183 __netif_rx_schedule(dev, &tp->napi);
2184 }
2185 }
2186
2187 /* Check uncommon events with one test. */
2188 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2189 rtl8139_weird_interrupt (dev, tp, ioaddr,
2190 status, link_changed);
2191
2192 if (status & (TxOK | TxErr)) {
2193 rtl8139_tx_interrupt (dev, tp, ioaddr);
2194 if (status & TxErr)
2195 RTL_W16 (IntrStatus, TxErr);
2196 }
2197 out:
2198 spin_unlock (&tp->lock);
2199
2200 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2201 dev->name, RTL_R16 (IntrStatus));
2202 return IRQ_RETVAL(handled);
2203 }
2204
2205 #ifdef CONFIG_NET_POLL_CONTROLLER
2206 /*
2207 * Polling receive - used by netconsole and other diagnostic tools
2208 * to allow network i/o with interrupts disabled.
2209 */
2210 static void rtl8139_poll_controller(struct net_device *dev)
2211 {
2212 disable_irq(dev->irq);
2213 rtl8139_interrupt(dev->irq, dev);
2214 enable_irq(dev->irq);
2215 }
2216 #endif
2217
2218 static int rtl8139_close (struct net_device *dev)
2219 {
2220 struct rtl8139_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
2222 unsigned long flags;
2223
2224 netif_stop_queue(dev);
2225 napi_disable(&tp->napi);
2226
2227 if (netif_msg_ifdown(tp))
2228 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2229 dev->name, RTL_R16 (IntrStatus));
2230
2231 spin_lock_irqsave (&tp->lock, flags);
2232
2233 /* Stop the chip's Tx and Rx DMA processes. */
2234 RTL_W8 (ChipCmd, 0);
2235
2236 /* Disable interrupts by clearing the interrupt mask. */
2237 RTL_W16 (IntrMask, 0);
2238
2239 /* Update the error counts. */
2240 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2241 RTL_W32 (RxMissed, 0);
2242
2243 spin_unlock_irqrestore (&tp->lock, flags);
2244
2245 free_irq (dev->irq, dev);
2246
2247 rtl8139_tx_clear (tp);
2248
2249 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2250 tp->rx_ring, tp->rx_ring_dma);
2251 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2252 tp->tx_bufs, tp->tx_bufs_dma);
2253 tp->rx_ring = NULL;
2254 tp->tx_bufs = NULL;
2255
2256 /* Green! Put the chip in low-power mode. */
2257 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2258
2259 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2260 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2261
2262 return 0;
2263 }
2264
2265
2266 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2267 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2268 other threads or interrupts aren't messing with the 8139. */
2269 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2270 {
2271 struct rtl8139_private *np = netdev_priv(dev);
2272 void __iomem *ioaddr = np->mmio_addr;
2273
2274 spin_lock_irq(&np->lock);
2275 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2276 u8 cfg3 = RTL_R8 (Config3);
2277 u8 cfg5 = RTL_R8 (Config5);
2278
2279 wol->supported = WAKE_PHY | WAKE_MAGIC
2280 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2281
2282 wol->wolopts = 0;
2283 if (cfg3 & Cfg3_LinkUp)
2284 wol->wolopts |= WAKE_PHY;
2285 if (cfg3 & Cfg3_Magic)
2286 wol->wolopts |= WAKE_MAGIC;
2287 /* (KON)FIXME: See how netdev_set_wol() handles the
2288 following constants. */
2289 if (cfg5 & Cfg5_UWF)
2290 wol->wolopts |= WAKE_UCAST;
2291 if (cfg5 & Cfg5_MWF)
2292 wol->wolopts |= WAKE_MCAST;
2293 if (cfg5 & Cfg5_BWF)
2294 wol->wolopts |= WAKE_BCAST;
2295 }
2296 spin_unlock_irq(&np->lock);
2297 }
2298
2299
2300 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2301 that wol points to kernel memory and other threads or interrupts
2302 aren't messing with the 8139. */
2303 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2304 {
2305 struct rtl8139_private *np = netdev_priv(dev);
2306 void __iomem *ioaddr = np->mmio_addr;
2307 u32 support;
2308 u8 cfg3, cfg5;
2309
2310 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2311 ? (WAKE_PHY | WAKE_MAGIC
2312 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2313 : 0);
2314 if (wol->wolopts & ~support)
2315 return -EINVAL;
2316
2317 spin_lock_irq(&np->lock);
2318 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2319 if (wol->wolopts & WAKE_PHY)
2320 cfg3 |= Cfg3_LinkUp;
2321 if (wol->wolopts & WAKE_MAGIC)
2322 cfg3 |= Cfg3_Magic;
2323 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2324 RTL_W8 (Config3, cfg3);
2325 RTL_W8 (Cfg9346, Cfg9346_Lock);
2326
2327 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2328 /* (KON)FIXME: These are untested. We may have to set the
2329 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2330 documentation. */
2331 if (wol->wolopts & WAKE_UCAST)
2332 cfg5 |= Cfg5_UWF;
2333 if (wol->wolopts & WAKE_MCAST)
2334 cfg5 |= Cfg5_MWF;
2335 if (wol->wolopts & WAKE_BCAST)
2336 cfg5 |= Cfg5_BWF;
2337 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2338 spin_unlock_irq(&np->lock);
2339
2340 return 0;
2341 }
2342
2343 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2344 {
2345 struct rtl8139_private *np = netdev_priv(dev);
2346 strcpy(info->driver, DRV_NAME);
2347 strcpy(info->version, DRV_VERSION);
2348 strcpy(info->bus_info, pci_name(np->pci_dev));
2349 info->regdump_len = np->regs_len;
2350 }
2351
2352 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2353 {
2354 struct rtl8139_private *np = netdev_priv(dev);
2355 spin_lock_irq(&np->lock);
2356 mii_ethtool_gset(&np->mii, cmd);
2357 spin_unlock_irq(&np->lock);
2358 return 0;
2359 }
2360
2361 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2362 {
2363 struct rtl8139_private *np = netdev_priv(dev);
2364 int rc;
2365 spin_lock_irq(&np->lock);
2366 rc = mii_ethtool_sset(&np->mii, cmd);
2367 spin_unlock_irq(&np->lock);
2368 return rc;
2369 }
2370
2371 static int rtl8139_nway_reset(struct net_device *dev)
2372 {
2373 struct rtl8139_private *np = netdev_priv(dev);
2374 return mii_nway_restart(&np->mii);
2375 }
2376
2377 static u32 rtl8139_get_link(struct net_device *dev)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 return mii_link_ok(&np->mii);
2381 }
2382
2383 static u32 rtl8139_get_msglevel(struct net_device *dev)
2384 {
2385 struct rtl8139_private *np = netdev_priv(dev);
2386 return np->msg_enable;
2387 }
2388
2389 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2390 {
2391 struct rtl8139_private *np = netdev_priv(dev);
2392 np->msg_enable = datum;
2393 }
2394
2395 static int rtl8139_get_regs_len(struct net_device *dev)
2396 {
2397 struct rtl8139_private *np;
2398 /* TODO: we are too slack to do reg dumping for pio, for now */
2399 if (use_io)
2400 return 0;
2401 np = netdev_priv(dev);
2402 return np->regs_len;
2403 }
2404
2405 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2406 {
2407 struct rtl8139_private *np;
2408
2409 /* TODO: we are too slack to do reg dumping for pio, for now */
2410 if (use_io)
2411 return;
2412 np = netdev_priv(dev);
2413
2414 regs->version = RTL_REGS_VER;
2415
2416 spin_lock_irq(&np->lock);
2417 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2418 spin_unlock_irq(&np->lock);
2419 }
2420
2421 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2422 {
2423 switch (sset) {
2424 case ETH_SS_STATS:
2425 return RTL_NUM_STATS;
2426 default:
2427 return -EOPNOTSUPP;
2428 }
2429 }
2430
2431 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2432 {
2433 struct rtl8139_private *np = netdev_priv(dev);
2434
2435 data[0] = np->xstats.early_rx;
2436 data[1] = np->xstats.tx_buf_mapped;
2437 data[2] = np->xstats.tx_timeouts;
2438 data[3] = np->xstats.rx_lost_in_ring;
2439 }
2440
2441 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2442 {
2443 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2444 }
2445
2446 static const struct ethtool_ops rtl8139_ethtool_ops = {
2447 .get_drvinfo = rtl8139_get_drvinfo,
2448 .get_settings = rtl8139_get_settings,
2449 .set_settings = rtl8139_set_settings,
2450 .get_regs_len = rtl8139_get_regs_len,
2451 .get_regs = rtl8139_get_regs,
2452 .nway_reset = rtl8139_nway_reset,
2453 .get_link = rtl8139_get_link,
2454 .get_msglevel = rtl8139_get_msglevel,
2455 .set_msglevel = rtl8139_set_msglevel,
2456 .get_wol = rtl8139_get_wol,
2457 .set_wol = rtl8139_set_wol,
2458 .get_strings = rtl8139_get_strings,
2459 .get_sset_count = rtl8139_get_sset_count,
2460 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2461 };
2462
2463 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2464 {
2465 struct rtl8139_private *np = netdev_priv(dev);
2466 int rc;
2467
2468 if (!netif_running(dev))
2469 return -EINVAL;
2470
2471 spin_lock_irq(&np->lock);
2472 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2473 spin_unlock_irq(&np->lock);
2474
2475 return rc;
2476 }
2477
2478
2479 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2480 {
2481 struct rtl8139_private *tp = netdev_priv(dev);
2482 void __iomem *ioaddr = tp->mmio_addr;
2483 unsigned long flags;
2484
2485 if (netif_running(dev)) {
2486 spin_lock_irqsave (&tp->lock, flags);
2487 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2488 RTL_W32 (RxMissed, 0);
2489 spin_unlock_irqrestore (&tp->lock, flags);
2490 }
2491
2492 return &dev->stats;
2493 }
2494
2495 /* Set or clear the multicast filter for this adaptor.
2496 This routine is not state sensitive and need not be SMP locked. */
2497
2498 static void __set_rx_mode (struct net_device *dev)
2499 {
2500 struct rtl8139_private *tp = netdev_priv(dev);
2501 void __iomem *ioaddr = tp->mmio_addr;
2502 u32 mc_filter[2]; /* Multicast hash filter */
2503 int i, rx_mode;
2504 u32 tmp;
2505
2506 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2507 dev->name, dev->flags, RTL_R32 (RxConfig));
2508
2509 /* Note: do not reorder, GCC is clever about common statements. */
2510 if (dev->flags & IFF_PROMISC) {
2511 rx_mode =
2512 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2513 AcceptAllPhys;
2514 mc_filter[1] = mc_filter[0] = 0xffffffff;
2515 } else if ((dev->mc_count > multicast_filter_limit)
2516 || (dev->flags & IFF_ALLMULTI)) {
2517 /* Too many to filter perfectly -- accept all multicasts. */
2518 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2519 mc_filter[1] = mc_filter[0] = 0xffffffff;
2520 } else {
2521 struct dev_mc_list *mclist;
2522 rx_mode = AcceptBroadcast | AcceptMyPhys;
2523 mc_filter[1] = mc_filter[0] = 0;
2524 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2525 i++, mclist = mclist->next) {
2526 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2527
2528 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2529 rx_mode |= AcceptMulticast;
2530 }
2531 }
2532
2533 /* We can safely update without stopping the chip. */
2534 tmp = rtl8139_rx_config | rx_mode;
2535 if (tp->rx_config != tmp) {
2536 RTL_W32_F (RxConfig, tmp);
2537 tp->rx_config = tmp;
2538 }
2539 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2540 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2541 }
2542
2543 static void rtl8139_set_rx_mode (struct net_device *dev)
2544 {
2545 unsigned long flags;
2546 struct rtl8139_private *tp = netdev_priv(dev);
2547
2548 spin_lock_irqsave (&tp->lock, flags);
2549 __set_rx_mode(dev);
2550 spin_unlock_irqrestore (&tp->lock, flags);
2551 }
2552
2553 #ifdef CONFIG_PM
2554
2555 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2556 {
2557 struct net_device *dev = pci_get_drvdata (pdev);
2558 struct rtl8139_private *tp = netdev_priv(dev);
2559 void __iomem *ioaddr = tp->mmio_addr;
2560 unsigned long flags;
2561
2562 pci_save_state (pdev);
2563
2564 if (!netif_running (dev))
2565 return 0;
2566
2567 netif_device_detach (dev);
2568
2569 spin_lock_irqsave (&tp->lock, flags);
2570
2571 /* Disable interrupts, stop Tx and Rx. */
2572 RTL_W16 (IntrMask, 0);
2573 RTL_W8 (ChipCmd, 0);
2574
2575 /* Update the error counts. */
2576 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2577 RTL_W32 (RxMissed, 0);
2578
2579 spin_unlock_irqrestore (&tp->lock, flags);
2580
2581 pci_set_power_state (pdev, PCI_D3hot);
2582
2583 return 0;
2584 }
2585
2586
2587 static int rtl8139_resume (struct pci_dev *pdev)
2588 {
2589 struct net_device *dev = pci_get_drvdata (pdev);
2590
2591 pci_restore_state (pdev);
2592 if (!netif_running (dev))
2593 return 0;
2594 pci_set_power_state (pdev, PCI_D0);
2595 rtl8139_init_ring (dev);
2596 rtl8139_hw_start (dev);
2597 netif_device_attach (dev);
2598 return 0;
2599 }
2600
2601 #endif /* CONFIG_PM */
2602
2603
2604 static struct pci_driver rtl8139_pci_driver = {
2605 .name = DRV_NAME,
2606 .id_table = rtl8139_pci_tbl,
2607 .probe = rtl8139_init_one,
2608 .remove = __devexit_p(rtl8139_remove_one),
2609 #ifdef CONFIG_PM
2610 .suspend = rtl8139_suspend,
2611 .resume = rtl8139_resume,
2612 #endif /* CONFIG_PM */
2613 };
2614
2615
2616 static int __init rtl8139_init_module (void)
2617 {
2618 /* when we're a module, we always print a version message,
2619 * even if no 8139 board is found.
2620 */
2621 #ifdef MODULE
2622 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2623 #endif
2624
2625 return pci_register_driver(&rtl8139_pci_driver);
2626 }
2627
2628
2629 static void __exit rtl8139_cleanup_module (void)
2630 {
2631 pci_unregister_driver (&rtl8139_pci_driver);
2632 }
2633
2634
2635 module_init(rtl8139_init_module);
2636 module_exit(rtl8139_cleanup_module);
Linux kernel - Deliverables
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