projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: TWL4030: Add functionalty to reset the registers
[deliverable/linux.git] / drivers / net / 8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/io.h>
112 #include <linux/uaccess.h>
113 #include <asm/irq.h>
114
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* define to 1, 2 or 3 to enable copious debugging info */
124 #define RTL8139_DEBUG 0
125
126 /* define to 1 to disable lightweight runtime debugging checks */
127 #undef RTL8139_NDEBUG
128
129
130 #ifdef RTL8139_NDEBUG
131 # define assert(expr) do {} while (0)
132 #else
133 # define assert(expr) \
134 if (unlikely(!(expr))) { \
135 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
136 #expr, __FILE__, __func__, __LINE__); \
137 }
138 #endif
139
140
141 /* A few user-configurable values. */
142 /* media options */
143 #define MAX_UNITS 8
144 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
145 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
146
147 /* Whether to use MMIO or PIO. Default to MMIO. */
148 #ifdef CONFIG_8139TOO_PIO
149 static int use_io = 1;
150 #else
151 static int use_io = 0;
152 #endif
153
154 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
155 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
156 static int multicast_filter_limit = 32;
157
158 /* bitmapped message enable number */
159 static int debug = -1;
160
161 /*
162 * Receive ring size
163 * Warning: 64K ring has hardware issues and may lock up.
164 */
165 #if defined(CONFIG_SH_DREAMCAST)
166 #define RX_BUF_IDX 0 /* 8K ring */
167 #else
168 #define RX_BUF_IDX 2 /* 32K ring */
169 #endif
170 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
171 #define RX_BUF_PAD 16
172 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
173
174 #if RX_BUF_LEN == 65536
175 #define RX_BUF_TOT_LEN RX_BUF_LEN
176 #else
177 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
178 #endif
179
180 /* Number of Tx descriptor registers. */
181 #define NUM_TX_DESC 4
182
183 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
184 #define MAX_ETH_FRAME_SIZE 1536
185
186 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
187 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
188 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
189
190 /* PCI Tuning Parameters
191 Threshold is bytes transferred to chip before transmission starts. */
192 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
193
194 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
195 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
196 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
197 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
198 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
199
200 /* Operational parameters that usually are not changed. */
201 /* Time in jiffies before concluding the transmitter is hung. */
202 #define TX_TIMEOUT (6*HZ)
203
204
205 enum {
206 HAS_MII_XCVR = 0x010000,
207 HAS_CHIP_XCVR = 0x020000,
208 HAS_LNK_CHNG = 0x040000,
209 };
210
211 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
212 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
213 #define RTL_MIN_IO_SIZE 0x80
214 #define RTL8139B_IO_SIZE 256
215
216 #define RTL8129_CAPS HAS_MII_XCVR
217 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
218
219 typedef enum {
220 RTL8139 = 0,
221 RTL8129,
222 } board_t;
223
224
225 /* indexed by board_t, above */
226 static const struct {
227 const char *name;
228 u32 hw_flags;
229 } board_info[] __devinitdata = {
230 { "RealTek RTL8139", RTL8139_CAPS },
231 { "RealTek RTL8129", RTL8129_CAPS },
232 };
233
234
235 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
236 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
237 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
238 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255
256 #ifdef CONFIG_SH_SECUREEDGE5410
257 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
258 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 #endif
260 #ifdef CONFIG_8139TOO_8129
261 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
262 #endif
263
264 /* some crazy cards report invalid vendor ids like
265 * 0x0001 here. The other ids are valid and constant,
266 * so we simply don't match on the main vendor id.
267 */
268 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
269 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
270 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
271
272 {0,}
273 };
274 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
275
276 static struct {
277 const char str[ETH_GSTRING_LEN];
278 } ethtool_stats_keys[] = {
279 { "early_rx" },
280 { "tx_buf_mapped" },
281 { "tx_timeouts" },
282 { "rx_lost_in_ring" },
283 };
284
285 /* The rest of these values should never change. */
286
287 /* Symbolic offsets to registers. */
288 enum RTL8139_registers {
289 MAC0 = 0, /* Ethernet hardware address. */
290 MAR0 = 8, /* Multicast filter. */
291 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
292 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
293 RxBuf = 0x30,
294 ChipCmd = 0x37,
295 RxBufPtr = 0x38,
296 RxBufAddr = 0x3A,
297 IntrMask = 0x3C,
298 IntrStatus = 0x3E,
299 TxConfig = 0x40,
300 RxConfig = 0x44,
301 Timer = 0x48, /* A general-purpose counter. */
302 RxMissed = 0x4C, /* 24 bits valid, write clears. */
303 Cfg9346 = 0x50,
304 Config0 = 0x51,
305 Config1 = 0x52,
306 TimerInt = 0x54,
307 MediaStatus = 0x58,
308 Config3 = 0x59,
309 Config4 = 0x5A, /* absent on RTL-8139A */
310 HltClk = 0x5B,
311 MultiIntr = 0x5C,
312 TxSummary = 0x60,
313 BasicModeCtrl = 0x62,
314 BasicModeStatus = 0x64,
315 NWayAdvert = 0x66,
316 NWayLPAR = 0x68,
317 NWayExpansion = 0x6A,
318 /* Undocumented registers, but required for proper operation. */
319 FIFOTMS = 0x70, /* FIFO Control and test. */
320 CSCR = 0x74, /* Chip Status and Configuration Register. */
321 PARA78 = 0x78,
322 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
323 PARA7c = 0x7c, /* Magic transceiver parameter register. */
324 Config5 = 0xD8, /* absent on RTL-8139A */
325 };
326
327 enum ClearBitMasks {
328 MultiIntrClear = 0xF000,
329 ChipCmdClear = 0xE2,
330 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
331 };
332
333 enum ChipCmdBits {
334 CmdReset = 0x10,
335 CmdRxEnb = 0x08,
336 CmdTxEnb = 0x04,
337 RxBufEmpty = 0x01,
338 };
339
340 /* Interrupt register bits, using my own meaningful names. */
341 enum IntrStatusBits {
342 PCIErr = 0x8000,
343 PCSTimeout = 0x4000,
344 RxFIFOOver = 0x40,
345 RxUnderrun = 0x20,
346 RxOverflow = 0x10,
347 TxErr = 0x08,
348 TxOK = 0x04,
349 RxErr = 0x02,
350 RxOK = 0x01,
351
352 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
353 };
354
355 enum TxStatusBits {
356 TxHostOwns = 0x2000,
357 TxUnderrun = 0x4000,
358 TxStatOK = 0x8000,
359 TxOutOfWindow = 0x20000000,
360 TxAborted = 0x40000000,
361 TxCarrierLost = 0x80000000,
362 };
363 enum RxStatusBits {
364 RxMulticast = 0x8000,
365 RxPhysical = 0x4000,
366 RxBroadcast = 0x2000,
367 RxBadSymbol = 0x0020,
368 RxRunt = 0x0010,
369 RxTooLong = 0x0008,
370 RxCRCErr = 0x0004,
371 RxBadAlign = 0x0002,
372 RxStatusOK = 0x0001,
373 };
374
375 /* Bits in RxConfig. */
376 enum rx_mode_bits {
377 AcceptErr = 0x20,
378 AcceptRunt = 0x10,
379 AcceptBroadcast = 0x08,
380 AcceptMulticast = 0x04,
381 AcceptMyPhys = 0x02,
382 AcceptAllPhys = 0x01,
383 };
384
385 /* Bits in TxConfig. */
386 enum tx_config_bits {
387 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
388 TxIFGShift = 24,
389 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
390 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
391 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
392 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
393
394 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
395 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
396 TxClearAbt = (1 << 0), /* Clear abort (WO) */
397 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
398 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
399
400 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
401 };
402
403 /* Bits in Config1 */
404 enum Config1Bits {
405 Cfg1_PM_Enable = 0x01,
406 Cfg1_VPD_Enable = 0x02,
407 Cfg1_PIO = 0x04,
408 Cfg1_MMIO = 0x08,
409 LWAKE = 0x10, /* not on 8139, 8139A */
410 Cfg1_Driver_Load = 0x20,
411 Cfg1_LED0 = 0x40,
412 Cfg1_LED1 = 0x80,
413 SLEEP = (1 << 1), /* only on 8139, 8139A */
414 PWRDN = (1 << 0), /* only on 8139, 8139A */
415 };
416
417 /* Bits in Config3 */
418 enum Config3Bits {
419 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
420 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
421 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
422 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
423 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
424 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
425 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
426 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
427 };
428
429 /* Bits in Config4 */
430 enum Config4Bits {
431 LWPTN = (1 << 2), /* not on 8139, 8139A */
432 };
433
434 /* Bits in Config5 */
435 enum Config5Bits {
436 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
437 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
438 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
439 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
440 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
441 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
442 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
443 };
444
445 enum RxConfigBits {
446 /* rx fifo threshold */
447 RxCfgFIFOShift = 13,
448 RxCfgFIFONone = (7 << RxCfgFIFOShift),
449
450 /* Max DMA burst */
451 RxCfgDMAShift = 8,
452 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
453
454 /* rx ring buffer length */
455 RxCfgRcv8K = 0,
456 RxCfgRcv16K = (1 << 11),
457 RxCfgRcv32K = (1 << 12),
458 RxCfgRcv64K = (1 << 11) | (1 << 12),
459
460 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
461 RxNoWrap = (1 << 7),
462 };
463
464 /* Twister tuning parameters from RealTek.
465 Completely undocumented, but required to tune bad links on some boards. */
466 enum CSCRBits {
467 CSCR_LinkOKBit = 0x0400,
468 CSCR_LinkChangeBit = 0x0800,
469 CSCR_LinkStatusBits = 0x0f000,
470 CSCR_LinkDownOffCmd = 0x003c0,
471 CSCR_LinkDownCmd = 0x0f3c0,
472 };
473
474 enum Cfg9346Bits {
475 Cfg9346_Lock = 0x00,
476 Cfg9346_Unlock = 0xC0,
477 };
478
479 typedef enum {
480 CH_8139 = 0,
481 CH_8139_K,
482 CH_8139A,
483 CH_8139A_G,
484 CH_8139B,
485 CH_8130,
486 CH_8139C,
487 CH_8100,
488 CH_8100B_8139D,
489 CH_8101,
490 } chip_t;
491
492 enum chip_flags {
493 HasHltClk = (1 << 0),
494 HasLWake = (1 << 1),
495 };
496
497 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
498 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
499 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
500
501 /* directly indexed by chip_t, above */
502 static const struct {
503 const char *name;
504 u32 version; /* from RTL8139C/RTL8139D docs */
505 u32 flags;
506 } rtl_chip_info[] = {
507 { "RTL-8139",
508 HW_REVID(1, 0, 0, 0, 0, 0, 0),
509 HasHltClk,
510 },
511
512 { "RTL-8139 rev K",
513 HW_REVID(1, 1, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139A",
518 HW_REVID(1, 1, 1, 0, 0, 0, 0),
519 HasHltClk, /* XXX undocumented? */
520 },
521
522 { "RTL-8139A rev G",
523 HW_REVID(1, 1, 1, 0, 0, 1, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139B",
528 HW_REVID(1, 1, 1, 1, 0, 0, 0),
529 HasLWake,
530 },
531
532 { "RTL-8130",
533 HW_REVID(1, 1, 1, 1, 1, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8139C",
538 HW_REVID(1, 1, 1, 0, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8100",
543 HW_REVID(1, 1, 1, 1, 0, 1, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100B/8139D",
548 HW_REVID(1, 1, 1, 0, 1, 0, 1),
549 HasHltClk /* XXX undocumented? */
550 | HasLWake,
551 },
552
553 { "RTL-8101",
554 HW_REVID(1, 1, 1, 0, 1, 1, 1),
555 HasLWake,
556 },
557 };
558
559 struct rtl_extra_stats {
560 unsigned long early_rx;
561 unsigned long tx_buf_mapped;
562 unsigned long tx_timeouts;
563 unsigned long rx_lost_in_ring;
564 };
565
566 struct rtl8139_private {
567 void __iomem *mmio_addr;
568 int drv_flags;
569 struct pci_dev *pci_dev;
570 u32 msg_enable;
571 struct napi_struct napi;
572 struct net_device *dev;
573
574 unsigned char *rx_ring;
575 unsigned int cur_rx; /* RX buf index of next pkt */
576 dma_addr_t rx_ring_dma;
577
578 unsigned int tx_flag;
579 unsigned long cur_tx;
580 unsigned long dirty_tx;
581 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
582 unsigned char *tx_bufs; /* Tx bounce buffer region. */
583 dma_addr_t tx_bufs_dma;
584
585 signed char phys[4]; /* MII device addresses. */
586
587 /* Twister tune state. */
588 char twistie, twist_row, twist_col;
589
590 unsigned int watchdog_fired : 1;
591 unsigned int default_port : 4; /* Last dev->if_port value. */
592 unsigned int have_thread : 1;
593
594 spinlock_t lock;
595 spinlock_t rx_lock;
596
597 chip_t chipset;
598 u32 rx_config;
599 struct rtl_extra_stats xstats;
600
601 struct delayed_work thread;
602
603 struct mii_if_info mii;
604 unsigned int regs_len;
605 unsigned long fifo_copy_timeout;
606 };
607
608 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
609 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
610 MODULE_LICENSE("GPL");
611 MODULE_VERSION(DRV_VERSION);
612
613 module_param(use_io, int, 0);
614 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
615 module_param(multicast_filter_limit, int, 0);
616 module_param_array(media, int, NULL, 0);
617 module_param_array(full_duplex, int, NULL, 0);
618 module_param(debug, int, 0);
619 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
620 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
621 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
622 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
623
624 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
625 static int rtl8139_open (struct net_device *dev);
626 static int mdio_read (struct net_device *dev, int phy_id, int location);
627 static void mdio_write (struct net_device *dev, int phy_id, int location,
628 int val);
629 static void rtl8139_start_thread(struct rtl8139_private *tp);
630 static void rtl8139_tx_timeout (struct net_device *dev);
631 static void rtl8139_init_ring (struct net_device *dev);
632 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
633 struct net_device *dev);
634 #ifdef CONFIG_NET_POLL_CONTROLLER
635 static void rtl8139_poll_controller(struct net_device *dev);
636 #endif
637 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
638 static int rtl8139_poll(struct napi_struct *napi, int budget);
639 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
640 static int rtl8139_close (struct net_device *dev);
641 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
642 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
643 static void rtl8139_set_rx_mode (struct net_device *dev);
644 static void __set_rx_mode (struct net_device *dev);
645 static void rtl8139_hw_start (struct net_device *dev);
646 static void rtl8139_thread (struct work_struct *work);
647 static void rtl8139_tx_timeout_task(struct work_struct *work);
648 static const struct ethtool_ops rtl8139_ethtool_ops;
649
650 /* write MMIO register, with flush */
651 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
652 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
653 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
654 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
655
656 /* write MMIO register */
657 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
658 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
659 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
660
661 /* read MMIO register */
662 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
663 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
664 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
665
666
667 static const u16 rtl8139_intr_mask =
668 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
669 TxErr | TxOK | RxErr | RxOK;
670
671 static const u16 rtl8139_norx_intr_mask =
672 PCIErr | PCSTimeout | RxUnderrun |
673 TxErr | TxOK | RxErr ;
674
675 #if RX_BUF_IDX == 0
676 static const unsigned int rtl8139_rx_config =
677 RxCfgRcv8K | RxNoWrap |
678 (RX_FIFO_THRESH << RxCfgFIFOShift) |
679 (RX_DMA_BURST << RxCfgDMAShift);
680 #elif RX_BUF_IDX == 1
681 static const unsigned int rtl8139_rx_config =
682 RxCfgRcv16K | RxNoWrap |
683 (RX_FIFO_THRESH << RxCfgFIFOShift) |
684 (RX_DMA_BURST << RxCfgDMAShift);
685 #elif RX_BUF_IDX == 2
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv32K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 3
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv64K |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #else
696 #error "Invalid configuration for 8139_RXBUF_IDX"
697 #endif
698
699 static const unsigned int rtl8139_tx_config =
700 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
701
702 static void __rtl8139_cleanup_dev (struct net_device *dev)
703 {
704 struct rtl8139_private *tp = netdev_priv(dev);
705 struct pci_dev *pdev;
706
707 assert (dev != NULL);
708 assert (tp->pci_dev != NULL);
709 pdev = tp->pci_dev;
710
711 if (tp->mmio_addr)
712 pci_iounmap (pdev, tp->mmio_addr);
713
714 /* it's ok to call this even if we have no regions to free */
715 pci_release_regions (pdev);
716
717 free_netdev(dev);
718 pci_set_drvdata (pdev, NULL);
719 }
720
721
722 static void rtl8139_chip_reset (void __iomem *ioaddr)
723 {
724 int i;
725
726 /* Soft reset the chip. */
727 RTL_W8 (ChipCmd, CmdReset);
728
729 /* Check that the chip has finished the reset. */
730 for (i = 1000; i > 0; i--) {
731 barrier();
732 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
733 break;
734 udelay (10);
735 }
736 }
737
738
739 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
740 {
741 void __iomem *ioaddr;
742 struct net_device *dev;
743 struct rtl8139_private *tp;
744 u8 tmp8;
745 int rc, disable_dev_on_err = 0;
746 unsigned int i;
747 unsigned long pio_start, pio_end, pio_flags, pio_len;
748 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
749 u32 version;
750
751 assert (pdev != NULL);
752
753 /* dev and priv zeroed in alloc_etherdev */
754 dev = alloc_etherdev (sizeof (*tp));
755 if (dev == NULL) {
756 dev_err(&pdev->dev, "Unable to alloc new net device\n");
757 return ERR_PTR(-ENOMEM);
758 }
759 SET_NETDEV_DEV(dev, &pdev->dev);
760
761 tp = netdev_priv(dev);
762 tp->pci_dev = pdev;
763
764 /* enable device (incl. PCI PM wakeup and hotplug setup) */
765 rc = pci_enable_device (pdev);
766 if (rc)
767 goto err_out;
768
769 pio_start = pci_resource_start (pdev, 0);
770 pio_end = pci_resource_end (pdev, 0);
771 pio_flags = pci_resource_flags (pdev, 0);
772 pio_len = pci_resource_len (pdev, 0);
773
774 mmio_start = pci_resource_start (pdev, 1);
775 mmio_end = pci_resource_end (pdev, 1);
776 mmio_flags = pci_resource_flags (pdev, 1);
777 mmio_len = pci_resource_len (pdev, 1);
778
779 /* set this immediately, we need to know before
780 * we talk to the chip directly */
781 pr_debug("PIO region size == 0x%02lX\n", pio_len);
782 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
783
784 retry:
785 if (use_io) {
786 /* make sure PCI base addr 0 is PIO */
787 if (!(pio_flags & IORESOURCE_IO)) {
788 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
789 rc = -ENODEV;
790 goto err_out;
791 }
792 /* check for weird/broken PCI region reporting */
793 if (pio_len < RTL_MIN_IO_SIZE) {
794 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
795 rc = -ENODEV;
796 goto err_out;
797 }
798 } else {
799 /* make sure PCI base addr 1 is MMIO */
800 if (!(mmio_flags & IORESOURCE_MEM)) {
801 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
802 rc = -ENODEV;
803 goto err_out;
804 }
805 if (mmio_len < RTL_MIN_IO_SIZE) {
806 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
807 rc = -ENODEV;
808 goto err_out;
809 }
810 }
811
812 rc = pci_request_regions (pdev, DRV_NAME);
813 if (rc)
814 goto err_out;
815 disable_dev_on_err = 1;
816
817 /* enable PCI bus-mastering */
818 pci_set_master (pdev);
819
820 if (use_io) {
821 ioaddr = pci_iomap(pdev, 0, 0);
822 if (!ioaddr) {
823 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
824 rc = -EIO;
825 goto err_out;
826 }
827 dev->base_addr = pio_start;
828 tp->regs_len = pio_len;
829 } else {
830 /* ioremap MMIO region */
831 ioaddr = pci_iomap(pdev, 1, 0);
832 if (ioaddr == NULL) {
833 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
834 pci_release_regions(pdev);
835 use_io = 1;
836 goto retry;
837 }
838 dev->base_addr = (long) ioaddr;
839 tp->regs_len = mmio_len;
840 }
841 tp->mmio_addr = ioaddr;
842
843 /* Bring old chips out of low-power mode. */
844 RTL_W8 (HltClk, 'R');
845
846 /* check for missing/broken hardware */
847 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
848 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
849 rc = -EIO;
850 goto err_out;
851 }
852
853 /* identify chip attached to board */
854 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
855 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
856 if (version == rtl_chip_info[i].version) {
857 tp->chipset = i;
858 goto match;
859 }
860
861 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
862 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
863 dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
864 tp->chipset = 0;
865
866 match:
867 pr_debug("chipset id (%d) == index %d, '%s'\n",
868 version, i, rtl_chip_info[i].name);
869
870 if (tp->chipset >= CH_8139B) {
871 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
872 pr_debug("PCI PM wakeup\n");
873 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
874 (tmp8 & LWAKE))
875 new_tmp8 &= ~LWAKE;
876 new_tmp8 |= Cfg1_PM_Enable;
877 if (new_tmp8 != tmp8) {
878 RTL_W8 (Cfg9346, Cfg9346_Unlock);
879 RTL_W8 (Config1, tmp8);
880 RTL_W8 (Cfg9346, Cfg9346_Lock);
881 }
882 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
883 tmp8 = RTL_R8 (Config4);
884 if (tmp8 & LWPTN) {
885 RTL_W8 (Cfg9346, Cfg9346_Unlock);
886 RTL_W8 (Config4, tmp8 & ~LWPTN);
887 RTL_W8 (Cfg9346, Cfg9346_Lock);
888 }
889 }
890 } else {
891 pr_debug("Old chip wakeup\n");
892 tmp8 = RTL_R8 (Config1);
893 tmp8 &= ~(SLEEP | PWRDN);
894 RTL_W8 (Config1, tmp8);
895 }
896
897 rtl8139_chip_reset (ioaddr);
898
899 return dev;
900
901 err_out:
902 __rtl8139_cleanup_dev (dev);
903 if (disable_dev_on_err)
904 pci_disable_device (pdev);
905 return ERR_PTR(rc);
906 }
907
908 static const struct net_device_ops rtl8139_netdev_ops = {
909 .ndo_open = rtl8139_open,
910 .ndo_stop = rtl8139_close,
911 .ndo_get_stats = rtl8139_get_stats,
912 .ndo_change_mtu = eth_change_mtu,
913 .ndo_validate_addr = eth_validate_addr,
914 .ndo_set_mac_address = rtl8139_set_mac_address,
915 .ndo_start_xmit = rtl8139_start_xmit,
916 .ndo_set_multicast_list = rtl8139_set_rx_mode,
917 .ndo_do_ioctl = netdev_ioctl,
918 .ndo_tx_timeout = rtl8139_tx_timeout,
919 #ifdef CONFIG_NET_POLL_CONTROLLER
920 .ndo_poll_controller = rtl8139_poll_controller,
921 #endif
922 };
923
924 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
925 const struct pci_device_id *ent)
926 {
927 struct net_device *dev = NULL;
928 struct rtl8139_private *tp;
929 int i, addr_len, option;
930 void __iomem *ioaddr;
931 static int board_idx = -1;
932
933 assert (pdev != NULL);
934 assert (ent != NULL);
935
936 board_idx++;
937
938 /* when we're built into the kernel, the driver version message
939 * is only printed if at least one 8139 board has been found
940 */
941 #ifndef MODULE
942 {
943 static int printed_version;
944 if (!printed_version++)
945 pr_info(RTL8139_DRIVER_NAME "\n");
946 }
947 #endif
948
949 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
950 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
951 dev_info(&pdev->dev,
952 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
953 pdev->vendor, pdev->device, pdev->revision);
954 return -ENODEV;
955 }
956
957 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
958 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
959 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
960 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
961 pr_info("OQO Model 2 detected. Forcing PIO\n");
962 use_io = 1;
963 }
964
965 dev = rtl8139_init_board (pdev);
966 if (IS_ERR(dev))
967 return PTR_ERR(dev);
968
969 assert (dev != NULL);
970 tp = netdev_priv(dev);
971 tp->dev = dev;
972
973 ioaddr = tp->mmio_addr;
974 assert (ioaddr != NULL);
975
976 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
977 for (i = 0; i < 3; i++)
978 ((__le16 *) (dev->dev_addr))[i] =
979 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
980 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
981
982 /* The Rtl8139-specific entries in the device structure. */
983 dev->netdev_ops = &rtl8139_netdev_ops;
984 dev->ethtool_ops = &rtl8139_ethtool_ops;
985 dev->watchdog_timeo = TX_TIMEOUT;
986 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
987
988 /* note: the hardware is not capable of sg/csum/highdma, however
989 * through the use of skb_copy_and_csum_dev we enable these
990 * features
991 */
992 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
993
994 dev->irq = pdev->irq;
995
996 /* tp zeroed and aligned in alloc_etherdev */
997 tp = netdev_priv(dev);
998
999 /* note: tp->chipset set in rtl8139_init_board */
1000 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1001 tp->mmio_addr = ioaddr;
1002 tp->msg_enable =
1003 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1004 spin_lock_init (&tp->lock);
1005 spin_lock_init (&tp->rx_lock);
1006 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1007 tp->mii.dev = dev;
1008 tp->mii.mdio_read = mdio_read;
1009 tp->mii.mdio_write = mdio_write;
1010 tp->mii.phy_id_mask = 0x3f;
1011 tp->mii.reg_num_mask = 0x1f;
1012
1013 /* dev is fully set up and ready to use now */
1014 pr_debug("about to register device named %s (%p)...\n",
1015 dev->name, dev);
1016 i = register_netdev (dev);
1017 if (i) goto err_out;
1018
1019 pci_set_drvdata (pdev, dev);
1020
1021 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n",
1022 board_info[ent->driver_data].name,
1023 dev->base_addr, dev->dev_addr, dev->irq);
1024
1025 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1026 rtl_chip_info[tp->chipset].name);
1027
1028 /* Find the connected MII xcvrs.
1029 Doing this in open() would allow detecting external xcvrs later, but
1030 takes too much time. */
1031 #ifdef CONFIG_8139TOO_8129
1032 if (tp->drv_flags & HAS_MII_XCVR) {
1033 int phy, phy_idx = 0;
1034 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1035 int mii_status = mdio_read(dev, phy, 1);
1036 if (mii_status != 0xffff && mii_status != 0x0000) {
1037 u16 advertising = mdio_read(dev, phy, 4);
1038 tp->phys[phy_idx++] = phy;
1039 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1040 phy, mii_status, advertising);
1041 }
1042 }
1043 if (phy_idx == 0) {
1044 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1045 tp->phys[0] = 32;
1046 }
1047 } else
1048 #endif
1049 tp->phys[0] = 32;
1050 tp->mii.phy_id = tp->phys[0];
1051
1052 /* The lower four bits are the media type. */
1053 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1054 if (option > 0) {
1055 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1056 tp->default_port = option & 0xFF;
1057 if (tp->default_port)
1058 tp->mii.force_media = 1;
1059 }
1060 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1061 tp->mii.full_duplex = full_duplex[board_idx];
1062 if (tp->mii.full_duplex) {
1063 netdev_info(dev, "Media type forced to Full Duplex\n");
1064 /* Changing the MII-advertised media because might prevent
1065 re-connection. */
1066 tp->mii.force_media = 1;
1067 }
1068 if (tp->default_port) {
1069 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1070 (option & 0x20 ? 100 : 10),
1071 (option & 0x10 ? "full" : "half"));
1072 mdio_write(dev, tp->phys[0], 0,
1073 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1074 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1075 }
1076
1077 /* Put the chip into low-power mode. */
1078 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1079 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1080
1081 return 0;
1082
1083 err_out:
1084 __rtl8139_cleanup_dev (dev);
1085 pci_disable_device (pdev);
1086 return i;
1087 }
1088
1089
1090 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1091 {
1092 struct net_device *dev = pci_get_drvdata (pdev);
1093
1094 assert (dev != NULL);
1095
1096 flush_scheduled_work();
1097
1098 unregister_netdev (dev);
1099
1100 __rtl8139_cleanup_dev (dev);
1101 pci_disable_device (pdev);
1102 }
1103
1104
1105 /* Serial EEPROM section. */
1106
1107 /* EEPROM_Ctrl bits. */
1108 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1109 #define EE_CS 0x08 /* EEPROM chip select. */
1110 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1111 #define EE_WRITE_0 0x00
1112 #define EE_WRITE_1 0x02
1113 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1114 #define EE_ENB (0x80 | EE_CS)
1115
1116 /* Delay between EEPROM clock transitions.
1117 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1118 */
1119
1120 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1121
1122 /* The EEPROM commands include the alway-set leading bit. */
1123 #define EE_WRITE_CMD (5)
1124 #define EE_READ_CMD (6)
1125 #define EE_ERASE_CMD (7)
1126
1127 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1128 {
1129 int i;
1130 unsigned retval = 0;
1131 int read_cmd = location | (EE_READ_CMD << addr_len);
1132
1133 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1134 RTL_W8 (Cfg9346, EE_ENB);
1135 eeprom_delay ();
1136
1137 /* Shift the read command bits out. */
1138 for (i = 4 + addr_len; i >= 0; i--) {
1139 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1140 RTL_W8 (Cfg9346, EE_ENB | dataval);
1141 eeprom_delay ();
1142 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1143 eeprom_delay ();
1144 }
1145 RTL_W8 (Cfg9346, EE_ENB);
1146 eeprom_delay ();
1147
1148 for (i = 16; i > 0; i--) {
1149 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1150 eeprom_delay ();
1151 retval =
1152 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1153 0);
1154 RTL_W8 (Cfg9346, EE_ENB);
1155 eeprom_delay ();
1156 }
1157
1158 /* Terminate the EEPROM access. */
1159 RTL_W8 (Cfg9346, ~EE_CS);
1160 eeprom_delay ();
1161
1162 return retval;
1163 }
1164
1165 /* MII serial management: mostly bogus for now. */
1166 /* Read and write the MII management registers using software-generated
1167 serial MDIO protocol.
1168 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1169 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1170 "overclocking" issues. */
1171 #define MDIO_DIR 0x80
1172 #define MDIO_DATA_OUT 0x04
1173 #define MDIO_DATA_IN 0x02
1174 #define MDIO_CLK 0x01
1175 #define MDIO_WRITE0 (MDIO_DIR)
1176 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1177
1178 #define mdio_delay() RTL_R8(Config4)
1179
1180
1181 static const char mii_2_8139_map[8] = {
1182 BasicModeCtrl,
1183 BasicModeStatus,
1184 0,
1185 0,
1186 NWayAdvert,
1187 NWayLPAR,
1188 NWayExpansion,
1189 0
1190 };
1191
1192
1193 #ifdef CONFIG_8139TOO_8129
1194 /* Syncronize the MII management interface by shifting 32 one bits out. */
1195 static void mdio_sync (void __iomem *ioaddr)
1196 {
1197 int i;
1198
1199 for (i = 32; i >= 0; i--) {
1200 RTL_W8 (Config4, MDIO_WRITE1);
1201 mdio_delay ();
1202 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1203 mdio_delay ();
1204 }
1205 }
1206 #endif
1207
1208 static int mdio_read (struct net_device *dev, int phy_id, int location)
1209 {
1210 struct rtl8139_private *tp = netdev_priv(dev);
1211 int retval = 0;
1212 #ifdef CONFIG_8139TOO_8129
1213 void __iomem *ioaddr = tp->mmio_addr;
1214 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1215 int i;
1216 #endif
1217
1218 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1219 void __iomem *ioaddr = tp->mmio_addr;
1220 return location < 8 && mii_2_8139_map[location] ?
1221 RTL_R16 (mii_2_8139_map[location]) : 0;
1222 }
1223
1224 #ifdef CONFIG_8139TOO_8129
1225 mdio_sync (ioaddr);
1226 /* Shift the read command bits out. */
1227 for (i = 15; i >= 0; i--) {
1228 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1229
1230 RTL_W8 (Config4, MDIO_DIR | dataval);
1231 mdio_delay ();
1232 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1233 mdio_delay ();
1234 }
1235
1236 /* Read the two transition, 16 data, and wire-idle bits. */
1237 for (i = 19; i > 0; i--) {
1238 RTL_W8 (Config4, 0);
1239 mdio_delay ();
1240 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1241 RTL_W8 (Config4, MDIO_CLK);
1242 mdio_delay ();
1243 }
1244 #endif
1245
1246 return (retval >> 1) & 0xffff;
1247 }
1248
1249
1250 static void mdio_write (struct net_device *dev, int phy_id, int location,
1251 int value)
1252 {
1253 struct rtl8139_private *tp = netdev_priv(dev);
1254 #ifdef CONFIG_8139TOO_8129
1255 void __iomem *ioaddr = tp->mmio_addr;
1256 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1257 int i;
1258 #endif
1259
1260 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1261 void __iomem *ioaddr = tp->mmio_addr;
1262 if (location == 0) {
1263 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1264 RTL_W16 (BasicModeCtrl, value);
1265 RTL_W8 (Cfg9346, Cfg9346_Lock);
1266 } else if (location < 8 && mii_2_8139_map[location])
1267 RTL_W16 (mii_2_8139_map[location], value);
1268 return;
1269 }
1270
1271 #ifdef CONFIG_8139TOO_8129
1272 mdio_sync (ioaddr);
1273
1274 /* Shift the command bits out. */
1275 for (i = 31; i >= 0; i--) {
1276 int dataval =
1277 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1278 RTL_W8 (Config4, dataval);
1279 mdio_delay ();
1280 RTL_W8 (Config4, dataval | MDIO_CLK);
1281 mdio_delay ();
1282 }
1283 /* Clear out extra bits. */
1284 for (i = 2; i > 0; i--) {
1285 RTL_W8 (Config4, 0);
1286 mdio_delay ();
1287 RTL_W8 (Config4, MDIO_CLK);
1288 mdio_delay ();
1289 }
1290 #endif
1291 }
1292
1293
1294 static int rtl8139_open (struct net_device *dev)
1295 {
1296 struct rtl8139_private *tp = netdev_priv(dev);
1297 int retval;
1298 void __iomem *ioaddr = tp->mmio_addr;
1299
1300 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1301 if (retval)
1302 return retval;
1303
1304 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1305 &tp->tx_bufs_dma, GFP_KERNEL);
1306 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1307 &tp->rx_ring_dma, GFP_KERNEL);
1308 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1309 free_irq(dev->irq, dev);
1310
1311 if (tp->tx_bufs)
1312 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1313 tp->tx_bufs, tp->tx_bufs_dma);
1314 if (tp->rx_ring)
1315 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1316 tp->rx_ring, tp->rx_ring_dma);
1317
1318 return -ENOMEM;
1319
1320 }
1321
1322 napi_enable(&tp->napi);
1323
1324 tp->mii.full_duplex = tp->mii.force_media;
1325 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1326
1327 rtl8139_init_ring (dev);
1328 rtl8139_hw_start (dev);
1329 netif_start_queue (dev);
1330
1331 netif_dbg(tp, ifup, dev,
1332 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1333 __func__,
1334 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1335 dev->irq, RTL_R8 (MediaStatus),
1336 tp->mii.full_duplex ? "full" : "half");
1337
1338 rtl8139_start_thread(tp);
1339
1340 return 0;
1341 }
1342
1343
1344 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1345 {
1346 struct rtl8139_private *tp = netdev_priv(dev);
1347
1348 if (tp->phys[0] >= 0) {
1349 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1350 }
1351 }
1352
1353 /* Start the hardware at open or resume. */
1354 static void rtl8139_hw_start (struct net_device *dev)
1355 {
1356 struct rtl8139_private *tp = netdev_priv(dev);
1357 void __iomem *ioaddr = tp->mmio_addr;
1358 u32 i;
1359 u8 tmp;
1360
1361 /* Bring old chips out of low-power mode. */
1362 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1363 RTL_W8 (HltClk, 'R');
1364
1365 rtl8139_chip_reset (ioaddr);
1366
1367 /* unlock Config[01234] and BMCR register writes */
1368 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1369 /* Restore our idea of the MAC address. */
1370 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1371 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1372
1373 tp->cur_rx = 0;
1374
1375 /* init Rx ring buffer DMA address */
1376 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1377
1378 /* Must enable Tx/Rx before setting transfer thresholds! */
1379 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1380
1381 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1382 RTL_W32 (RxConfig, tp->rx_config);
1383 RTL_W32 (TxConfig, rtl8139_tx_config);
1384
1385 rtl_check_media (dev, 1);
1386
1387 if (tp->chipset >= CH_8139B) {
1388 /* Disable magic packet scanning, which is enabled
1389 * when PM is enabled in Config1. It can be reenabled
1390 * via ETHTOOL_SWOL if desired. */
1391 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1392 }
1393
1394 netdev_dbg(dev, "init buffer addresses\n");
1395
1396 /* Lock Config[01234] and BMCR register writes */
1397 RTL_W8 (Cfg9346, Cfg9346_Lock);
1398
1399 /* init Tx buffer DMA addresses */
1400 for (i = 0; i < NUM_TX_DESC; i++)
1401 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1402
1403 RTL_W32 (RxMissed, 0);
1404
1405 rtl8139_set_rx_mode (dev);
1406
1407 /* no early-rx interrupts */
1408 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1409
1410 /* make sure RxTx has started */
1411 tmp = RTL_R8 (ChipCmd);
1412 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1413 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1414
1415 /* Enable all known interrupts by setting the interrupt mask. */
1416 RTL_W16 (IntrMask, rtl8139_intr_mask);
1417 }
1418
1419
1420 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1421 static void rtl8139_init_ring (struct net_device *dev)
1422 {
1423 struct rtl8139_private *tp = netdev_priv(dev);
1424 int i;
1425
1426 tp->cur_rx = 0;
1427 tp->cur_tx = 0;
1428 tp->dirty_tx = 0;
1429
1430 for (i = 0; i < NUM_TX_DESC; i++)
1431 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1432 }
1433
1434
1435 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1436 static int next_tick = 3 * HZ;
1437
1438 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1439 static inline void rtl8139_tune_twister (struct net_device *dev,
1440 struct rtl8139_private *tp) {}
1441 #else
1442 enum TwisterParamVals {
1443 PARA78_default = 0x78fa8388,
1444 PARA7c_default = 0xcb38de43, /* param[0][3] */
1445 PARA7c_xxx = 0xcb38de43,
1446 };
1447
1448 static const unsigned long param[4][4] = {
1449 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1450 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1451 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1452 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1453 };
1454
1455 static void rtl8139_tune_twister (struct net_device *dev,
1456 struct rtl8139_private *tp)
1457 {
1458 int linkcase;
1459 void __iomem *ioaddr = tp->mmio_addr;
1460
1461 /* This is a complicated state machine to configure the "twister" for
1462 impedance/echos based on the cable length.
1463 All of this is magic and undocumented.
1464 */
1465 switch (tp->twistie) {
1466 case 1:
1467 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1468 /* We have link beat, let us tune the twister. */
1469 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1470 tp->twistie = 2; /* Change to state 2. */
1471 next_tick = HZ / 10;
1472 } else {
1473 /* Just put in some reasonable defaults for when beat returns. */
1474 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1475 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1476 RTL_W32 (PARA78, PARA78_default);
1477 RTL_W32 (PARA7c, PARA7c_default);
1478 tp->twistie = 0; /* Bail from future actions. */
1479 }
1480 break;
1481 case 2:
1482 /* Read how long it took to hear the echo. */
1483 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1484 if (linkcase == 0x7000)
1485 tp->twist_row = 3;
1486 else if (linkcase == 0x3000)
1487 tp->twist_row = 2;
1488 else if (linkcase == 0x1000)
1489 tp->twist_row = 1;
1490 else
1491 tp->twist_row = 0;
1492 tp->twist_col = 0;
1493 tp->twistie = 3; /* Change to state 2. */
1494 next_tick = HZ / 10;
1495 break;
1496 case 3:
1497 /* Put out four tuning parameters, one per 100msec. */
1498 if (tp->twist_col == 0)
1499 RTL_W16 (FIFOTMS, 0);
1500 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1501 [(int) tp->twist_col]);
1502 next_tick = HZ / 10;
1503 if (++tp->twist_col >= 4) {
1504 /* For short cables we are done.
1505 For long cables (row == 3) check for mistune. */
1506 tp->twistie =
1507 (tp->twist_row == 3) ? 4 : 0;
1508 }
1509 break;
1510 case 4:
1511 /* Special case for long cables: check for mistune. */
1512 if ((RTL_R16 (CSCR) &
1513 CSCR_LinkStatusBits) == 0x7000) {
1514 tp->twistie = 0;
1515 break;
1516 } else {
1517 RTL_W32 (PARA7c, 0xfb38de03);
1518 tp->twistie = 5;
1519 next_tick = HZ / 10;
1520 }
1521 break;
1522 case 5:
1523 /* Retune for shorter cable (column 2). */
1524 RTL_W32 (FIFOTMS, 0x20);
1525 RTL_W32 (PARA78, PARA78_default);
1526 RTL_W32 (PARA7c, PARA7c_default);
1527 RTL_W32 (FIFOTMS, 0x00);
1528 tp->twist_row = 2;
1529 tp->twist_col = 0;
1530 tp->twistie = 3;
1531 next_tick = HZ / 10;
1532 break;
1533
1534 default:
1535 /* do nothing */
1536 break;
1537 }
1538 }
1539 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1540
1541 static inline void rtl8139_thread_iter (struct net_device *dev,
1542 struct rtl8139_private *tp,
1543 void __iomem *ioaddr)
1544 {
1545 int mii_lpa;
1546
1547 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1548
1549 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1550 int duplex = ((mii_lpa & LPA_100FULL) ||
1551 (mii_lpa & 0x01C0) == 0x0040);
1552 if (tp->mii.full_duplex != duplex) {
1553 tp->mii.full_duplex = duplex;
1554
1555 if (mii_lpa) {
1556 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1557 tp->mii.full_duplex ? "full" : "half",
1558 tp->phys[0], mii_lpa);
1559 } else {
1560 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1561 }
1562 #if 0
1563 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1564 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1565 RTL_W8 (Cfg9346, Cfg9346_Lock);
1566 #endif
1567 }
1568 }
1569
1570 next_tick = HZ * 60;
1571
1572 rtl8139_tune_twister (dev, tp);
1573
1574 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1575 RTL_R16(NWayLPAR));
1576 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1577 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1578 netdev_dbg(dev, "Chip config %02x %02x\n",
1579 RTL_R8(Config0), RTL_R8(Config1));
1580 }
1581
1582 static void rtl8139_thread (struct work_struct *work)
1583 {
1584 struct rtl8139_private *tp =
1585 container_of(work, struct rtl8139_private, thread.work);
1586 struct net_device *dev = tp->mii.dev;
1587 unsigned long thr_delay = next_tick;
1588
1589 rtnl_lock();
1590
1591 if (!netif_running(dev))
1592 goto out_unlock;
1593
1594 if (tp->watchdog_fired) {
1595 tp->watchdog_fired = 0;
1596 rtl8139_tx_timeout_task(work);
1597 } else
1598 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1599
1600 if (tp->have_thread)
1601 schedule_delayed_work(&tp->thread, thr_delay);
1602 out_unlock:
1603 rtnl_unlock ();
1604 }
1605
1606 static void rtl8139_start_thread(struct rtl8139_private *tp)
1607 {
1608 tp->twistie = 0;
1609 if (tp->chipset == CH_8139_K)
1610 tp->twistie = 1;
1611 else if (tp->drv_flags & HAS_LNK_CHNG)
1612 return;
1613
1614 tp->have_thread = 1;
1615 tp->watchdog_fired = 0;
1616
1617 schedule_delayed_work(&tp->thread, next_tick);
1618 }
1619
1620 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1621 {
1622 tp->cur_tx = 0;
1623 tp->dirty_tx = 0;
1624
1625 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1626 }
1627
1628 static void rtl8139_tx_timeout_task (struct work_struct *work)
1629 {
1630 struct rtl8139_private *tp =
1631 container_of(work, struct rtl8139_private, thread.work);
1632 struct net_device *dev = tp->mii.dev;
1633 void __iomem *ioaddr = tp->mmio_addr;
1634 int i;
1635 u8 tmp8;
1636
1637 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1638 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1639 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1640 /* Emit info to figure out what went wrong. */
1641 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1642 tp->cur_tx, tp->dirty_tx);
1643 for (i = 0; i < NUM_TX_DESC; i++)
1644 netdev_dbg(dev, "Tx descriptor %d is %08lx%s\n",
1645 i, RTL_R32(TxStatus0 + (i * 4)),
1646 i == tp->dirty_tx % NUM_TX_DESC ?
1647 " (queue head)" : "");
1648
1649 tp->xstats.tx_timeouts++;
1650
1651 /* disable Tx ASAP, if not already */
1652 tmp8 = RTL_R8 (ChipCmd);
1653 if (tmp8 & CmdTxEnb)
1654 RTL_W8 (ChipCmd, CmdRxEnb);
1655
1656 spin_lock_bh(&tp->rx_lock);
1657 /* Disable interrupts by clearing the interrupt mask. */
1658 RTL_W16 (IntrMask, 0x0000);
1659
1660 /* Stop a shared interrupt from scavenging while we are. */
1661 spin_lock_irq(&tp->lock);
1662 rtl8139_tx_clear (tp);
1663 spin_unlock_irq(&tp->lock);
1664
1665 /* ...and finally, reset everything */
1666 if (netif_running(dev)) {
1667 rtl8139_hw_start (dev);
1668 netif_wake_queue (dev);
1669 }
1670 spin_unlock_bh(&tp->rx_lock);
1671 }
1672
1673 static void rtl8139_tx_timeout (struct net_device *dev)
1674 {
1675 struct rtl8139_private *tp = netdev_priv(dev);
1676
1677 tp->watchdog_fired = 1;
1678 if (!tp->have_thread) {
1679 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1680 schedule_delayed_work(&tp->thread, next_tick);
1681 }
1682 }
1683
1684 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1685 struct net_device *dev)
1686 {
1687 struct rtl8139_private *tp = netdev_priv(dev);
1688 void __iomem *ioaddr = tp->mmio_addr;
1689 unsigned int entry;
1690 unsigned int len = skb->len;
1691 unsigned long flags;
1692
1693 /* Calculate the next Tx descriptor entry. */
1694 entry = tp->cur_tx % NUM_TX_DESC;
1695
1696 /* Note: the chip doesn't have auto-pad! */
1697 if (likely(len < TX_BUF_SIZE)) {
1698 if (len < ETH_ZLEN)
1699 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1700 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1701 dev_kfree_skb(skb);
1702 } else {
1703 dev_kfree_skb(skb);
1704 dev->stats.tx_dropped++;
1705 return NETDEV_TX_OK;
1706 }
1707
1708 spin_lock_irqsave(&tp->lock, flags);
1709 /*
1710 * Writing to TxStatus triggers a DMA transfer of the data
1711 * copied to tp->tx_buf[entry] above. Use a memory barrier
1712 * to make sure that the device sees the updated data.
1713 */
1714 wmb();
1715 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1716 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1717
1718 dev->trans_start = jiffies;
1719
1720 tp->cur_tx++;
1721
1722 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1723 netif_stop_queue (dev);
1724 spin_unlock_irqrestore(&tp->lock, flags);
1725
1726 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1727 len, entry);
1728
1729 return NETDEV_TX_OK;
1730 }
1731
1732
1733 static void rtl8139_tx_interrupt (struct net_device *dev,
1734 struct rtl8139_private *tp,
1735 void __iomem *ioaddr)
1736 {
1737 unsigned long dirty_tx, tx_left;
1738
1739 assert (dev != NULL);
1740 assert (ioaddr != NULL);
1741
1742 dirty_tx = tp->dirty_tx;
1743 tx_left = tp->cur_tx - dirty_tx;
1744 while (tx_left > 0) {
1745 int entry = dirty_tx % NUM_TX_DESC;
1746 int txstatus;
1747
1748 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1749
1750 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1751 break; /* It still hasn't been Txed */
1752
1753 /* Note: TxCarrierLost is always asserted at 100mbps. */
1754 if (txstatus & (TxOutOfWindow | TxAborted)) {
1755 /* There was an major error, log it. */
1756 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1757 txstatus);
1758 dev->stats.tx_errors++;
1759 if (txstatus & TxAborted) {
1760 dev->stats.tx_aborted_errors++;
1761 RTL_W32 (TxConfig, TxClearAbt);
1762 RTL_W16 (IntrStatus, TxErr);
1763 wmb();
1764 }
1765 if (txstatus & TxCarrierLost)
1766 dev->stats.tx_carrier_errors++;
1767 if (txstatus & TxOutOfWindow)
1768 dev->stats.tx_window_errors++;
1769 } else {
1770 if (txstatus & TxUnderrun) {
1771 /* Add 64 to the Tx FIFO threshold. */
1772 if (tp->tx_flag < 0x00300000)
1773 tp->tx_flag += 0x00020000;
1774 dev->stats.tx_fifo_errors++;
1775 }
1776 dev->stats.collisions += (txstatus >> 24) & 15;
1777 dev->stats.tx_bytes += txstatus & 0x7ff;
1778 dev->stats.tx_packets++;
1779 }
1780
1781 dirty_tx++;
1782 tx_left--;
1783 }
1784
1785 #ifndef RTL8139_NDEBUG
1786 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1787 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1788 dirty_tx, tp->cur_tx);
1789 dirty_tx += NUM_TX_DESC;
1790 }
1791 #endif /* RTL8139_NDEBUG */
1792
1793 /* only wake the queue if we did work, and the queue is stopped */
1794 if (tp->dirty_tx != dirty_tx) {
1795 tp->dirty_tx = dirty_tx;
1796 mb();
1797 netif_wake_queue (dev);
1798 }
1799 }
1800
1801
1802 /* TODO: clean this up! Rx reset need not be this intensive */
1803 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1804 struct rtl8139_private *tp, void __iomem *ioaddr)
1805 {
1806 u8 tmp8;
1807 #ifdef CONFIG_8139_OLD_RX_RESET
1808 int tmp_work;
1809 #endif
1810
1811 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1812 rx_status);
1813 dev->stats.rx_errors++;
1814 if (!(rx_status & RxStatusOK)) {
1815 if (rx_status & RxTooLong) {
1816 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1817 rx_status);
1818 /* A.C.: The chip hangs here. */
1819 }
1820 if (rx_status & (RxBadSymbol | RxBadAlign))
1821 dev->stats.rx_frame_errors++;
1822 if (rx_status & (RxRunt | RxTooLong))
1823 dev->stats.rx_length_errors++;
1824 if (rx_status & RxCRCErr)
1825 dev->stats.rx_crc_errors++;
1826 } else {
1827 tp->xstats.rx_lost_in_ring++;
1828 }
1829
1830 #ifndef CONFIG_8139_OLD_RX_RESET
1831 tmp8 = RTL_R8 (ChipCmd);
1832 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1833 RTL_W8 (ChipCmd, tmp8);
1834 RTL_W32 (RxConfig, tp->rx_config);
1835 tp->cur_rx = 0;
1836 #else
1837 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1838
1839 /* disable receive */
1840 RTL_W8_F (ChipCmd, CmdTxEnb);
1841 tmp_work = 200;
1842 while (--tmp_work > 0) {
1843 udelay(1);
1844 tmp8 = RTL_R8 (ChipCmd);
1845 if (!(tmp8 & CmdRxEnb))
1846 break;
1847 }
1848 if (tmp_work <= 0)
1849 netdev_warn(dev, "rx stop wait too long\n");
1850 /* restart receive */
1851 tmp_work = 200;
1852 while (--tmp_work > 0) {
1853 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1854 udelay(1);
1855 tmp8 = RTL_R8 (ChipCmd);
1856 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1857 break;
1858 }
1859 if (tmp_work <= 0)
1860 netdev_warn(dev, "tx/rx enable wait too long\n");
1861
1862 /* and reinitialize all rx related registers */
1863 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1864 /* Must enable Tx/Rx before setting transfer thresholds! */
1865 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1866
1867 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1868 RTL_W32 (RxConfig, tp->rx_config);
1869 tp->cur_rx = 0;
1870
1871 netdev_dbg(dev, "init buffer addresses\n");
1872
1873 /* Lock Config[01234] and BMCR register writes */
1874 RTL_W8 (Cfg9346, Cfg9346_Lock);
1875
1876 /* init Rx ring buffer DMA address */
1877 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1878
1879 /* A.C.: Reset the multicast list. */
1880 __set_rx_mode (dev);
1881 #endif
1882 }
1883
1884 #if RX_BUF_IDX == 3
1885 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1886 u32 offset, unsigned int size)
1887 {
1888 u32 left = RX_BUF_LEN - offset;
1889
1890 if (size > left) {
1891 skb_copy_to_linear_data(skb, ring + offset, left);
1892 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1893 } else
1894 skb_copy_to_linear_data(skb, ring + offset, size);
1895 }
1896 #endif
1897
1898 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1899 {
1900 void __iomem *ioaddr = tp->mmio_addr;
1901 u16 status;
1902
1903 status = RTL_R16 (IntrStatus) & RxAckBits;
1904
1905 /* Clear out errors and receive interrupts */
1906 if (likely(status != 0)) {
1907 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1908 tp->dev->stats.rx_errors++;
1909 if (status & RxFIFOOver)
1910 tp->dev->stats.rx_fifo_errors++;
1911 }
1912 RTL_W16_F (IntrStatus, RxAckBits);
1913 }
1914 }
1915
1916 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1917 int budget)
1918 {
1919 void __iomem *ioaddr = tp->mmio_addr;
1920 int received = 0;
1921 unsigned char *rx_ring = tp->rx_ring;
1922 unsigned int cur_rx = tp->cur_rx;
1923 unsigned int rx_size = 0;
1924
1925 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1926 __func__, (u16)cur_rx,
1927 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1928
1929 while (netif_running(dev) && received < budget &&
1930 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1931 u32 ring_offset = cur_rx % RX_BUF_LEN;
1932 u32 rx_status;
1933 unsigned int pkt_size;
1934 struct sk_buff *skb;
1935
1936 rmb();
1937
1938 /* read size+status of next frame from DMA ring buffer */
1939 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1940 rx_size = rx_status >> 16;
1941 pkt_size = rx_size - 4;
1942
1943 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1944 __func__, rx_status, rx_size, cur_rx);
1945 #if RTL8139_DEBUG > 2
1946 print_dump_hex(KERN_DEBUG, "Frame contents: ",
1947 DUMP_PREFIX_OFFSET, 16, 1,
1948 &rx_ring[ring_offset], 70, true);
1949 #endif
1950
1951 /* Packet copy from FIFO still in progress.
1952 * Theoretically, this should never happen
1953 * since EarlyRx is disabled.
1954 */
1955 if (unlikely(rx_size == 0xfff0)) {
1956 if (!tp->fifo_copy_timeout)
1957 tp->fifo_copy_timeout = jiffies + 2;
1958 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1959 netdev_dbg(dev, "hung FIFO. Reset\n");
1960 rx_size = 0;
1961 goto no_early_rx;
1962 }
1963 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1964 tp->xstats.early_rx++;
1965 break;
1966 }
1967
1968 no_early_rx:
1969 tp->fifo_copy_timeout = 0;
1970
1971 /* If Rx err or invalid rx_size/rx_status received
1972 * (which happens if we get lost in the ring),
1973 * Rx process gets reset, so we abort any further
1974 * Rx processing.
1975 */
1976 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1977 (rx_size < 8) ||
1978 (!(rx_status & RxStatusOK)))) {
1979 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1980 received = -1;
1981 goto out;
1982 }
1983
1984 /* Malloc up new buffer, compatible with net-2e. */
1985 /* Omit the four octet CRC from the length. */
1986
1987 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
1988 if (likely(skb)) {
1989 #if RX_BUF_IDX == 3
1990 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
1991 #else
1992 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1993 #endif
1994 skb_put (skb, pkt_size);
1995
1996 skb->protocol = eth_type_trans (skb, dev);
1997
1998 dev->stats.rx_bytes += pkt_size;
1999 dev->stats.rx_packets++;
2000
2001 netif_receive_skb (skb);
2002 } else {
2003 if (net_ratelimit())
2004 netdev_warn(dev, "Memory squeeze, dropping packet\n");
2005 dev->stats.rx_dropped++;
2006 }
2007 received++;
2008
2009 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2010 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2011
2012 rtl8139_isr_ack(tp);
2013 }
2014
2015 if (unlikely(!received || rx_size == 0xfff0))
2016 rtl8139_isr_ack(tp);
2017
2018 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2019 __func__, cur_rx,
2020 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2021
2022 tp->cur_rx = cur_rx;
2023
2024 /*
2025 * The receive buffer should be mostly empty.
2026 * Tell NAPI to reenable the Rx irq.
2027 */
2028 if (tp->fifo_copy_timeout)
2029 received = budget;
2030
2031 out:
2032 return received;
2033 }
2034
2035
2036 static void rtl8139_weird_interrupt (struct net_device *dev,
2037 struct rtl8139_private *tp,
2038 void __iomem *ioaddr,
2039 int status, int link_changed)
2040 {
2041 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2042
2043 assert (dev != NULL);
2044 assert (tp != NULL);
2045 assert (ioaddr != NULL);
2046
2047 /* Update the error count. */
2048 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2049 RTL_W32 (RxMissed, 0);
2050
2051 if ((status & RxUnderrun) && link_changed &&
2052 (tp->drv_flags & HAS_LNK_CHNG)) {
2053 rtl_check_media(dev, 0);
2054 status &= ~RxUnderrun;
2055 }
2056
2057 if (status & (RxUnderrun | RxErr))
2058 dev->stats.rx_errors++;
2059
2060 if (status & PCSTimeout)
2061 dev->stats.rx_length_errors++;
2062 if (status & RxUnderrun)
2063 dev->stats.rx_fifo_errors++;
2064 if (status & PCIErr) {
2065 u16 pci_cmd_status;
2066 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2067 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2068
2069 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2070 }
2071 }
2072
2073 static int rtl8139_poll(struct napi_struct *napi, int budget)
2074 {
2075 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2076 struct net_device *dev = tp->dev;
2077 void __iomem *ioaddr = tp->mmio_addr;
2078 int work_done;
2079
2080 spin_lock(&tp->rx_lock);
2081 work_done = 0;
2082 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2083 work_done += rtl8139_rx(dev, tp, budget);
2084
2085 if (work_done < budget) {
2086 unsigned long flags;
2087 /*
2088 * Order is important since data can get interrupted
2089 * again when we think we are done.
2090 */
2091 spin_lock_irqsave(&tp->lock, flags);
2092 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2093 __napi_complete(napi);
2094 spin_unlock_irqrestore(&tp->lock, flags);
2095 }
2096 spin_unlock(&tp->rx_lock);
2097
2098 return work_done;
2099 }
2100
2101 /* The interrupt handler does all of the Rx thread work and cleans up
2102 after the Tx thread. */
2103 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2104 {
2105 struct net_device *dev = (struct net_device *) dev_instance;
2106 struct rtl8139_private *tp = netdev_priv(dev);
2107 void __iomem *ioaddr = tp->mmio_addr;
2108 u16 status, ackstat;
2109 int link_changed = 0; /* avoid bogus "uninit" warning */
2110 int handled = 0;
2111
2112 spin_lock (&tp->lock);
2113 status = RTL_R16 (IntrStatus);
2114
2115 /* shared irq? */
2116 if (unlikely((status & rtl8139_intr_mask) == 0))
2117 goto out;
2118
2119 handled = 1;
2120
2121 /* h/w no longer present (hotplug?) or major error, bail */
2122 if (unlikely(status == 0xFFFF))
2123 goto out;
2124
2125 /* close possible race's with dev_close */
2126 if (unlikely(!netif_running(dev))) {
2127 RTL_W16 (IntrMask, 0);
2128 goto out;
2129 }
2130
2131 /* Acknowledge all of the current interrupt sources ASAP, but
2132 an first get an additional status bit from CSCR. */
2133 if (unlikely(status & RxUnderrun))
2134 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2135
2136 ackstat = status & ~(RxAckBits | TxErr);
2137 if (ackstat)
2138 RTL_W16 (IntrStatus, ackstat);
2139
2140 /* Receive packets are processed by poll routine.
2141 If not running start it now. */
2142 if (status & RxAckBits){
2143 if (napi_schedule_prep(&tp->napi)) {
2144 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2145 __napi_schedule(&tp->napi);
2146 }
2147 }
2148
2149 /* Check uncommon events with one test. */
2150 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2151 rtl8139_weird_interrupt (dev, tp, ioaddr,
2152 status, link_changed);
2153
2154 if (status & (TxOK | TxErr)) {
2155 rtl8139_tx_interrupt (dev, tp, ioaddr);
2156 if (status & TxErr)
2157 RTL_W16 (IntrStatus, TxErr);
2158 }
2159 out:
2160 spin_unlock (&tp->lock);
2161
2162 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2163 RTL_R16(IntrStatus));
2164 return IRQ_RETVAL(handled);
2165 }
2166
2167 #ifdef CONFIG_NET_POLL_CONTROLLER
2168 /*
2169 * Polling receive - used by netconsole and other diagnostic tools
2170 * to allow network i/o with interrupts disabled.
2171 */
2172 static void rtl8139_poll_controller(struct net_device *dev)
2173 {
2174 disable_irq(dev->irq);
2175 rtl8139_interrupt(dev->irq, dev);
2176 enable_irq(dev->irq);
2177 }
2178 #endif
2179
2180 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2181 {
2182 struct rtl8139_private *tp = netdev_priv(dev);
2183 void __iomem *ioaddr = tp->mmio_addr;
2184 struct sockaddr *addr = p;
2185
2186 if (!is_valid_ether_addr(addr->sa_data))
2187 return -EADDRNOTAVAIL;
2188
2189 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2190
2191 spin_lock_irq(&tp->lock);
2192
2193 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2194 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2195 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2196 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2197
2198 spin_unlock_irq(&tp->lock);
2199
2200 return 0;
2201 }
2202
2203 static int rtl8139_close (struct net_device *dev)
2204 {
2205 struct rtl8139_private *tp = netdev_priv(dev);
2206 void __iomem *ioaddr = tp->mmio_addr;
2207 unsigned long flags;
2208
2209 netif_stop_queue(dev);
2210 napi_disable(&tp->napi);
2211
2212 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2213 RTL_R16(IntrStatus));
2214
2215 spin_lock_irqsave (&tp->lock, flags);
2216
2217 /* Stop the chip's Tx and Rx DMA processes. */
2218 RTL_W8 (ChipCmd, 0);
2219
2220 /* Disable interrupts by clearing the interrupt mask. */
2221 RTL_W16 (IntrMask, 0);
2222
2223 /* Update the error counts. */
2224 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2225 RTL_W32 (RxMissed, 0);
2226
2227 spin_unlock_irqrestore (&tp->lock, flags);
2228
2229 free_irq (dev->irq, dev);
2230
2231 rtl8139_tx_clear (tp);
2232
2233 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2234 tp->rx_ring, tp->rx_ring_dma);
2235 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2236 tp->tx_bufs, tp->tx_bufs_dma);
2237 tp->rx_ring = NULL;
2238 tp->tx_bufs = NULL;
2239
2240 /* Green! Put the chip in low-power mode. */
2241 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2242
2243 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2244 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2245
2246 return 0;
2247 }
2248
2249
2250 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2251 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2252 other threads or interrupts aren't messing with the 8139. */
2253 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2254 {
2255 struct rtl8139_private *tp = netdev_priv(dev);
2256 void __iomem *ioaddr = tp->mmio_addr;
2257
2258 spin_lock_irq(&tp->lock);
2259 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2260 u8 cfg3 = RTL_R8 (Config3);
2261 u8 cfg5 = RTL_R8 (Config5);
2262
2263 wol->supported = WAKE_PHY | WAKE_MAGIC
2264 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2265
2266 wol->wolopts = 0;
2267 if (cfg3 & Cfg3_LinkUp)
2268 wol->wolopts |= WAKE_PHY;
2269 if (cfg3 & Cfg3_Magic)
2270 wol->wolopts |= WAKE_MAGIC;
2271 /* (KON)FIXME: See how netdev_set_wol() handles the
2272 following constants. */
2273 if (cfg5 & Cfg5_UWF)
2274 wol->wolopts |= WAKE_UCAST;
2275 if (cfg5 & Cfg5_MWF)
2276 wol->wolopts |= WAKE_MCAST;
2277 if (cfg5 & Cfg5_BWF)
2278 wol->wolopts |= WAKE_BCAST;
2279 }
2280 spin_unlock_irq(&tp->lock);
2281 }
2282
2283
2284 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2285 that wol points to kernel memory and other threads or interrupts
2286 aren't messing with the 8139. */
2287 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2288 {
2289 struct rtl8139_private *tp = netdev_priv(dev);
2290 void __iomem *ioaddr = tp->mmio_addr;
2291 u32 support;
2292 u8 cfg3, cfg5;
2293
2294 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2295 ? (WAKE_PHY | WAKE_MAGIC
2296 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2297 : 0);
2298 if (wol->wolopts & ~support)
2299 return -EINVAL;
2300
2301 spin_lock_irq(&tp->lock);
2302 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2303 if (wol->wolopts & WAKE_PHY)
2304 cfg3 |= Cfg3_LinkUp;
2305 if (wol->wolopts & WAKE_MAGIC)
2306 cfg3 |= Cfg3_Magic;
2307 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2308 RTL_W8 (Config3, cfg3);
2309 RTL_W8 (Cfg9346, Cfg9346_Lock);
2310
2311 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2312 /* (KON)FIXME: These are untested. We may have to set the
2313 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2314 documentation. */
2315 if (wol->wolopts & WAKE_UCAST)
2316 cfg5 |= Cfg5_UWF;
2317 if (wol->wolopts & WAKE_MCAST)
2318 cfg5 |= Cfg5_MWF;
2319 if (wol->wolopts & WAKE_BCAST)
2320 cfg5 |= Cfg5_BWF;
2321 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2322 spin_unlock_irq(&tp->lock);
2323
2324 return 0;
2325 }
2326
2327 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2328 {
2329 struct rtl8139_private *tp = netdev_priv(dev);
2330 strcpy(info->driver, DRV_NAME);
2331 strcpy(info->version, DRV_VERSION);
2332 strcpy(info->bus_info, pci_name(tp->pci_dev));
2333 info->regdump_len = tp->regs_len;
2334 }
2335
2336 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2337 {
2338 struct rtl8139_private *tp = netdev_priv(dev);
2339 spin_lock_irq(&tp->lock);
2340 mii_ethtool_gset(&tp->mii, cmd);
2341 spin_unlock_irq(&tp->lock);
2342 return 0;
2343 }
2344
2345 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2346 {
2347 struct rtl8139_private *tp = netdev_priv(dev);
2348 int rc;
2349 spin_lock_irq(&tp->lock);
2350 rc = mii_ethtool_sset(&tp->mii, cmd);
2351 spin_unlock_irq(&tp->lock);
2352 return rc;
2353 }
2354
2355 static int rtl8139_nway_reset(struct net_device *dev)
2356 {
2357 struct rtl8139_private *tp = netdev_priv(dev);
2358 return mii_nway_restart(&tp->mii);
2359 }
2360
2361 static u32 rtl8139_get_link(struct net_device *dev)
2362 {
2363 struct rtl8139_private *tp = netdev_priv(dev);
2364 return mii_link_ok(&tp->mii);
2365 }
2366
2367 static u32 rtl8139_get_msglevel(struct net_device *dev)
2368 {
2369 struct rtl8139_private *tp = netdev_priv(dev);
2370 return tp->msg_enable;
2371 }
2372
2373 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2374 {
2375 struct rtl8139_private *tp = netdev_priv(dev);
2376 tp->msg_enable = datum;
2377 }
2378
2379 static int rtl8139_get_regs_len(struct net_device *dev)
2380 {
2381 struct rtl8139_private *tp;
2382 /* TODO: we are too slack to do reg dumping for pio, for now */
2383 if (use_io)
2384 return 0;
2385 tp = netdev_priv(dev);
2386 return tp->regs_len;
2387 }
2388
2389 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2390 {
2391 struct rtl8139_private *tp;
2392
2393 /* TODO: we are too slack to do reg dumping for pio, for now */
2394 if (use_io)
2395 return;
2396 tp = netdev_priv(dev);
2397
2398 regs->version = RTL_REGS_VER;
2399
2400 spin_lock_irq(&tp->lock);
2401 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2402 spin_unlock_irq(&tp->lock);
2403 }
2404
2405 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2406 {
2407 switch (sset) {
2408 case ETH_SS_STATS:
2409 return RTL_NUM_STATS;
2410 default:
2411 return -EOPNOTSUPP;
2412 }
2413 }
2414
2415 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2416 {
2417 struct rtl8139_private *tp = netdev_priv(dev);
2418
2419 data[0] = tp->xstats.early_rx;
2420 data[1] = tp->xstats.tx_buf_mapped;
2421 data[2] = tp->xstats.tx_timeouts;
2422 data[3] = tp->xstats.rx_lost_in_ring;
2423 }
2424
2425 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2426 {
2427 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2428 }
2429
2430 static const struct ethtool_ops rtl8139_ethtool_ops = {
2431 .get_drvinfo = rtl8139_get_drvinfo,
2432 .get_settings = rtl8139_get_settings,
2433 .set_settings = rtl8139_set_settings,
2434 .get_regs_len = rtl8139_get_regs_len,
2435 .get_regs = rtl8139_get_regs,
2436 .nway_reset = rtl8139_nway_reset,
2437 .get_link = rtl8139_get_link,
2438 .get_msglevel = rtl8139_get_msglevel,
2439 .set_msglevel = rtl8139_set_msglevel,
2440 .get_wol = rtl8139_get_wol,
2441 .set_wol = rtl8139_set_wol,
2442 .get_strings = rtl8139_get_strings,
2443 .get_sset_count = rtl8139_get_sset_count,
2444 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2445 };
2446
2447 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2448 {
2449 struct rtl8139_private *tp = netdev_priv(dev);
2450 int rc;
2451
2452 if (!netif_running(dev))
2453 return -EINVAL;
2454
2455 spin_lock_irq(&tp->lock);
2456 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2457 spin_unlock_irq(&tp->lock);
2458
2459 return rc;
2460 }
2461
2462
2463 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2464 {
2465 struct rtl8139_private *tp = netdev_priv(dev);
2466 void __iomem *ioaddr = tp->mmio_addr;
2467 unsigned long flags;
2468
2469 if (netif_running(dev)) {
2470 spin_lock_irqsave (&tp->lock, flags);
2471 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2472 RTL_W32 (RxMissed, 0);
2473 spin_unlock_irqrestore (&tp->lock, flags);
2474 }
2475
2476 return &dev->stats;
2477 }
2478
2479 /* Set or clear the multicast filter for this adaptor.
2480 This routine is not state sensitive and need not be SMP locked. */
2481
2482 static void __set_rx_mode (struct net_device *dev)
2483 {
2484 struct rtl8139_private *tp = netdev_priv(dev);
2485 void __iomem *ioaddr = tp->mmio_addr;
2486 u32 mc_filter[2]; /* Multicast hash filter */
2487 int rx_mode;
2488 u32 tmp;
2489
2490 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08lx\n",
2491 dev->flags, RTL_R32(RxConfig));
2492
2493 /* Note: do not reorder, GCC is clever about common statements. */
2494 if (dev->flags & IFF_PROMISC) {
2495 rx_mode =
2496 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2497 AcceptAllPhys;
2498 mc_filter[1] = mc_filter[0] = 0xffffffff;
2499 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2500 (dev->flags & IFF_ALLMULTI)) {
2501 /* Too many to filter perfectly -- accept all multicasts. */
2502 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2503 mc_filter[1] = mc_filter[0] = 0xffffffff;
2504 } else {
2505 struct dev_mc_list *mclist;
2506 rx_mode = AcceptBroadcast | AcceptMyPhys;
2507 mc_filter[1] = mc_filter[0] = 0;
2508 netdev_for_each_mc_addr(mclist, dev) {
2509 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2510
2511 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2512 rx_mode |= AcceptMulticast;
2513 }
2514 }
2515
2516 /* We can safely update without stopping the chip. */
2517 tmp = rtl8139_rx_config | rx_mode;
2518 if (tp->rx_config != tmp) {
2519 RTL_W32_F (RxConfig, tmp);
2520 tp->rx_config = tmp;
2521 }
2522 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2523 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2524 }
2525
2526 static void rtl8139_set_rx_mode (struct net_device *dev)
2527 {
2528 unsigned long flags;
2529 struct rtl8139_private *tp = netdev_priv(dev);
2530
2531 spin_lock_irqsave (&tp->lock, flags);
2532 __set_rx_mode(dev);
2533 spin_unlock_irqrestore (&tp->lock, flags);
2534 }
2535
2536 #ifdef CONFIG_PM
2537
2538 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2539 {
2540 struct net_device *dev = pci_get_drvdata (pdev);
2541 struct rtl8139_private *tp = netdev_priv(dev);
2542 void __iomem *ioaddr = tp->mmio_addr;
2543 unsigned long flags;
2544
2545 pci_save_state (pdev);
2546
2547 if (!netif_running (dev))
2548 return 0;
2549
2550 netif_device_detach (dev);
2551
2552 spin_lock_irqsave (&tp->lock, flags);
2553
2554 /* Disable interrupts, stop Tx and Rx. */
2555 RTL_W16 (IntrMask, 0);
2556 RTL_W8 (ChipCmd, 0);
2557
2558 /* Update the error counts. */
2559 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2560 RTL_W32 (RxMissed, 0);
2561
2562 spin_unlock_irqrestore (&tp->lock, flags);
2563
2564 pci_set_power_state (pdev, PCI_D3hot);
2565
2566 return 0;
2567 }
2568
2569
2570 static int rtl8139_resume (struct pci_dev *pdev)
2571 {
2572 struct net_device *dev = pci_get_drvdata (pdev);
2573
2574 pci_restore_state (pdev);
2575 if (!netif_running (dev))
2576 return 0;
2577 pci_set_power_state (pdev, PCI_D0);
2578 rtl8139_init_ring (dev);
2579 rtl8139_hw_start (dev);
2580 netif_device_attach (dev);
2581 return 0;
2582 }
2583
2584 #endif /* CONFIG_PM */
2585
2586
2587 static struct pci_driver rtl8139_pci_driver = {
2588 .name = DRV_NAME,
2589 .id_table = rtl8139_pci_tbl,
2590 .probe = rtl8139_init_one,
2591 .remove = __devexit_p(rtl8139_remove_one),
2592 #ifdef CONFIG_PM
2593 .suspend = rtl8139_suspend,
2594 .resume = rtl8139_resume,
2595 #endif /* CONFIG_PM */
2596 };
2597
2598
2599 static int __init rtl8139_init_module (void)
2600 {
2601 /* when we're a module, we always print a version message,
2602 * even if no 8139 board is found.
2603 */
2604 #ifdef MODULE
2605 pr_info(RTL8139_DRIVER_NAME "\n");
2606 #endif
2607
2608 return pci_register_driver(&rtl8139_pci_driver);
2609 }
2610
2611
2612 static void __exit rtl8139_cleanup_module (void)
2613 {
2614 pci_unregister_driver (&rtl8139_pci_driver);
2615 }
2616
2617
2618 module_init(rtl8139_init_module);
2619 module_exit(rtl8139_cleanup_module);
Linux kernel - Deliverables
This page took 0.089599 seconds and 5 git commands to generate.