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[NET]: Nuke SET_MODULE_OWNER macro.
[deliverable/linux.git] / drivers / net / 8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
392 TxIFGShift = 24,
393 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
394 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
395 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
396 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
397
398 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
399 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
400 TxClearAbt = (1 << 0), /* Clear abort (WO) */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
402 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
403
404 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 };
406
407 /* Bits in Config1 */
408 enum Config1Bits {
409 Cfg1_PM_Enable = 0x01,
410 Cfg1_VPD_Enable = 0x02,
411 Cfg1_PIO = 0x04,
412 Cfg1_MMIO = 0x08,
413 LWAKE = 0x10, /* not on 8139, 8139A */
414 Cfg1_Driver_Load = 0x20,
415 Cfg1_LED0 = 0x40,
416 Cfg1_LED1 = 0x80,
417 SLEEP = (1 << 1), /* only on 8139, 8139A */
418 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 };
420
421 /* Bits in Config3 */
422 enum Config3Bits {
423 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
424 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
425 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
426 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
427 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
428 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
429 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
430 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 };
432
433 /* Bits in Config4 */
434 enum Config4Bits {
435 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 };
437
438 /* Bits in Config5 */
439 enum Config5Bits {
440 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
441 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
442 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
443 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
444 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
445 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
446 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 };
448
449 enum RxConfigBits {
450 /* rx fifo threshold */
451 RxCfgFIFOShift = 13,
452 RxCfgFIFONone = (7 << RxCfgFIFOShift),
453
454 /* Max DMA burst */
455 RxCfgDMAShift = 8,
456 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
457
458 /* rx ring buffer length */
459 RxCfgRcv8K = 0,
460 RxCfgRcv16K = (1 << 11),
461 RxCfgRcv32K = (1 << 12),
462 RxCfgRcv64K = (1 << 11) | (1 << 12),
463
464 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
465 RxNoWrap = (1 << 7),
466 };
467
468 /* Twister tuning parameters from RealTek.
469 Completely undocumented, but required to tune bad links on some boards. */
470 enum CSCRBits {
471 CSCR_LinkOKBit = 0x0400,
472 CSCR_LinkChangeBit = 0x0800,
473 CSCR_LinkStatusBits = 0x0f000,
474 CSCR_LinkDownOffCmd = 0x003c0,
475 CSCR_LinkDownCmd = 0x0f3c0,
476 };
477
478 enum Cfg9346Bits {
479 Cfg9346_Lock = 0x00,
480 Cfg9346_Unlock = 0xC0,
481 };
482
483 typedef enum {
484 CH_8139 = 0,
485 CH_8139_K,
486 CH_8139A,
487 CH_8139A_G,
488 CH_8139B,
489 CH_8130,
490 CH_8139C,
491 CH_8100,
492 CH_8100B_8139D,
493 CH_8101,
494 } chip_t;
495
496 enum chip_flags {
497 HasHltClk = (1 << 0),
498 HasLWake = (1 << 1),
499 };
500
501 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
502 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
503 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
504
505 /* directly indexed by chip_t, above */
506 static const struct {
507 const char *name;
508 u32 version; /* from RTL8139C/RTL8139D docs */
509 u32 flags;
510 } rtl_chip_info[] = {
511 { "RTL-8139",
512 HW_REVID(1, 0, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139 rev K",
517 HW_REVID(1, 1, 0, 0, 0, 0, 0),
518 HasHltClk,
519 },
520
521 { "RTL-8139A",
522 HW_REVID(1, 1, 1, 0, 0, 0, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139A rev G",
527 HW_REVID(1, 1, 1, 0, 0, 1, 0),
528 HasHltClk, /* XXX undocumented? */
529 },
530
531 { "RTL-8139B",
532 HW_REVID(1, 1, 1, 1, 0, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8130",
537 HW_REVID(1, 1, 1, 1, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8139C",
542 HW_REVID(1, 1, 1, 0, 1, 0, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100",
547 HW_REVID(1, 1, 1, 1, 0, 1, 0),
548 HasLWake,
549 },
550
551 { "RTL-8100B/8139D",
552 HW_REVID(1, 1, 1, 0, 1, 0, 1),
553 HasHltClk /* XXX undocumented? */
554 | HasLWake,
555 },
556
557 { "RTL-8101",
558 HW_REVID(1, 1, 1, 0, 1, 1, 1),
559 HasLWake,
560 },
561 };
562
563 struct rtl_extra_stats {
564 unsigned long early_rx;
565 unsigned long tx_buf_mapped;
566 unsigned long tx_timeouts;
567 unsigned long rx_lost_in_ring;
568 };
569
570 struct rtl8139_private {
571 void __iomem *mmio_addr;
572 int drv_flags;
573 struct pci_dev *pci_dev;
574 u32 msg_enable;
575 struct napi_struct napi;
576 struct net_device *dev;
577 struct net_device_stats stats;
578
579 unsigned char *rx_ring;
580 unsigned int cur_rx; /* RX buf index of next pkt */
581 dma_addr_t rx_ring_dma;
582
583 unsigned int tx_flag;
584 unsigned long cur_tx;
585 unsigned long dirty_tx;
586 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
587 unsigned char *tx_bufs; /* Tx bounce buffer region. */
588 dma_addr_t tx_bufs_dma;
589
590 signed char phys[4]; /* MII device addresses. */
591
592 /* Twister tune state. */
593 char twistie, twist_row, twist_col;
594
595 unsigned int watchdog_fired : 1;
596 unsigned int default_port : 4; /* Last dev->if_port value. */
597 unsigned int have_thread : 1;
598
599 spinlock_t lock;
600 spinlock_t rx_lock;
601
602 chip_t chipset;
603 u32 rx_config;
604 struct rtl_extra_stats xstats;
605
606 struct delayed_work thread;
607
608 struct mii_if_info mii;
609 unsigned int regs_len;
610 unsigned long fifo_copy_timeout;
611 };
612
613 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
614 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
615 MODULE_LICENSE("GPL");
616 MODULE_VERSION(DRV_VERSION);
617
618 module_param(multicast_filter_limit, int, 0);
619 module_param_array(media, int, NULL, 0);
620 module_param_array(full_duplex, int, NULL, 0);
621 module_param(debug, int, 0);
622 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
623 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
624 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
625 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
626
627 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
628 static int rtl8139_open (struct net_device *dev);
629 static int mdio_read (struct net_device *dev, int phy_id, int location);
630 static void mdio_write (struct net_device *dev, int phy_id, int location,
631 int val);
632 static void rtl8139_start_thread(struct rtl8139_private *tp);
633 static void rtl8139_tx_timeout (struct net_device *dev);
634 static void rtl8139_init_ring (struct net_device *dev);
635 static int rtl8139_start_xmit (struct sk_buff *skb,
636 struct net_device *dev);
637 #ifdef CONFIG_NET_POLL_CONTROLLER
638 static void rtl8139_poll_controller(struct net_device *dev);
639 #endif
640 static int rtl8139_poll(struct napi_struct *napi, int budget);
641 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
642 static int rtl8139_close (struct net_device *dev);
643 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
644 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
645 static void rtl8139_set_rx_mode (struct net_device *dev);
646 static void __set_rx_mode (struct net_device *dev);
647 static void rtl8139_hw_start (struct net_device *dev);
648 static void rtl8139_thread (struct work_struct *work);
649 static void rtl8139_tx_timeout_task(struct work_struct *work);
650 static const struct ethtool_ops rtl8139_ethtool_ops;
651
652 /* write MMIO register, with flush */
653 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
654 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
655 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
656 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
657
658 /* write MMIO register */
659 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
660 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
661 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
662
663 /* read MMIO register */
664 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
665 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
666 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
667
668
669 static const u16 rtl8139_intr_mask =
670 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
671 TxErr | TxOK | RxErr | RxOK;
672
673 static const u16 rtl8139_norx_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun |
675 TxErr | TxOK | RxErr ;
676
677 #if RX_BUF_IDX == 0
678 static const unsigned int rtl8139_rx_config =
679 RxCfgRcv8K | RxNoWrap |
680 (RX_FIFO_THRESH << RxCfgFIFOShift) |
681 (RX_DMA_BURST << RxCfgDMAShift);
682 #elif RX_BUF_IDX == 1
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv16K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 2
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv32K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 3
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv64K |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #else
698 #error "Invalid configuration for 8139_RXBUF_IDX"
699 #endif
700
701 static const unsigned int rtl8139_tx_config =
702 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
703
704 static void __rtl8139_cleanup_dev (struct net_device *dev)
705 {
706 struct rtl8139_private *tp = netdev_priv(dev);
707 struct pci_dev *pdev;
708
709 assert (dev != NULL);
710 assert (tp->pci_dev != NULL);
711 pdev = tp->pci_dev;
712
713 #ifdef USE_IO_OPS
714 if (tp->mmio_addr)
715 ioport_unmap (tp->mmio_addr);
716 #else
717 if (tp->mmio_addr)
718 pci_iounmap (pdev, tp->mmio_addr);
719 #endif /* USE_IO_OPS */
720
721 /* it's ok to call this even if we have no regions to free */
722 pci_release_regions (pdev);
723
724 free_netdev(dev);
725 pci_set_drvdata (pdev, NULL);
726 }
727
728
729 static void rtl8139_chip_reset (void __iomem *ioaddr)
730 {
731 int i;
732
733 /* Soft reset the chip. */
734 RTL_W8 (ChipCmd, CmdReset);
735
736 /* Check that the chip has finished the reset. */
737 for (i = 1000; i > 0; i--) {
738 barrier();
739 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
740 break;
741 udelay (10);
742 }
743 }
744
745
746 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
747 struct net_device **dev_out)
748 {
749 void __iomem *ioaddr;
750 struct net_device *dev;
751 struct rtl8139_private *tp;
752 u8 tmp8;
753 int rc, disable_dev_on_err = 0;
754 unsigned int i;
755 unsigned long pio_start, pio_end, pio_flags, pio_len;
756 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
757 u32 version;
758
759 assert (pdev != NULL);
760
761 *dev_out = NULL;
762
763 /* dev and priv zeroed in alloc_etherdev */
764 dev = alloc_etherdev (sizeof (*tp));
765 if (dev == NULL) {
766 dev_err(&pdev->dev, "Unable to alloc new net device\n");
767 return -ENOMEM;
768 }
769 SET_NETDEV_DEV(dev, &pdev->dev);
770
771 tp = netdev_priv(dev);
772 tp->pci_dev = pdev;
773
774 /* enable device (incl. PCI PM wakeup and hotplug setup) */
775 rc = pci_enable_device (pdev);
776 if (rc)
777 goto err_out;
778
779 pio_start = pci_resource_start (pdev, 0);
780 pio_end = pci_resource_end (pdev, 0);
781 pio_flags = pci_resource_flags (pdev, 0);
782 pio_len = pci_resource_len (pdev, 0);
783
784 mmio_start = pci_resource_start (pdev, 1);
785 mmio_end = pci_resource_end (pdev, 1);
786 mmio_flags = pci_resource_flags (pdev, 1);
787 mmio_len = pci_resource_len (pdev, 1);
788
789 /* set this immediately, we need to know before
790 * we talk to the chip directly */
791 DPRINTK("PIO region size == 0x%02X\n", pio_len);
792 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
793
794 #ifdef USE_IO_OPS
795 /* make sure PCI base addr 0 is PIO */
796 if (!(pio_flags & IORESOURCE_IO)) {
797 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
798 rc = -ENODEV;
799 goto err_out;
800 }
801 /* check for weird/broken PCI region reporting */
802 if (pio_len < RTL_MIN_IO_SIZE) {
803 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
804 rc = -ENODEV;
805 goto err_out;
806 }
807 #else
808 /* make sure PCI base addr 1 is MMIO */
809 if (!(mmio_flags & IORESOURCE_MEM)) {
810 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
811 rc = -ENODEV;
812 goto err_out;
813 }
814 if (mmio_len < RTL_MIN_IO_SIZE) {
815 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
816 rc = -ENODEV;
817 goto err_out;
818 }
819 #endif
820
821 rc = pci_request_regions (pdev, DRV_NAME);
822 if (rc)
823 goto err_out;
824 disable_dev_on_err = 1;
825
826 /* enable PCI bus-mastering */
827 pci_set_master (pdev);
828
829 #ifdef USE_IO_OPS
830 ioaddr = ioport_map(pio_start, pio_len);
831 if (!ioaddr) {
832 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
833 rc = -EIO;
834 goto err_out;
835 }
836 dev->base_addr = pio_start;
837 tp->mmio_addr = ioaddr;
838 tp->regs_len = pio_len;
839 #else
840 /* ioremap MMIO region */
841 ioaddr = pci_iomap(pdev, 1, 0);
842 if (ioaddr == NULL) {
843 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
844 rc = -EIO;
845 goto err_out;
846 }
847 dev->base_addr = (long) ioaddr;
848 tp->mmio_addr = ioaddr;
849 tp->regs_len = mmio_len;
850 #endif /* USE_IO_OPS */
851
852 /* Bring old chips out of low-power mode. */
853 RTL_W8 (HltClk, 'R');
854
855 /* check for missing/broken hardware */
856 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
857 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
858 rc = -EIO;
859 goto err_out;
860 }
861
862 /* identify chip attached to board */
863 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
864 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
865 if (version == rtl_chip_info[i].version) {
866 tp->chipset = i;
867 goto match;
868 }
869
870 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
871 dev_printk (KERN_DEBUG, &pdev->dev,
872 "unknown chip version, assuming RTL-8139\n");
873 dev_printk (KERN_DEBUG, &pdev->dev,
874 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
875 tp->chipset = 0;
876
877 match:
878 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
879 version, i, rtl_chip_info[i].name);
880
881 if (tp->chipset >= CH_8139B) {
882 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
883 DPRINTK("PCI PM wakeup\n");
884 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
885 (tmp8 & LWAKE))
886 new_tmp8 &= ~LWAKE;
887 new_tmp8 |= Cfg1_PM_Enable;
888 if (new_tmp8 != tmp8) {
889 RTL_W8 (Cfg9346, Cfg9346_Unlock);
890 RTL_W8 (Config1, tmp8);
891 RTL_W8 (Cfg9346, Cfg9346_Lock);
892 }
893 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
894 tmp8 = RTL_R8 (Config4);
895 if (tmp8 & LWPTN) {
896 RTL_W8 (Cfg9346, Cfg9346_Unlock);
897 RTL_W8 (Config4, tmp8 & ~LWPTN);
898 RTL_W8 (Cfg9346, Cfg9346_Lock);
899 }
900 }
901 } else {
902 DPRINTK("Old chip wakeup\n");
903 tmp8 = RTL_R8 (Config1);
904 tmp8 &= ~(SLEEP | PWRDN);
905 RTL_W8 (Config1, tmp8);
906 }
907
908 rtl8139_chip_reset (ioaddr);
909
910 *dev_out = dev;
911 return 0;
912
913 err_out:
914 __rtl8139_cleanup_dev (dev);
915 if (disable_dev_on_err)
916 pci_disable_device (pdev);
917 return rc;
918 }
919
920
921 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
922 const struct pci_device_id *ent)
923 {
924 struct net_device *dev = NULL;
925 struct rtl8139_private *tp;
926 int i, addr_len, option;
927 void __iomem *ioaddr;
928 static int board_idx = -1;
929
930 assert (pdev != NULL);
931 assert (ent != NULL);
932
933 board_idx++;
934
935 /* when we're built into the kernel, the driver version message
936 * is only printed if at least one 8139 board has been found
937 */
938 #ifndef MODULE
939 {
940 static int printed_version;
941 if (!printed_version++)
942 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
943 }
944 #endif
945
946 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
947 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
948 dev_info(&pdev->dev,
949 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
950 pdev->vendor, pdev->device, pdev->revision);
951 dev_info(&pdev->dev,
952 "Use the \"8139cp\" driver for improved performance and stability.\n");
953 }
954
955 i = rtl8139_init_board (pdev, &dev);
956 if (i < 0)
957 return i;
958
959 assert (dev != NULL);
960 tp = netdev_priv(dev);
961 tp->dev = dev;
962
963 ioaddr = tp->mmio_addr;
964 assert (ioaddr != NULL);
965
966 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
967 for (i = 0; i < 3; i++)
968 ((u16 *) (dev->dev_addr))[i] =
969 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
970 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
971
972 /* The Rtl8139-specific entries in the device structure. */
973 dev->open = rtl8139_open;
974 dev->hard_start_xmit = rtl8139_start_xmit;
975 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
976 dev->stop = rtl8139_close;
977 dev->get_stats = rtl8139_get_stats;
978 dev->set_multicast_list = rtl8139_set_rx_mode;
979 dev->do_ioctl = netdev_ioctl;
980 dev->ethtool_ops = &rtl8139_ethtool_ops;
981 dev->tx_timeout = rtl8139_tx_timeout;
982 dev->watchdog_timeo = TX_TIMEOUT;
983 #ifdef CONFIG_NET_POLL_CONTROLLER
984 dev->poll_controller = rtl8139_poll_controller;
985 #endif
986
987 /* note: the hardware is not capable of sg/csum/highdma, however
988 * through the use of skb_copy_and_csum_dev we enable these
989 * features
990 */
991 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
992
993 dev->irq = pdev->irq;
994
995 /* tp zeroed and aligned in alloc_etherdev */
996 tp = netdev_priv(dev);
997
998 /* note: tp->chipset set in rtl8139_init_board */
999 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1000 tp->mmio_addr = ioaddr;
1001 tp->msg_enable =
1002 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1003 spin_lock_init (&tp->lock);
1004 spin_lock_init (&tp->rx_lock);
1005 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1006 tp->mii.dev = dev;
1007 tp->mii.mdio_read = mdio_read;
1008 tp->mii.mdio_write = mdio_write;
1009 tp->mii.phy_id_mask = 0x3f;
1010 tp->mii.reg_num_mask = 0x1f;
1011
1012 /* dev is fully set up and ready to use now */
1013 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1014 i = register_netdev (dev);
1015 if (i) goto err_out;
1016
1017 pci_set_drvdata (pdev, dev);
1018
1019 printk (KERN_INFO "%s: %s at 0x%lx, "
1020 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1021 "IRQ %d\n",
1022 dev->name,
1023 board_info[ent->driver_data].name,
1024 dev->base_addr,
1025 dev->dev_addr[0], dev->dev_addr[1],
1026 dev->dev_addr[2], dev->dev_addr[3],
1027 dev->dev_addr[4], dev->dev_addr[5],
1028 dev->irq);
1029
1030 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1031 dev->name, rtl_chip_info[tp->chipset].name);
1032
1033 /* Find the connected MII xcvrs.
1034 Doing this in open() would allow detecting external xcvrs later, but
1035 takes too much time. */
1036 #ifdef CONFIG_8139TOO_8129
1037 if (tp->drv_flags & HAS_MII_XCVR) {
1038 int phy, phy_idx = 0;
1039 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1040 int mii_status = mdio_read(dev, phy, 1);
1041 if (mii_status != 0xffff && mii_status != 0x0000) {
1042 u16 advertising = mdio_read(dev, phy, 4);
1043 tp->phys[phy_idx++] = phy;
1044 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1045 "advertising %4.4x.\n",
1046 dev->name, phy, mii_status, advertising);
1047 }
1048 }
1049 if (phy_idx == 0) {
1050 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1051 "transceiver.\n",
1052 dev->name);
1053 tp->phys[0] = 32;
1054 }
1055 } else
1056 #endif
1057 tp->phys[0] = 32;
1058 tp->mii.phy_id = tp->phys[0];
1059
1060 /* The lower four bits are the media type. */
1061 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1062 if (option > 0) {
1063 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1064 tp->default_port = option & 0xFF;
1065 if (tp->default_port)
1066 tp->mii.force_media = 1;
1067 }
1068 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1069 tp->mii.full_duplex = full_duplex[board_idx];
1070 if (tp->mii.full_duplex) {
1071 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1072 /* Changing the MII-advertised media because might prevent
1073 re-connection. */
1074 tp->mii.force_media = 1;
1075 }
1076 if (tp->default_port) {
1077 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1078 (option & 0x20 ? 100 : 10),
1079 (option & 0x10 ? "full" : "half"));
1080 mdio_write(dev, tp->phys[0], 0,
1081 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1082 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1083 }
1084
1085 /* Put the chip into low-power mode. */
1086 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1087 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1088
1089 return 0;
1090
1091 err_out:
1092 __rtl8139_cleanup_dev (dev);
1093 pci_disable_device (pdev);
1094 return i;
1095 }
1096
1097
1098 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1099 {
1100 struct net_device *dev = pci_get_drvdata (pdev);
1101
1102 assert (dev != NULL);
1103
1104 flush_scheduled_work();
1105
1106 unregister_netdev (dev);
1107
1108 __rtl8139_cleanup_dev (dev);
1109 pci_disable_device (pdev);
1110 }
1111
1112
1113 /* Serial EEPROM section. */
1114
1115 /* EEPROM_Ctrl bits. */
1116 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1117 #define EE_CS 0x08 /* EEPROM chip select. */
1118 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1119 #define EE_WRITE_0 0x00
1120 #define EE_WRITE_1 0x02
1121 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1122 #define EE_ENB (0x80 | EE_CS)
1123
1124 /* Delay between EEPROM clock transitions.
1125 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1126 */
1127
1128 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1129
1130 /* The EEPROM commands include the alway-set leading bit. */
1131 #define EE_WRITE_CMD (5)
1132 #define EE_READ_CMD (6)
1133 #define EE_ERASE_CMD (7)
1134
1135 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1136 {
1137 int i;
1138 unsigned retval = 0;
1139 int read_cmd = location | (EE_READ_CMD << addr_len);
1140
1141 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1142 RTL_W8 (Cfg9346, EE_ENB);
1143 eeprom_delay ();
1144
1145 /* Shift the read command bits out. */
1146 for (i = 4 + addr_len; i >= 0; i--) {
1147 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1148 RTL_W8 (Cfg9346, EE_ENB | dataval);
1149 eeprom_delay ();
1150 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1151 eeprom_delay ();
1152 }
1153 RTL_W8 (Cfg9346, EE_ENB);
1154 eeprom_delay ();
1155
1156 for (i = 16; i > 0; i--) {
1157 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1158 eeprom_delay ();
1159 retval =
1160 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1161 0);
1162 RTL_W8 (Cfg9346, EE_ENB);
1163 eeprom_delay ();
1164 }
1165
1166 /* Terminate the EEPROM access. */
1167 RTL_W8 (Cfg9346, ~EE_CS);
1168 eeprom_delay ();
1169
1170 return retval;
1171 }
1172
1173 /* MII serial management: mostly bogus for now. */
1174 /* Read and write the MII management registers using software-generated
1175 serial MDIO protocol.
1176 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1177 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1178 "overclocking" issues. */
1179 #define MDIO_DIR 0x80
1180 #define MDIO_DATA_OUT 0x04
1181 #define MDIO_DATA_IN 0x02
1182 #define MDIO_CLK 0x01
1183 #define MDIO_WRITE0 (MDIO_DIR)
1184 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1185
1186 #define mdio_delay() RTL_R8(Config4)
1187
1188
1189 static const char mii_2_8139_map[8] = {
1190 BasicModeCtrl,
1191 BasicModeStatus,
1192 0,
1193 0,
1194 NWayAdvert,
1195 NWayLPAR,
1196 NWayExpansion,
1197 0
1198 };
1199
1200
1201 #ifdef CONFIG_8139TOO_8129
1202 /* Syncronize the MII management interface by shifting 32 one bits out. */
1203 static void mdio_sync (void __iomem *ioaddr)
1204 {
1205 int i;
1206
1207 for (i = 32; i >= 0; i--) {
1208 RTL_W8 (Config4, MDIO_WRITE1);
1209 mdio_delay ();
1210 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1211 mdio_delay ();
1212 }
1213 }
1214 #endif
1215
1216 static int mdio_read (struct net_device *dev, int phy_id, int location)
1217 {
1218 struct rtl8139_private *tp = netdev_priv(dev);
1219 int retval = 0;
1220 #ifdef CONFIG_8139TOO_8129
1221 void __iomem *ioaddr = tp->mmio_addr;
1222 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1223 int i;
1224 #endif
1225
1226 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1227 void __iomem *ioaddr = tp->mmio_addr;
1228 return location < 8 && mii_2_8139_map[location] ?
1229 RTL_R16 (mii_2_8139_map[location]) : 0;
1230 }
1231
1232 #ifdef CONFIG_8139TOO_8129
1233 mdio_sync (ioaddr);
1234 /* Shift the read command bits out. */
1235 for (i = 15; i >= 0; i--) {
1236 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1237
1238 RTL_W8 (Config4, MDIO_DIR | dataval);
1239 mdio_delay ();
1240 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1241 mdio_delay ();
1242 }
1243
1244 /* Read the two transition, 16 data, and wire-idle bits. */
1245 for (i = 19; i > 0; i--) {
1246 RTL_W8 (Config4, 0);
1247 mdio_delay ();
1248 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1249 RTL_W8 (Config4, MDIO_CLK);
1250 mdio_delay ();
1251 }
1252 #endif
1253
1254 return (retval >> 1) & 0xffff;
1255 }
1256
1257
1258 static void mdio_write (struct net_device *dev, int phy_id, int location,
1259 int value)
1260 {
1261 struct rtl8139_private *tp = netdev_priv(dev);
1262 #ifdef CONFIG_8139TOO_8129
1263 void __iomem *ioaddr = tp->mmio_addr;
1264 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1265 int i;
1266 #endif
1267
1268 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1269 void __iomem *ioaddr = tp->mmio_addr;
1270 if (location == 0) {
1271 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1272 RTL_W16 (BasicModeCtrl, value);
1273 RTL_W8 (Cfg9346, Cfg9346_Lock);
1274 } else if (location < 8 && mii_2_8139_map[location])
1275 RTL_W16 (mii_2_8139_map[location], value);
1276 return;
1277 }
1278
1279 #ifdef CONFIG_8139TOO_8129
1280 mdio_sync (ioaddr);
1281
1282 /* Shift the command bits out. */
1283 for (i = 31; i >= 0; i--) {
1284 int dataval =
1285 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1286 RTL_W8 (Config4, dataval);
1287 mdio_delay ();
1288 RTL_W8 (Config4, dataval | MDIO_CLK);
1289 mdio_delay ();
1290 }
1291 /* Clear out extra bits. */
1292 for (i = 2; i > 0; i--) {
1293 RTL_W8 (Config4, 0);
1294 mdio_delay ();
1295 RTL_W8 (Config4, MDIO_CLK);
1296 mdio_delay ();
1297 }
1298 #endif
1299 }
1300
1301
1302 static int rtl8139_open (struct net_device *dev)
1303 {
1304 struct rtl8139_private *tp = netdev_priv(dev);
1305 int retval;
1306 void __iomem *ioaddr = tp->mmio_addr;
1307
1308 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1309 if (retval)
1310 return retval;
1311
1312 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1313 &tp->tx_bufs_dma, GFP_KERNEL);
1314 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1315 &tp->rx_ring_dma, GFP_KERNEL);
1316 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1317 free_irq(dev->irq, dev);
1318
1319 if (tp->tx_bufs)
1320 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1321 tp->tx_bufs, tp->tx_bufs_dma);
1322 if (tp->rx_ring)
1323 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1324 tp->rx_ring, tp->rx_ring_dma);
1325
1326 return -ENOMEM;
1327
1328 }
1329
1330 napi_enable(&tp->napi);
1331
1332 tp->mii.full_duplex = tp->mii.force_media;
1333 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1334
1335 rtl8139_init_ring (dev);
1336 rtl8139_hw_start (dev);
1337 netif_start_queue (dev);
1338
1339 if (netif_msg_ifup(tp))
1340 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1341 " GP Pins %2.2x %s-duplex.\n", dev->name,
1342 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1343 dev->irq, RTL_R8 (MediaStatus),
1344 tp->mii.full_duplex ? "full" : "half");
1345
1346 rtl8139_start_thread(tp);
1347
1348 return 0;
1349 }
1350
1351
1352 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1353 {
1354 struct rtl8139_private *tp = netdev_priv(dev);
1355
1356 if (tp->phys[0] >= 0) {
1357 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1358 }
1359 }
1360
1361 /* Start the hardware at open or resume. */
1362 static void rtl8139_hw_start (struct net_device *dev)
1363 {
1364 struct rtl8139_private *tp = netdev_priv(dev);
1365 void __iomem *ioaddr = tp->mmio_addr;
1366 u32 i;
1367 u8 tmp;
1368
1369 /* Bring old chips out of low-power mode. */
1370 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1371 RTL_W8 (HltClk, 'R');
1372
1373 rtl8139_chip_reset (ioaddr);
1374
1375 /* unlock Config[01234] and BMCR register writes */
1376 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1377 /* Restore our idea of the MAC address. */
1378 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1379 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1380
1381 /* Must enable Tx/Rx before setting transfer thresholds! */
1382 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1383
1384 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1385 RTL_W32 (RxConfig, tp->rx_config);
1386 RTL_W32 (TxConfig, rtl8139_tx_config);
1387
1388 tp->cur_rx = 0;
1389
1390 rtl_check_media (dev, 1);
1391
1392 if (tp->chipset >= CH_8139B) {
1393 /* Disable magic packet scanning, which is enabled
1394 * when PM is enabled in Config1. It can be reenabled
1395 * via ETHTOOL_SWOL if desired. */
1396 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1397 }
1398
1399 DPRINTK("init buffer addresses\n");
1400
1401 /* Lock Config[01234] and BMCR register writes */
1402 RTL_W8 (Cfg9346, Cfg9346_Lock);
1403
1404 /* init Rx ring buffer DMA address */
1405 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1406
1407 /* init Tx buffer DMA addresses */
1408 for (i = 0; i < NUM_TX_DESC; i++)
1409 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1410
1411 RTL_W32 (RxMissed, 0);
1412
1413 rtl8139_set_rx_mode (dev);
1414
1415 /* no early-rx interrupts */
1416 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1417
1418 /* make sure RxTx has started */
1419 tmp = RTL_R8 (ChipCmd);
1420 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1421 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1422
1423 /* Enable all known interrupts by setting the interrupt mask. */
1424 RTL_W16 (IntrMask, rtl8139_intr_mask);
1425 }
1426
1427
1428 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1429 static void rtl8139_init_ring (struct net_device *dev)
1430 {
1431 struct rtl8139_private *tp = netdev_priv(dev);
1432 int i;
1433
1434 tp->cur_rx = 0;
1435 tp->cur_tx = 0;
1436 tp->dirty_tx = 0;
1437
1438 for (i = 0; i < NUM_TX_DESC; i++)
1439 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1440 }
1441
1442
1443 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1444 static int next_tick = 3 * HZ;
1445
1446 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1447 static inline void rtl8139_tune_twister (struct net_device *dev,
1448 struct rtl8139_private *tp) {}
1449 #else
1450 enum TwisterParamVals {
1451 PARA78_default = 0x78fa8388,
1452 PARA7c_default = 0xcb38de43, /* param[0][3] */
1453 PARA7c_xxx = 0xcb38de43,
1454 };
1455
1456 static const unsigned long param[4][4] = {
1457 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1458 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1459 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1460 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1461 };
1462
1463 static void rtl8139_tune_twister (struct net_device *dev,
1464 struct rtl8139_private *tp)
1465 {
1466 int linkcase;
1467 void __iomem *ioaddr = tp->mmio_addr;
1468
1469 /* This is a complicated state machine to configure the "twister" for
1470 impedance/echos based on the cable length.
1471 All of this is magic and undocumented.
1472 */
1473 switch (tp->twistie) {
1474 case 1:
1475 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1476 /* We have link beat, let us tune the twister. */
1477 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1478 tp->twistie = 2; /* Change to state 2. */
1479 next_tick = HZ / 10;
1480 } else {
1481 /* Just put in some reasonable defaults for when beat returns. */
1482 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1483 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1484 RTL_W32 (PARA78, PARA78_default);
1485 RTL_W32 (PARA7c, PARA7c_default);
1486 tp->twistie = 0; /* Bail from future actions. */
1487 }
1488 break;
1489 case 2:
1490 /* Read how long it took to hear the echo. */
1491 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1492 if (linkcase == 0x7000)
1493 tp->twist_row = 3;
1494 else if (linkcase == 0x3000)
1495 tp->twist_row = 2;
1496 else if (linkcase == 0x1000)
1497 tp->twist_row = 1;
1498 else
1499 tp->twist_row = 0;
1500 tp->twist_col = 0;
1501 tp->twistie = 3; /* Change to state 2. */
1502 next_tick = HZ / 10;
1503 break;
1504 case 3:
1505 /* Put out four tuning parameters, one per 100msec. */
1506 if (tp->twist_col == 0)
1507 RTL_W16 (FIFOTMS, 0);
1508 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1509 [(int) tp->twist_col]);
1510 next_tick = HZ / 10;
1511 if (++tp->twist_col >= 4) {
1512 /* For short cables we are done.
1513 For long cables (row == 3) check for mistune. */
1514 tp->twistie =
1515 (tp->twist_row == 3) ? 4 : 0;
1516 }
1517 break;
1518 case 4:
1519 /* Special case for long cables: check for mistune. */
1520 if ((RTL_R16 (CSCR) &
1521 CSCR_LinkStatusBits) == 0x7000) {
1522 tp->twistie = 0;
1523 break;
1524 } else {
1525 RTL_W32 (PARA7c, 0xfb38de03);
1526 tp->twistie = 5;
1527 next_tick = HZ / 10;
1528 }
1529 break;
1530 case 5:
1531 /* Retune for shorter cable (column 2). */
1532 RTL_W32 (FIFOTMS, 0x20);
1533 RTL_W32 (PARA78, PARA78_default);
1534 RTL_W32 (PARA7c, PARA7c_default);
1535 RTL_W32 (FIFOTMS, 0x00);
1536 tp->twist_row = 2;
1537 tp->twist_col = 0;
1538 tp->twistie = 3;
1539 next_tick = HZ / 10;
1540 break;
1541
1542 default:
1543 /* do nothing */
1544 break;
1545 }
1546 }
1547 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1548
1549 static inline void rtl8139_thread_iter (struct net_device *dev,
1550 struct rtl8139_private *tp,
1551 void __iomem *ioaddr)
1552 {
1553 int mii_lpa;
1554
1555 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1556
1557 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1558 int duplex = (mii_lpa & LPA_100FULL)
1559 || (mii_lpa & 0x01C0) == 0x0040;
1560 if (tp->mii.full_duplex != duplex) {
1561 tp->mii.full_duplex = duplex;
1562
1563 if (mii_lpa) {
1564 printk (KERN_INFO
1565 "%s: Setting %s-duplex based on MII #%d link"
1566 " partner ability of %4.4x.\n",
1567 dev->name,
1568 tp->mii.full_duplex ? "full" : "half",
1569 tp->phys[0], mii_lpa);
1570 } else {
1571 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1572 dev->name);
1573 }
1574 #if 0
1575 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1576 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1577 RTL_W8 (Cfg9346, Cfg9346_Lock);
1578 #endif
1579 }
1580 }
1581
1582 next_tick = HZ * 60;
1583
1584 rtl8139_tune_twister (dev, tp);
1585
1586 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1587 dev->name, RTL_R16 (NWayLPAR));
1588 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1589 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1590 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1591 dev->name, RTL_R8 (Config0),
1592 RTL_R8 (Config1));
1593 }
1594
1595 static void rtl8139_thread (struct work_struct *work)
1596 {
1597 struct rtl8139_private *tp =
1598 container_of(work, struct rtl8139_private, thread.work);
1599 struct net_device *dev = tp->mii.dev;
1600 unsigned long thr_delay = next_tick;
1601
1602 rtnl_lock();
1603
1604 if (!netif_running(dev))
1605 goto out_unlock;
1606
1607 if (tp->watchdog_fired) {
1608 tp->watchdog_fired = 0;
1609 rtl8139_tx_timeout_task(work);
1610 } else
1611 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1612
1613 if (tp->have_thread)
1614 schedule_delayed_work(&tp->thread, thr_delay);
1615 out_unlock:
1616 rtnl_unlock ();
1617 }
1618
1619 static void rtl8139_start_thread(struct rtl8139_private *tp)
1620 {
1621 tp->twistie = 0;
1622 if (tp->chipset == CH_8139_K)
1623 tp->twistie = 1;
1624 else if (tp->drv_flags & HAS_LNK_CHNG)
1625 return;
1626
1627 tp->have_thread = 1;
1628 tp->watchdog_fired = 0;
1629
1630 schedule_delayed_work(&tp->thread, next_tick);
1631 }
1632
1633 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1634 {
1635 tp->cur_tx = 0;
1636 tp->dirty_tx = 0;
1637
1638 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1639 }
1640
1641 static void rtl8139_tx_timeout_task (struct work_struct *work)
1642 {
1643 struct rtl8139_private *tp =
1644 container_of(work, struct rtl8139_private, thread.work);
1645 struct net_device *dev = tp->mii.dev;
1646 void __iomem *ioaddr = tp->mmio_addr;
1647 int i;
1648 u8 tmp8;
1649
1650 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1651 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1652 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1653 /* Emit info to figure out what went wrong. */
1654 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1655 dev->name, tp->cur_tx, tp->dirty_tx);
1656 for (i = 0; i < NUM_TX_DESC; i++)
1657 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1658 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1659 i == tp->dirty_tx % NUM_TX_DESC ?
1660 " (queue head)" : "");
1661
1662 tp->xstats.tx_timeouts++;
1663
1664 /* disable Tx ASAP, if not already */
1665 tmp8 = RTL_R8 (ChipCmd);
1666 if (tmp8 & CmdTxEnb)
1667 RTL_W8 (ChipCmd, CmdRxEnb);
1668
1669 spin_lock_bh(&tp->rx_lock);
1670 /* Disable interrupts by clearing the interrupt mask. */
1671 RTL_W16 (IntrMask, 0x0000);
1672
1673 /* Stop a shared interrupt from scavenging while we are. */
1674 spin_lock_irq(&tp->lock);
1675 rtl8139_tx_clear (tp);
1676 spin_unlock_irq(&tp->lock);
1677
1678 /* ...and finally, reset everything */
1679 if (netif_running(dev)) {
1680 rtl8139_hw_start (dev);
1681 netif_wake_queue (dev);
1682 }
1683 spin_unlock_bh(&tp->rx_lock);
1684 }
1685
1686 static void rtl8139_tx_timeout (struct net_device *dev)
1687 {
1688 struct rtl8139_private *tp = netdev_priv(dev);
1689
1690 tp->watchdog_fired = 1;
1691 if (!tp->have_thread) {
1692 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1693 schedule_delayed_work(&tp->thread, next_tick);
1694 }
1695 }
1696
1697 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1698 {
1699 struct rtl8139_private *tp = netdev_priv(dev);
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 unsigned int entry;
1702 unsigned int len = skb->len;
1703 unsigned long flags;
1704
1705 /* Calculate the next Tx descriptor entry. */
1706 entry = tp->cur_tx % NUM_TX_DESC;
1707
1708 /* Note: the chip doesn't have auto-pad! */
1709 if (likely(len < TX_BUF_SIZE)) {
1710 if (len < ETH_ZLEN)
1711 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1712 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1713 dev_kfree_skb(skb);
1714 } else {
1715 dev_kfree_skb(skb);
1716 tp->stats.tx_dropped++;
1717 return 0;
1718 }
1719
1720 spin_lock_irqsave(&tp->lock, flags);
1721 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1722 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1723
1724 dev->trans_start = jiffies;
1725
1726 tp->cur_tx++;
1727 wmb();
1728
1729 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1730 netif_stop_queue (dev);
1731 spin_unlock_irqrestore(&tp->lock, flags);
1732
1733 if (netif_msg_tx_queued(tp))
1734 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1735 dev->name, len, entry);
1736
1737 return 0;
1738 }
1739
1740
1741 static void rtl8139_tx_interrupt (struct net_device *dev,
1742 struct rtl8139_private *tp,
1743 void __iomem *ioaddr)
1744 {
1745 unsigned long dirty_tx, tx_left;
1746
1747 assert (dev != NULL);
1748 assert (ioaddr != NULL);
1749
1750 dirty_tx = tp->dirty_tx;
1751 tx_left = tp->cur_tx - dirty_tx;
1752 while (tx_left > 0) {
1753 int entry = dirty_tx % NUM_TX_DESC;
1754 int txstatus;
1755
1756 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1757
1758 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1759 break; /* It still hasn't been Txed */
1760
1761 /* Note: TxCarrierLost is always asserted at 100mbps. */
1762 if (txstatus & (TxOutOfWindow | TxAborted)) {
1763 /* There was an major error, log it. */
1764 if (netif_msg_tx_err(tp))
1765 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1766 dev->name, txstatus);
1767 tp->stats.tx_errors++;
1768 if (txstatus & TxAborted) {
1769 tp->stats.tx_aborted_errors++;
1770 RTL_W32 (TxConfig, TxClearAbt);
1771 RTL_W16 (IntrStatus, TxErr);
1772 wmb();
1773 }
1774 if (txstatus & TxCarrierLost)
1775 tp->stats.tx_carrier_errors++;
1776 if (txstatus & TxOutOfWindow)
1777 tp->stats.tx_window_errors++;
1778 } else {
1779 if (txstatus & TxUnderrun) {
1780 /* Add 64 to the Tx FIFO threshold. */
1781 if (tp->tx_flag < 0x00300000)
1782 tp->tx_flag += 0x00020000;
1783 tp->stats.tx_fifo_errors++;
1784 }
1785 tp->stats.collisions += (txstatus >> 24) & 15;
1786 tp->stats.tx_bytes += txstatus & 0x7ff;
1787 tp->stats.tx_packets++;
1788 }
1789
1790 dirty_tx++;
1791 tx_left--;
1792 }
1793
1794 #ifndef RTL8139_NDEBUG
1795 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1796 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1797 dev->name, dirty_tx, tp->cur_tx);
1798 dirty_tx += NUM_TX_DESC;
1799 }
1800 #endif /* RTL8139_NDEBUG */
1801
1802 /* only wake the queue if we did work, and the queue is stopped */
1803 if (tp->dirty_tx != dirty_tx) {
1804 tp->dirty_tx = dirty_tx;
1805 mb();
1806 netif_wake_queue (dev);
1807 }
1808 }
1809
1810
1811 /* TODO: clean this up! Rx reset need not be this intensive */
1812 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1813 struct rtl8139_private *tp, void __iomem *ioaddr)
1814 {
1815 u8 tmp8;
1816 #ifdef CONFIG_8139_OLD_RX_RESET
1817 int tmp_work;
1818 #endif
1819
1820 if (netif_msg_rx_err (tp))
1821 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1822 dev->name, rx_status);
1823 tp->stats.rx_errors++;
1824 if (!(rx_status & RxStatusOK)) {
1825 if (rx_status & RxTooLong) {
1826 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1827 dev->name, rx_status);
1828 /* A.C.: The chip hangs here. */
1829 }
1830 if (rx_status & (RxBadSymbol | RxBadAlign))
1831 tp->stats.rx_frame_errors++;
1832 if (rx_status & (RxRunt | RxTooLong))
1833 tp->stats.rx_length_errors++;
1834 if (rx_status & RxCRCErr)
1835 tp->stats.rx_crc_errors++;
1836 } else {
1837 tp->xstats.rx_lost_in_ring++;
1838 }
1839
1840 #ifndef CONFIG_8139_OLD_RX_RESET
1841 tmp8 = RTL_R8 (ChipCmd);
1842 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1843 RTL_W8 (ChipCmd, tmp8);
1844 RTL_W32 (RxConfig, tp->rx_config);
1845 tp->cur_rx = 0;
1846 #else
1847 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1848
1849 /* disable receive */
1850 RTL_W8_F (ChipCmd, CmdTxEnb);
1851 tmp_work = 200;
1852 while (--tmp_work > 0) {
1853 udelay(1);
1854 tmp8 = RTL_R8 (ChipCmd);
1855 if (!(tmp8 & CmdRxEnb))
1856 break;
1857 }
1858 if (tmp_work <= 0)
1859 printk (KERN_WARNING PFX "rx stop wait too long\n");
1860 /* restart receive */
1861 tmp_work = 200;
1862 while (--tmp_work > 0) {
1863 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1864 udelay(1);
1865 tmp8 = RTL_R8 (ChipCmd);
1866 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1867 break;
1868 }
1869 if (tmp_work <= 0)
1870 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1871
1872 /* and reinitialize all rx related registers */
1873 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1874 /* Must enable Tx/Rx before setting transfer thresholds! */
1875 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1876
1877 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1878 RTL_W32 (RxConfig, tp->rx_config);
1879 tp->cur_rx = 0;
1880
1881 DPRINTK("init buffer addresses\n");
1882
1883 /* Lock Config[01234] and BMCR register writes */
1884 RTL_W8 (Cfg9346, Cfg9346_Lock);
1885
1886 /* init Rx ring buffer DMA address */
1887 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1888
1889 /* A.C.: Reset the multicast list. */
1890 __set_rx_mode (dev);
1891 #endif
1892 }
1893
1894 #if RX_BUF_IDX == 3
1895 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1896 u32 offset, unsigned int size)
1897 {
1898 u32 left = RX_BUF_LEN - offset;
1899
1900 if (size > left) {
1901 skb_copy_to_linear_data(skb, ring + offset, left);
1902 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1903 } else
1904 skb_copy_to_linear_data(skb, ring + offset, size);
1905 }
1906 #endif
1907
1908 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1909 {
1910 void __iomem *ioaddr = tp->mmio_addr;
1911 u16 status;
1912
1913 status = RTL_R16 (IntrStatus) & RxAckBits;
1914
1915 /* Clear out errors and receive interrupts */
1916 if (likely(status != 0)) {
1917 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1918 tp->stats.rx_errors++;
1919 if (status & RxFIFOOver)
1920 tp->stats.rx_fifo_errors++;
1921 }
1922 RTL_W16_F (IntrStatus, RxAckBits);
1923 }
1924 }
1925
1926 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1927 int budget)
1928 {
1929 void __iomem *ioaddr = tp->mmio_addr;
1930 int received = 0;
1931 unsigned char *rx_ring = tp->rx_ring;
1932 unsigned int cur_rx = tp->cur_rx;
1933 unsigned int rx_size = 0;
1934
1935 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1936 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1937 RTL_R16 (RxBufAddr),
1938 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1939
1940 while (netif_running(dev) && received < budget
1941 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1942 u32 ring_offset = cur_rx % RX_BUF_LEN;
1943 u32 rx_status;
1944 unsigned int pkt_size;
1945 struct sk_buff *skb;
1946
1947 rmb();
1948
1949 /* read size+status of next frame from DMA ring buffer */
1950 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1951 rx_size = rx_status >> 16;
1952 pkt_size = rx_size - 4;
1953
1954 if (netif_msg_rx_status(tp))
1955 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1956 " cur %4.4x.\n", dev->name, rx_status,
1957 rx_size, cur_rx);
1958 #if RTL8139_DEBUG > 2
1959 {
1960 int i;
1961 DPRINTK ("%s: Frame contents ", dev->name);
1962 for (i = 0; i < 70; i++)
1963 printk (" %2.2x",
1964 rx_ring[ring_offset + i]);
1965 printk (".\n");
1966 }
1967 #endif
1968
1969 /* Packet copy from FIFO still in progress.
1970 * Theoretically, this should never happen
1971 * since EarlyRx is disabled.
1972 */
1973 if (unlikely(rx_size == 0xfff0)) {
1974 if (!tp->fifo_copy_timeout)
1975 tp->fifo_copy_timeout = jiffies + 2;
1976 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1977 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1978 rx_size = 0;
1979 goto no_early_rx;
1980 }
1981 if (netif_msg_intr(tp)) {
1982 printk(KERN_DEBUG "%s: fifo copy in progress.",
1983 dev->name);
1984 }
1985 tp->xstats.early_rx++;
1986 break;
1987 }
1988
1989 no_early_rx:
1990 tp->fifo_copy_timeout = 0;
1991
1992 /* If Rx err or invalid rx_size/rx_status received
1993 * (which happens if we get lost in the ring),
1994 * Rx process gets reset, so we abort any further
1995 * Rx processing.
1996 */
1997 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1998 (rx_size < 8) ||
1999 (!(rx_status & RxStatusOK)))) {
2000 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2001 received = -1;
2002 goto out;
2003 }
2004
2005 /* Malloc up new buffer, compatible with net-2e. */
2006 /* Omit the four octet CRC from the length. */
2007
2008 skb = dev_alloc_skb (pkt_size + 2);
2009 if (likely(skb)) {
2010 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2011 #if RX_BUF_IDX == 3
2012 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2013 #else
2014 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2015 #endif
2016 skb_put (skb, pkt_size);
2017
2018 skb->protocol = eth_type_trans (skb, dev);
2019
2020 dev->last_rx = jiffies;
2021 tp->stats.rx_bytes += pkt_size;
2022 tp->stats.rx_packets++;
2023
2024 netif_receive_skb (skb);
2025 } else {
2026 if (net_ratelimit())
2027 printk (KERN_WARNING
2028 "%s: Memory squeeze, dropping packet.\n",
2029 dev->name);
2030 tp->stats.rx_dropped++;
2031 }
2032 received++;
2033
2034 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2035 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2036
2037 rtl8139_isr_ack(tp);
2038 }
2039
2040 if (unlikely(!received || rx_size == 0xfff0))
2041 rtl8139_isr_ack(tp);
2042
2043 #if RTL8139_DEBUG > 1
2044 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2045 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2046 RTL_R16 (RxBufAddr),
2047 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2048 #endif
2049
2050 tp->cur_rx = cur_rx;
2051
2052 /*
2053 * The receive buffer should be mostly empty.
2054 * Tell NAPI to reenable the Rx irq.
2055 */
2056 if (tp->fifo_copy_timeout)
2057 received = budget;
2058
2059 out:
2060 return received;
2061 }
2062
2063
2064 static void rtl8139_weird_interrupt (struct net_device *dev,
2065 struct rtl8139_private *tp,
2066 void __iomem *ioaddr,
2067 int status, int link_changed)
2068 {
2069 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2070 dev->name, status);
2071
2072 assert (dev != NULL);
2073 assert (tp != NULL);
2074 assert (ioaddr != NULL);
2075
2076 /* Update the error count. */
2077 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2078 RTL_W32 (RxMissed, 0);
2079
2080 if ((status & RxUnderrun) && link_changed &&
2081 (tp->drv_flags & HAS_LNK_CHNG)) {
2082 rtl_check_media(dev, 0);
2083 status &= ~RxUnderrun;
2084 }
2085
2086 if (status & (RxUnderrun | RxErr))
2087 tp->stats.rx_errors++;
2088
2089 if (status & PCSTimeout)
2090 tp->stats.rx_length_errors++;
2091 if (status & RxUnderrun)
2092 tp->stats.rx_fifo_errors++;
2093 if (status & PCIErr) {
2094 u16 pci_cmd_status;
2095 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2096 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2097
2098 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2099 dev->name, pci_cmd_status);
2100 }
2101 }
2102
2103 static int rtl8139_poll(struct napi_struct *napi, int budget)
2104 {
2105 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2106 struct net_device *dev = tp->dev;
2107 void __iomem *ioaddr = tp->mmio_addr;
2108 int work_done;
2109
2110 spin_lock(&tp->rx_lock);
2111 work_done = 0;
2112 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2113 work_done += rtl8139_rx(dev, tp, budget);
2114
2115 if (work_done < budget) {
2116 unsigned long flags;
2117 /*
2118 * Order is important since data can get interrupted
2119 * again when we think we are done.
2120 */
2121 spin_lock_irqsave(&tp->lock, flags);
2122 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2123 __netif_rx_complete(dev, napi);
2124 spin_unlock_irqrestore(&tp->lock, flags);
2125 }
2126 spin_unlock(&tp->rx_lock);
2127
2128 return work_done;
2129 }
2130
2131 /* The interrupt handler does all of the Rx thread work and cleans up
2132 after the Tx thread. */
2133 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2134 {
2135 struct net_device *dev = (struct net_device *) dev_instance;
2136 struct rtl8139_private *tp = netdev_priv(dev);
2137 void __iomem *ioaddr = tp->mmio_addr;
2138 u16 status, ackstat;
2139 int link_changed = 0; /* avoid bogus "uninit" warning */
2140 int handled = 0;
2141
2142 spin_lock (&tp->lock);
2143 status = RTL_R16 (IntrStatus);
2144
2145 /* shared irq? */
2146 if (unlikely((status & rtl8139_intr_mask) == 0))
2147 goto out;
2148
2149 handled = 1;
2150
2151 /* h/w no longer present (hotplug?) or major error, bail */
2152 if (unlikely(status == 0xFFFF))
2153 goto out;
2154
2155 /* close possible race's with dev_close */
2156 if (unlikely(!netif_running(dev))) {
2157 RTL_W16 (IntrMask, 0);
2158 goto out;
2159 }
2160
2161 /* Acknowledge all of the current interrupt sources ASAP, but
2162 an first get an additional status bit from CSCR. */
2163 if (unlikely(status & RxUnderrun))
2164 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2165
2166 ackstat = status & ~(RxAckBits | TxErr);
2167 if (ackstat)
2168 RTL_W16 (IntrStatus, ackstat);
2169
2170 /* Receive packets are processed by poll routine.
2171 If not running start it now. */
2172 if (status & RxAckBits){
2173 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2174 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2175 __netif_rx_schedule(dev, &tp->napi);
2176 }
2177 }
2178
2179 /* Check uncommon events with one test. */
2180 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2181 rtl8139_weird_interrupt (dev, tp, ioaddr,
2182 status, link_changed);
2183
2184 if (status & (TxOK | TxErr)) {
2185 rtl8139_tx_interrupt (dev, tp, ioaddr);
2186 if (status & TxErr)
2187 RTL_W16 (IntrStatus, TxErr);
2188 }
2189 out:
2190 spin_unlock (&tp->lock);
2191
2192 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2193 dev->name, RTL_R16 (IntrStatus));
2194 return IRQ_RETVAL(handled);
2195 }
2196
2197 #ifdef CONFIG_NET_POLL_CONTROLLER
2198 /*
2199 * Polling receive - used by netconsole and other diagnostic tools
2200 * to allow network i/o with interrupts disabled.
2201 */
2202 static void rtl8139_poll_controller(struct net_device *dev)
2203 {
2204 disable_irq(dev->irq);
2205 rtl8139_interrupt(dev->irq, dev);
2206 enable_irq(dev->irq);
2207 }
2208 #endif
2209
2210 static int rtl8139_close (struct net_device *dev)
2211 {
2212 struct rtl8139_private *tp = netdev_priv(dev);
2213 void __iomem *ioaddr = tp->mmio_addr;
2214 unsigned long flags;
2215
2216 netif_stop_queue(dev);
2217 napi_disable(&tp->napi);
2218
2219 if (netif_msg_ifdown(tp))
2220 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2221 dev->name, RTL_R16 (IntrStatus));
2222
2223 spin_lock_irqsave (&tp->lock, flags);
2224
2225 /* Stop the chip's Tx and Rx DMA processes. */
2226 RTL_W8 (ChipCmd, 0);
2227
2228 /* Disable interrupts by clearing the interrupt mask. */
2229 RTL_W16 (IntrMask, 0);
2230
2231 /* Update the error counts. */
2232 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2233 RTL_W32 (RxMissed, 0);
2234
2235 spin_unlock_irqrestore (&tp->lock, flags);
2236
2237 synchronize_irq (dev->irq); /* racy, but that's ok here */
2238 free_irq (dev->irq, dev);
2239
2240 rtl8139_tx_clear (tp);
2241
2242 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2243 tp->rx_ring, tp->rx_ring_dma);
2244 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2245 tp->tx_bufs, tp->tx_bufs_dma);
2246 tp->rx_ring = NULL;
2247 tp->tx_bufs = NULL;
2248
2249 /* Green! Put the chip in low-power mode. */
2250 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2251
2252 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2253 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2254
2255 return 0;
2256 }
2257
2258
2259 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2260 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2261 other threads or interrupts aren't messing with the 8139. */
2262 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2263 {
2264 struct rtl8139_private *np = netdev_priv(dev);
2265 void __iomem *ioaddr = np->mmio_addr;
2266
2267 spin_lock_irq(&np->lock);
2268 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2269 u8 cfg3 = RTL_R8 (Config3);
2270 u8 cfg5 = RTL_R8 (Config5);
2271
2272 wol->supported = WAKE_PHY | WAKE_MAGIC
2273 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2274
2275 wol->wolopts = 0;
2276 if (cfg3 & Cfg3_LinkUp)
2277 wol->wolopts |= WAKE_PHY;
2278 if (cfg3 & Cfg3_Magic)
2279 wol->wolopts |= WAKE_MAGIC;
2280 /* (KON)FIXME: See how netdev_set_wol() handles the
2281 following constants. */
2282 if (cfg5 & Cfg5_UWF)
2283 wol->wolopts |= WAKE_UCAST;
2284 if (cfg5 & Cfg5_MWF)
2285 wol->wolopts |= WAKE_MCAST;
2286 if (cfg5 & Cfg5_BWF)
2287 wol->wolopts |= WAKE_BCAST;
2288 }
2289 spin_unlock_irq(&np->lock);
2290 }
2291
2292
2293 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2294 that wol points to kernel memory and other threads or interrupts
2295 aren't messing with the 8139. */
2296 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2297 {
2298 struct rtl8139_private *np = netdev_priv(dev);
2299 void __iomem *ioaddr = np->mmio_addr;
2300 u32 support;
2301 u8 cfg3, cfg5;
2302
2303 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2304 ? (WAKE_PHY | WAKE_MAGIC
2305 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2306 : 0);
2307 if (wol->wolopts & ~support)
2308 return -EINVAL;
2309
2310 spin_lock_irq(&np->lock);
2311 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2312 if (wol->wolopts & WAKE_PHY)
2313 cfg3 |= Cfg3_LinkUp;
2314 if (wol->wolopts & WAKE_MAGIC)
2315 cfg3 |= Cfg3_Magic;
2316 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2317 RTL_W8 (Config3, cfg3);
2318 RTL_W8 (Cfg9346, Cfg9346_Lock);
2319
2320 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2321 /* (KON)FIXME: These are untested. We may have to set the
2322 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2323 documentation. */
2324 if (wol->wolopts & WAKE_UCAST)
2325 cfg5 |= Cfg5_UWF;
2326 if (wol->wolopts & WAKE_MCAST)
2327 cfg5 |= Cfg5_MWF;
2328 if (wol->wolopts & WAKE_BCAST)
2329 cfg5 |= Cfg5_BWF;
2330 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2331 spin_unlock_irq(&np->lock);
2332
2333 return 0;
2334 }
2335
2336 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2337 {
2338 struct rtl8139_private *np = netdev_priv(dev);
2339 strcpy(info->driver, DRV_NAME);
2340 strcpy(info->version, DRV_VERSION);
2341 strcpy(info->bus_info, pci_name(np->pci_dev));
2342 info->regdump_len = np->regs_len;
2343 }
2344
2345 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2346 {
2347 struct rtl8139_private *np = netdev_priv(dev);
2348 spin_lock_irq(&np->lock);
2349 mii_ethtool_gset(&np->mii, cmd);
2350 spin_unlock_irq(&np->lock);
2351 return 0;
2352 }
2353
2354 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2355 {
2356 struct rtl8139_private *np = netdev_priv(dev);
2357 int rc;
2358 spin_lock_irq(&np->lock);
2359 rc = mii_ethtool_sset(&np->mii, cmd);
2360 spin_unlock_irq(&np->lock);
2361 return rc;
2362 }
2363
2364 static int rtl8139_nway_reset(struct net_device *dev)
2365 {
2366 struct rtl8139_private *np = netdev_priv(dev);
2367 return mii_nway_restart(&np->mii);
2368 }
2369
2370 static u32 rtl8139_get_link(struct net_device *dev)
2371 {
2372 struct rtl8139_private *np = netdev_priv(dev);
2373 return mii_link_ok(&np->mii);
2374 }
2375
2376 static u32 rtl8139_get_msglevel(struct net_device *dev)
2377 {
2378 struct rtl8139_private *np = netdev_priv(dev);
2379 return np->msg_enable;
2380 }
2381
2382 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2383 {
2384 struct rtl8139_private *np = netdev_priv(dev);
2385 np->msg_enable = datum;
2386 }
2387
2388 /* TODO: we are too slack to do reg dumping for pio, for now */
2389 #ifdef CONFIG_8139TOO_PIO
2390 #define rtl8139_get_regs_len NULL
2391 #define rtl8139_get_regs NULL
2392 #else
2393 static int rtl8139_get_regs_len(struct net_device *dev)
2394 {
2395 struct rtl8139_private *np = netdev_priv(dev);
2396 return np->regs_len;
2397 }
2398
2399 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2400 {
2401 struct rtl8139_private *np = netdev_priv(dev);
2402
2403 regs->version = RTL_REGS_VER;
2404
2405 spin_lock_irq(&np->lock);
2406 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2407 spin_unlock_irq(&np->lock);
2408 }
2409 #endif /* CONFIG_8139TOO_MMIO */
2410
2411 static int rtl8139_get_stats_count(struct net_device *dev)
2412 {
2413 return RTL_NUM_STATS;
2414 }
2415
2416 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2417 {
2418 struct rtl8139_private *np = netdev_priv(dev);
2419
2420 data[0] = np->xstats.early_rx;
2421 data[1] = np->xstats.tx_buf_mapped;
2422 data[2] = np->xstats.tx_timeouts;
2423 data[3] = np->xstats.rx_lost_in_ring;
2424 }
2425
2426 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2427 {
2428 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2429 }
2430
2431 static const struct ethtool_ops rtl8139_ethtool_ops = {
2432 .get_drvinfo = rtl8139_get_drvinfo,
2433 .get_settings = rtl8139_get_settings,
2434 .set_settings = rtl8139_set_settings,
2435 .get_regs_len = rtl8139_get_regs_len,
2436 .get_regs = rtl8139_get_regs,
2437 .nway_reset = rtl8139_nway_reset,
2438 .get_link = rtl8139_get_link,
2439 .get_msglevel = rtl8139_get_msglevel,
2440 .set_msglevel = rtl8139_set_msglevel,
2441 .get_wol = rtl8139_get_wol,
2442 .set_wol = rtl8139_set_wol,
2443 .get_strings = rtl8139_get_strings,
2444 .get_stats_count = rtl8139_get_stats_count,
2445 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2446 };
2447
2448 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2449 {
2450 struct rtl8139_private *np = netdev_priv(dev);
2451 int rc;
2452
2453 if (!netif_running(dev))
2454 return -EINVAL;
2455
2456 spin_lock_irq(&np->lock);
2457 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2458 spin_unlock_irq(&np->lock);
2459
2460 return rc;
2461 }
2462
2463
2464 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2465 {
2466 struct rtl8139_private *tp = netdev_priv(dev);
2467 void __iomem *ioaddr = tp->mmio_addr;
2468 unsigned long flags;
2469
2470 if (netif_running(dev)) {
2471 spin_lock_irqsave (&tp->lock, flags);
2472 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2473 RTL_W32 (RxMissed, 0);
2474 spin_unlock_irqrestore (&tp->lock, flags);
2475 }
2476
2477 return &tp->stats;
2478 }
2479
2480 /* Set or clear the multicast filter for this adaptor.
2481 This routine is not state sensitive and need not be SMP locked. */
2482
2483 static void __set_rx_mode (struct net_device *dev)
2484 {
2485 struct rtl8139_private *tp = netdev_priv(dev);
2486 void __iomem *ioaddr = tp->mmio_addr;
2487 u32 mc_filter[2]; /* Multicast hash filter */
2488 int i, rx_mode;
2489 u32 tmp;
2490
2491 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2492 dev->name, dev->flags, RTL_R32 (RxConfig));
2493
2494 /* Note: do not reorder, GCC is clever about common statements. */
2495 if (dev->flags & IFF_PROMISC) {
2496 rx_mode =
2497 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2498 AcceptAllPhys;
2499 mc_filter[1] = mc_filter[0] = 0xffffffff;
2500 } else if ((dev->mc_count > multicast_filter_limit)
2501 || (dev->flags & IFF_ALLMULTI)) {
2502 /* Too many to filter perfectly -- accept all multicasts. */
2503 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2504 mc_filter[1] = mc_filter[0] = 0xffffffff;
2505 } else {
2506 struct dev_mc_list *mclist;
2507 rx_mode = AcceptBroadcast | AcceptMyPhys;
2508 mc_filter[1] = mc_filter[0] = 0;
2509 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2510 i++, mclist = mclist->next) {
2511 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2512
2513 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2514 rx_mode |= AcceptMulticast;
2515 }
2516 }
2517
2518 /* We can safely update without stopping the chip. */
2519 tmp = rtl8139_rx_config | rx_mode;
2520 if (tp->rx_config != tmp) {
2521 RTL_W32_F (RxConfig, tmp);
2522 tp->rx_config = tmp;
2523 }
2524 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2525 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2526 }
2527
2528 static void rtl8139_set_rx_mode (struct net_device *dev)
2529 {
2530 unsigned long flags;
2531 struct rtl8139_private *tp = netdev_priv(dev);
2532
2533 spin_lock_irqsave (&tp->lock, flags);
2534 __set_rx_mode(dev);
2535 spin_unlock_irqrestore (&tp->lock, flags);
2536 }
2537
2538 #ifdef CONFIG_PM
2539
2540 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2541 {
2542 struct net_device *dev = pci_get_drvdata (pdev);
2543 struct rtl8139_private *tp = netdev_priv(dev);
2544 void __iomem *ioaddr = tp->mmio_addr;
2545 unsigned long flags;
2546
2547 pci_save_state (pdev);
2548
2549 if (!netif_running (dev))
2550 return 0;
2551
2552 netif_device_detach (dev);
2553
2554 spin_lock_irqsave (&tp->lock, flags);
2555
2556 /* Disable interrupts, stop Tx and Rx. */
2557 RTL_W16 (IntrMask, 0);
2558 RTL_W8 (ChipCmd, 0);
2559
2560 /* Update the error counts. */
2561 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2562 RTL_W32 (RxMissed, 0);
2563
2564 spin_unlock_irqrestore (&tp->lock, flags);
2565
2566 pci_set_power_state (pdev, PCI_D3hot);
2567
2568 return 0;
2569 }
2570
2571
2572 static int rtl8139_resume (struct pci_dev *pdev)
2573 {
2574 struct net_device *dev = pci_get_drvdata (pdev);
2575
2576 pci_restore_state (pdev);
2577 if (!netif_running (dev))
2578 return 0;
2579 pci_set_power_state (pdev, PCI_D0);
2580 rtl8139_init_ring (dev);
2581 rtl8139_hw_start (dev);
2582 netif_device_attach (dev);
2583 return 0;
2584 }
2585
2586 #endif /* CONFIG_PM */
2587
2588
2589 static struct pci_driver rtl8139_pci_driver = {
2590 .name = DRV_NAME,
2591 .id_table = rtl8139_pci_tbl,
2592 .probe = rtl8139_init_one,
2593 .remove = __devexit_p(rtl8139_remove_one),
2594 #ifdef CONFIG_PM
2595 .suspend = rtl8139_suspend,
2596 .resume = rtl8139_resume,
2597 #endif /* CONFIG_PM */
2598 };
2599
2600
2601 static int __init rtl8139_init_module (void)
2602 {
2603 /* when we're a module, we always print a version message,
2604 * even if no 8139 board is found.
2605 */
2606 #ifdef MODULE
2607 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2608 #endif
2609
2610 return pci_register_driver(&rtl8139_pci_driver);
2611 }
2612
2613
2614 static void __exit rtl8139_cleanup_module (void)
2615 {
2616 pci_unregister_driver (&rtl8139_pci_driver);
2617 }
2618
2619
2620 module_init(rtl8139_init_module);
2621 module_exit(rtl8139_cleanup_module);
Linux kernel - Deliverables
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