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[8139too]: tab-align enums and structs; remove dead code
[deliverable/linux.git] / drivers / net / 8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
392 TxIFGShift = 24,
393 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
394 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
395 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
396 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
397
398 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
399 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
400 TxClearAbt = (1 << 0), /* Clear abort (WO) */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
402 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
403
404 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 };
406
407 /* Bits in Config1 */
408 enum Config1Bits {
409 Cfg1_PM_Enable = 0x01,
410 Cfg1_VPD_Enable = 0x02,
411 Cfg1_PIO = 0x04,
412 Cfg1_MMIO = 0x08,
413 LWAKE = 0x10, /* not on 8139, 8139A */
414 Cfg1_Driver_Load = 0x20,
415 Cfg1_LED0 = 0x40,
416 Cfg1_LED1 = 0x80,
417 SLEEP = (1 << 1), /* only on 8139, 8139A */
418 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 };
420
421 /* Bits in Config3 */
422 enum Config3Bits {
423 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
424 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
425 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
426 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
427 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
428 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
429 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
430 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 };
432
433 /* Bits in Config4 */
434 enum Config4Bits {
435 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 };
437
438 /* Bits in Config5 */
439 enum Config5Bits {
440 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
441 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
442 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
443 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
444 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
445 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
446 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 };
448
449 enum RxConfigBits {
450 /* rx fifo threshold */
451 RxCfgFIFOShift = 13,
452 RxCfgFIFONone = (7 << RxCfgFIFOShift),
453
454 /* Max DMA burst */
455 RxCfgDMAShift = 8,
456 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
457
458 /* rx ring buffer length */
459 RxCfgRcv8K = 0,
460 RxCfgRcv16K = (1 << 11),
461 RxCfgRcv32K = (1 << 12),
462 RxCfgRcv64K = (1 << 11) | (1 << 12),
463
464 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
465 RxNoWrap = (1 << 7),
466 };
467
468 /* Twister tuning parameters from RealTek.
469 Completely undocumented, but required to tune bad links on some boards. */
470 enum CSCRBits {
471 CSCR_LinkOKBit = 0x0400,
472 CSCR_LinkChangeBit = 0x0800,
473 CSCR_LinkStatusBits = 0x0f000,
474 CSCR_LinkDownOffCmd = 0x003c0,
475 CSCR_LinkDownCmd = 0x0f3c0,
476 };
477
478 enum Cfg9346Bits {
479 Cfg9346_Lock = 0x00,
480 Cfg9346_Unlock = 0xC0,
481 };
482
483 typedef enum {
484 CH_8139 = 0,
485 CH_8139_K,
486 CH_8139A,
487 CH_8139A_G,
488 CH_8139B,
489 CH_8130,
490 CH_8139C,
491 CH_8100,
492 CH_8100B_8139D,
493 CH_8101,
494 } chip_t;
495
496 enum chip_flags {
497 HasHltClk = (1 << 0),
498 HasLWake = (1 << 1),
499 };
500
501 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
502 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
503 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
504
505 /* directly indexed by chip_t, above */
506 static const struct {
507 const char *name;
508 u32 version; /* from RTL8139C/RTL8139D docs */
509 u32 flags;
510 } rtl_chip_info[] = {
511 { "RTL-8139",
512 HW_REVID(1, 0, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139 rev K",
517 HW_REVID(1, 1, 0, 0, 0, 0, 0),
518 HasHltClk,
519 },
520
521 { "RTL-8139A",
522 HW_REVID(1, 1, 1, 0, 0, 0, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139A rev G",
527 HW_REVID(1, 1, 1, 0, 0, 1, 0),
528 HasHltClk, /* XXX undocumented? */
529 },
530
531 { "RTL-8139B",
532 HW_REVID(1, 1, 1, 1, 0, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8130",
537 HW_REVID(1, 1, 1, 1, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8139C",
542 HW_REVID(1, 1, 1, 0, 1, 0, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100",
547 HW_REVID(1, 1, 1, 1, 0, 1, 0),
548 HasLWake,
549 },
550
551 { "RTL-8100B/8139D",
552 HW_REVID(1, 1, 1, 0, 1, 0, 1),
553 HasHltClk /* XXX undocumented? */
554 | HasLWake,
555 },
556
557 { "RTL-8101",
558 HW_REVID(1, 1, 1, 0, 1, 1, 1),
559 HasLWake,
560 },
561 };
562
563 struct rtl_extra_stats {
564 unsigned long early_rx;
565 unsigned long tx_buf_mapped;
566 unsigned long tx_timeouts;
567 unsigned long rx_lost_in_ring;
568 };
569
570 struct rtl8139_private {
571 void __iomem *mmio_addr;
572 int drv_flags;
573 struct pci_dev *pci_dev;
574 u32 msg_enable;
575 struct napi_struct napi;
576 struct net_device *dev;
577 struct net_device_stats stats;
578
579 unsigned char *rx_ring;
580 unsigned int cur_rx; /* RX buf index of next pkt */
581 dma_addr_t rx_ring_dma;
582
583 unsigned int tx_flag;
584 unsigned long cur_tx;
585 unsigned long dirty_tx;
586 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
587 unsigned char *tx_bufs; /* Tx bounce buffer region. */
588 dma_addr_t tx_bufs_dma;
589
590 signed char phys[4]; /* MII device addresses. */
591
592 /* Twister tune state. */
593 char twistie, twist_row, twist_col;
594
595 unsigned int watchdog_fired : 1;
596 unsigned int default_port : 4; /* Last dev->if_port value. */
597 unsigned int have_thread : 1;
598
599 spinlock_t lock;
600 spinlock_t rx_lock;
601
602 chip_t chipset;
603 u32 rx_config;
604 struct rtl_extra_stats xstats;
605
606 struct delayed_work thread;
607
608 struct mii_if_info mii;
609 unsigned int regs_len;
610 unsigned long fifo_copy_timeout;
611 };
612
613 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
614 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
615 MODULE_LICENSE("GPL");
616 MODULE_VERSION(DRV_VERSION);
617
618 module_param(multicast_filter_limit, int, 0);
619 module_param_array(media, int, NULL, 0);
620 module_param_array(full_duplex, int, NULL, 0);
621 module_param(debug, int, 0);
622 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
623 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
624 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
625 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
626
627 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
628 static int rtl8139_open (struct net_device *dev);
629 static int mdio_read (struct net_device *dev, int phy_id, int location);
630 static void mdio_write (struct net_device *dev, int phy_id, int location,
631 int val);
632 static void rtl8139_start_thread(struct rtl8139_private *tp);
633 static void rtl8139_tx_timeout (struct net_device *dev);
634 static void rtl8139_init_ring (struct net_device *dev);
635 static int rtl8139_start_xmit (struct sk_buff *skb,
636 struct net_device *dev);
637 #ifdef CONFIG_NET_POLL_CONTROLLER
638 static void rtl8139_poll_controller(struct net_device *dev);
639 #endif
640 static int rtl8139_poll(struct napi_struct *napi, int budget);
641 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
642 static int rtl8139_close (struct net_device *dev);
643 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
644 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
645 static void rtl8139_set_rx_mode (struct net_device *dev);
646 static void __set_rx_mode (struct net_device *dev);
647 static void rtl8139_hw_start (struct net_device *dev);
648 static void rtl8139_thread (struct work_struct *work);
649 static void rtl8139_tx_timeout_task(struct work_struct *work);
650 static const struct ethtool_ops rtl8139_ethtool_ops;
651
652 /* write MMIO register, with flush */
653 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
654 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
655 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
656 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
657
658 /* write MMIO register */
659 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
660 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
661 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
662
663 /* read MMIO register */
664 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
665 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
666 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
667
668
669 static const u16 rtl8139_intr_mask =
670 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
671 TxErr | TxOK | RxErr | RxOK;
672
673 static const u16 rtl8139_norx_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun |
675 TxErr | TxOK | RxErr ;
676
677 #if RX_BUF_IDX == 0
678 static const unsigned int rtl8139_rx_config =
679 RxCfgRcv8K | RxNoWrap |
680 (RX_FIFO_THRESH << RxCfgFIFOShift) |
681 (RX_DMA_BURST << RxCfgDMAShift);
682 #elif RX_BUF_IDX == 1
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv16K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 2
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv32K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 3
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv64K |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #else
698 #error "Invalid configuration for 8139_RXBUF_IDX"
699 #endif
700
701 static const unsigned int rtl8139_tx_config =
702 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
703
704 static void __rtl8139_cleanup_dev (struct net_device *dev)
705 {
706 struct rtl8139_private *tp = netdev_priv(dev);
707 struct pci_dev *pdev;
708
709 assert (dev != NULL);
710 assert (tp->pci_dev != NULL);
711 pdev = tp->pci_dev;
712
713 #ifdef USE_IO_OPS
714 if (tp->mmio_addr)
715 ioport_unmap (tp->mmio_addr);
716 #else
717 if (tp->mmio_addr)
718 pci_iounmap (pdev, tp->mmio_addr);
719 #endif /* USE_IO_OPS */
720
721 /* it's ok to call this even if we have no regions to free */
722 pci_release_regions (pdev);
723
724 free_netdev(dev);
725 pci_set_drvdata (pdev, NULL);
726 }
727
728
729 static void rtl8139_chip_reset (void __iomem *ioaddr)
730 {
731 int i;
732
733 /* Soft reset the chip. */
734 RTL_W8 (ChipCmd, CmdReset);
735
736 /* Check that the chip has finished the reset. */
737 for (i = 1000; i > 0; i--) {
738 barrier();
739 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
740 break;
741 udelay (10);
742 }
743 }
744
745
746 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
747 struct net_device **dev_out)
748 {
749 void __iomem *ioaddr;
750 struct net_device *dev;
751 struct rtl8139_private *tp;
752 u8 tmp8;
753 int rc, disable_dev_on_err = 0;
754 unsigned int i;
755 unsigned long pio_start, pio_end, pio_flags, pio_len;
756 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
757 u32 version;
758
759 assert (pdev != NULL);
760
761 *dev_out = NULL;
762
763 /* dev and priv zeroed in alloc_etherdev */
764 dev = alloc_etherdev (sizeof (*tp));
765 if (dev == NULL) {
766 dev_err(&pdev->dev, "Unable to alloc new net device\n");
767 return -ENOMEM;
768 }
769 SET_MODULE_OWNER(dev);
770 SET_NETDEV_DEV(dev, &pdev->dev);
771
772 tp = netdev_priv(dev);
773 tp->pci_dev = pdev;
774
775 /* enable device (incl. PCI PM wakeup and hotplug setup) */
776 rc = pci_enable_device (pdev);
777 if (rc)
778 goto err_out;
779
780 pio_start = pci_resource_start (pdev, 0);
781 pio_end = pci_resource_end (pdev, 0);
782 pio_flags = pci_resource_flags (pdev, 0);
783 pio_len = pci_resource_len (pdev, 0);
784
785 mmio_start = pci_resource_start (pdev, 1);
786 mmio_end = pci_resource_end (pdev, 1);
787 mmio_flags = pci_resource_flags (pdev, 1);
788 mmio_len = pci_resource_len (pdev, 1);
789
790 /* set this immediately, we need to know before
791 * we talk to the chip directly */
792 DPRINTK("PIO region size == 0x%02X\n", pio_len);
793 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
794
795 #ifdef USE_IO_OPS
796 /* make sure PCI base addr 0 is PIO */
797 if (!(pio_flags & IORESOURCE_IO)) {
798 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
799 rc = -ENODEV;
800 goto err_out;
801 }
802 /* check for weird/broken PCI region reporting */
803 if (pio_len < RTL_MIN_IO_SIZE) {
804 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
805 rc = -ENODEV;
806 goto err_out;
807 }
808 #else
809 /* make sure PCI base addr 1 is MMIO */
810 if (!(mmio_flags & IORESOURCE_MEM)) {
811 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
812 rc = -ENODEV;
813 goto err_out;
814 }
815 if (mmio_len < RTL_MIN_IO_SIZE) {
816 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
817 rc = -ENODEV;
818 goto err_out;
819 }
820 #endif
821
822 rc = pci_request_regions (pdev, DRV_NAME);
823 if (rc)
824 goto err_out;
825 disable_dev_on_err = 1;
826
827 /* enable PCI bus-mastering */
828 pci_set_master (pdev);
829
830 #ifdef USE_IO_OPS
831 ioaddr = ioport_map(pio_start, pio_len);
832 if (!ioaddr) {
833 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
834 rc = -EIO;
835 goto err_out;
836 }
837 dev->base_addr = pio_start;
838 tp->mmio_addr = ioaddr;
839 tp->regs_len = pio_len;
840 #else
841 /* ioremap MMIO region */
842 ioaddr = pci_iomap(pdev, 1, 0);
843 if (ioaddr == NULL) {
844 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
845 rc = -EIO;
846 goto err_out;
847 }
848 dev->base_addr = (long) ioaddr;
849 tp->mmio_addr = ioaddr;
850 tp->regs_len = mmio_len;
851 #endif /* USE_IO_OPS */
852
853 /* Bring old chips out of low-power mode. */
854 RTL_W8 (HltClk, 'R');
855
856 /* check for missing/broken hardware */
857 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
858 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
859 rc = -EIO;
860 goto err_out;
861 }
862
863 /* identify chip attached to board */
864 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
865 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
866 if (version == rtl_chip_info[i].version) {
867 tp->chipset = i;
868 goto match;
869 }
870
871 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
872 dev_printk (KERN_DEBUG, &pdev->dev,
873 "unknown chip version, assuming RTL-8139\n");
874 dev_printk (KERN_DEBUG, &pdev->dev,
875 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
876 tp->chipset = 0;
877
878 match:
879 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
880 version, i, rtl_chip_info[i].name);
881
882 if (tp->chipset >= CH_8139B) {
883 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
884 DPRINTK("PCI PM wakeup\n");
885 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
886 (tmp8 & LWAKE))
887 new_tmp8 &= ~LWAKE;
888 new_tmp8 |= Cfg1_PM_Enable;
889 if (new_tmp8 != tmp8) {
890 RTL_W8 (Cfg9346, Cfg9346_Unlock);
891 RTL_W8 (Config1, tmp8);
892 RTL_W8 (Cfg9346, Cfg9346_Lock);
893 }
894 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
895 tmp8 = RTL_R8 (Config4);
896 if (tmp8 & LWPTN) {
897 RTL_W8 (Cfg9346, Cfg9346_Unlock);
898 RTL_W8 (Config4, tmp8 & ~LWPTN);
899 RTL_W8 (Cfg9346, Cfg9346_Lock);
900 }
901 }
902 } else {
903 DPRINTK("Old chip wakeup\n");
904 tmp8 = RTL_R8 (Config1);
905 tmp8 &= ~(SLEEP | PWRDN);
906 RTL_W8 (Config1, tmp8);
907 }
908
909 rtl8139_chip_reset (ioaddr);
910
911 *dev_out = dev;
912 return 0;
913
914 err_out:
915 __rtl8139_cleanup_dev (dev);
916 if (disable_dev_on_err)
917 pci_disable_device (pdev);
918 return rc;
919 }
920
921
922 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
923 const struct pci_device_id *ent)
924 {
925 struct net_device *dev = NULL;
926 struct rtl8139_private *tp;
927 int i, addr_len, option;
928 void __iomem *ioaddr;
929 static int board_idx = -1;
930
931 assert (pdev != NULL);
932 assert (ent != NULL);
933
934 board_idx++;
935
936 /* when we're built into the kernel, the driver version message
937 * is only printed if at least one 8139 board has been found
938 */
939 #ifndef MODULE
940 {
941 static int printed_version;
942 if (!printed_version++)
943 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
944 }
945 #endif
946
947 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
948 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
949 dev_info(&pdev->dev,
950 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
951 pdev->vendor, pdev->device, pdev->revision);
952 dev_info(&pdev->dev,
953 "Use the \"8139cp\" driver for improved performance and stability.\n");
954 }
955
956 i = rtl8139_init_board (pdev, &dev);
957 if (i < 0)
958 return i;
959
960 assert (dev != NULL);
961 tp = netdev_priv(dev);
962 tp->dev = dev;
963
964 ioaddr = tp->mmio_addr;
965 assert (ioaddr != NULL);
966
967 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
968 for (i = 0; i < 3; i++)
969 ((u16 *) (dev->dev_addr))[i] =
970 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
971 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
972
973 /* The Rtl8139-specific entries in the device structure. */
974 dev->open = rtl8139_open;
975 dev->hard_start_xmit = rtl8139_start_xmit;
976 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
977 dev->stop = rtl8139_close;
978 dev->get_stats = rtl8139_get_stats;
979 dev->set_multicast_list = rtl8139_set_rx_mode;
980 dev->do_ioctl = netdev_ioctl;
981 dev->ethtool_ops = &rtl8139_ethtool_ops;
982 dev->tx_timeout = rtl8139_tx_timeout;
983 dev->watchdog_timeo = TX_TIMEOUT;
984 #ifdef CONFIG_NET_POLL_CONTROLLER
985 dev->poll_controller = rtl8139_poll_controller;
986 #endif
987
988 /* note: the hardware is not capable of sg/csum/highdma, however
989 * through the use of skb_copy_and_csum_dev we enable these
990 * features
991 */
992 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
993
994 dev->irq = pdev->irq;
995
996 /* tp zeroed and aligned in alloc_etherdev */
997 tp = netdev_priv(dev);
998
999 /* note: tp->chipset set in rtl8139_init_board */
1000 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1001 tp->mmio_addr = ioaddr;
1002 tp->msg_enable =
1003 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1004 spin_lock_init (&tp->lock);
1005 spin_lock_init (&tp->rx_lock);
1006 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1007 tp->mii.dev = dev;
1008 tp->mii.mdio_read = mdio_read;
1009 tp->mii.mdio_write = mdio_write;
1010 tp->mii.phy_id_mask = 0x3f;
1011 tp->mii.reg_num_mask = 0x1f;
1012
1013 /* dev is fully set up and ready to use now */
1014 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1015 i = register_netdev (dev);
1016 if (i) goto err_out;
1017
1018 pci_set_drvdata (pdev, dev);
1019
1020 printk (KERN_INFO "%s: %s at 0x%lx, "
1021 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1022 "IRQ %d\n",
1023 dev->name,
1024 board_info[ent->driver_data].name,
1025 dev->base_addr,
1026 dev->dev_addr[0], dev->dev_addr[1],
1027 dev->dev_addr[2], dev->dev_addr[3],
1028 dev->dev_addr[4], dev->dev_addr[5],
1029 dev->irq);
1030
1031 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1032 dev->name, rtl_chip_info[tp->chipset].name);
1033
1034 /* Find the connected MII xcvrs.
1035 Doing this in open() would allow detecting external xcvrs later, but
1036 takes too much time. */
1037 #ifdef CONFIG_8139TOO_8129
1038 if (tp->drv_flags & HAS_MII_XCVR) {
1039 int phy, phy_idx = 0;
1040 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1041 int mii_status = mdio_read(dev, phy, 1);
1042 if (mii_status != 0xffff && mii_status != 0x0000) {
1043 u16 advertising = mdio_read(dev, phy, 4);
1044 tp->phys[phy_idx++] = phy;
1045 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1046 "advertising %4.4x.\n",
1047 dev->name, phy, mii_status, advertising);
1048 }
1049 }
1050 if (phy_idx == 0) {
1051 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1052 "transceiver.\n",
1053 dev->name);
1054 tp->phys[0] = 32;
1055 }
1056 } else
1057 #endif
1058 tp->phys[0] = 32;
1059 tp->mii.phy_id = tp->phys[0];
1060
1061 /* The lower four bits are the media type. */
1062 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1063 if (option > 0) {
1064 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1065 tp->default_port = option & 0xFF;
1066 if (tp->default_port)
1067 tp->mii.force_media = 1;
1068 }
1069 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1070 tp->mii.full_duplex = full_duplex[board_idx];
1071 if (tp->mii.full_duplex) {
1072 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1073 /* Changing the MII-advertised media because might prevent
1074 re-connection. */
1075 tp->mii.force_media = 1;
1076 }
1077 if (tp->default_port) {
1078 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1079 (option & 0x20 ? 100 : 10),
1080 (option & 0x10 ? "full" : "half"));
1081 mdio_write(dev, tp->phys[0], 0,
1082 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1083 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1084 }
1085
1086 /* Put the chip into low-power mode. */
1087 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1088 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1089
1090 return 0;
1091
1092 err_out:
1093 __rtl8139_cleanup_dev (dev);
1094 pci_disable_device (pdev);
1095 return i;
1096 }
1097
1098
1099 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1100 {
1101 struct net_device *dev = pci_get_drvdata (pdev);
1102
1103 assert (dev != NULL);
1104
1105 flush_scheduled_work();
1106
1107 unregister_netdev (dev);
1108
1109 __rtl8139_cleanup_dev (dev);
1110 pci_disable_device (pdev);
1111 }
1112
1113
1114 /* Serial EEPROM section. */
1115
1116 /* EEPROM_Ctrl bits. */
1117 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1118 #define EE_CS 0x08 /* EEPROM chip select. */
1119 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1120 #define EE_WRITE_0 0x00
1121 #define EE_WRITE_1 0x02
1122 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1123 #define EE_ENB (0x80 | EE_CS)
1124
1125 /* Delay between EEPROM clock transitions.
1126 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1127 */
1128
1129 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1130
1131 /* The EEPROM commands include the alway-set leading bit. */
1132 #define EE_WRITE_CMD (5)
1133 #define EE_READ_CMD (6)
1134 #define EE_ERASE_CMD (7)
1135
1136 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1137 {
1138 int i;
1139 unsigned retval = 0;
1140 int read_cmd = location | (EE_READ_CMD << addr_len);
1141
1142 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1143 RTL_W8 (Cfg9346, EE_ENB);
1144 eeprom_delay ();
1145
1146 /* Shift the read command bits out. */
1147 for (i = 4 + addr_len; i >= 0; i--) {
1148 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1149 RTL_W8 (Cfg9346, EE_ENB | dataval);
1150 eeprom_delay ();
1151 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1152 eeprom_delay ();
1153 }
1154 RTL_W8 (Cfg9346, EE_ENB);
1155 eeprom_delay ();
1156
1157 for (i = 16; i > 0; i--) {
1158 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1159 eeprom_delay ();
1160 retval =
1161 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1162 0);
1163 RTL_W8 (Cfg9346, EE_ENB);
1164 eeprom_delay ();
1165 }
1166
1167 /* Terminate the EEPROM access. */
1168 RTL_W8 (Cfg9346, ~EE_CS);
1169 eeprom_delay ();
1170
1171 return retval;
1172 }
1173
1174 /* MII serial management: mostly bogus for now. */
1175 /* Read and write the MII management registers using software-generated
1176 serial MDIO protocol.
1177 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1178 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1179 "overclocking" issues. */
1180 #define MDIO_DIR 0x80
1181 #define MDIO_DATA_OUT 0x04
1182 #define MDIO_DATA_IN 0x02
1183 #define MDIO_CLK 0x01
1184 #define MDIO_WRITE0 (MDIO_DIR)
1185 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1186
1187 #define mdio_delay() RTL_R8(Config4)
1188
1189
1190 static const char mii_2_8139_map[8] = {
1191 BasicModeCtrl,
1192 BasicModeStatus,
1193 0,
1194 0,
1195 NWayAdvert,
1196 NWayLPAR,
1197 NWayExpansion,
1198 0
1199 };
1200
1201
1202 #ifdef CONFIG_8139TOO_8129
1203 /* Syncronize the MII management interface by shifting 32 one bits out. */
1204 static void mdio_sync (void __iomem *ioaddr)
1205 {
1206 int i;
1207
1208 for (i = 32; i >= 0; i--) {
1209 RTL_W8 (Config4, MDIO_WRITE1);
1210 mdio_delay ();
1211 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1212 mdio_delay ();
1213 }
1214 }
1215 #endif
1216
1217 static int mdio_read (struct net_device *dev, int phy_id, int location)
1218 {
1219 struct rtl8139_private *tp = netdev_priv(dev);
1220 int retval = 0;
1221 #ifdef CONFIG_8139TOO_8129
1222 void __iomem *ioaddr = tp->mmio_addr;
1223 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1224 int i;
1225 #endif
1226
1227 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 return location < 8 && mii_2_8139_map[location] ?
1230 RTL_R16 (mii_2_8139_map[location]) : 0;
1231 }
1232
1233 #ifdef CONFIG_8139TOO_8129
1234 mdio_sync (ioaddr);
1235 /* Shift the read command bits out. */
1236 for (i = 15; i >= 0; i--) {
1237 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1238
1239 RTL_W8 (Config4, MDIO_DIR | dataval);
1240 mdio_delay ();
1241 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1242 mdio_delay ();
1243 }
1244
1245 /* Read the two transition, 16 data, and wire-idle bits. */
1246 for (i = 19; i > 0; i--) {
1247 RTL_W8 (Config4, 0);
1248 mdio_delay ();
1249 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1250 RTL_W8 (Config4, MDIO_CLK);
1251 mdio_delay ();
1252 }
1253 #endif
1254
1255 return (retval >> 1) & 0xffff;
1256 }
1257
1258
1259 static void mdio_write (struct net_device *dev, int phy_id, int location,
1260 int value)
1261 {
1262 struct rtl8139_private *tp = netdev_priv(dev);
1263 #ifdef CONFIG_8139TOO_8129
1264 void __iomem *ioaddr = tp->mmio_addr;
1265 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1266 int i;
1267 #endif
1268
1269 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 if (location == 0) {
1272 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1273 RTL_W16 (BasicModeCtrl, value);
1274 RTL_W8 (Cfg9346, Cfg9346_Lock);
1275 } else if (location < 8 && mii_2_8139_map[location])
1276 RTL_W16 (mii_2_8139_map[location], value);
1277 return;
1278 }
1279
1280 #ifdef CONFIG_8139TOO_8129
1281 mdio_sync (ioaddr);
1282
1283 /* Shift the command bits out. */
1284 for (i = 31; i >= 0; i--) {
1285 int dataval =
1286 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1287 RTL_W8 (Config4, dataval);
1288 mdio_delay ();
1289 RTL_W8 (Config4, dataval | MDIO_CLK);
1290 mdio_delay ();
1291 }
1292 /* Clear out extra bits. */
1293 for (i = 2; i > 0; i--) {
1294 RTL_W8 (Config4, 0);
1295 mdio_delay ();
1296 RTL_W8 (Config4, MDIO_CLK);
1297 mdio_delay ();
1298 }
1299 #endif
1300 }
1301
1302
1303 static int rtl8139_open (struct net_device *dev)
1304 {
1305 struct rtl8139_private *tp = netdev_priv(dev);
1306 int retval;
1307 void __iomem *ioaddr = tp->mmio_addr;
1308
1309 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1310 if (retval)
1311 return retval;
1312
1313 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1314 &tp->tx_bufs_dma, GFP_KERNEL);
1315 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1316 &tp->rx_ring_dma, GFP_KERNEL);
1317 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1318 free_irq(dev->irq, dev);
1319
1320 if (tp->tx_bufs)
1321 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1322 tp->tx_bufs, tp->tx_bufs_dma);
1323 if (tp->rx_ring)
1324 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1325 tp->rx_ring, tp->rx_ring_dma);
1326
1327 return -ENOMEM;
1328
1329 }
1330
1331 napi_enable(&tp->napi);
1332
1333 tp->mii.full_duplex = tp->mii.force_media;
1334 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1335
1336 rtl8139_init_ring (dev);
1337 rtl8139_hw_start (dev);
1338 netif_start_queue (dev);
1339
1340 if (netif_msg_ifup(tp))
1341 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1342 " GP Pins %2.2x %s-duplex.\n", dev->name,
1343 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1344 dev->irq, RTL_R8 (MediaStatus),
1345 tp->mii.full_duplex ? "full" : "half");
1346
1347 rtl8139_start_thread(tp);
1348
1349 return 0;
1350 }
1351
1352
1353 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1354 {
1355 struct rtl8139_private *tp = netdev_priv(dev);
1356
1357 if (tp->phys[0] >= 0) {
1358 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1359 }
1360 }
1361
1362 /* Start the hardware at open or resume. */
1363 static void rtl8139_hw_start (struct net_device *dev)
1364 {
1365 struct rtl8139_private *tp = netdev_priv(dev);
1366 void __iomem *ioaddr = tp->mmio_addr;
1367 u32 i;
1368 u8 tmp;
1369
1370 /* Bring old chips out of low-power mode. */
1371 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1372 RTL_W8 (HltClk, 'R');
1373
1374 rtl8139_chip_reset (ioaddr);
1375
1376 /* unlock Config[01234] and BMCR register writes */
1377 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1378 /* Restore our idea of the MAC address. */
1379 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1380 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1381
1382 /* Must enable Tx/Rx before setting transfer thresholds! */
1383 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1384
1385 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1386 RTL_W32 (RxConfig, tp->rx_config);
1387 RTL_W32 (TxConfig, rtl8139_tx_config);
1388
1389 tp->cur_rx = 0;
1390
1391 rtl_check_media (dev, 1);
1392
1393 if (tp->chipset >= CH_8139B) {
1394 /* Disable magic packet scanning, which is enabled
1395 * when PM is enabled in Config1. It can be reenabled
1396 * via ETHTOOL_SWOL if desired. */
1397 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1398 }
1399
1400 DPRINTK("init buffer addresses\n");
1401
1402 /* Lock Config[01234] and BMCR register writes */
1403 RTL_W8 (Cfg9346, Cfg9346_Lock);
1404
1405 /* init Rx ring buffer DMA address */
1406 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1407
1408 /* init Tx buffer DMA addresses */
1409 for (i = 0; i < NUM_TX_DESC; i++)
1410 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1411
1412 RTL_W32 (RxMissed, 0);
1413
1414 rtl8139_set_rx_mode (dev);
1415
1416 /* no early-rx interrupts */
1417 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1418
1419 /* make sure RxTx has started */
1420 tmp = RTL_R8 (ChipCmd);
1421 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1422 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1423
1424 /* Enable all known interrupts by setting the interrupt mask. */
1425 RTL_W16 (IntrMask, rtl8139_intr_mask);
1426 }
1427
1428
1429 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1430 static void rtl8139_init_ring (struct net_device *dev)
1431 {
1432 struct rtl8139_private *tp = netdev_priv(dev);
1433 int i;
1434
1435 tp->cur_rx = 0;
1436 tp->cur_tx = 0;
1437 tp->dirty_tx = 0;
1438
1439 for (i = 0; i < NUM_TX_DESC; i++)
1440 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1441 }
1442
1443
1444 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1445 static int next_tick = 3 * HZ;
1446
1447 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1448 static inline void rtl8139_tune_twister (struct net_device *dev,
1449 struct rtl8139_private *tp) {}
1450 #else
1451 enum TwisterParamVals {
1452 PARA78_default = 0x78fa8388,
1453 PARA7c_default = 0xcb38de43, /* param[0][3] */
1454 PARA7c_xxx = 0xcb38de43,
1455 };
1456
1457 static const unsigned long param[4][4] = {
1458 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1459 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1460 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1461 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1462 };
1463
1464 static void rtl8139_tune_twister (struct net_device *dev,
1465 struct rtl8139_private *tp)
1466 {
1467 int linkcase;
1468 void __iomem *ioaddr = tp->mmio_addr;
1469
1470 /* This is a complicated state machine to configure the "twister" for
1471 impedance/echos based on the cable length.
1472 All of this is magic and undocumented.
1473 */
1474 switch (tp->twistie) {
1475 case 1:
1476 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1477 /* We have link beat, let us tune the twister. */
1478 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1479 tp->twistie = 2; /* Change to state 2. */
1480 next_tick = HZ / 10;
1481 } else {
1482 /* Just put in some reasonable defaults for when beat returns. */
1483 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1484 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1485 RTL_W32 (PARA78, PARA78_default);
1486 RTL_W32 (PARA7c, PARA7c_default);
1487 tp->twistie = 0; /* Bail from future actions. */
1488 }
1489 break;
1490 case 2:
1491 /* Read how long it took to hear the echo. */
1492 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1493 if (linkcase == 0x7000)
1494 tp->twist_row = 3;
1495 else if (linkcase == 0x3000)
1496 tp->twist_row = 2;
1497 else if (linkcase == 0x1000)
1498 tp->twist_row = 1;
1499 else
1500 tp->twist_row = 0;
1501 tp->twist_col = 0;
1502 tp->twistie = 3; /* Change to state 2. */
1503 next_tick = HZ / 10;
1504 break;
1505 case 3:
1506 /* Put out four tuning parameters, one per 100msec. */
1507 if (tp->twist_col == 0)
1508 RTL_W16 (FIFOTMS, 0);
1509 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1510 [(int) tp->twist_col]);
1511 next_tick = HZ / 10;
1512 if (++tp->twist_col >= 4) {
1513 /* For short cables we are done.
1514 For long cables (row == 3) check for mistune. */
1515 tp->twistie =
1516 (tp->twist_row == 3) ? 4 : 0;
1517 }
1518 break;
1519 case 4:
1520 /* Special case for long cables: check for mistune. */
1521 if ((RTL_R16 (CSCR) &
1522 CSCR_LinkStatusBits) == 0x7000) {
1523 tp->twistie = 0;
1524 break;
1525 } else {
1526 RTL_W32 (PARA7c, 0xfb38de03);
1527 tp->twistie = 5;
1528 next_tick = HZ / 10;
1529 }
1530 break;
1531 case 5:
1532 /* Retune for shorter cable (column 2). */
1533 RTL_W32 (FIFOTMS, 0x20);
1534 RTL_W32 (PARA78, PARA78_default);
1535 RTL_W32 (PARA7c, PARA7c_default);
1536 RTL_W32 (FIFOTMS, 0x00);
1537 tp->twist_row = 2;
1538 tp->twist_col = 0;
1539 tp->twistie = 3;
1540 next_tick = HZ / 10;
1541 break;
1542
1543 default:
1544 /* do nothing */
1545 break;
1546 }
1547 }
1548 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1549
1550 static inline void rtl8139_thread_iter (struct net_device *dev,
1551 struct rtl8139_private *tp,
1552 void __iomem *ioaddr)
1553 {
1554 int mii_lpa;
1555
1556 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1557
1558 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1559 int duplex = (mii_lpa & LPA_100FULL)
1560 || (mii_lpa & 0x01C0) == 0x0040;
1561 if (tp->mii.full_duplex != duplex) {
1562 tp->mii.full_duplex = duplex;
1563
1564 if (mii_lpa) {
1565 printk (KERN_INFO
1566 "%s: Setting %s-duplex based on MII #%d link"
1567 " partner ability of %4.4x.\n",
1568 dev->name,
1569 tp->mii.full_duplex ? "full" : "half",
1570 tp->phys[0], mii_lpa);
1571 } else {
1572 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1573 dev->name);
1574 }
1575 #if 0
1576 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1577 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1578 RTL_W8 (Cfg9346, Cfg9346_Lock);
1579 #endif
1580 }
1581 }
1582
1583 next_tick = HZ * 60;
1584
1585 rtl8139_tune_twister (dev, tp);
1586
1587 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1588 dev->name, RTL_R16 (NWayLPAR));
1589 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1590 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1591 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1592 dev->name, RTL_R8 (Config0),
1593 RTL_R8 (Config1));
1594 }
1595
1596 static void rtl8139_thread (struct work_struct *work)
1597 {
1598 struct rtl8139_private *tp =
1599 container_of(work, struct rtl8139_private, thread.work);
1600 struct net_device *dev = tp->mii.dev;
1601 unsigned long thr_delay = next_tick;
1602
1603 rtnl_lock();
1604
1605 if (!netif_running(dev))
1606 goto out_unlock;
1607
1608 if (tp->watchdog_fired) {
1609 tp->watchdog_fired = 0;
1610 rtl8139_tx_timeout_task(work);
1611 } else
1612 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1613
1614 if (tp->have_thread)
1615 schedule_delayed_work(&tp->thread, thr_delay);
1616 out_unlock:
1617 rtnl_unlock ();
1618 }
1619
1620 static void rtl8139_start_thread(struct rtl8139_private *tp)
1621 {
1622 tp->twistie = 0;
1623 if (tp->chipset == CH_8139_K)
1624 tp->twistie = 1;
1625 else if (tp->drv_flags & HAS_LNK_CHNG)
1626 return;
1627
1628 tp->have_thread = 1;
1629 tp->watchdog_fired = 0;
1630
1631 schedule_delayed_work(&tp->thread, next_tick);
1632 }
1633
1634 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1635 {
1636 tp->cur_tx = 0;
1637 tp->dirty_tx = 0;
1638
1639 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1640 }
1641
1642 static void rtl8139_tx_timeout_task (struct work_struct *work)
1643 {
1644 struct rtl8139_private *tp =
1645 container_of(work, struct rtl8139_private, thread.work);
1646 struct net_device *dev = tp->mii.dev;
1647 void __iomem *ioaddr = tp->mmio_addr;
1648 int i;
1649 u8 tmp8;
1650
1651 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1652 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1653 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1654 /* Emit info to figure out what went wrong. */
1655 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1656 dev->name, tp->cur_tx, tp->dirty_tx);
1657 for (i = 0; i < NUM_TX_DESC; i++)
1658 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1659 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1660 i == tp->dirty_tx % NUM_TX_DESC ?
1661 " (queue head)" : "");
1662
1663 tp->xstats.tx_timeouts++;
1664
1665 /* disable Tx ASAP, if not already */
1666 tmp8 = RTL_R8 (ChipCmd);
1667 if (tmp8 & CmdTxEnb)
1668 RTL_W8 (ChipCmd, CmdRxEnb);
1669
1670 spin_lock_bh(&tp->rx_lock);
1671 /* Disable interrupts by clearing the interrupt mask. */
1672 RTL_W16 (IntrMask, 0x0000);
1673
1674 /* Stop a shared interrupt from scavenging while we are. */
1675 spin_lock_irq(&tp->lock);
1676 rtl8139_tx_clear (tp);
1677 spin_unlock_irq(&tp->lock);
1678
1679 /* ...and finally, reset everything */
1680 if (netif_running(dev)) {
1681 rtl8139_hw_start (dev);
1682 netif_wake_queue (dev);
1683 }
1684 spin_unlock_bh(&tp->rx_lock);
1685 }
1686
1687 static void rtl8139_tx_timeout (struct net_device *dev)
1688 {
1689 struct rtl8139_private *tp = netdev_priv(dev);
1690
1691 tp->watchdog_fired = 1;
1692 if (!tp->have_thread) {
1693 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1694 schedule_delayed_work(&tp->thread, next_tick);
1695 }
1696 }
1697
1698 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1699 {
1700 struct rtl8139_private *tp = netdev_priv(dev);
1701 void __iomem *ioaddr = tp->mmio_addr;
1702 unsigned int entry;
1703 unsigned int len = skb->len;
1704 unsigned long flags;
1705
1706 /* Calculate the next Tx descriptor entry. */
1707 entry = tp->cur_tx % NUM_TX_DESC;
1708
1709 /* Note: the chip doesn't have auto-pad! */
1710 if (likely(len < TX_BUF_SIZE)) {
1711 if (len < ETH_ZLEN)
1712 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1713 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1714 dev_kfree_skb(skb);
1715 } else {
1716 dev_kfree_skb(skb);
1717 tp->stats.tx_dropped++;
1718 return 0;
1719 }
1720
1721 spin_lock_irqsave(&tp->lock, flags);
1722 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1723 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1724
1725 dev->trans_start = jiffies;
1726
1727 tp->cur_tx++;
1728 wmb();
1729
1730 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1731 netif_stop_queue (dev);
1732 spin_unlock_irqrestore(&tp->lock, flags);
1733
1734 if (netif_msg_tx_queued(tp))
1735 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1736 dev->name, len, entry);
1737
1738 return 0;
1739 }
1740
1741
1742 static void rtl8139_tx_interrupt (struct net_device *dev,
1743 struct rtl8139_private *tp,
1744 void __iomem *ioaddr)
1745 {
1746 unsigned long dirty_tx, tx_left;
1747
1748 assert (dev != NULL);
1749 assert (ioaddr != NULL);
1750
1751 dirty_tx = tp->dirty_tx;
1752 tx_left = tp->cur_tx - dirty_tx;
1753 while (tx_left > 0) {
1754 int entry = dirty_tx % NUM_TX_DESC;
1755 int txstatus;
1756
1757 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1758
1759 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1760 break; /* It still hasn't been Txed */
1761
1762 /* Note: TxCarrierLost is always asserted at 100mbps. */
1763 if (txstatus & (TxOutOfWindow | TxAborted)) {
1764 /* There was an major error, log it. */
1765 if (netif_msg_tx_err(tp))
1766 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1767 dev->name, txstatus);
1768 tp->stats.tx_errors++;
1769 if (txstatus & TxAborted) {
1770 tp->stats.tx_aborted_errors++;
1771 RTL_W32 (TxConfig, TxClearAbt);
1772 RTL_W16 (IntrStatus, TxErr);
1773 wmb();
1774 }
1775 if (txstatus & TxCarrierLost)
1776 tp->stats.tx_carrier_errors++;
1777 if (txstatus & TxOutOfWindow)
1778 tp->stats.tx_window_errors++;
1779 } else {
1780 if (txstatus & TxUnderrun) {
1781 /* Add 64 to the Tx FIFO threshold. */
1782 if (tp->tx_flag < 0x00300000)
1783 tp->tx_flag += 0x00020000;
1784 tp->stats.tx_fifo_errors++;
1785 }
1786 tp->stats.collisions += (txstatus >> 24) & 15;
1787 tp->stats.tx_bytes += txstatus & 0x7ff;
1788 tp->stats.tx_packets++;
1789 }
1790
1791 dirty_tx++;
1792 tx_left--;
1793 }
1794
1795 #ifndef RTL8139_NDEBUG
1796 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1797 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1798 dev->name, dirty_tx, tp->cur_tx);
1799 dirty_tx += NUM_TX_DESC;
1800 }
1801 #endif /* RTL8139_NDEBUG */
1802
1803 /* only wake the queue if we did work, and the queue is stopped */
1804 if (tp->dirty_tx != dirty_tx) {
1805 tp->dirty_tx = dirty_tx;
1806 mb();
1807 netif_wake_queue (dev);
1808 }
1809 }
1810
1811
1812 /* TODO: clean this up! Rx reset need not be this intensive */
1813 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1814 struct rtl8139_private *tp, void __iomem *ioaddr)
1815 {
1816 u8 tmp8;
1817 #ifdef CONFIG_8139_OLD_RX_RESET
1818 int tmp_work;
1819 #endif
1820
1821 if (netif_msg_rx_err (tp))
1822 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1823 dev->name, rx_status);
1824 tp->stats.rx_errors++;
1825 if (!(rx_status & RxStatusOK)) {
1826 if (rx_status & RxTooLong) {
1827 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1828 dev->name, rx_status);
1829 /* A.C.: The chip hangs here. */
1830 }
1831 if (rx_status & (RxBadSymbol | RxBadAlign))
1832 tp->stats.rx_frame_errors++;
1833 if (rx_status & (RxRunt | RxTooLong))
1834 tp->stats.rx_length_errors++;
1835 if (rx_status & RxCRCErr)
1836 tp->stats.rx_crc_errors++;
1837 } else {
1838 tp->xstats.rx_lost_in_ring++;
1839 }
1840
1841 #ifndef CONFIG_8139_OLD_RX_RESET
1842 tmp8 = RTL_R8 (ChipCmd);
1843 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1844 RTL_W8 (ChipCmd, tmp8);
1845 RTL_W32 (RxConfig, tp->rx_config);
1846 tp->cur_rx = 0;
1847 #else
1848 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1849
1850 /* disable receive */
1851 RTL_W8_F (ChipCmd, CmdTxEnb);
1852 tmp_work = 200;
1853 while (--tmp_work > 0) {
1854 udelay(1);
1855 tmp8 = RTL_R8 (ChipCmd);
1856 if (!(tmp8 & CmdRxEnb))
1857 break;
1858 }
1859 if (tmp_work <= 0)
1860 printk (KERN_WARNING PFX "rx stop wait too long\n");
1861 /* restart receive */
1862 tmp_work = 200;
1863 while (--tmp_work > 0) {
1864 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1865 udelay(1);
1866 tmp8 = RTL_R8 (ChipCmd);
1867 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1868 break;
1869 }
1870 if (tmp_work <= 0)
1871 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1872
1873 /* and reinitialize all rx related registers */
1874 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1875 /* Must enable Tx/Rx before setting transfer thresholds! */
1876 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1877
1878 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1879 RTL_W32 (RxConfig, tp->rx_config);
1880 tp->cur_rx = 0;
1881
1882 DPRINTK("init buffer addresses\n");
1883
1884 /* Lock Config[01234] and BMCR register writes */
1885 RTL_W8 (Cfg9346, Cfg9346_Lock);
1886
1887 /* init Rx ring buffer DMA address */
1888 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1889
1890 /* A.C.: Reset the multicast list. */
1891 __set_rx_mode (dev);
1892 #endif
1893 }
1894
1895 #if RX_BUF_IDX == 3
1896 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1897 u32 offset, unsigned int size)
1898 {
1899 u32 left = RX_BUF_LEN - offset;
1900
1901 if (size > left) {
1902 skb_copy_to_linear_data(skb, ring + offset, left);
1903 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1904 } else
1905 skb_copy_to_linear_data(skb, ring + offset, size);
1906 }
1907 #endif
1908
1909 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1910 {
1911 void __iomem *ioaddr = tp->mmio_addr;
1912 u16 status;
1913
1914 status = RTL_R16 (IntrStatus) & RxAckBits;
1915
1916 /* Clear out errors and receive interrupts */
1917 if (likely(status != 0)) {
1918 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1919 tp->stats.rx_errors++;
1920 if (status & RxFIFOOver)
1921 tp->stats.rx_fifo_errors++;
1922 }
1923 RTL_W16_F (IntrStatus, RxAckBits);
1924 }
1925 }
1926
1927 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1928 int budget)
1929 {
1930 void __iomem *ioaddr = tp->mmio_addr;
1931 int received = 0;
1932 unsigned char *rx_ring = tp->rx_ring;
1933 unsigned int cur_rx = tp->cur_rx;
1934 unsigned int rx_size = 0;
1935
1936 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1937 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1938 RTL_R16 (RxBufAddr),
1939 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1940
1941 while (netif_running(dev) && received < budget
1942 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1943 u32 ring_offset = cur_rx % RX_BUF_LEN;
1944 u32 rx_status;
1945 unsigned int pkt_size;
1946 struct sk_buff *skb;
1947
1948 rmb();
1949
1950 /* read size+status of next frame from DMA ring buffer */
1951 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1952 rx_size = rx_status >> 16;
1953 pkt_size = rx_size - 4;
1954
1955 if (netif_msg_rx_status(tp))
1956 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1957 " cur %4.4x.\n", dev->name, rx_status,
1958 rx_size, cur_rx);
1959 #if RTL8139_DEBUG > 2
1960 {
1961 int i;
1962 DPRINTK ("%s: Frame contents ", dev->name);
1963 for (i = 0; i < 70; i++)
1964 printk (" %2.2x",
1965 rx_ring[ring_offset + i]);
1966 printk (".\n");
1967 }
1968 #endif
1969
1970 /* Packet copy from FIFO still in progress.
1971 * Theoretically, this should never happen
1972 * since EarlyRx is disabled.
1973 */
1974 if (unlikely(rx_size == 0xfff0)) {
1975 if (!tp->fifo_copy_timeout)
1976 tp->fifo_copy_timeout = jiffies + 2;
1977 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1978 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1979 rx_size = 0;
1980 goto no_early_rx;
1981 }
1982 if (netif_msg_intr(tp)) {
1983 printk(KERN_DEBUG "%s: fifo copy in progress.",
1984 dev->name);
1985 }
1986 tp->xstats.early_rx++;
1987 break;
1988 }
1989
1990 no_early_rx:
1991 tp->fifo_copy_timeout = 0;
1992
1993 /* If Rx err or invalid rx_size/rx_status received
1994 * (which happens if we get lost in the ring),
1995 * Rx process gets reset, so we abort any further
1996 * Rx processing.
1997 */
1998 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1999 (rx_size < 8) ||
2000 (!(rx_status & RxStatusOK)))) {
2001 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2002 received = -1;
2003 goto out;
2004 }
2005
2006 /* Malloc up new buffer, compatible with net-2e. */
2007 /* Omit the four octet CRC from the length. */
2008
2009 skb = dev_alloc_skb (pkt_size + 2);
2010 if (likely(skb)) {
2011 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2012 #if RX_BUF_IDX == 3
2013 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2014 #else
2015 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2016 #endif
2017 skb_put (skb, pkt_size);
2018
2019 skb->protocol = eth_type_trans (skb, dev);
2020
2021 dev->last_rx = jiffies;
2022 tp->stats.rx_bytes += pkt_size;
2023 tp->stats.rx_packets++;
2024
2025 netif_receive_skb (skb);
2026 } else {
2027 if (net_ratelimit())
2028 printk (KERN_WARNING
2029 "%s: Memory squeeze, dropping packet.\n",
2030 dev->name);
2031 tp->stats.rx_dropped++;
2032 }
2033 received++;
2034
2035 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2036 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2037
2038 rtl8139_isr_ack(tp);
2039 }
2040
2041 if (unlikely(!received || rx_size == 0xfff0))
2042 rtl8139_isr_ack(tp);
2043
2044 #if RTL8139_DEBUG > 1
2045 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2046 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2047 RTL_R16 (RxBufAddr),
2048 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2049 #endif
2050
2051 tp->cur_rx = cur_rx;
2052
2053 /*
2054 * The receive buffer should be mostly empty.
2055 * Tell NAPI to reenable the Rx irq.
2056 */
2057 if (tp->fifo_copy_timeout)
2058 received = budget;
2059
2060 out:
2061 return received;
2062 }
2063
2064
2065 static void rtl8139_weird_interrupt (struct net_device *dev,
2066 struct rtl8139_private *tp,
2067 void __iomem *ioaddr,
2068 int status, int link_changed)
2069 {
2070 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2071 dev->name, status);
2072
2073 assert (dev != NULL);
2074 assert (tp != NULL);
2075 assert (ioaddr != NULL);
2076
2077 /* Update the error count. */
2078 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2079 RTL_W32 (RxMissed, 0);
2080
2081 if ((status & RxUnderrun) && link_changed &&
2082 (tp->drv_flags & HAS_LNK_CHNG)) {
2083 rtl_check_media(dev, 0);
2084 status &= ~RxUnderrun;
2085 }
2086
2087 if (status & (RxUnderrun | RxErr))
2088 tp->stats.rx_errors++;
2089
2090 if (status & PCSTimeout)
2091 tp->stats.rx_length_errors++;
2092 if (status & RxUnderrun)
2093 tp->stats.rx_fifo_errors++;
2094 if (status & PCIErr) {
2095 u16 pci_cmd_status;
2096 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2097 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2098
2099 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2100 dev->name, pci_cmd_status);
2101 }
2102 }
2103
2104 static int rtl8139_poll(struct napi_struct *napi, int budget)
2105 {
2106 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2107 struct net_device *dev = tp->dev;
2108 void __iomem *ioaddr = tp->mmio_addr;
2109 int work_done;
2110
2111 spin_lock(&tp->rx_lock);
2112 work_done = 0;
2113 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2114 work_done += rtl8139_rx(dev, tp, budget);
2115
2116 if (work_done < budget) {
2117 unsigned long flags;
2118 /*
2119 * Order is important since data can get interrupted
2120 * again when we think we are done.
2121 */
2122 spin_lock_irqsave(&tp->lock, flags);
2123 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2124 __netif_rx_complete(dev, napi);
2125 spin_unlock_irqrestore(&tp->lock, flags);
2126 }
2127 spin_unlock(&tp->rx_lock);
2128
2129 return work_done;
2130 }
2131
2132 /* The interrupt handler does all of the Rx thread work and cleans up
2133 after the Tx thread. */
2134 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2135 {
2136 struct net_device *dev = (struct net_device *) dev_instance;
2137 struct rtl8139_private *tp = netdev_priv(dev);
2138 void __iomem *ioaddr = tp->mmio_addr;
2139 u16 status, ackstat;
2140 int link_changed = 0; /* avoid bogus "uninit" warning */
2141 int handled = 0;
2142
2143 spin_lock (&tp->lock);
2144 status = RTL_R16 (IntrStatus);
2145
2146 /* shared irq? */
2147 if (unlikely((status & rtl8139_intr_mask) == 0))
2148 goto out;
2149
2150 handled = 1;
2151
2152 /* h/w no longer present (hotplug?) or major error, bail */
2153 if (unlikely(status == 0xFFFF))
2154 goto out;
2155
2156 /* close possible race's with dev_close */
2157 if (unlikely(!netif_running(dev))) {
2158 RTL_W16 (IntrMask, 0);
2159 goto out;
2160 }
2161
2162 /* Acknowledge all of the current interrupt sources ASAP, but
2163 an first get an additional status bit from CSCR. */
2164 if (unlikely(status & RxUnderrun))
2165 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2166
2167 ackstat = status & ~(RxAckBits | TxErr);
2168 if (ackstat)
2169 RTL_W16 (IntrStatus, ackstat);
2170
2171 /* Receive packets are processed by poll routine.
2172 If not running start it now. */
2173 if (status & RxAckBits){
2174 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2175 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2176 __netif_rx_schedule(dev, &tp->napi);
2177 }
2178 }
2179
2180 /* Check uncommon events with one test. */
2181 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2182 rtl8139_weird_interrupt (dev, tp, ioaddr,
2183 status, link_changed);
2184
2185 if (status & (TxOK | TxErr)) {
2186 rtl8139_tx_interrupt (dev, tp, ioaddr);
2187 if (status & TxErr)
2188 RTL_W16 (IntrStatus, TxErr);
2189 }
2190 out:
2191 spin_unlock (&tp->lock);
2192
2193 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2194 dev->name, RTL_R16 (IntrStatus));
2195 return IRQ_RETVAL(handled);
2196 }
2197
2198 #ifdef CONFIG_NET_POLL_CONTROLLER
2199 /*
2200 * Polling receive - used by netconsole and other diagnostic tools
2201 * to allow network i/o with interrupts disabled.
2202 */
2203 static void rtl8139_poll_controller(struct net_device *dev)
2204 {
2205 disable_irq(dev->irq);
2206 rtl8139_interrupt(dev->irq, dev);
2207 enable_irq(dev->irq);
2208 }
2209 #endif
2210
2211 static int rtl8139_close (struct net_device *dev)
2212 {
2213 struct rtl8139_private *tp = netdev_priv(dev);
2214 void __iomem *ioaddr = tp->mmio_addr;
2215 unsigned long flags;
2216
2217 netif_stop_queue(dev);
2218 napi_disable(&tp->napi);
2219
2220 if (netif_msg_ifdown(tp))
2221 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2222 dev->name, RTL_R16 (IntrStatus));
2223
2224 spin_lock_irqsave (&tp->lock, flags);
2225
2226 /* Stop the chip's Tx and Rx DMA processes. */
2227 RTL_W8 (ChipCmd, 0);
2228
2229 /* Disable interrupts by clearing the interrupt mask. */
2230 RTL_W16 (IntrMask, 0);
2231
2232 /* Update the error counts. */
2233 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2234 RTL_W32 (RxMissed, 0);
2235
2236 spin_unlock_irqrestore (&tp->lock, flags);
2237
2238 synchronize_irq (dev->irq); /* racy, but that's ok here */
2239 free_irq (dev->irq, dev);
2240
2241 rtl8139_tx_clear (tp);
2242
2243 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2244 tp->rx_ring, tp->rx_ring_dma);
2245 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2246 tp->tx_bufs, tp->tx_bufs_dma);
2247 tp->rx_ring = NULL;
2248 tp->tx_bufs = NULL;
2249
2250 /* Green! Put the chip in low-power mode. */
2251 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2252
2253 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2254 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2255
2256 return 0;
2257 }
2258
2259
2260 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2261 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2262 other threads or interrupts aren't messing with the 8139. */
2263 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2264 {
2265 struct rtl8139_private *np = netdev_priv(dev);
2266 void __iomem *ioaddr = np->mmio_addr;
2267
2268 spin_lock_irq(&np->lock);
2269 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2270 u8 cfg3 = RTL_R8 (Config3);
2271 u8 cfg5 = RTL_R8 (Config5);
2272
2273 wol->supported = WAKE_PHY | WAKE_MAGIC
2274 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2275
2276 wol->wolopts = 0;
2277 if (cfg3 & Cfg3_LinkUp)
2278 wol->wolopts |= WAKE_PHY;
2279 if (cfg3 & Cfg3_Magic)
2280 wol->wolopts |= WAKE_MAGIC;
2281 /* (KON)FIXME: See how netdev_set_wol() handles the
2282 following constants. */
2283 if (cfg5 & Cfg5_UWF)
2284 wol->wolopts |= WAKE_UCAST;
2285 if (cfg5 & Cfg5_MWF)
2286 wol->wolopts |= WAKE_MCAST;
2287 if (cfg5 & Cfg5_BWF)
2288 wol->wolopts |= WAKE_BCAST;
2289 }
2290 spin_unlock_irq(&np->lock);
2291 }
2292
2293
2294 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2295 that wol points to kernel memory and other threads or interrupts
2296 aren't messing with the 8139. */
2297 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2298 {
2299 struct rtl8139_private *np = netdev_priv(dev);
2300 void __iomem *ioaddr = np->mmio_addr;
2301 u32 support;
2302 u8 cfg3, cfg5;
2303
2304 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2305 ? (WAKE_PHY | WAKE_MAGIC
2306 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2307 : 0);
2308 if (wol->wolopts & ~support)
2309 return -EINVAL;
2310
2311 spin_lock_irq(&np->lock);
2312 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2313 if (wol->wolopts & WAKE_PHY)
2314 cfg3 |= Cfg3_LinkUp;
2315 if (wol->wolopts & WAKE_MAGIC)
2316 cfg3 |= Cfg3_Magic;
2317 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2318 RTL_W8 (Config3, cfg3);
2319 RTL_W8 (Cfg9346, Cfg9346_Lock);
2320
2321 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2322 /* (KON)FIXME: These are untested. We may have to set the
2323 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2324 documentation. */
2325 if (wol->wolopts & WAKE_UCAST)
2326 cfg5 |= Cfg5_UWF;
2327 if (wol->wolopts & WAKE_MCAST)
2328 cfg5 |= Cfg5_MWF;
2329 if (wol->wolopts & WAKE_BCAST)
2330 cfg5 |= Cfg5_BWF;
2331 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2332 spin_unlock_irq(&np->lock);
2333
2334 return 0;
2335 }
2336
2337 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2338 {
2339 struct rtl8139_private *np = netdev_priv(dev);
2340 strcpy(info->driver, DRV_NAME);
2341 strcpy(info->version, DRV_VERSION);
2342 strcpy(info->bus_info, pci_name(np->pci_dev));
2343 info->regdump_len = np->regs_len;
2344 }
2345
2346 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2347 {
2348 struct rtl8139_private *np = netdev_priv(dev);
2349 spin_lock_irq(&np->lock);
2350 mii_ethtool_gset(&np->mii, cmd);
2351 spin_unlock_irq(&np->lock);
2352 return 0;
2353 }
2354
2355 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2356 {
2357 struct rtl8139_private *np = netdev_priv(dev);
2358 int rc;
2359 spin_lock_irq(&np->lock);
2360 rc = mii_ethtool_sset(&np->mii, cmd);
2361 spin_unlock_irq(&np->lock);
2362 return rc;
2363 }
2364
2365 static int rtl8139_nway_reset(struct net_device *dev)
2366 {
2367 struct rtl8139_private *np = netdev_priv(dev);
2368 return mii_nway_restart(&np->mii);
2369 }
2370
2371 static u32 rtl8139_get_link(struct net_device *dev)
2372 {
2373 struct rtl8139_private *np = netdev_priv(dev);
2374 return mii_link_ok(&np->mii);
2375 }
2376
2377 static u32 rtl8139_get_msglevel(struct net_device *dev)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 return np->msg_enable;
2381 }
2382
2383 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2384 {
2385 struct rtl8139_private *np = netdev_priv(dev);
2386 np->msg_enable = datum;
2387 }
2388
2389 /* TODO: we are too slack to do reg dumping for pio, for now */
2390 #ifdef CONFIG_8139TOO_PIO
2391 #define rtl8139_get_regs_len NULL
2392 #define rtl8139_get_regs NULL
2393 #else
2394 static int rtl8139_get_regs_len(struct net_device *dev)
2395 {
2396 struct rtl8139_private *np = netdev_priv(dev);
2397 return np->regs_len;
2398 }
2399
2400 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403
2404 regs->version = RTL_REGS_VER;
2405
2406 spin_lock_irq(&np->lock);
2407 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2408 spin_unlock_irq(&np->lock);
2409 }
2410 #endif /* CONFIG_8139TOO_MMIO */
2411
2412 static int rtl8139_get_stats_count(struct net_device *dev)
2413 {
2414 return RTL_NUM_STATS;
2415 }
2416
2417 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2418 {
2419 struct rtl8139_private *np = netdev_priv(dev);
2420
2421 data[0] = np->xstats.early_rx;
2422 data[1] = np->xstats.tx_buf_mapped;
2423 data[2] = np->xstats.tx_timeouts;
2424 data[3] = np->xstats.rx_lost_in_ring;
2425 }
2426
2427 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2428 {
2429 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2430 }
2431
2432 static const struct ethtool_ops rtl8139_ethtool_ops = {
2433 .get_drvinfo = rtl8139_get_drvinfo,
2434 .get_settings = rtl8139_get_settings,
2435 .set_settings = rtl8139_set_settings,
2436 .get_regs_len = rtl8139_get_regs_len,
2437 .get_regs = rtl8139_get_regs,
2438 .nway_reset = rtl8139_nway_reset,
2439 .get_link = rtl8139_get_link,
2440 .get_msglevel = rtl8139_get_msglevel,
2441 .set_msglevel = rtl8139_set_msglevel,
2442 .get_wol = rtl8139_get_wol,
2443 .set_wol = rtl8139_set_wol,
2444 .get_strings = rtl8139_get_strings,
2445 .get_stats_count = rtl8139_get_stats_count,
2446 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2447 };
2448
2449 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2450 {
2451 struct rtl8139_private *np = netdev_priv(dev);
2452 int rc;
2453
2454 if (!netif_running(dev))
2455 return -EINVAL;
2456
2457 spin_lock_irq(&np->lock);
2458 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2459 spin_unlock_irq(&np->lock);
2460
2461 return rc;
2462 }
2463
2464
2465 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2466 {
2467 struct rtl8139_private *tp = netdev_priv(dev);
2468 void __iomem *ioaddr = tp->mmio_addr;
2469 unsigned long flags;
2470
2471 if (netif_running(dev)) {
2472 spin_lock_irqsave (&tp->lock, flags);
2473 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2474 RTL_W32 (RxMissed, 0);
2475 spin_unlock_irqrestore (&tp->lock, flags);
2476 }
2477
2478 return &tp->stats;
2479 }
2480
2481 /* Set or clear the multicast filter for this adaptor.
2482 This routine is not state sensitive and need not be SMP locked. */
2483
2484 static void __set_rx_mode (struct net_device *dev)
2485 {
2486 struct rtl8139_private *tp = netdev_priv(dev);
2487 void __iomem *ioaddr = tp->mmio_addr;
2488 u32 mc_filter[2]; /* Multicast hash filter */
2489 int i, rx_mode;
2490 u32 tmp;
2491
2492 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2493 dev->name, dev->flags, RTL_R32 (RxConfig));
2494
2495 /* Note: do not reorder, GCC is clever about common statements. */
2496 if (dev->flags & IFF_PROMISC) {
2497 rx_mode =
2498 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2499 AcceptAllPhys;
2500 mc_filter[1] = mc_filter[0] = 0xffffffff;
2501 } else if ((dev->mc_count > multicast_filter_limit)
2502 || (dev->flags & IFF_ALLMULTI)) {
2503 /* Too many to filter perfectly -- accept all multicasts. */
2504 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2505 mc_filter[1] = mc_filter[0] = 0xffffffff;
2506 } else {
2507 struct dev_mc_list *mclist;
2508 rx_mode = AcceptBroadcast | AcceptMyPhys;
2509 mc_filter[1] = mc_filter[0] = 0;
2510 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2511 i++, mclist = mclist->next) {
2512 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2513
2514 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2515 rx_mode |= AcceptMulticast;
2516 }
2517 }
2518
2519 /* We can safely update without stopping the chip. */
2520 tmp = rtl8139_rx_config | rx_mode;
2521 if (tp->rx_config != tmp) {
2522 RTL_W32_F (RxConfig, tmp);
2523 tp->rx_config = tmp;
2524 }
2525 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2526 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2527 }
2528
2529 static void rtl8139_set_rx_mode (struct net_device *dev)
2530 {
2531 unsigned long flags;
2532 struct rtl8139_private *tp = netdev_priv(dev);
2533
2534 spin_lock_irqsave (&tp->lock, flags);
2535 __set_rx_mode(dev);
2536 spin_unlock_irqrestore (&tp->lock, flags);
2537 }
2538
2539 #ifdef CONFIG_PM
2540
2541 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2542 {
2543 struct net_device *dev = pci_get_drvdata (pdev);
2544 struct rtl8139_private *tp = netdev_priv(dev);
2545 void __iomem *ioaddr = tp->mmio_addr;
2546 unsigned long flags;
2547
2548 pci_save_state (pdev);
2549
2550 if (!netif_running (dev))
2551 return 0;
2552
2553 netif_device_detach (dev);
2554
2555 spin_lock_irqsave (&tp->lock, flags);
2556
2557 /* Disable interrupts, stop Tx and Rx. */
2558 RTL_W16 (IntrMask, 0);
2559 RTL_W8 (ChipCmd, 0);
2560
2561 /* Update the error counts. */
2562 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2563 RTL_W32 (RxMissed, 0);
2564
2565 spin_unlock_irqrestore (&tp->lock, flags);
2566
2567 pci_set_power_state (pdev, PCI_D3hot);
2568
2569 return 0;
2570 }
2571
2572
2573 static int rtl8139_resume (struct pci_dev *pdev)
2574 {
2575 struct net_device *dev = pci_get_drvdata (pdev);
2576
2577 pci_restore_state (pdev);
2578 if (!netif_running (dev))
2579 return 0;
2580 pci_set_power_state (pdev, PCI_D0);
2581 rtl8139_init_ring (dev);
2582 rtl8139_hw_start (dev);
2583 netif_device_attach (dev);
2584 return 0;
2585 }
2586
2587 #endif /* CONFIG_PM */
2588
2589
2590 static struct pci_driver rtl8139_pci_driver = {
2591 .name = DRV_NAME,
2592 .id_table = rtl8139_pci_tbl,
2593 .probe = rtl8139_init_one,
2594 .remove = __devexit_p(rtl8139_remove_one),
2595 #ifdef CONFIG_PM
2596 .suspend = rtl8139_suspend,
2597 .resume = rtl8139_resume,
2598 #endif /* CONFIG_PM */
2599 };
2600
2601
2602 static int __init rtl8139_init_module (void)
2603 {
2604 /* when we're a module, we always print a version message,
2605 * even if no 8139 board is found.
2606 */
2607 #ifdef MODULE
2608 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2609 #endif
2610
2611 return pci_register_driver(&rtl8139_pci_driver);
2612 }
2613
2614
2615 static void __exit rtl8139_cleanup_module (void)
2616 {
2617 pci_unregister_driver (&rtl8139_pci_driver);
2618 }
2619
2620
2621 module_init(rtl8139_init_module);
2622 module_exit(rtl8139_cleanup_module);
Linux kernel - Deliverables
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