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net: trans_start cleanups
[deliverable/linux.git] / drivers / net / arm / ep93xx_eth.c
1 /*
2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
13
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/init.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <mach/hardware.h>
29
30 #define DRV_MODULE_NAME "ep93xx-eth"
31 #define DRV_MODULE_VERSION "0.1"
32
33 #define RX_QUEUE_ENTRIES 64
34 #define TX_QUEUE_ENTRIES 8
35
36 #define MAX_PKT_SIZE 2044
37 #define PKT_BUF_SIZE 2048
38
39 #define REG_RXCTL 0x0000
40 #define REG_RXCTL_DEFAULT 0x00073800
41 #define REG_TXCTL 0x0004
42 #define REG_TXCTL_ENABLE 0x00000001
43 #define REG_MIICMD 0x0010
44 #define REG_MIICMD_READ 0x00008000
45 #define REG_MIICMD_WRITE 0x00004000
46 #define REG_MIIDATA 0x0014
47 #define REG_MIISTS 0x0018
48 #define REG_MIISTS_BUSY 0x00000001
49 #define REG_SELFCTL 0x0020
50 #define REG_SELFCTL_RESET 0x00000001
51 #define REG_INTEN 0x0024
52 #define REG_INTEN_TX 0x00000008
53 #define REG_INTEN_RX 0x00000007
54 #define REG_INTSTSP 0x0028
55 #define REG_INTSTS_TX 0x00000008
56 #define REG_INTSTS_RX 0x00000004
57 #define REG_INTSTSC 0x002c
58 #define REG_AFP 0x004c
59 #define REG_INDAD0 0x0050
60 #define REG_INDAD1 0x0051
61 #define REG_INDAD2 0x0052
62 #define REG_INDAD3 0x0053
63 #define REG_INDAD4 0x0054
64 #define REG_INDAD5 0x0055
65 #define REG_GIINTMSK 0x0064
66 #define REG_GIINTMSK_ENABLE 0x00008000
67 #define REG_BMCTL 0x0080
68 #define REG_BMCTL_ENABLE_TX 0x00000100
69 #define REG_BMCTL_ENABLE_RX 0x00000001
70 #define REG_BMSTS 0x0084
71 #define REG_BMSTS_RX_ACTIVE 0x00000008
72 #define REG_RXDQBADD 0x0090
73 #define REG_RXDQBLEN 0x0094
74 #define REG_RXDCURADD 0x0098
75 #define REG_RXDENQ 0x009c
76 #define REG_RXSTSQBADD 0x00a0
77 #define REG_RXSTSQBLEN 0x00a4
78 #define REG_RXSTSQCURADD 0x00a8
79 #define REG_RXSTSENQ 0x00ac
80 #define REG_TXDQBADD 0x00b0
81 #define REG_TXDQBLEN 0x00b4
82 #define REG_TXDQCURADD 0x00b8
83 #define REG_TXDENQ 0x00bc
84 #define REG_TXSTSQBADD 0x00c0
85 #define REG_TXSTSQBLEN 0x00c4
86 #define REG_TXSTSQCURADD 0x00c8
87 #define REG_MAXFRMLEN 0x00e8
88
89 struct ep93xx_rdesc
90 {
91 u32 buf_addr;
92 u32 rdesc1;
93 };
94
95 #define RDESC1_NSOF 0x80000000
96 #define RDESC1_BUFFER_INDEX 0x7fff0000
97 #define RDESC1_BUFFER_LENGTH 0x0000ffff
98
99 struct ep93xx_rstat
100 {
101 u32 rstat0;
102 u32 rstat1;
103 };
104
105 #define RSTAT0_RFP 0x80000000
106 #define RSTAT0_RWE 0x40000000
107 #define RSTAT0_EOF 0x20000000
108 #define RSTAT0_EOB 0x10000000
109 #define RSTAT0_AM 0x00c00000
110 #define RSTAT0_RX_ERR 0x00200000
111 #define RSTAT0_OE 0x00100000
112 #define RSTAT0_FE 0x00080000
113 #define RSTAT0_RUNT 0x00040000
114 #define RSTAT0_EDATA 0x00020000
115 #define RSTAT0_CRCE 0x00010000
116 #define RSTAT0_CRCI 0x00008000
117 #define RSTAT0_HTI 0x00003f00
118 #define RSTAT1_RFP 0x80000000
119 #define RSTAT1_BUFFER_INDEX 0x7fff0000
120 #define RSTAT1_FRAME_LENGTH 0x0000ffff
121
122 struct ep93xx_tdesc
123 {
124 u32 buf_addr;
125 u32 tdesc1;
126 };
127
128 #define TDESC1_EOF 0x80000000
129 #define TDESC1_BUFFER_INDEX 0x7fff0000
130 #define TDESC1_BUFFER_ABORT 0x00008000
131 #define TDESC1_BUFFER_LENGTH 0x00000fff
132
133 struct ep93xx_tstat
134 {
135 u32 tstat0;
136 };
137
138 #define TSTAT0_TXFP 0x80000000
139 #define TSTAT0_TXWE 0x40000000
140 #define TSTAT0_FA 0x20000000
141 #define TSTAT0_LCRS 0x10000000
142 #define TSTAT0_OW 0x04000000
143 #define TSTAT0_TXU 0x02000000
144 #define TSTAT0_ECOLL 0x01000000
145 #define TSTAT0_NCOLL 0x001f0000
146 #define TSTAT0_BUFFER_INDEX 0x00007fff
147
148 struct ep93xx_descs
149 {
150 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
151 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
152 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
153 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
154 };
155
156 struct ep93xx_priv
157 {
158 struct resource *res;
159 void __iomem *base_addr;
160 int irq;
161
162 struct ep93xx_descs *descs;
163 dma_addr_t descs_dma_addr;
164
165 void *rx_buf[RX_QUEUE_ENTRIES];
166 void *tx_buf[TX_QUEUE_ENTRIES];
167
168 spinlock_t rx_lock;
169 unsigned int rx_pointer;
170 unsigned int tx_clean_pointer;
171 unsigned int tx_pointer;
172 spinlock_t tx_pending_lock;
173 unsigned int tx_pending;
174
175 struct net_device *dev;
176 struct napi_struct napi;
177
178 struct net_device_stats stats;
179
180 struct mii_if_info mii;
181 u8 mdc_divisor;
182 };
183
184 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
185 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
186 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
187 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
188 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
189 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
190
191 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
192 {
193 struct ep93xx_priv *ep = netdev_priv(dev);
194 int data;
195 int i;
196
197 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
198
199 for (i = 0; i < 10; i++) {
200 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
201 break;
202 msleep(1);
203 }
204
205 if (i == 10) {
206 pr_info("mdio read timed out\n");
207 data = 0xffff;
208 } else {
209 data = rdl(ep, REG_MIIDATA);
210 }
211
212 return data;
213 }
214
215 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
216 {
217 struct ep93xx_priv *ep = netdev_priv(dev);
218 int i;
219
220 wrl(ep, REG_MIIDATA, data);
221 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
222
223 for (i = 0; i < 10; i++) {
224 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
225 break;
226 msleep(1);
227 }
228
229 if (i == 10)
230 pr_info("mdio write timed out\n");
231 }
232
233 static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
234 {
235 struct ep93xx_priv *ep = netdev_priv(dev);
236 return &(ep->stats);
237 }
238
239 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
240 {
241 struct ep93xx_priv *ep = netdev_priv(dev);
242
243 while (processed < budget) {
244 int entry;
245 struct ep93xx_rstat *rstat;
246 u32 rstat0;
247 u32 rstat1;
248 int length;
249 struct sk_buff *skb;
250
251 entry = ep->rx_pointer;
252 rstat = ep->descs->rstat + entry;
253
254 rstat0 = rstat->rstat0;
255 rstat1 = rstat->rstat1;
256 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
257 break;
258
259 rstat->rstat0 = 0;
260 rstat->rstat1 = 0;
261
262 if (!(rstat0 & RSTAT0_EOF))
263 pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
264 if (!(rstat0 & RSTAT0_EOB))
265 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
266 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
267 pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
268
269 if (!(rstat0 & RSTAT0_RWE)) {
270 ep->stats.rx_errors++;
271 if (rstat0 & RSTAT0_OE)
272 ep->stats.rx_fifo_errors++;
273 if (rstat0 & RSTAT0_FE)
274 ep->stats.rx_frame_errors++;
275 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
276 ep->stats.rx_length_errors++;
277 if (rstat0 & RSTAT0_CRCE)
278 ep->stats.rx_crc_errors++;
279 goto err;
280 }
281
282 length = rstat1 & RSTAT1_FRAME_LENGTH;
283 if (length > MAX_PKT_SIZE) {
284 pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
285 goto err;
286 }
287
288 /* Strip FCS. */
289 if (rstat0 & RSTAT0_CRCI)
290 length -= 4;
291
292 skb = dev_alloc_skb(length + 2);
293 if (likely(skb != NULL)) {
294 skb_reserve(skb, 2);
295 dma_sync_single_for_cpu(NULL, ep->descs->rdesc[entry].buf_addr,
296 length, DMA_FROM_DEVICE);
297 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
298 skb_put(skb, length);
299 skb->protocol = eth_type_trans(skb, dev);
300
301 netif_receive_skb(skb);
302
303 ep->stats.rx_packets++;
304 ep->stats.rx_bytes += length;
305 } else {
306 ep->stats.rx_dropped++;
307 }
308
309 err:
310 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
311 processed++;
312 }
313
314 if (processed) {
315 wrw(ep, REG_RXDENQ, processed);
316 wrw(ep, REG_RXSTSENQ, processed);
317 }
318
319 return processed;
320 }
321
322 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
323 {
324 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
325 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
326 }
327
328 static int ep93xx_poll(struct napi_struct *napi, int budget)
329 {
330 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
331 struct net_device *dev = ep->dev;
332 int rx = 0;
333
334 poll_some_more:
335 rx = ep93xx_rx(dev, rx, budget);
336 if (rx < budget) {
337 int more = 0;
338
339 spin_lock_irq(&ep->rx_lock);
340 __napi_complete(napi);
341 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
342 if (ep93xx_have_more_rx(ep)) {
343 wrl(ep, REG_INTEN, REG_INTEN_TX);
344 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
345 more = 1;
346 }
347 spin_unlock_irq(&ep->rx_lock);
348
349 if (more && napi_reschedule(napi))
350 goto poll_some_more;
351 }
352
353 return rx;
354 }
355
356 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
357 {
358 struct ep93xx_priv *ep = netdev_priv(dev);
359 int entry;
360
361 if (unlikely(skb->len > MAX_PKT_SIZE)) {
362 ep->stats.tx_dropped++;
363 dev_kfree_skb(skb);
364 return NETDEV_TX_OK;
365 }
366
367 entry = ep->tx_pointer;
368 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
369
370 ep->descs->tdesc[entry].tdesc1 =
371 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
372 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
373 dma_sync_single_for_cpu(NULL, ep->descs->tdesc[entry].buf_addr,
374 skb->len, DMA_TO_DEVICE);
375 dev_kfree_skb(skb);
376
377 spin_lock_irq(&ep->tx_pending_lock);
378 ep->tx_pending++;
379 if (ep->tx_pending == TX_QUEUE_ENTRIES)
380 netif_stop_queue(dev);
381 spin_unlock_irq(&ep->tx_pending_lock);
382
383 wrl(ep, REG_TXDENQ, 1);
384
385 return NETDEV_TX_OK;
386 }
387
388 static void ep93xx_tx_complete(struct net_device *dev)
389 {
390 struct ep93xx_priv *ep = netdev_priv(dev);
391 int wake;
392
393 wake = 0;
394
395 spin_lock(&ep->tx_pending_lock);
396 while (1) {
397 int entry;
398 struct ep93xx_tstat *tstat;
399 u32 tstat0;
400
401 entry = ep->tx_clean_pointer;
402 tstat = ep->descs->tstat + entry;
403
404 tstat0 = tstat->tstat0;
405 if (!(tstat0 & TSTAT0_TXFP))
406 break;
407
408 tstat->tstat0 = 0;
409
410 if (tstat0 & TSTAT0_FA)
411 pr_crit("frame aborted %.8x\n", tstat0);
412 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
413 pr_crit("entry mismatch %.8x\n", tstat0);
414
415 if (tstat0 & TSTAT0_TXWE) {
416 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
417
418 ep->stats.tx_packets++;
419 ep->stats.tx_bytes += length;
420 } else {
421 ep->stats.tx_errors++;
422 }
423
424 if (tstat0 & TSTAT0_OW)
425 ep->stats.tx_window_errors++;
426 if (tstat0 & TSTAT0_TXU)
427 ep->stats.tx_fifo_errors++;
428 ep->stats.collisions += (tstat0 >> 16) & 0x1f;
429
430 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
431 if (ep->tx_pending == TX_QUEUE_ENTRIES)
432 wake = 1;
433 ep->tx_pending--;
434 }
435 spin_unlock(&ep->tx_pending_lock);
436
437 if (wake)
438 netif_wake_queue(dev);
439 }
440
441 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
442 {
443 struct net_device *dev = dev_id;
444 struct ep93xx_priv *ep = netdev_priv(dev);
445 u32 status;
446
447 status = rdl(ep, REG_INTSTSC);
448 if (status == 0)
449 return IRQ_NONE;
450
451 if (status & REG_INTSTS_RX) {
452 spin_lock(&ep->rx_lock);
453 if (likely(napi_schedule_prep(&ep->napi))) {
454 wrl(ep, REG_INTEN, REG_INTEN_TX);
455 __napi_schedule(&ep->napi);
456 }
457 spin_unlock(&ep->rx_lock);
458 }
459
460 if (status & REG_INTSTS_TX)
461 ep93xx_tx_complete(dev);
462
463 return IRQ_HANDLED;
464 }
465
466 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
467 {
468 int i;
469
470 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
471 dma_addr_t d;
472
473 d = ep->descs->rdesc[i].buf_addr;
474 if (d)
475 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
476
477 if (ep->rx_buf[i] != NULL)
478 free_page((unsigned long)ep->rx_buf[i]);
479 }
480
481 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
482 dma_addr_t d;
483
484 d = ep->descs->tdesc[i].buf_addr;
485 if (d)
486 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
487
488 if (ep->tx_buf[i] != NULL)
489 free_page((unsigned long)ep->tx_buf[i]);
490 }
491
492 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
493 ep->descs_dma_addr);
494 }
495
496 /*
497 * The hardware enforces a sub-2K maximum packet size, so we put
498 * two buffers on every hardware page.
499 */
500 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
501 {
502 int i;
503
504 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
505 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
506 if (ep->descs == NULL)
507 return 1;
508
509 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
510 void *page;
511 dma_addr_t d;
512
513 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
514 if (page == NULL)
515 goto err;
516
517 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
518 if (dma_mapping_error(NULL, d)) {
519 free_page((unsigned long)page);
520 goto err;
521 }
522
523 ep->rx_buf[i] = page;
524 ep->descs->rdesc[i].buf_addr = d;
525 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
526
527 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
528 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
529 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
530 }
531
532 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
533 void *page;
534 dma_addr_t d;
535
536 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
537 if (page == NULL)
538 goto err;
539
540 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
541 if (dma_mapping_error(NULL, d)) {
542 free_page((unsigned long)page);
543 goto err;
544 }
545
546 ep->tx_buf[i] = page;
547 ep->descs->tdesc[i].buf_addr = d;
548
549 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
550 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
551 }
552
553 return 0;
554
555 err:
556 ep93xx_free_buffers(ep);
557 return 1;
558 }
559
560 static int ep93xx_start_hw(struct net_device *dev)
561 {
562 struct ep93xx_priv *ep = netdev_priv(dev);
563 unsigned long addr;
564 int i;
565
566 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
567 for (i = 0; i < 10; i++) {
568 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
569 break;
570 msleep(1);
571 }
572
573 if (i == 10) {
574 pr_crit("hw failed to reset\n");
575 return 1;
576 }
577
578 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
579
580 /* Does the PHY support preamble suppress? */
581 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
582 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
583
584 /* Receive descriptor ring. */
585 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
586 wrl(ep, REG_RXDQBADD, addr);
587 wrl(ep, REG_RXDCURADD, addr);
588 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
589
590 /* Receive status ring. */
591 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
592 wrl(ep, REG_RXSTSQBADD, addr);
593 wrl(ep, REG_RXSTSQCURADD, addr);
594 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
595
596 /* Transmit descriptor ring. */
597 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
598 wrl(ep, REG_TXDQBADD, addr);
599 wrl(ep, REG_TXDQCURADD, addr);
600 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
601
602 /* Transmit status ring. */
603 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
604 wrl(ep, REG_TXSTSQBADD, addr);
605 wrl(ep, REG_TXSTSQCURADD, addr);
606 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
607
608 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
609 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
610 wrl(ep, REG_GIINTMSK, 0);
611
612 for (i = 0; i < 10; i++) {
613 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
614 break;
615 msleep(1);
616 }
617
618 if (i == 10) {
619 pr_crit("hw failed to start\n");
620 return 1;
621 }
622
623 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
624 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
625
626 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
627 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
628 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
629 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
630 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
631 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
632 wrl(ep, REG_AFP, 0);
633
634 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
635
636 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
637 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
638
639 return 0;
640 }
641
642 static void ep93xx_stop_hw(struct net_device *dev)
643 {
644 struct ep93xx_priv *ep = netdev_priv(dev);
645 int i;
646
647 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
648 for (i = 0; i < 10; i++) {
649 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
650 break;
651 msleep(1);
652 }
653
654 if (i == 10)
655 pr_crit("hw failed to reset\n");
656 }
657
658 static int ep93xx_open(struct net_device *dev)
659 {
660 struct ep93xx_priv *ep = netdev_priv(dev);
661 int err;
662
663 if (ep93xx_alloc_buffers(ep))
664 return -ENOMEM;
665
666 napi_enable(&ep->napi);
667
668 if (ep93xx_start_hw(dev)) {
669 napi_disable(&ep->napi);
670 ep93xx_free_buffers(ep);
671 return -EIO;
672 }
673
674 spin_lock_init(&ep->rx_lock);
675 ep->rx_pointer = 0;
676 ep->tx_clean_pointer = 0;
677 ep->tx_pointer = 0;
678 spin_lock_init(&ep->tx_pending_lock);
679 ep->tx_pending = 0;
680
681 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
682 if (err) {
683 napi_disable(&ep->napi);
684 ep93xx_stop_hw(dev);
685 ep93xx_free_buffers(ep);
686 return err;
687 }
688
689 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
690
691 netif_start_queue(dev);
692
693 return 0;
694 }
695
696 static int ep93xx_close(struct net_device *dev)
697 {
698 struct ep93xx_priv *ep = netdev_priv(dev);
699
700 napi_disable(&ep->napi);
701 netif_stop_queue(dev);
702
703 wrl(ep, REG_GIINTMSK, 0);
704 free_irq(ep->irq, dev);
705 ep93xx_stop_hw(dev);
706 ep93xx_free_buffers(ep);
707
708 return 0;
709 }
710
711 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
712 {
713 struct ep93xx_priv *ep = netdev_priv(dev);
714 struct mii_ioctl_data *data = if_mii(ifr);
715
716 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
717 }
718
719 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
720 {
721 strcpy(info->driver, DRV_MODULE_NAME);
722 strcpy(info->version, DRV_MODULE_VERSION);
723 }
724
725 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
726 {
727 struct ep93xx_priv *ep = netdev_priv(dev);
728 return mii_ethtool_gset(&ep->mii, cmd);
729 }
730
731 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
732 {
733 struct ep93xx_priv *ep = netdev_priv(dev);
734 return mii_ethtool_sset(&ep->mii, cmd);
735 }
736
737 static int ep93xx_nway_reset(struct net_device *dev)
738 {
739 struct ep93xx_priv *ep = netdev_priv(dev);
740 return mii_nway_restart(&ep->mii);
741 }
742
743 static u32 ep93xx_get_link(struct net_device *dev)
744 {
745 struct ep93xx_priv *ep = netdev_priv(dev);
746 return mii_link_ok(&ep->mii);
747 }
748
749 static const struct ethtool_ops ep93xx_ethtool_ops = {
750 .get_drvinfo = ep93xx_get_drvinfo,
751 .get_settings = ep93xx_get_settings,
752 .set_settings = ep93xx_set_settings,
753 .nway_reset = ep93xx_nway_reset,
754 .get_link = ep93xx_get_link,
755 };
756
757 static const struct net_device_ops ep93xx_netdev_ops = {
758 .ndo_open = ep93xx_open,
759 .ndo_stop = ep93xx_close,
760 .ndo_start_xmit = ep93xx_xmit,
761 .ndo_get_stats = ep93xx_get_stats,
762 .ndo_do_ioctl = ep93xx_ioctl,
763 .ndo_validate_addr = eth_validate_addr,
764 .ndo_change_mtu = eth_change_mtu,
765 .ndo_set_mac_address = eth_mac_addr,
766 };
767
768 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
769 {
770 struct net_device *dev;
771
772 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
773 if (dev == NULL)
774 return NULL;
775
776 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
777
778 dev->ethtool_ops = &ep93xx_ethtool_ops;
779 dev->netdev_ops = &ep93xx_netdev_ops;
780
781 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
782
783 return dev;
784 }
785
786
787 static int ep93xx_eth_remove(struct platform_device *pdev)
788 {
789 struct net_device *dev;
790 struct ep93xx_priv *ep;
791
792 dev = platform_get_drvdata(pdev);
793 if (dev == NULL)
794 return 0;
795 platform_set_drvdata(pdev, NULL);
796
797 ep = netdev_priv(dev);
798
799 /* @@@ Force down. */
800 unregister_netdev(dev);
801 ep93xx_free_buffers(ep);
802
803 if (ep->base_addr != NULL)
804 iounmap(ep->base_addr);
805
806 if (ep->res != NULL) {
807 release_resource(ep->res);
808 kfree(ep->res);
809 }
810
811 free_netdev(dev);
812
813 return 0;
814 }
815
816 static int ep93xx_eth_probe(struct platform_device *pdev)
817 {
818 struct ep93xx_eth_data *data;
819 struct net_device *dev;
820 struct ep93xx_priv *ep;
821 struct resource *mem;
822 int irq;
823 int err;
824
825 if (pdev == NULL)
826 return -ENODEV;
827 data = pdev->dev.platform_data;
828
829 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 irq = platform_get_irq(pdev, 0);
831 if (!mem || irq < 0)
832 return -ENXIO;
833
834 dev = ep93xx_dev_alloc(data);
835 if (dev == NULL) {
836 err = -ENOMEM;
837 goto err_out;
838 }
839 ep = netdev_priv(dev);
840 ep->dev = dev;
841 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
842
843 platform_set_drvdata(pdev, dev);
844
845 ep->res = request_mem_region(mem->start, resource_size(mem),
846 dev_name(&pdev->dev));
847 if (ep->res == NULL) {
848 dev_err(&pdev->dev, "Could not reserve memory region\n");
849 err = -ENOMEM;
850 goto err_out;
851 }
852
853 ep->base_addr = ioremap(mem->start, resource_size(mem));
854 if (ep->base_addr == NULL) {
855 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
856 err = -EIO;
857 goto err_out;
858 }
859 ep->irq = irq;
860
861 ep->mii.phy_id = data->phy_id;
862 ep->mii.phy_id_mask = 0x1f;
863 ep->mii.reg_num_mask = 0x1f;
864 ep->mii.dev = dev;
865 ep->mii.mdio_read = ep93xx_mdio_read;
866 ep->mii.mdio_write = ep93xx_mdio_write;
867 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
868
869 if (is_zero_ether_addr(dev->dev_addr))
870 random_ether_addr(dev->dev_addr);
871
872 err = register_netdev(dev);
873 if (err) {
874 dev_err(&pdev->dev, "Failed to register netdev\n");
875 goto err_out;
876 }
877
878 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
879 dev->name, ep->irq, dev->dev_addr);
880
881 return 0;
882
883 err_out:
884 ep93xx_eth_remove(pdev);
885 return err;
886 }
887
888
889 static struct platform_driver ep93xx_eth_driver = {
890 .probe = ep93xx_eth_probe,
891 .remove = ep93xx_eth_remove,
892 .driver = {
893 .name = "ep93xx-eth",
894 .owner = THIS_MODULE,
895 },
896 };
897
898 static int __init ep93xx_eth_init_module(void)
899 {
900 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
901 return platform_driver_register(&ep93xx_eth_driver);
902 }
903
904 static void __exit ep93xx_eth_cleanup_module(void)
905 {
906 platform_driver_unregister(&ep93xx_eth_driver);
907 }
908
909 module_init(ep93xx_eth_init_module);
910 module_exit(ep93xx_eth_cleanup_module);
911 MODULE_LICENSE("GPL");
912 MODULE_ALIAS("platform:ep93xx-eth");
Linux kernel - Deliverables
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