2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
32 * This version is adapted from the Attansic reference driver.
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
43 * interrupt coalescing
47 #include <asm/atomic.h>
48 #include <asm/byteorder.h>
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
59 #include <linux/interrupt.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
81 #include <net/checksum.h>
85 #define ATLX_DRIVER_VERSION "2.1.3"
86 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
87 Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
88 MODULE_LICENSE("GPL");
89 MODULE_VERSION(ATLX_DRIVER_VERSION
);
91 /* Temporary hack for merging atl1 and atl2 */
95 * This is the only thing that needs to be changed to adjust the
96 * maximum number of ports that the driver can manage.
98 #define ATL1_MAX_NIC 4
100 #define OPTION_UNSET -1
101 #define OPTION_DISABLED 0
102 #define OPTION_ENABLED 1
104 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
107 * Interrupt Moderate Timer in units of 2 us
109 * Valid Range: 10-65535
111 * Default Value: 100 (200us)
113 static int __devinitdata int_mod_timer
[ATL1_MAX_NIC
+1] = ATL1_PARAM_INIT
;
114 static unsigned int num_int_mod_timer
;
115 module_param_array_named(int_mod_timer
, int_mod_timer
, int,
116 &num_int_mod_timer
, 0);
117 MODULE_PARM_DESC(int_mod_timer
, "Interrupt moderator timer");
119 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
120 #define MAX_INT_MOD_CNT 65000
121 #define MIN_INT_MOD_CNT 50
124 enum { enable_option
, range_option
, list_option
} type
;
129 struct { /* range_option info */
133 struct { /* list_option info */
135 struct atl1_opt_list
{
143 static int __devinit
atl1_validate_option(int *value
, struct atl1_option
*opt
,
144 struct pci_dev
*pdev
)
146 if (*value
== OPTION_UNSET
) {
155 dev_info(&pdev
->dev
, "%s enabled\n", opt
->name
);
157 case OPTION_DISABLED
:
158 dev_info(&pdev
->dev
, "%s disabled\n", opt
->name
);
163 if (*value
>= opt
->arg
.r
.min
&& *value
<= opt
->arg
.r
.max
) {
164 dev_info(&pdev
->dev
, "%s set to %i\n", opt
->name
,
171 struct atl1_opt_list
*ent
;
173 for (i
= 0; i
< opt
->arg
.l
.nr
; i
++) {
174 ent
= &opt
->arg
.l
.p
[i
];
175 if (*value
== ent
->i
) {
176 if (ent
->str
[0] != '\0')
177 dev_info(&pdev
->dev
, "%s\n",
189 dev_info(&pdev
->dev
, "invalid %s specified (%i) %s\n",
190 opt
->name
, *value
, opt
->err
);
196 * atl1_check_options - Range Checking for Command Line Parameters
197 * @adapter: board private structure
199 * This routine checks all command line parameters for valid user
200 * input. If an invalid value is given, or if no user specified
201 * value exists, a default value is used. The final value is stored
202 * in a variable in the adapter structure.
204 static void __devinit
atl1_check_options(struct atl1_adapter
*adapter
)
206 struct pci_dev
*pdev
= adapter
->pdev
;
207 int bd
= adapter
->bd_number
;
208 if (bd
>= ATL1_MAX_NIC
) {
209 dev_notice(&pdev
->dev
, "no configuration for board#%i\n", bd
);
210 dev_notice(&pdev
->dev
, "using defaults for all values\n");
212 { /* Interrupt Moderate Timer */
213 struct atl1_option opt
= {
214 .type
= range_option
,
215 .name
= "Interrupt Moderator Timer",
216 .err
= "using default of "
217 __MODULE_STRING(DEFAULT_INT_MOD_CNT
),
218 .def
= DEFAULT_INT_MOD_CNT
,
219 .arg
= {.r
= {.min
= MIN_INT_MOD_CNT
,
220 .max
= MAX_INT_MOD_CNT
} }
223 if (num_int_mod_timer
> bd
) {
224 val
= int_mod_timer
[bd
];
225 atl1_validate_option(&val
, &opt
, pdev
);
226 adapter
->imt
= (u16
) val
;
228 adapter
->imt
= (u16
) (opt
.def
);
233 * atl1_pci_tbl - PCI Device ID Table
235 static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl
) = {
236 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC
, PCI_DEVICE_ID_ATTANSIC_L1
)},
237 /* required last entry */
240 MODULE_DEVICE_TABLE(pci
, atl1_pci_tbl
);
242 static const u32 atl1_default_msg
= NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
243 NETIF_MSG_LINK
| NETIF_MSG_TIMER
| NETIF_MSG_IFDOWN
| NETIF_MSG_IFUP
;
245 static int debug
= -1;
246 module_param(debug
, int, 0);
247 MODULE_PARM_DESC(debug
, "Message level (0=none,...,16=all)");
250 * Reset the transmit and receive units; mask and clear all interrupts.
251 * hw - Struct containing variables accessed by shared code
252 * return : 0 or idle status (if error)
254 static s32
atl1_reset_hw(struct atl1_hw
*hw
)
256 struct pci_dev
*pdev
= hw
->back
->pdev
;
257 struct atl1_adapter
*adapter
= hw
->back
;
262 * Clear Interrupt mask to stop board from generating
263 * interrupts & Clear any pending interrupt events
266 * iowrite32(0, hw->hw_addr + REG_IMR);
267 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
271 * Issue Soft Reset to the MAC. This will reset the chip's
272 * transmit, receive, DMA. It will not effect
273 * the current PCI configuration. The global reset bit is self-
274 * clearing, and should clear within a microsecond.
276 iowrite32(MASTER_CTRL_SOFT_RST
, hw
->hw_addr
+ REG_MASTER_CTRL
);
277 ioread32(hw
->hw_addr
+ REG_MASTER_CTRL
);
279 iowrite16(1, hw
->hw_addr
+ REG_PHY_ENABLE
);
280 ioread16(hw
->hw_addr
+ REG_PHY_ENABLE
);
282 /* delay about 1ms */
285 /* Wait at least 10ms for All module to be Idle */
286 for (i
= 0; i
< 10; i
++) {
287 icr
= ioread32(hw
->hw_addr
+ REG_IDLE_STATUS
);
292 /* FIXME: still the right way to do this? */
297 if (netif_msg_hw(adapter
))
298 dev_dbg(&pdev
->dev
, "ICR = 0x%x\n", icr
);
305 /* function about EEPROM
308 * return 0 if eeprom exist
310 static int atl1_check_eeprom_exist(struct atl1_hw
*hw
)
313 value
= ioread32(hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
314 if (value
& SPI_FLASH_CTRL_EN_VPD
) {
315 value
&= ~SPI_FLASH_CTRL_EN_VPD
;
316 iowrite32(value
, hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
319 value
= ioread16(hw
->hw_addr
+ REG_PCIE_CAP_LIST
);
320 return ((value
& 0xFF00) == 0x6C00) ? 0 : 1;
323 static bool atl1_read_eeprom(struct atl1_hw
*hw
, u32 offset
, u32
*p_value
)
329 /* address do not align */
332 iowrite32(0, hw
->hw_addr
+ REG_VPD_DATA
);
333 control
= (offset
& VPD_CAP_VPD_ADDR_MASK
) << VPD_CAP_VPD_ADDR_SHIFT
;
334 iowrite32(control
, hw
->hw_addr
+ REG_VPD_CAP
);
335 ioread32(hw
->hw_addr
+ REG_VPD_CAP
);
337 for (i
= 0; i
< 10; i
++) {
339 control
= ioread32(hw
->hw_addr
+ REG_VPD_CAP
);
340 if (control
& VPD_CAP_VPD_FLAG
)
343 if (control
& VPD_CAP_VPD_FLAG
) {
344 *p_value
= ioread32(hw
->hw_addr
+ REG_VPD_DATA
);
352 * Reads the value from a PHY register
353 * hw - Struct containing variables accessed by shared code
354 * reg_addr - address of the PHY register to read
356 s32
atl1_read_phy_reg(struct atl1_hw
*hw
, u16 reg_addr
, u16
*phy_data
)
361 val
= ((u32
) (reg_addr
& MDIO_REG_ADDR_MASK
)) << MDIO_REG_ADDR_SHIFT
|
362 MDIO_START
| MDIO_SUP_PREAMBLE
| MDIO_RW
| MDIO_CLK_25_4
<<
364 iowrite32(val
, hw
->hw_addr
+ REG_MDIO_CTRL
);
365 ioread32(hw
->hw_addr
+ REG_MDIO_CTRL
);
367 for (i
= 0; i
< MDIO_WAIT_TIMES
; i
++) {
369 val
= ioread32(hw
->hw_addr
+ REG_MDIO_CTRL
);
370 if (!(val
& (MDIO_START
| MDIO_BUSY
)))
373 if (!(val
& (MDIO_START
| MDIO_BUSY
))) {
374 *phy_data
= (u16
) val
;
380 #define CUSTOM_SPI_CS_SETUP 2
381 #define CUSTOM_SPI_CLK_HI 2
382 #define CUSTOM_SPI_CLK_LO 2
383 #define CUSTOM_SPI_CS_HOLD 2
384 #define CUSTOM_SPI_CS_HI 3
386 static bool atl1_spi_read(struct atl1_hw
*hw
, u32 addr
, u32
*buf
)
391 iowrite32(0, hw
->hw_addr
+ REG_SPI_DATA
);
392 iowrite32(addr
, hw
->hw_addr
+ REG_SPI_ADDR
);
394 value
= SPI_FLASH_CTRL_WAIT_READY
|
395 (CUSTOM_SPI_CS_SETUP
& SPI_FLASH_CTRL_CS_SETUP_MASK
) <<
396 SPI_FLASH_CTRL_CS_SETUP_SHIFT
| (CUSTOM_SPI_CLK_HI
&
397 SPI_FLASH_CTRL_CLK_HI_MASK
) <<
398 SPI_FLASH_CTRL_CLK_HI_SHIFT
| (CUSTOM_SPI_CLK_LO
&
399 SPI_FLASH_CTRL_CLK_LO_MASK
) <<
400 SPI_FLASH_CTRL_CLK_LO_SHIFT
| (CUSTOM_SPI_CS_HOLD
&
401 SPI_FLASH_CTRL_CS_HOLD_MASK
) <<
402 SPI_FLASH_CTRL_CS_HOLD_SHIFT
| (CUSTOM_SPI_CS_HI
&
403 SPI_FLASH_CTRL_CS_HI_MASK
) <<
404 SPI_FLASH_CTRL_CS_HI_SHIFT
| (1 & SPI_FLASH_CTRL_INS_MASK
) <<
405 SPI_FLASH_CTRL_INS_SHIFT
;
407 iowrite32(value
, hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
409 value
|= SPI_FLASH_CTRL_START
;
410 iowrite32(value
, hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
411 ioread32(hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
413 for (i
= 0; i
< 10; i
++) {
415 value
= ioread32(hw
->hw_addr
+ REG_SPI_FLASH_CTRL
);
416 if (!(value
& SPI_FLASH_CTRL_START
))
420 if (value
& SPI_FLASH_CTRL_START
)
423 *buf
= ioread32(hw
->hw_addr
+ REG_SPI_DATA
);
429 * get_permanent_address
430 * return 0 if get valid mac address,
432 static int atl1_get_permanent_address(struct atl1_hw
*hw
)
437 u8 eth_addr
[ETH_ALEN
];
440 if (is_valid_ether_addr(hw
->perm_mac_addr
))
444 addr
[0] = addr
[1] = 0;
446 if (!atl1_check_eeprom_exist(hw
)) {
449 /* Read out all EEPROM content */
452 if (atl1_read_eeprom(hw
, i
+ 0x100, &control
)) {
454 if (reg
== REG_MAC_STA_ADDR
)
456 else if (reg
== (REG_MAC_STA_ADDR
+ 4))
459 } else if ((control
& 0xff) == 0x5A) {
461 reg
= (u16
) (control
>> 16);
470 *(u32
*) ð_addr
[2] = swab32(addr
[0]);
471 *(u16
*) ð_addr
[0] = swab16(*(u16
*) &addr
[1]);
472 if (is_valid_ether_addr(eth_addr
)) {
473 memcpy(hw
->perm_mac_addr
, eth_addr
, ETH_ALEN
);
478 /* see if SPI FLAGS exist ? */
479 addr
[0] = addr
[1] = 0;
484 if (atl1_spi_read(hw
, i
+ 0x1f000, &control
)) {
486 if (reg
== REG_MAC_STA_ADDR
)
488 else if (reg
== (REG_MAC_STA_ADDR
+ 4))
491 } else if ((control
& 0xff) == 0x5A) {
493 reg
= (u16
) (control
>> 16);
503 *(u32
*) ð_addr
[2] = swab32(addr
[0]);
504 *(u16
*) ð_addr
[0] = swab16(*(u16
*) &addr
[1]);
505 if (is_valid_ether_addr(eth_addr
)) {
506 memcpy(hw
->perm_mac_addr
, eth_addr
, ETH_ALEN
);
511 * On some motherboards, the MAC address is written by the
512 * BIOS directly to the MAC register during POST, and is
513 * not stored in eeprom. If all else thus far has failed
514 * to fetch the permanent MAC address, try reading it directly.
516 addr
[0] = ioread32(hw
->hw_addr
+ REG_MAC_STA_ADDR
);
517 addr
[1] = ioread16(hw
->hw_addr
+ (REG_MAC_STA_ADDR
+ 4));
518 *(u32
*) ð_addr
[2] = swab32(addr
[0]);
519 *(u16
*) ð_addr
[0] = swab16(*(u16
*) &addr
[1]);
520 if (is_valid_ether_addr(eth_addr
)) {
521 memcpy(hw
->perm_mac_addr
, eth_addr
, ETH_ALEN
);
529 * Reads the adapter's MAC address from the EEPROM
530 * hw - Struct containing variables accessed by shared code
532 static s32
atl1_read_mac_addr(struct atl1_hw
*hw
)
536 if (atl1_get_permanent_address(hw
))
537 random_ether_addr(hw
->perm_mac_addr
);
539 for (i
= 0; i
< ETH_ALEN
; i
++)
540 hw
->mac_addr
[i
] = hw
->perm_mac_addr
[i
];
545 * Hashes an address to determine its location in the multicast table
546 * hw - Struct containing variables accessed by shared code
547 * mc_addr - the multicast address to hash
551 * set hash value for a multicast address
552 * hash calcu processing :
553 * 1. calcu 32bit CRC for multicast address
554 * 2. reverse crc with MSB to LSB
556 u32
atl1_hash_mc_addr(struct atl1_hw
*hw
, u8
*mc_addr
)
558 u32 crc32
, value
= 0;
561 crc32
= ether_crc_le(6, mc_addr
);
562 for (i
= 0; i
< 32; i
++)
563 value
|= (((crc32
>> i
) & 1) << (31 - i
));
569 * Sets the bit in the multicast table corresponding to the hash value.
570 * hw - Struct containing variables accessed by shared code
571 * hash_value - Multicast address hash value
573 void atl1_hash_set(struct atl1_hw
*hw
, u32 hash_value
)
575 u32 hash_bit
, hash_reg
;
579 * The HASH Table is a register array of 2 32-bit registers.
580 * It is treated like an array of 64 bits. We want to set
581 * bit BitArray[hash_value]. So we figure out what register
582 * the bit is in, read it, OR in the new bit, then write
583 * back the new value. The register is determined by the
584 * upper 7 bits of the hash value and the bit within that
585 * register are determined by the lower 5 bits of the value.
587 hash_reg
= (hash_value
>> 31) & 0x1;
588 hash_bit
= (hash_value
>> 26) & 0x1F;
589 mta
= ioread32((hw
->hw_addr
+ REG_RX_HASH_TABLE
) + (hash_reg
<< 2));
590 mta
|= (1 << hash_bit
);
591 iowrite32(mta
, (hw
->hw_addr
+ REG_RX_HASH_TABLE
) + (hash_reg
<< 2));
595 * Writes a value to a PHY register
596 * hw - Struct containing variables accessed by shared code
597 * reg_addr - address of the PHY register to write
598 * data - data to write to the PHY
600 static s32
atl1_write_phy_reg(struct atl1_hw
*hw
, u32 reg_addr
, u16 phy_data
)
605 val
= ((u32
) (phy_data
& MDIO_DATA_MASK
)) << MDIO_DATA_SHIFT
|
606 (reg_addr
& MDIO_REG_ADDR_MASK
) << MDIO_REG_ADDR_SHIFT
|
608 MDIO_START
| MDIO_CLK_25_4
<< MDIO_CLK_SEL_SHIFT
;
609 iowrite32(val
, hw
->hw_addr
+ REG_MDIO_CTRL
);
610 ioread32(hw
->hw_addr
+ REG_MDIO_CTRL
);
612 for (i
= 0; i
< MDIO_WAIT_TIMES
; i
++) {
614 val
= ioread32(hw
->hw_addr
+ REG_MDIO_CTRL
);
615 if (!(val
& (MDIO_START
| MDIO_BUSY
)))
619 if (!(val
& (MDIO_START
| MDIO_BUSY
)))
626 * Make L001's PHY out of Power Saving State (bug)
627 * hw - Struct containing variables accessed by shared code
628 * when power on, L001's PHY always on Power saving State
629 * (Gigabit Link forbidden)
631 static s32
atl1_phy_leave_power_saving(struct atl1_hw
*hw
)
634 ret
= atl1_write_phy_reg(hw
, 29, 0x0029);
637 return atl1_write_phy_reg(hw
, 30, 0);
641 * Resets the PHY and make all config validate
642 * hw - Struct containing variables accessed by shared code
644 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
646 static s32
atl1_phy_reset(struct atl1_hw
*hw
)
648 struct pci_dev
*pdev
= hw
->back
->pdev
;
649 struct atl1_adapter
*adapter
= hw
->back
;
653 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
654 hw
->media_type
== MEDIA_TYPE_1000M_FULL
)
655 phy_data
= MII_CR_RESET
| MII_CR_AUTO_NEG_EN
;
657 switch (hw
->media_type
) {
658 case MEDIA_TYPE_100M_FULL
:
660 MII_CR_FULL_DUPLEX
| MII_CR_SPEED_100
|
663 case MEDIA_TYPE_100M_HALF
:
664 phy_data
= MII_CR_SPEED_100
| MII_CR_RESET
;
666 case MEDIA_TYPE_10M_FULL
:
668 MII_CR_FULL_DUPLEX
| MII_CR_SPEED_10
| MII_CR_RESET
;
671 /* MEDIA_TYPE_10M_HALF: */
672 phy_data
= MII_CR_SPEED_10
| MII_CR_RESET
;
677 ret_val
= atl1_write_phy_reg(hw
, MII_BMCR
, phy_data
);
681 /* pcie serdes link may be down! */
682 if (netif_msg_hw(adapter
))
683 dev_dbg(&pdev
->dev
, "pcie phy link down\n");
685 for (i
= 0; i
< 25; i
++) {
687 val
= ioread32(hw
->hw_addr
+ REG_MDIO_CTRL
);
688 if (!(val
& (MDIO_START
| MDIO_BUSY
)))
692 if ((val
& (MDIO_START
| MDIO_BUSY
)) != 0) {
693 if (netif_msg_hw(adapter
))
695 "pcie link down at least 25ms\n");
703 * Configures PHY autoneg and flow control advertisement settings
704 * hw - Struct containing variables accessed by shared code
706 static s32
atl1_phy_setup_autoneg_adv(struct atl1_hw
*hw
)
709 s16 mii_autoneg_adv_reg
;
710 s16 mii_1000t_ctrl_reg
;
712 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
713 mii_autoneg_adv_reg
= MII_AR_DEFAULT_CAP_MASK
;
715 /* Read the MII 1000Base-T Control Register (Address 9). */
716 mii_1000t_ctrl_reg
= MII_ATLX_CR_1000T_DEFAULT_CAP_MASK
;
719 * First we clear all the 10/100 mb speed bits in the Auto-Neg
720 * Advertisement Register (Address 4) and the 1000 mb speed bits in
721 * the 1000Base-T Control Register (Address 9).
723 mii_autoneg_adv_reg
&= ~MII_AR_SPEED_MASK
;
724 mii_1000t_ctrl_reg
&= ~MII_ATLX_CR_1000T_SPEED_MASK
;
727 * Need to parse media_type and set up
728 * the appropriate PHY registers.
730 switch (hw
->media_type
) {
731 case MEDIA_TYPE_AUTO_SENSOR
:
732 mii_autoneg_adv_reg
|= (MII_AR_10T_HD_CAPS
|
734 MII_AR_100TX_HD_CAPS
|
735 MII_AR_100TX_FD_CAPS
);
736 mii_1000t_ctrl_reg
|= MII_ATLX_CR_1000T_FD_CAPS
;
739 case MEDIA_TYPE_1000M_FULL
:
740 mii_1000t_ctrl_reg
|= MII_ATLX_CR_1000T_FD_CAPS
;
743 case MEDIA_TYPE_100M_FULL
:
744 mii_autoneg_adv_reg
|= MII_AR_100TX_FD_CAPS
;
747 case MEDIA_TYPE_100M_HALF
:
748 mii_autoneg_adv_reg
|= MII_AR_100TX_HD_CAPS
;
751 case MEDIA_TYPE_10M_FULL
:
752 mii_autoneg_adv_reg
|= MII_AR_10T_FD_CAPS
;
756 mii_autoneg_adv_reg
|= MII_AR_10T_HD_CAPS
;
760 /* flow control fixed to enable all */
761 mii_autoneg_adv_reg
|= (MII_AR_ASM_DIR
| MII_AR_PAUSE
);
763 hw
->mii_autoneg_adv_reg
= mii_autoneg_adv_reg
;
764 hw
->mii_1000t_ctrl_reg
= mii_1000t_ctrl_reg
;
766 ret_val
= atl1_write_phy_reg(hw
, MII_ADVERTISE
, mii_autoneg_adv_reg
);
770 ret_val
= atl1_write_phy_reg(hw
, MII_ATLX_CR
, mii_1000t_ctrl_reg
);
778 * Configures link settings.
779 * hw - Struct containing variables accessed by shared code
780 * Assumes the hardware has previously been reset and the
781 * transmitter and receiver are not enabled.
783 static s32
atl1_setup_link(struct atl1_hw
*hw
)
785 struct pci_dev
*pdev
= hw
->back
->pdev
;
786 struct atl1_adapter
*adapter
= hw
->back
;
791 * PHY will advertise value(s) parsed from
792 * autoneg_advertised and fc
793 * no matter what autoneg is , We will not wait link result.
795 ret_val
= atl1_phy_setup_autoneg_adv(hw
);
797 if (netif_msg_link(adapter
))
799 "error setting up autonegotiation\n");
802 /* SW.Reset , En-Auto-Neg if needed */
803 ret_val
= atl1_phy_reset(hw
);
805 if (netif_msg_link(adapter
))
806 dev_dbg(&pdev
->dev
, "error resetting phy\n");
809 hw
->phy_configured
= true;
813 static void atl1_init_flash_opcode(struct atl1_hw
*hw
)
815 if (hw
->flash_vendor
>= ARRAY_SIZE(flash_table
))
817 hw
->flash_vendor
= 0;
820 iowrite8(flash_table
[hw
->flash_vendor
].cmd_program
,
821 hw
->hw_addr
+ REG_SPI_FLASH_OP_PROGRAM
);
822 iowrite8(flash_table
[hw
->flash_vendor
].cmd_sector_erase
,
823 hw
->hw_addr
+ REG_SPI_FLASH_OP_SC_ERASE
);
824 iowrite8(flash_table
[hw
->flash_vendor
].cmd_chip_erase
,
825 hw
->hw_addr
+ REG_SPI_FLASH_OP_CHIP_ERASE
);
826 iowrite8(flash_table
[hw
->flash_vendor
].cmd_rdid
,
827 hw
->hw_addr
+ REG_SPI_FLASH_OP_RDID
);
828 iowrite8(flash_table
[hw
->flash_vendor
].cmd_wren
,
829 hw
->hw_addr
+ REG_SPI_FLASH_OP_WREN
);
830 iowrite8(flash_table
[hw
->flash_vendor
].cmd_rdsr
,
831 hw
->hw_addr
+ REG_SPI_FLASH_OP_RDSR
);
832 iowrite8(flash_table
[hw
->flash_vendor
].cmd_wrsr
,
833 hw
->hw_addr
+ REG_SPI_FLASH_OP_WRSR
);
834 iowrite8(flash_table
[hw
->flash_vendor
].cmd_read
,
835 hw
->hw_addr
+ REG_SPI_FLASH_OP_READ
);
839 * Performs basic configuration of the adapter.
840 * hw - Struct containing variables accessed by shared code
841 * Assumes that the controller has previously been reset and is in a
842 * post-reset uninitialized state. Initializes multicast table,
843 * and Calls routines to setup link
844 * Leaves the transmit and receive units disabled and uninitialized.
846 static s32
atl1_init_hw(struct atl1_hw
*hw
)
850 /* Zero out the Multicast HASH table */
851 iowrite32(0, hw
->hw_addr
+ REG_RX_HASH_TABLE
);
852 /* clear the old settings from the multicast hash table */
853 iowrite32(0, (hw
->hw_addr
+ REG_RX_HASH_TABLE
) + (1 << 2));
855 atl1_init_flash_opcode(hw
);
857 if (!hw
->phy_configured
) {
858 /* enable GPHY LinkChange Interrrupt */
859 ret_val
= atl1_write_phy_reg(hw
, 18, 0xC00);
862 /* make PHY out of power-saving state */
863 ret_val
= atl1_phy_leave_power_saving(hw
);
866 /* Call a subroutine to configure the link */
867 ret_val
= atl1_setup_link(hw
);
873 * Detects the current speed and duplex settings of the hardware.
874 * hw - Struct containing variables accessed by shared code
875 * speed - Speed of the connection
876 * duplex - Duplex setting of the connection
878 static s32
atl1_get_speed_and_duplex(struct atl1_hw
*hw
, u16
*speed
, u16
*duplex
)
880 struct pci_dev
*pdev
= hw
->back
->pdev
;
881 struct atl1_adapter
*adapter
= hw
->back
;
885 /* ; --- Read PHY Specific Status Register (17) */
886 ret_val
= atl1_read_phy_reg(hw
, MII_ATLX_PSSR
, &phy_data
);
890 if (!(phy_data
& MII_ATLX_PSSR_SPD_DPLX_RESOLVED
))
891 return ATLX_ERR_PHY_RES
;
893 switch (phy_data
& MII_ATLX_PSSR_SPEED
) {
894 case MII_ATLX_PSSR_1000MBS
:
897 case MII_ATLX_PSSR_100MBS
:
900 case MII_ATLX_PSSR_10MBS
:
904 if (netif_msg_hw(adapter
))
905 dev_dbg(&pdev
->dev
, "error getting speed\n");
906 return ATLX_ERR_PHY_SPEED
;
909 if (phy_data
& MII_ATLX_PSSR_DPLX
)
910 *duplex
= FULL_DUPLEX
;
912 *duplex
= HALF_DUPLEX
;
917 void atl1_set_mac_addr(struct atl1_hw
*hw
)
922 * 0: 6AF600DC 1: 000B
925 value
= (((u32
) hw
->mac_addr
[2]) << 24) |
926 (((u32
) hw
->mac_addr
[3]) << 16) |
927 (((u32
) hw
->mac_addr
[4]) << 8) | (((u32
) hw
->mac_addr
[5]));
928 iowrite32(value
, hw
->hw_addr
+ REG_MAC_STA_ADDR
);
930 value
= (((u32
) hw
->mac_addr
[0]) << 8) | (((u32
) hw
->mac_addr
[1]));
931 iowrite32(value
, (hw
->hw_addr
+ REG_MAC_STA_ADDR
) + (1 << 2));
935 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
936 * @adapter: board private structure to initialize
938 * atl1_sw_init initializes the Adapter private data structure.
939 * Fields are initialized based on PCI device information and
940 * OS network device settings (MTU size).
942 static int __devinit
atl1_sw_init(struct atl1_adapter
*adapter
)
944 struct atl1_hw
*hw
= &adapter
->hw
;
945 struct net_device
*netdev
= adapter
->netdev
;
947 hw
->max_frame_size
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
948 hw
->min_frame_size
= ETH_ZLEN
+ ETH_FCS_LEN
;
951 adapter
->rx_buffer_len
= (hw
->max_frame_size
+ 7) & ~7;
952 adapter
->ict
= 50000; /* 100ms */
953 adapter
->link_speed
= SPEED_0
; /* hardware init */
954 adapter
->link_duplex
= FULL_DUPLEX
;
956 hw
->phy_configured
= false;
957 hw
->preamble_len
= 7;
967 hw
->rfd_fetch_gap
= 1;
968 hw
->rx_jumbo_th
= adapter
->rx_buffer_len
/ 8;
969 hw
->rx_jumbo_lkah
= 1;
970 hw
->rrd_ret_timer
= 16;
972 hw
->tpd_fetch_th
= 16;
973 hw
->txf_burst
= 0x100;
974 hw
->tx_jumbo_task_th
= (hw
->max_frame_size
+ 7) >> 3;
975 hw
->tpd_fetch_gap
= 1;
976 hw
->rcb_value
= atl1_rcb_64
;
977 hw
->dma_ord
= atl1_dma_ord_enh
;
978 hw
->dmar_block
= atl1_dma_req_256
;
979 hw
->dmaw_block
= atl1_dma_req_256
;
982 hw
->cmb_rx_timer
= 1; /* about 2us */
983 hw
->cmb_tx_timer
= 1; /* about 2us */
984 hw
->smb_timer
= 100000; /* about 200ms */
986 spin_lock_init(&adapter
->lock
);
987 spin_lock_init(&adapter
->mb_lock
);
992 static int mdio_read(struct net_device
*netdev
, int phy_id
, int reg_num
)
994 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
997 atl1_read_phy_reg(&adapter
->hw
, reg_num
& 0x1f, &result
);
1002 static void mdio_write(struct net_device
*netdev
, int phy_id
, int reg_num
,
1005 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
1007 atl1_write_phy_reg(&adapter
->hw
, reg_num
, val
);
1016 static int atl1_mii_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
1018 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
1019 unsigned long flags
;
1022 if (!netif_running(netdev
))
1025 spin_lock_irqsave(&adapter
->lock
, flags
);
1026 retval
= generic_mii_ioctl(&adapter
->mii
, if_mii(ifr
), cmd
, NULL
);
1027 spin_unlock_irqrestore(&adapter
->lock
, flags
);
1033 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1034 * @adapter: board private structure
1036 * Return 0 on success, negative on failure
1038 static s32
atl1_setup_ring_resources(struct atl1_adapter
*adapter
)
1040 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
1041 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1042 struct atl1_rrd_ring
*rrd_ring
= &adapter
->rrd_ring
;
1043 struct atl1_ring_header
*ring_header
= &adapter
->ring_header
;
1044 struct pci_dev
*pdev
= adapter
->pdev
;
1048 size
= sizeof(struct atl1_buffer
) * (tpd_ring
->count
+ rfd_ring
->count
);
1049 tpd_ring
->buffer_info
= kzalloc(size
, GFP_KERNEL
);
1050 if (unlikely(!tpd_ring
->buffer_info
)) {
1051 if (netif_msg_drv(adapter
))
1052 dev_err(&pdev
->dev
, "kzalloc failed , size = D%d\n",
1056 rfd_ring
->buffer_info
=
1057 (struct atl1_buffer
*)(tpd_ring
->buffer_info
+ tpd_ring
->count
);
1060 * real ring DMA buffer
1061 * each ring/block may need up to 8 bytes for alignment, hence the
1062 * additional 40 bytes tacked onto the end.
1064 ring_header
->size
= size
=
1065 sizeof(struct tx_packet_desc
) * tpd_ring
->count
1066 + sizeof(struct rx_free_desc
) * rfd_ring
->count
1067 + sizeof(struct rx_return_desc
) * rrd_ring
->count
1068 + sizeof(struct coals_msg_block
)
1069 + sizeof(struct stats_msg_block
)
1072 ring_header
->desc
= pci_alloc_consistent(pdev
, ring_header
->size
,
1074 if (unlikely(!ring_header
->desc
)) {
1075 if (netif_msg_drv(adapter
))
1076 dev_err(&pdev
->dev
, "pci_alloc_consistent failed\n");
1080 memset(ring_header
->desc
, 0, ring_header
->size
);
1083 tpd_ring
->dma
= ring_header
->dma
;
1084 offset
= (tpd_ring
->dma
& 0x7) ? (8 - (ring_header
->dma
& 0x7)) : 0;
1085 tpd_ring
->dma
+= offset
;
1086 tpd_ring
->desc
= (u8
*) ring_header
->desc
+ offset
;
1087 tpd_ring
->size
= sizeof(struct tx_packet_desc
) * tpd_ring
->count
;
1090 rfd_ring
->dma
= tpd_ring
->dma
+ tpd_ring
->size
;
1091 offset
= (rfd_ring
->dma
& 0x7) ? (8 - (rfd_ring
->dma
& 0x7)) : 0;
1092 rfd_ring
->dma
+= offset
;
1093 rfd_ring
->desc
= (u8
*) tpd_ring
->desc
+ (tpd_ring
->size
+ offset
);
1094 rfd_ring
->size
= sizeof(struct rx_free_desc
) * rfd_ring
->count
;
1098 rrd_ring
->dma
= rfd_ring
->dma
+ rfd_ring
->size
;
1099 offset
= (rrd_ring
->dma
& 0x7) ? (8 - (rrd_ring
->dma
& 0x7)) : 0;
1100 rrd_ring
->dma
+= offset
;
1101 rrd_ring
->desc
= (u8
*) rfd_ring
->desc
+ (rfd_ring
->size
+ offset
);
1102 rrd_ring
->size
= sizeof(struct rx_return_desc
) * rrd_ring
->count
;
1106 adapter
->cmb
.dma
= rrd_ring
->dma
+ rrd_ring
->size
;
1107 offset
= (adapter
->cmb
.dma
& 0x7) ? (8 - (adapter
->cmb
.dma
& 0x7)) : 0;
1108 adapter
->cmb
.dma
+= offset
;
1109 adapter
->cmb
.cmb
= (struct coals_msg_block
*)
1110 ((u8
*) rrd_ring
->desc
+ (rrd_ring
->size
+ offset
));
1113 adapter
->smb
.dma
= adapter
->cmb
.dma
+ sizeof(struct coals_msg_block
);
1114 offset
= (adapter
->smb
.dma
& 0x7) ? (8 - (adapter
->smb
.dma
& 0x7)) : 0;
1115 adapter
->smb
.dma
+= offset
;
1116 adapter
->smb
.smb
= (struct stats_msg_block
*)
1117 ((u8
*) adapter
->cmb
.cmb
+
1118 (sizeof(struct coals_msg_block
) + offset
));
1123 kfree(tpd_ring
->buffer_info
);
1127 static void atl1_init_ring_ptrs(struct atl1_adapter
*adapter
)
1129 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
1130 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1131 struct atl1_rrd_ring
*rrd_ring
= &adapter
->rrd_ring
;
1133 atomic_set(&tpd_ring
->next_to_use
, 0);
1134 atomic_set(&tpd_ring
->next_to_clean
, 0);
1136 rfd_ring
->next_to_clean
= 0;
1137 atomic_set(&rfd_ring
->next_to_use
, 0);
1139 rrd_ring
->next_to_use
= 0;
1140 atomic_set(&rrd_ring
->next_to_clean
, 0);
1144 * atl1_clean_rx_ring - Free RFD Buffers
1145 * @adapter: board private structure
1147 static void atl1_clean_rx_ring(struct atl1_adapter
*adapter
)
1149 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1150 struct atl1_rrd_ring
*rrd_ring
= &adapter
->rrd_ring
;
1151 struct atl1_buffer
*buffer_info
;
1152 struct pci_dev
*pdev
= adapter
->pdev
;
1156 /* Free all the Rx ring sk_buffs */
1157 for (i
= 0; i
< rfd_ring
->count
; i
++) {
1158 buffer_info
= &rfd_ring
->buffer_info
[i
];
1159 if (buffer_info
->dma
) {
1160 pci_unmap_page(pdev
, buffer_info
->dma
,
1161 buffer_info
->length
, PCI_DMA_FROMDEVICE
);
1162 buffer_info
->dma
= 0;
1164 if (buffer_info
->skb
) {
1165 dev_kfree_skb(buffer_info
->skb
);
1166 buffer_info
->skb
= NULL
;
1170 size
= sizeof(struct atl1_buffer
) * rfd_ring
->count
;
1171 memset(rfd_ring
->buffer_info
, 0, size
);
1173 /* Zero out the descriptor ring */
1174 memset(rfd_ring
->desc
, 0, rfd_ring
->size
);
1176 rfd_ring
->next_to_clean
= 0;
1177 atomic_set(&rfd_ring
->next_to_use
, 0);
1179 rrd_ring
->next_to_use
= 0;
1180 atomic_set(&rrd_ring
->next_to_clean
, 0);
1184 * atl1_clean_tx_ring - Free Tx Buffers
1185 * @adapter: board private structure
1187 static void atl1_clean_tx_ring(struct atl1_adapter
*adapter
)
1189 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
1190 struct atl1_buffer
*buffer_info
;
1191 struct pci_dev
*pdev
= adapter
->pdev
;
1195 /* Free all the Tx ring sk_buffs */
1196 for (i
= 0; i
< tpd_ring
->count
; i
++) {
1197 buffer_info
= &tpd_ring
->buffer_info
[i
];
1198 if (buffer_info
->dma
) {
1199 pci_unmap_page(pdev
, buffer_info
->dma
,
1200 buffer_info
->length
, PCI_DMA_TODEVICE
);
1201 buffer_info
->dma
= 0;
1205 for (i
= 0; i
< tpd_ring
->count
; i
++) {
1206 buffer_info
= &tpd_ring
->buffer_info
[i
];
1207 if (buffer_info
->skb
) {
1208 dev_kfree_skb_any(buffer_info
->skb
);
1209 buffer_info
->skb
= NULL
;
1213 size
= sizeof(struct atl1_buffer
) * tpd_ring
->count
;
1214 memset(tpd_ring
->buffer_info
, 0, size
);
1216 /* Zero out the descriptor ring */
1217 memset(tpd_ring
->desc
, 0, tpd_ring
->size
);
1219 atomic_set(&tpd_ring
->next_to_use
, 0);
1220 atomic_set(&tpd_ring
->next_to_clean
, 0);
1224 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1225 * @adapter: board private structure
1227 * Free all transmit software resources
1229 static void atl1_free_ring_resources(struct atl1_adapter
*adapter
)
1231 struct pci_dev
*pdev
= adapter
->pdev
;
1232 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
1233 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1234 struct atl1_rrd_ring
*rrd_ring
= &adapter
->rrd_ring
;
1235 struct atl1_ring_header
*ring_header
= &adapter
->ring_header
;
1237 atl1_clean_tx_ring(adapter
);
1238 atl1_clean_rx_ring(adapter
);
1240 kfree(tpd_ring
->buffer_info
);
1241 pci_free_consistent(pdev
, ring_header
->size
, ring_header
->desc
,
1244 tpd_ring
->buffer_info
= NULL
;
1245 tpd_ring
->desc
= NULL
;
1248 rfd_ring
->buffer_info
= NULL
;
1249 rfd_ring
->desc
= NULL
;
1252 rrd_ring
->desc
= NULL
;
1255 adapter
->cmb
.dma
= 0;
1256 adapter
->cmb
.cmb
= NULL
;
1258 adapter
->smb
.dma
= 0;
1259 adapter
->smb
.smb
= NULL
;
1262 static void atl1_setup_mac_ctrl(struct atl1_adapter
*adapter
)
1265 struct atl1_hw
*hw
= &adapter
->hw
;
1266 struct net_device
*netdev
= adapter
->netdev
;
1267 /* Config MAC CTRL Register */
1268 value
= MAC_CTRL_TX_EN
| MAC_CTRL_RX_EN
;
1270 if (FULL_DUPLEX
== adapter
->link_duplex
)
1271 value
|= MAC_CTRL_DUPLX
;
1273 value
|= ((u32
) ((SPEED_1000
== adapter
->link_speed
) ?
1274 MAC_CTRL_SPEED_1000
: MAC_CTRL_SPEED_10_100
) <<
1275 MAC_CTRL_SPEED_SHIFT
);
1277 value
|= (MAC_CTRL_TX_FLOW
| MAC_CTRL_RX_FLOW
);
1279 value
|= (MAC_CTRL_ADD_CRC
| MAC_CTRL_PAD
);
1280 /* preamble length */
1281 value
|= (((u32
) adapter
->hw
.preamble_len
1282 & MAC_CTRL_PRMLEN_MASK
) << MAC_CTRL_PRMLEN_SHIFT
);
1285 value
|= MAC_CTRL_RMV_VLAN
;
1287 if (adapter->rx_csum)
1288 value |= MAC_CTRL_RX_CHKSUM_EN;
1291 value
|= MAC_CTRL_BC_EN
;
1292 if (netdev
->flags
& IFF_PROMISC
)
1293 value
|= MAC_CTRL_PROMIS_EN
;
1294 else if (netdev
->flags
& IFF_ALLMULTI
)
1295 value
|= MAC_CTRL_MC_ALL_EN
;
1296 /* value |= MAC_CTRL_LOOPBACK; */
1297 iowrite32(value
, hw
->hw_addr
+ REG_MAC_CTRL
);
1300 static u32
atl1_check_link(struct atl1_adapter
*adapter
)
1302 struct atl1_hw
*hw
= &adapter
->hw
;
1303 struct net_device
*netdev
= adapter
->netdev
;
1305 u16 speed
, duplex
, phy_data
;
1308 /* MII_BMSR must read twice */
1309 atl1_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
1310 atl1_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
1311 if (!(phy_data
& BMSR_LSTATUS
)) {
1313 if (netif_carrier_ok(netdev
)) {
1314 /* old link state: Up */
1315 if (netif_msg_link(adapter
))
1316 dev_info(&adapter
->pdev
->dev
, "link is down\n");
1317 adapter
->link_speed
= SPEED_0
;
1318 netif_carrier_off(netdev
);
1324 ret_val
= atl1_get_speed_and_duplex(hw
, &speed
, &duplex
);
1328 switch (hw
->media_type
) {
1329 case MEDIA_TYPE_1000M_FULL
:
1330 if (speed
!= SPEED_1000
|| duplex
!= FULL_DUPLEX
)
1333 case MEDIA_TYPE_100M_FULL
:
1334 if (speed
!= SPEED_100
|| duplex
!= FULL_DUPLEX
)
1337 case MEDIA_TYPE_100M_HALF
:
1338 if (speed
!= SPEED_100
|| duplex
!= HALF_DUPLEX
)
1341 case MEDIA_TYPE_10M_FULL
:
1342 if (speed
!= SPEED_10
|| duplex
!= FULL_DUPLEX
)
1345 case MEDIA_TYPE_10M_HALF
:
1346 if (speed
!= SPEED_10
|| duplex
!= HALF_DUPLEX
)
1351 /* link result is our setting */
1353 if (adapter
->link_speed
!= speed
||
1354 adapter
->link_duplex
!= duplex
) {
1355 adapter
->link_speed
= speed
;
1356 adapter
->link_duplex
= duplex
;
1357 atl1_setup_mac_ctrl(adapter
);
1358 if (netif_msg_link(adapter
))
1359 dev_info(&adapter
->pdev
->dev
,
1360 "%s link is up %d Mbps %s\n",
1361 netdev
->name
, adapter
->link_speed
,
1362 adapter
->link_duplex
== FULL_DUPLEX
?
1363 "full duplex" : "half duplex");
1365 if (!netif_carrier_ok(netdev
)) {
1366 /* Link down -> Up */
1367 netif_carrier_on(netdev
);
1372 /* change original link status */
1373 if (netif_carrier_ok(netdev
)) {
1374 adapter
->link_speed
= SPEED_0
;
1375 netif_carrier_off(netdev
);
1376 netif_stop_queue(netdev
);
1379 if (hw
->media_type
!= MEDIA_TYPE_AUTO_SENSOR
&&
1380 hw
->media_type
!= MEDIA_TYPE_1000M_FULL
) {
1381 switch (hw
->media_type
) {
1382 case MEDIA_TYPE_100M_FULL
:
1383 phy_data
= MII_CR_FULL_DUPLEX
| MII_CR_SPEED_100
|
1386 case MEDIA_TYPE_100M_HALF
:
1387 phy_data
= MII_CR_SPEED_100
| MII_CR_RESET
;
1389 case MEDIA_TYPE_10M_FULL
:
1391 MII_CR_FULL_DUPLEX
| MII_CR_SPEED_10
| MII_CR_RESET
;
1394 /* MEDIA_TYPE_10M_HALF: */
1395 phy_data
= MII_CR_SPEED_10
| MII_CR_RESET
;
1398 atl1_write_phy_reg(hw
, MII_BMCR
, phy_data
);
1402 /* auto-neg, insert timer to re-config phy */
1403 if (!adapter
->phy_timer_pending
) {
1404 adapter
->phy_timer_pending
= true;
1405 mod_timer(&adapter
->phy_config_timer
,
1406 round_jiffies(jiffies
+ 3 * HZ
));
1412 static void set_flow_ctrl_old(struct atl1_adapter
*adapter
)
1416 /* RFD Flow Control */
1417 value
= adapter
->rfd_ring
.count
;
1423 value
= ((hi
& RXQ_RXF_PAUSE_TH_HI_MASK
) << RXQ_RXF_PAUSE_TH_HI_SHIFT
) |
1424 ((lo
& RXQ_RXF_PAUSE_TH_LO_MASK
) << RXQ_RXF_PAUSE_TH_LO_SHIFT
);
1425 iowrite32(value
, adapter
->hw
.hw_addr
+ REG_RXQ_RXF_PAUSE_THRESH
);
1427 /* RRD Flow Control */
1428 value
= adapter
->rrd_ring
.count
;
1433 value
= ((hi
& RXQ_RRD_PAUSE_TH_HI_MASK
) << RXQ_RRD_PAUSE_TH_HI_SHIFT
) |
1434 ((lo
& RXQ_RRD_PAUSE_TH_LO_MASK
) << RXQ_RRD_PAUSE_TH_LO_SHIFT
);
1435 iowrite32(value
, adapter
->hw
.hw_addr
+ REG_RXQ_RRD_PAUSE_THRESH
);
1438 static void set_flow_ctrl_new(struct atl1_hw
*hw
)
1442 /* RXF Flow Control */
1443 value
= ioread32(hw
->hw_addr
+ REG_SRAM_RXF_LEN
);
1450 value
= ((hi
& RXQ_RXF_PAUSE_TH_HI_MASK
) << RXQ_RXF_PAUSE_TH_HI_SHIFT
) |
1451 ((lo
& RXQ_RXF_PAUSE_TH_LO_MASK
) << RXQ_RXF_PAUSE_TH_LO_SHIFT
);
1452 iowrite32(value
, hw
->hw_addr
+ REG_RXQ_RXF_PAUSE_THRESH
);
1454 /* RRD Flow Control */
1455 value
= ioread32(hw
->hw_addr
+ REG_SRAM_RRD_LEN
);
1462 value
= ((hi
& RXQ_RRD_PAUSE_TH_HI_MASK
) << RXQ_RRD_PAUSE_TH_HI_SHIFT
) |
1463 ((lo
& RXQ_RRD_PAUSE_TH_LO_MASK
) << RXQ_RRD_PAUSE_TH_LO_SHIFT
);
1464 iowrite32(value
, hw
->hw_addr
+ REG_RXQ_RRD_PAUSE_THRESH
);
1468 * atl1_configure - Configure Transmit&Receive Unit after Reset
1469 * @adapter: board private structure
1471 * Configure the Tx /Rx unit of the MAC after a reset.
1473 static u32
atl1_configure(struct atl1_adapter
*adapter
)
1475 struct atl1_hw
*hw
= &adapter
->hw
;
1478 /* clear interrupt status */
1479 iowrite32(0xffffffff, adapter
->hw
.hw_addr
+ REG_ISR
);
1481 /* set MAC Address */
1482 value
= (((u32
) hw
->mac_addr
[2]) << 24) |
1483 (((u32
) hw
->mac_addr
[3]) << 16) |
1484 (((u32
) hw
->mac_addr
[4]) << 8) |
1485 (((u32
) hw
->mac_addr
[5]));
1486 iowrite32(value
, hw
->hw_addr
+ REG_MAC_STA_ADDR
);
1487 value
= (((u32
) hw
->mac_addr
[0]) << 8) | (((u32
) hw
->mac_addr
[1]));
1488 iowrite32(value
, hw
->hw_addr
+ (REG_MAC_STA_ADDR
+ 4));
1492 /* HI base address */
1493 iowrite32((u32
) ((adapter
->tpd_ring
.dma
& 0xffffffff00000000ULL
) >> 32),
1494 hw
->hw_addr
+ REG_DESC_BASE_ADDR_HI
);
1495 /* LO base address */
1496 iowrite32((u32
) (adapter
->rfd_ring
.dma
& 0x00000000ffffffffULL
),
1497 hw
->hw_addr
+ REG_DESC_RFD_ADDR_LO
);
1498 iowrite32((u32
) (adapter
->rrd_ring
.dma
& 0x00000000ffffffffULL
),
1499 hw
->hw_addr
+ REG_DESC_RRD_ADDR_LO
);
1500 iowrite32((u32
) (adapter
->tpd_ring
.dma
& 0x00000000ffffffffULL
),
1501 hw
->hw_addr
+ REG_DESC_TPD_ADDR_LO
);
1502 iowrite32((u32
) (adapter
->cmb
.dma
& 0x00000000ffffffffULL
),
1503 hw
->hw_addr
+ REG_DESC_CMB_ADDR_LO
);
1504 iowrite32((u32
) (adapter
->smb
.dma
& 0x00000000ffffffffULL
),
1505 hw
->hw_addr
+ REG_DESC_SMB_ADDR_LO
);
1508 value
= adapter
->rrd_ring
.count
;
1510 value
+= adapter
->rfd_ring
.count
;
1511 iowrite32(value
, hw
->hw_addr
+ REG_DESC_RFD_RRD_RING_SIZE
);
1512 iowrite32(adapter
->tpd_ring
.count
, hw
->hw_addr
+
1513 REG_DESC_TPD_RING_SIZE
);
1516 iowrite32(1, hw
->hw_addr
+ REG_LOAD_PTR
);
1518 /* config Mailbox */
1519 value
= ((atomic_read(&adapter
->tpd_ring
.next_to_use
)
1520 & MB_TPD_PROD_INDX_MASK
) << MB_TPD_PROD_INDX_SHIFT
) |
1521 ((atomic_read(&adapter
->rrd_ring
.next_to_clean
)
1522 & MB_RRD_CONS_INDX_MASK
) << MB_RRD_CONS_INDX_SHIFT
) |
1523 ((atomic_read(&adapter
->rfd_ring
.next_to_use
)
1524 & MB_RFD_PROD_INDX_MASK
) << MB_RFD_PROD_INDX_SHIFT
);
1525 iowrite32(value
, hw
->hw_addr
+ REG_MAILBOX
);
1527 /* config IPG/IFG */
1528 value
= (((u32
) hw
->ipgt
& MAC_IPG_IFG_IPGT_MASK
)
1529 << MAC_IPG_IFG_IPGT_SHIFT
) |
1530 (((u32
) hw
->min_ifg
& MAC_IPG_IFG_MIFG_MASK
)
1531 << MAC_IPG_IFG_MIFG_SHIFT
) |
1532 (((u32
) hw
->ipgr1
& MAC_IPG_IFG_IPGR1_MASK
)
1533 << MAC_IPG_IFG_IPGR1_SHIFT
) |
1534 (((u32
) hw
->ipgr2
& MAC_IPG_IFG_IPGR2_MASK
)
1535 << MAC_IPG_IFG_IPGR2_SHIFT
);
1536 iowrite32(value
, hw
->hw_addr
+ REG_MAC_IPG_IFG
);
1538 /* config Half-Duplex Control */
1539 value
= ((u32
) hw
->lcol
& MAC_HALF_DUPLX_CTRL_LCOL_MASK
) |
1540 (((u32
) hw
->max_retry
& MAC_HALF_DUPLX_CTRL_RETRY_MASK
)
1541 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT
) |
1542 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN
|
1543 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT
) |
1544 (((u32
) hw
->jam_ipg
& MAC_HALF_DUPLX_CTRL_JAMIPG_MASK
)
1545 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT
);
1546 iowrite32(value
, hw
->hw_addr
+ REG_MAC_HALF_DUPLX_CTRL
);
1548 /* set Interrupt Moderator Timer */
1549 iowrite16(adapter
->imt
, hw
->hw_addr
+ REG_IRQ_MODU_TIMER_INIT
);
1550 iowrite32(MASTER_CTRL_ITIMER_EN
, hw
->hw_addr
+ REG_MASTER_CTRL
);
1552 /* set Interrupt Clear Timer */
1553 iowrite16(adapter
->ict
, hw
->hw_addr
+ REG_CMBDISDMA_TIMER
);
1555 /* set max frame size hw will accept */
1556 iowrite32(hw
->max_frame_size
, hw
->hw_addr
+ REG_MTU
);
1558 /* jumbo size & rrd retirement timer */
1559 value
= (((u32
) hw
->rx_jumbo_th
& RXQ_JMBOSZ_TH_MASK
)
1560 << RXQ_JMBOSZ_TH_SHIFT
) |
1561 (((u32
) hw
->rx_jumbo_lkah
& RXQ_JMBO_LKAH_MASK
)
1562 << RXQ_JMBO_LKAH_SHIFT
) |
1563 (((u32
) hw
->rrd_ret_timer
& RXQ_RRD_TIMER_MASK
)
1564 << RXQ_RRD_TIMER_SHIFT
);
1565 iowrite32(value
, hw
->hw_addr
+ REG_RXQ_JMBOSZ_RRDTIM
);
1568 switch (hw
->dev_rev
) {
1573 set_flow_ctrl_old(adapter
);
1576 set_flow_ctrl_new(hw
);
1581 value
= (((u32
) hw
->tpd_burst
& TXQ_CTRL_TPD_BURST_NUM_MASK
)
1582 << TXQ_CTRL_TPD_BURST_NUM_SHIFT
) |
1583 (((u32
) hw
->txf_burst
& TXQ_CTRL_TXF_BURST_NUM_MASK
)
1584 << TXQ_CTRL_TXF_BURST_NUM_SHIFT
) |
1585 (((u32
) hw
->tpd_fetch_th
& TXQ_CTRL_TPD_FETCH_TH_MASK
)
1586 << TXQ_CTRL_TPD_FETCH_TH_SHIFT
) | TXQ_CTRL_ENH_MODE
|
1588 iowrite32(value
, hw
->hw_addr
+ REG_TXQ_CTRL
);
1590 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1591 value
= (((u32
) hw
->tx_jumbo_task_th
& TX_JUMBO_TASK_TH_MASK
)
1592 << TX_JUMBO_TASK_TH_SHIFT
) |
1593 (((u32
) hw
->tpd_fetch_gap
& TX_TPD_MIN_IPG_MASK
)
1594 << TX_TPD_MIN_IPG_SHIFT
);
1595 iowrite32(value
, hw
->hw_addr
+ REG_TX_JUMBO_TASK_TH_TPD_IPG
);
1598 value
= (((u32
) hw
->rfd_burst
& RXQ_CTRL_RFD_BURST_NUM_MASK
)
1599 << RXQ_CTRL_RFD_BURST_NUM_SHIFT
) |
1600 (((u32
) hw
->rrd_burst
& RXQ_CTRL_RRD_BURST_THRESH_MASK
)
1601 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT
) |
1602 (((u32
) hw
->rfd_fetch_gap
& RXQ_CTRL_RFD_PREF_MIN_IPG_MASK
)
1603 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT
) | RXQ_CTRL_CUT_THRU_EN
|
1605 iowrite32(value
, hw
->hw_addr
+ REG_RXQ_CTRL
);
1607 /* config DMA Engine */
1608 value
= ((((u32
) hw
->dmar_block
) & DMA_CTRL_DMAR_BURST_LEN_MASK
)
1609 << DMA_CTRL_DMAR_BURST_LEN_SHIFT
) |
1610 ((((u32
) hw
->dmaw_block
) & DMA_CTRL_DMAW_BURST_LEN_MASK
)
1611 << DMA_CTRL_DMAW_BURST_LEN_SHIFT
) | DMA_CTRL_DMAR_EN
|
1613 value
|= (u32
) hw
->dma_ord
;
1614 if (atl1_rcb_128
== hw
->rcb_value
)
1615 value
|= DMA_CTRL_RCB_VALUE
;
1616 iowrite32(value
, hw
->hw_addr
+ REG_DMA_CTRL
);
1618 /* config CMB / SMB */
1619 value
= (hw
->cmb_tpd
> adapter
->tpd_ring
.count
) ?
1620 hw
->cmb_tpd
: adapter
->tpd_ring
.count
;
1622 value
|= hw
->cmb_rrd
;
1623 iowrite32(value
, hw
->hw_addr
+ REG_CMB_WRITE_TH
);
1624 value
= hw
->cmb_rx_timer
| ((u32
) hw
->cmb_tx_timer
<< 16);
1625 iowrite32(value
, hw
->hw_addr
+ REG_CMB_WRITE_TIMER
);
1626 iowrite32(hw
->smb_timer
, hw
->hw_addr
+ REG_SMB_TIMER
);
1628 /* --- enable CMB / SMB */
1629 value
= CSMB_CTRL_CMB_EN
| CSMB_CTRL_SMB_EN
;
1630 iowrite32(value
, hw
->hw_addr
+ REG_CSMB_CTRL
);
1632 value
= ioread32(adapter
->hw
.hw_addr
+ REG_ISR
);
1633 if (unlikely((value
& ISR_PHY_LINKDOWN
) != 0))
1634 value
= 1; /* config failed */
1638 /* clear all interrupt status */
1639 iowrite32(0x3fffffff, adapter
->hw
.hw_addr
+ REG_ISR
);
1640 iowrite32(0, adapter
->hw
.hw_addr
+ REG_ISR
);
1645 * atl1_pcie_patch - Patch for PCIE module
1647 static void atl1_pcie_patch(struct atl1_adapter
*adapter
)
1651 /* much vendor magic here */
1653 iowrite32(value
, adapter
->hw
.hw_addr
+ 0x12FC);
1654 /* pcie flow control mode change */
1655 value
= ioread32(adapter
->hw
.hw_addr
+ 0x1008);
1657 iowrite32(value
, adapter
->hw
.hw_addr
+ 0x1008);
1661 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1662 * on PCI Command register is disable.
1663 * The function enable this bit.
1664 * Brackett, 2006/03/15
1666 static void atl1_via_workaround(struct atl1_adapter
*adapter
)
1668 unsigned long value
;
1670 value
= ioread16(adapter
->hw
.hw_addr
+ PCI_COMMAND
);
1671 if (value
& PCI_COMMAND_INTX_DISABLE
)
1672 value
&= ~PCI_COMMAND_INTX_DISABLE
;
1673 iowrite32(value
, adapter
->hw
.hw_addr
+ PCI_COMMAND
);
1676 static void atl1_inc_smb(struct atl1_adapter
*adapter
)
1678 struct net_device
*netdev
= adapter
->netdev
;
1679 struct stats_msg_block
*smb
= adapter
->smb
.smb
;
1681 /* Fill out the OS statistics structure */
1682 adapter
->soft_stats
.rx_packets
+= smb
->rx_ok
;
1683 adapter
->soft_stats
.tx_packets
+= smb
->tx_ok
;
1684 adapter
->soft_stats
.rx_bytes
+= smb
->rx_byte_cnt
;
1685 adapter
->soft_stats
.tx_bytes
+= smb
->tx_byte_cnt
;
1686 adapter
->soft_stats
.multicast
+= smb
->rx_mcast
;
1687 adapter
->soft_stats
.collisions
+= (smb
->tx_1_col
+ smb
->tx_2_col
* 2 +
1688 smb
->tx_late_col
+ smb
->tx_abort_col
* adapter
->hw
.max_retry
);
1691 adapter
->soft_stats
.rx_errors
+= (smb
->rx_frag
+ smb
->rx_fcs_err
+
1692 smb
->rx_len_err
+ smb
->rx_sz_ov
+ smb
->rx_rxf_ov
+
1693 smb
->rx_rrd_ov
+ smb
->rx_align_err
);
1694 adapter
->soft_stats
.rx_fifo_errors
+= smb
->rx_rxf_ov
;
1695 adapter
->soft_stats
.rx_length_errors
+= smb
->rx_len_err
;
1696 adapter
->soft_stats
.rx_crc_errors
+= smb
->rx_fcs_err
;
1697 adapter
->soft_stats
.rx_frame_errors
+= smb
->rx_align_err
;
1698 adapter
->soft_stats
.rx_missed_errors
+= (smb
->rx_rrd_ov
+
1701 adapter
->soft_stats
.rx_pause
+= smb
->rx_pause
;
1702 adapter
->soft_stats
.rx_rrd_ov
+= smb
->rx_rrd_ov
;
1703 adapter
->soft_stats
.rx_trunc
+= smb
->rx_sz_ov
;
1706 adapter
->soft_stats
.tx_errors
+= (smb
->tx_late_col
+
1707 smb
->tx_abort_col
+ smb
->tx_underrun
+ smb
->tx_trunc
);
1708 adapter
->soft_stats
.tx_fifo_errors
+= smb
->tx_underrun
;
1709 adapter
->soft_stats
.tx_aborted_errors
+= smb
->tx_abort_col
;
1710 adapter
->soft_stats
.tx_window_errors
+= smb
->tx_late_col
;
1712 adapter
->soft_stats
.excecol
+= smb
->tx_abort_col
;
1713 adapter
->soft_stats
.deffer
+= smb
->tx_defer
;
1714 adapter
->soft_stats
.scc
+= smb
->tx_1_col
;
1715 adapter
->soft_stats
.mcc
+= smb
->tx_2_col
;
1716 adapter
->soft_stats
.latecol
+= smb
->tx_late_col
;
1717 adapter
->soft_stats
.tx_underun
+= smb
->tx_underrun
;
1718 adapter
->soft_stats
.tx_trunc
+= smb
->tx_trunc
;
1719 adapter
->soft_stats
.tx_pause
+= smb
->tx_pause
;
1721 netdev
->stats
.rx_packets
= adapter
->soft_stats
.rx_packets
;
1722 netdev
->stats
.tx_packets
= adapter
->soft_stats
.tx_packets
;
1723 netdev
->stats
.rx_bytes
= adapter
->soft_stats
.rx_bytes
;
1724 netdev
->stats
.tx_bytes
= adapter
->soft_stats
.tx_bytes
;
1725 netdev
->stats
.multicast
= adapter
->soft_stats
.multicast
;
1726 netdev
->stats
.collisions
= adapter
->soft_stats
.collisions
;
1727 netdev
->stats
.rx_errors
= adapter
->soft_stats
.rx_errors
;
1728 netdev
->stats
.rx_over_errors
=
1729 adapter
->soft_stats
.rx_missed_errors
;
1730 netdev
->stats
.rx_length_errors
=
1731 adapter
->soft_stats
.rx_length_errors
;
1732 netdev
->stats
.rx_crc_errors
= adapter
->soft_stats
.rx_crc_errors
;
1733 netdev
->stats
.rx_frame_errors
=
1734 adapter
->soft_stats
.rx_frame_errors
;
1735 netdev
->stats
.rx_fifo_errors
= adapter
->soft_stats
.rx_fifo_errors
;
1736 netdev
->stats
.rx_missed_errors
=
1737 adapter
->soft_stats
.rx_missed_errors
;
1738 netdev
->stats
.tx_errors
= adapter
->soft_stats
.tx_errors
;
1739 netdev
->stats
.tx_fifo_errors
= adapter
->soft_stats
.tx_fifo_errors
;
1740 netdev
->stats
.tx_aborted_errors
=
1741 adapter
->soft_stats
.tx_aborted_errors
;
1742 netdev
->stats
.tx_window_errors
=
1743 adapter
->soft_stats
.tx_window_errors
;
1744 netdev
->stats
.tx_carrier_errors
=
1745 adapter
->soft_stats
.tx_carrier_errors
;
1748 static void atl1_update_mailbox(struct atl1_adapter
*adapter
)
1750 unsigned long flags
;
1751 u32 tpd_next_to_use
;
1752 u32 rfd_next_to_use
;
1753 u32 rrd_next_to_clean
;
1756 spin_lock_irqsave(&adapter
->mb_lock
, flags
);
1758 tpd_next_to_use
= atomic_read(&adapter
->tpd_ring
.next_to_use
);
1759 rfd_next_to_use
= atomic_read(&adapter
->rfd_ring
.next_to_use
);
1760 rrd_next_to_clean
= atomic_read(&adapter
->rrd_ring
.next_to_clean
);
1762 value
= ((rfd_next_to_use
& MB_RFD_PROD_INDX_MASK
) <<
1763 MB_RFD_PROD_INDX_SHIFT
) |
1764 ((rrd_next_to_clean
& MB_RRD_CONS_INDX_MASK
) <<
1765 MB_RRD_CONS_INDX_SHIFT
) |
1766 ((tpd_next_to_use
& MB_TPD_PROD_INDX_MASK
) <<
1767 MB_TPD_PROD_INDX_SHIFT
);
1768 iowrite32(value
, adapter
->hw
.hw_addr
+ REG_MAILBOX
);
1770 spin_unlock_irqrestore(&adapter
->mb_lock
, flags
);
1773 static void atl1_clean_alloc_flag(struct atl1_adapter
*adapter
,
1774 struct rx_return_desc
*rrd
, u16 offset
)
1776 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1778 while (rfd_ring
->next_to_clean
!= (rrd
->buf_indx
+ offset
)) {
1779 rfd_ring
->buffer_info
[rfd_ring
->next_to_clean
].alloced
= 0;
1780 if (++rfd_ring
->next_to_clean
== rfd_ring
->count
) {
1781 rfd_ring
->next_to_clean
= 0;
1786 static void atl1_update_rfd_index(struct atl1_adapter
*adapter
,
1787 struct rx_return_desc
*rrd
)
1791 num_buf
= (rrd
->xsz
.xsum_sz
.pkt_size
+ adapter
->rx_buffer_len
- 1) /
1792 adapter
->rx_buffer_len
;
1793 if (rrd
->num_buf
== num_buf
)
1794 /* clean alloc flag for bad rrd */
1795 atl1_clean_alloc_flag(adapter
, rrd
, num_buf
);
1798 static void atl1_rx_checksum(struct atl1_adapter
*adapter
,
1799 struct rx_return_desc
*rrd
, struct sk_buff
*skb
)
1801 struct pci_dev
*pdev
= adapter
->pdev
;
1804 * The L1 hardware contains a bug that erroneously sets the
1805 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1806 * fragmented IP packet is received, even though the packet
1807 * is perfectly valid and its checksum is correct. There's
1808 * no way to distinguish between one of these good packets
1809 * and a packet that actually contains a TCP/UDP checksum
1810 * error, so all we can do is allow it to be handed up to
1811 * the higher layers and let it be sorted out there.
1814 skb_checksum_none_assert(skb
);
1816 if (unlikely(rrd
->pkt_flg
& PACKET_FLAG_ERR
)) {
1817 if (rrd
->err_flg
& (ERR_FLAG_CRC
| ERR_FLAG_TRUNC
|
1818 ERR_FLAG_CODE
| ERR_FLAG_OV
)) {
1819 adapter
->hw_csum_err
++;
1820 if (netif_msg_rx_err(adapter
))
1821 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1822 "rx checksum error\n");
1828 if (!(rrd
->pkt_flg
& PACKET_FLAG_IPV4
))
1829 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1833 if (likely(!(rrd
->err_flg
&
1834 (ERR_FLAG_IP_CHKSUM
| ERR_FLAG_L4_CHKSUM
)))) {
1835 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1836 adapter
->hw_csum_good
++;
1842 * atl1_alloc_rx_buffers - Replace used receive buffers
1843 * @adapter: address of board private structure
1845 static u16
atl1_alloc_rx_buffers(struct atl1_adapter
*adapter
)
1847 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1848 struct pci_dev
*pdev
= adapter
->pdev
;
1850 unsigned long offset
;
1851 struct atl1_buffer
*buffer_info
, *next_info
;
1852 struct sk_buff
*skb
;
1854 u16 rfd_next_to_use
, next_next
;
1855 struct rx_free_desc
*rfd_desc
;
1857 next_next
= rfd_next_to_use
= atomic_read(&rfd_ring
->next_to_use
);
1858 if (++next_next
== rfd_ring
->count
)
1860 buffer_info
= &rfd_ring
->buffer_info
[rfd_next_to_use
];
1861 next_info
= &rfd_ring
->buffer_info
[next_next
];
1863 while (!buffer_info
->alloced
&& !next_info
->alloced
) {
1864 if (buffer_info
->skb
) {
1865 buffer_info
->alloced
= 1;
1869 rfd_desc
= ATL1_RFD_DESC(rfd_ring
, rfd_next_to_use
);
1871 skb
= netdev_alloc_skb_ip_align(adapter
->netdev
,
1872 adapter
->rx_buffer_len
);
1873 if (unlikely(!skb
)) {
1874 /* Better luck next round */
1875 adapter
->netdev
->stats
.rx_dropped
++;
1879 buffer_info
->alloced
= 1;
1880 buffer_info
->skb
= skb
;
1881 buffer_info
->length
= (u16
) adapter
->rx_buffer_len
;
1882 page
= virt_to_page(skb
->data
);
1883 offset
= (unsigned long)skb
->data
& ~PAGE_MASK
;
1884 buffer_info
->dma
= pci_map_page(pdev
, page
, offset
,
1885 adapter
->rx_buffer_len
,
1886 PCI_DMA_FROMDEVICE
);
1887 rfd_desc
->buffer_addr
= cpu_to_le64(buffer_info
->dma
);
1888 rfd_desc
->buf_len
= cpu_to_le16(adapter
->rx_buffer_len
);
1889 rfd_desc
->coalese
= 0;
1892 rfd_next_to_use
= next_next
;
1893 if (unlikely(++next_next
== rfd_ring
->count
))
1896 buffer_info
= &rfd_ring
->buffer_info
[rfd_next_to_use
];
1897 next_info
= &rfd_ring
->buffer_info
[next_next
];
1903 * Force memory writes to complete before letting h/w
1904 * know there are new descriptors to fetch. (Only
1905 * applicable for weak-ordered memory model archs,
1909 atomic_set(&rfd_ring
->next_to_use
, (int)rfd_next_to_use
);
1914 static void atl1_intr_rx(struct atl1_adapter
*adapter
)
1918 u16 rrd_next_to_clean
;
1920 struct atl1_rfd_ring
*rfd_ring
= &adapter
->rfd_ring
;
1921 struct atl1_rrd_ring
*rrd_ring
= &adapter
->rrd_ring
;
1922 struct atl1_buffer
*buffer_info
;
1923 struct rx_return_desc
*rrd
;
1924 struct sk_buff
*skb
;
1928 rrd_next_to_clean
= atomic_read(&rrd_ring
->next_to_clean
);
1931 rrd
= ATL1_RRD_DESC(rrd_ring
, rrd_next_to_clean
);
1933 if (likely(rrd
->xsz
.valid
)) { /* packet valid */
1935 /* check rrd status */
1936 if (likely(rrd
->num_buf
== 1))
1938 else if (netif_msg_rx_err(adapter
)) {
1939 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1940 "unexpected RRD buffer count\n");
1941 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1942 "rx_buf_len = %d\n",
1943 adapter
->rx_buffer_len
);
1944 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1945 "RRD num_buf = %d\n",
1947 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1948 "RRD pkt_len = %d\n",
1949 rrd
->xsz
.xsum_sz
.pkt_size
);
1950 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1951 "RRD pkt_flg = 0x%08X\n",
1953 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1954 "RRD err_flg = 0x%08X\n",
1956 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1957 "RRD vlan_tag = 0x%08X\n",
1961 /* rrd seems to be bad */
1962 if (unlikely(i
-- > 0)) {
1963 /* rrd may not be DMAed completely */
1968 if (netif_msg_rx_err(adapter
))
1969 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
1971 /* see if update RFD index */
1972 if (rrd
->num_buf
> 1)
1973 atl1_update_rfd_index(adapter
, rrd
);
1977 if (++rrd_next_to_clean
== rrd_ring
->count
)
1978 rrd_next_to_clean
= 0;
1981 } else { /* current rrd still not be updated */
1986 /* clean alloc flag for bad rrd */
1987 atl1_clean_alloc_flag(adapter
, rrd
, 0);
1989 buffer_info
= &rfd_ring
->buffer_info
[rrd
->buf_indx
];
1990 if (++rfd_ring
->next_to_clean
== rfd_ring
->count
)
1991 rfd_ring
->next_to_clean
= 0;
1993 /* update rrd next to clean */
1994 if (++rrd_next_to_clean
== rrd_ring
->count
)
1995 rrd_next_to_clean
= 0;
1998 if (unlikely(rrd
->pkt_flg
& PACKET_FLAG_ERR
)) {
1999 if (!(rrd
->err_flg
&
2000 (ERR_FLAG_IP_CHKSUM
| ERR_FLAG_L4_CHKSUM
2002 /* packet error, don't need upstream */
2003 buffer_info
->alloced
= 0;
2010 pci_unmap_page(adapter
->pdev
, buffer_info
->dma
,
2011 buffer_info
->length
, PCI_DMA_FROMDEVICE
);
2012 buffer_info
->dma
= 0;
2013 skb
= buffer_info
->skb
;
2014 length
= le16_to_cpu(rrd
->xsz
.xsum_sz
.pkt_size
);
2016 skb_put(skb
, length
- ETH_FCS_LEN
);
2018 /* Receive Checksum Offload */
2019 atl1_rx_checksum(adapter
, rrd
, skb
);
2020 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
2022 if (adapter
->vlgrp
&& (rrd
->pkt_flg
& PACKET_FLAG_VLAN_INS
)) {
2023 u16 vlan_tag
= (rrd
->vlan_tag
>> 4) |
2024 ((rrd
->vlan_tag
& 7) << 13) |
2025 ((rrd
->vlan_tag
& 8) << 9);
2026 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, vlan_tag
);
2030 /* let protocol layer free skb */
2031 buffer_info
->skb
= NULL
;
2032 buffer_info
->alloced
= 0;
2036 atomic_set(&rrd_ring
->next_to_clean
, rrd_next_to_clean
);
2038 atl1_alloc_rx_buffers(adapter
);
2040 /* update mailbox ? */
2042 u32 tpd_next_to_use
;
2043 u32 rfd_next_to_use
;
2045 spin_lock(&adapter
->mb_lock
);
2047 tpd_next_to_use
= atomic_read(&adapter
->tpd_ring
.next_to_use
);
2049 atomic_read(&adapter
->rfd_ring
.next_to_use
);
2051 atomic_read(&adapter
->rrd_ring
.next_to_clean
);
2052 value
= ((rfd_next_to_use
& MB_RFD_PROD_INDX_MASK
) <<
2053 MB_RFD_PROD_INDX_SHIFT
) |
2054 ((rrd_next_to_clean
& MB_RRD_CONS_INDX_MASK
) <<
2055 MB_RRD_CONS_INDX_SHIFT
) |
2056 ((tpd_next_to_use
& MB_TPD_PROD_INDX_MASK
) <<
2057 MB_TPD_PROD_INDX_SHIFT
);
2058 iowrite32(value
, adapter
->hw
.hw_addr
+ REG_MAILBOX
);
2059 spin_unlock(&adapter
->mb_lock
);
2063 static void atl1_intr_tx(struct atl1_adapter
*adapter
)
2065 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
2066 struct atl1_buffer
*buffer_info
;
2067 u16 sw_tpd_next_to_clean
;
2068 u16 cmb_tpd_next_to_clean
;
2070 sw_tpd_next_to_clean
= atomic_read(&tpd_ring
->next_to_clean
);
2071 cmb_tpd_next_to_clean
= le16_to_cpu(adapter
->cmb
.cmb
->tpd_cons_idx
);
2073 while (cmb_tpd_next_to_clean
!= sw_tpd_next_to_clean
) {
2074 struct tx_packet_desc
*tpd
;
2076 tpd
= ATL1_TPD_DESC(tpd_ring
, sw_tpd_next_to_clean
);
2077 buffer_info
= &tpd_ring
->buffer_info
[sw_tpd_next_to_clean
];
2078 if (buffer_info
->dma
) {
2079 pci_unmap_page(adapter
->pdev
, buffer_info
->dma
,
2080 buffer_info
->length
, PCI_DMA_TODEVICE
);
2081 buffer_info
->dma
= 0;
2084 if (buffer_info
->skb
) {
2085 dev_kfree_skb_irq(buffer_info
->skb
);
2086 buffer_info
->skb
= NULL
;
2089 if (++sw_tpd_next_to_clean
== tpd_ring
->count
)
2090 sw_tpd_next_to_clean
= 0;
2092 atomic_set(&tpd_ring
->next_to_clean
, sw_tpd_next_to_clean
);
2094 if (netif_queue_stopped(adapter
->netdev
) &&
2095 netif_carrier_ok(adapter
->netdev
))
2096 netif_wake_queue(adapter
->netdev
);
2099 static u16
atl1_tpd_avail(struct atl1_tpd_ring
*tpd_ring
)
2101 u16 next_to_clean
= atomic_read(&tpd_ring
->next_to_clean
);
2102 u16 next_to_use
= atomic_read(&tpd_ring
->next_to_use
);
2103 return (next_to_clean
> next_to_use
) ?
2104 next_to_clean
- next_to_use
- 1 :
2105 tpd_ring
->count
+ next_to_clean
- next_to_use
- 1;
2108 static int atl1_tso(struct atl1_adapter
*adapter
, struct sk_buff
*skb
,
2109 struct tx_packet_desc
*ptpd
)
2115 if (skb_shinfo(skb
)->gso_size
) {
2116 if (skb_header_cloned(skb
)) {
2117 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
2122 if (skb
->protocol
== htons(ETH_P_IP
)) {
2123 struct iphdr
*iph
= ip_hdr(skb
);
2125 real_len
= (((unsigned char *)iph
- skb
->data
) +
2126 ntohs(iph
->tot_len
));
2127 if (real_len
< skb
->len
)
2128 pskb_trim(skb
, real_len
);
2129 hdr_len
= (skb_transport_offset(skb
) + tcp_hdrlen(skb
));
2130 if (skb
->len
== hdr_len
) {
2132 tcp_hdr(skb
)->check
=
2133 ~csum_tcpudp_magic(iph
->saddr
,
2134 iph
->daddr
, tcp_hdrlen(skb
),
2136 ptpd
->word3
|= (iph
->ihl
& TPD_IPHL_MASK
) <<
2138 ptpd
->word3
|= ((tcp_hdrlen(skb
) >> 2) &
2139 TPD_TCPHDRLEN_MASK
) <<
2140 TPD_TCPHDRLEN_SHIFT
;
2141 ptpd
->word3
|= 1 << TPD_IP_CSUM_SHIFT
;
2142 ptpd
->word3
|= 1 << TPD_TCP_CSUM_SHIFT
;
2147 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
2148 iph
->daddr
, 0, IPPROTO_TCP
, 0);
2149 ip_off
= (unsigned char *)iph
-
2150 (unsigned char *) skb_network_header(skb
);
2151 if (ip_off
== 8) /* 802.3-SNAP frame */
2152 ptpd
->word3
|= 1 << TPD_ETHTYPE_SHIFT
;
2153 else if (ip_off
!= 0)
2156 ptpd
->word3
|= (iph
->ihl
& TPD_IPHL_MASK
) <<
2158 ptpd
->word3
|= ((tcp_hdrlen(skb
) >> 2) &
2159 TPD_TCPHDRLEN_MASK
) << TPD_TCPHDRLEN_SHIFT
;
2160 ptpd
->word3
|= (skb_shinfo(skb
)->gso_size
&
2161 TPD_MSS_MASK
) << TPD_MSS_SHIFT
;
2162 ptpd
->word3
|= 1 << TPD_SEGMENT_EN_SHIFT
;
2169 static int atl1_tx_csum(struct atl1_adapter
*adapter
, struct sk_buff
*skb
,
2170 struct tx_packet_desc
*ptpd
)
2174 if (likely(skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
2175 css
= (u8
) (skb
->csum_start
- skb_headroom(skb
));
2176 cso
= css
+ (u8
) skb
->csum_offset
;
2177 if (unlikely(css
& 0x1)) {
2178 /* L1 hardware requires an even number here */
2179 if (netif_msg_tx_err(adapter
))
2180 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
2181 "payload offset not an even number\n");
2184 ptpd
->word3
|= (css
& TPD_PLOADOFFSET_MASK
) <<
2185 TPD_PLOADOFFSET_SHIFT
;
2186 ptpd
->word3
|= (cso
& TPD_CCSUMOFFSET_MASK
) <<
2187 TPD_CCSUMOFFSET_SHIFT
;
2188 ptpd
->word3
|= 1 << TPD_CUST_CSUM_EN_SHIFT
;
2194 static void atl1_tx_map(struct atl1_adapter
*adapter
, struct sk_buff
*skb
,
2195 struct tx_packet_desc
*ptpd
)
2197 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
2198 struct atl1_buffer
*buffer_info
;
2199 u16 buf_len
= skb
->len
;
2201 unsigned long offset
;
2202 unsigned int nr_frags
;
2209 buf_len
-= skb
->data_len
;
2210 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2211 next_to_use
= atomic_read(&tpd_ring
->next_to_use
);
2212 buffer_info
= &tpd_ring
->buffer_info
[next_to_use
];
2213 BUG_ON(buffer_info
->skb
);
2214 /* put skb in last TPD */
2215 buffer_info
->skb
= NULL
;
2217 retval
= (ptpd
->word3
>> TPD_SEGMENT_EN_SHIFT
) & TPD_SEGMENT_EN_MASK
;
2220 hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2221 buffer_info
->length
= hdr_len
;
2222 page
= virt_to_page(skb
->data
);
2223 offset
= (unsigned long)skb
->data
& ~PAGE_MASK
;
2224 buffer_info
->dma
= pci_map_page(adapter
->pdev
, page
,
2228 if (++next_to_use
== tpd_ring
->count
)
2231 if (buf_len
> hdr_len
) {
2234 data_len
= buf_len
- hdr_len
;
2235 nseg
= (data_len
+ ATL1_MAX_TX_BUF_LEN
- 1) /
2236 ATL1_MAX_TX_BUF_LEN
;
2237 for (i
= 0; i
< nseg
; i
++) {
2239 &tpd_ring
->buffer_info
[next_to_use
];
2240 buffer_info
->skb
= NULL
;
2241 buffer_info
->length
=
2242 (ATL1_MAX_TX_BUF_LEN
>=
2243 data_len
) ? ATL1_MAX_TX_BUF_LEN
: data_len
;
2244 data_len
-= buffer_info
->length
;
2245 page
= virt_to_page(skb
->data
+
2246 (hdr_len
+ i
* ATL1_MAX_TX_BUF_LEN
));
2247 offset
= (unsigned long)(skb
->data
+
2248 (hdr_len
+ i
* ATL1_MAX_TX_BUF_LEN
)) &
2250 buffer_info
->dma
= pci_map_page(adapter
->pdev
,
2251 page
, offset
, buffer_info
->length
,
2253 if (++next_to_use
== tpd_ring
->count
)
2259 buffer_info
->length
= buf_len
;
2260 page
= virt_to_page(skb
->data
);
2261 offset
= (unsigned long)skb
->data
& ~PAGE_MASK
;
2262 buffer_info
->dma
= pci_map_page(adapter
->pdev
, page
,
2263 offset
, buf_len
, PCI_DMA_TODEVICE
);
2264 if (++next_to_use
== tpd_ring
->count
)
2268 for (f
= 0; f
< nr_frags
; f
++) {
2269 struct skb_frag_struct
*frag
;
2272 frag
= &skb_shinfo(skb
)->frags
[f
];
2273 buf_len
= frag
->size
;
2275 nseg
= (buf_len
+ ATL1_MAX_TX_BUF_LEN
- 1) /
2276 ATL1_MAX_TX_BUF_LEN
;
2277 for (i
= 0; i
< nseg
; i
++) {
2278 buffer_info
= &tpd_ring
->buffer_info
[next_to_use
];
2279 BUG_ON(buffer_info
->skb
);
2281 buffer_info
->skb
= NULL
;
2282 buffer_info
->length
= (buf_len
> ATL1_MAX_TX_BUF_LEN
) ?
2283 ATL1_MAX_TX_BUF_LEN
: buf_len
;
2284 buf_len
-= buffer_info
->length
;
2285 buffer_info
->dma
= pci_map_page(adapter
->pdev
,
2287 frag
->page_offset
+ (i
* ATL1_MAX_TX_BUF_LEN
),
2288 buffer_info
->length
, PCI_DMA_TODEVICE
);
2290 if (++next_to_use
== tpd_ring
->count
)
2295 /* last tpd's buffer-info */
2296 buffer_info
->skb
= skb
;
2299 static void atl1_tx_queue(struct atl1_adapter
*adapter
, u16 count
,
2300 struct tx_packet_desc
*ptpd
)
2302 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
2303 struct atl1_buffer
*buffer_info
;
2304 struct tx_packet_desc
*tpd
;
2307 u16 next_to_use
= (u16
) atomic_read(&tpd_ring
->next_to_use
);
2309 for (j
= 0; j
< count
; j
++) {
2310 buffer_info
= &tpd_ring
->buffer_info
[next_to_use
];
2311 tpd
= ATL1_TPD_DESC(&adapter
->tpd_ring
, next_to_use
);
2313 memcpy(tpd
, ptpd
, sizeof(struct tx_packet_desc
));
2314 tpd
->buffer_addr
= cpu_to_le64(buffer_info
->dma
);
2315 tpd
->word2
&= ~(TPD_BUFLEN_MASK
<< TPD_BUFLEN_SHIFT
);
2316 tpd
->word2
|= (cpu_to_le16(buffer_info
->length
) &
2317 TPD_BUFLEN_MASK
) << TPD_BUFLEN_SHIFT
;
2320 * if this is the first packet in a TSO chain, set
2321 * TPD_HDRFLAG, otherwise, clear it.
2323 val
= (tpd
->word3
>> TPD_SEGMENT_EN_SHIFT
) &
2324 TPD_SEGMENT_EN_MASK
;
2327 tpd
->word3
|= 1 << TPD_HDRFLAG_SHIFT
;
2329 tpd
->word3
&= ~(1 << TPD_HDRFLAG_SHIFT
);
2332 if (j
== (count
- 1))
2333 tpd
->word3
|= 1 << TPD_EOP_SHIFT
;
2335 if (++next_to_use
== tpd_ring
->count
)
2339 * Force memory writes to complete before letting h/w
2340 * know there are new descriptors to fetch. (Only
2341 * applicable for weak-ordered memory model archs,
2346 atomic_set(&tpd_ring
->next_to_use
, next_to_use
);
2349 static netdev_tx_t
atl1_xmit_frame(struct sk_buff
*skb
,
2350 struct net_device
*netdev
)
2352 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2353 struct atl1_tpd_ring
*tpd_ring
= &adapter
->tpd_ring
;
2358 struct tx_packet_desc
*ptpd
;
2361 unsigned int nr_frags
= 0;
2362 unsigned int mss
= 0;
2364 unsigned int proto_hdr_len
;
2366 len
= skb_headlen(skb
);
2368 if (unlikely(skb
->len
<= 0)) {
2369 dev_kfree_skb_any(skb
);
2370 return NETDEV_TX_OK
;
2373 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2374 for (f
= 0; f
< nr_frags
; f
++) {
2375 frag_size
= skb_shinfo(skb
)->frags
[f
].size
;
2377 count
+= (frag_size
+ ATL1_MAX_TX_BUF_LEN
- 1) /
2378 ATL1_MAX_TX_BUF_LEN
;
2381 mss
= skb_shinfo(skb
)->gso_size
;
2383 if (skb
->protocol
== htons(ETH_P_IP
)) {
2384 proto_hdr_len
= (skb_transport_offset(skb
) +
2386 if (unlikely(proto_hdr_len
> len
)) {
2387 dev_kfree_skb_any(skb
);
2388 return NETDEV_TX_OK
;
2390 /* need additional TPD ? */
2391 if (proto_hdr_len
!= len
)
2392 count
+= (len
- proto_hdr_len
+
2393 ATL1_MAX_TX_BUF_LEN
- 1) /
2394 ATL1_MAX_TX_BUF_LEN
;
2398 if (atl1_tpd_avail(&adapter
->tpd_ring
) < count
) {
2399 /* not enough descriptors */
2400 netif_stop_queue(netdev
);
2401 if (netif_msg_tx_queued(adapter
))
2402 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
2404 return NETDEV_TX_BUSY
;
2407 ptpd
= ATL1_TPD_DESC(tpd_ring
,
2408 (u16
) atomic_read(&tpd_ring
->next_to_use
));
2409 memset(ptpd
, 0, sizeof(struct tx_packet_desc
));
2411 if (vlan_tx_tag_present(skb
)) {
2412 vlan_tag
= vlan_tx_tag_get(skb
);
2413 vlan_tag
= (vlan_tag
<< 4) | (vlan_tag
>> 13) |
2414 ((vlan_tag
>> 9) & 0x8);
2415 ptpd
->word3
|= 1 << TPD_INS_VL_TAG_SHIFT
;
2416 ptpd
->word2
|= (vlan_tag
& TPD_VLANTAG_MASK
) <<
2420 tso
= atl1_tso(adapter
, skb
, ptpd
);
2422 dev_kfree_skb_any(skb
);
2423 return NETDEV_TX_OK
;
2427 ret_val
= atl1_tx_csum(adapter
, skb
, ptpd
);
2429 dev_kfree_skb_any(skb
);
2430 return NETDEV_TX_OK
;
2434 atl1_tx_map(adapter
, skb
, ptpd
);
2435 atl1_tx_queue(adapter
, count
, ptpd
);
2436 atl1_update_mailbox(adapter
);
2438 return NETDEV_TX_OK
;
2442 * atl1_intr - Interrupt Handler
2443 * @irq: interrupt number
2444 * @data: pointer to a network interface device structure
2445 * @pt_regs: CPU registers structure
2447 static irqreturn_t
atl1_intr(int irq
, void *data
)
2449 struct atl1_adapter
*adapter
= netdev_priv(data
);
2453 status
= adapter
->cmb
.cmb
->int_stats
;
2458 /* clear CMB interrupt status at once */
2459 adapter
->cmb
.cmb
->int_stats
= 0;
2461 if (status
& ISR_GPHY
) /* clear phy status */
2462 atlx_clear_phy_int(adapter
);
2464 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2465 iowrite32(status
| ISR_DIS_INT
, adapter
->hw
.hw_addr
+ REG_ISR
);
2467 /* check if SMB intr */
2468 if (status
& ISR_SMB
)
2469 atl1_inc_smb(adapter
);
2471 /* check if PCIE PHY Link down */
2472 if (status
& ISR_PHY_LINKDOWN
) {
2473 if (netif_msg_intr(adapter
))
2474 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
2475 "pcie phy link down %x\n", status
);
2476 if (netif_running(adapter
->netdev
)) { /* reset MAC */
2477 iowrite32(0, adapter
->hw
.hw_addr
+ REG_IMR
);
2478 schedule_work(&adapter
->pcie_dma_to_rst_task
);
2483 /* check if DMA read/write error ? */
2484 if (status
& (ISR_DMAR_TO_RST
| ISR_DMAW_TO_RST
)) {
2485 if (netif_msg_intr(adapter
))
2486 dev_printk(KERN_DEBUG
, &adapter
->pdev
->dev
,
2487 "pcie DMA r/w error (status = 0x%x)\n",
2489 iowrite32(0, adapter
->hw
.hw_addr
+ REG_IMR
);
2490 schedule_work(&adapter
->pcie_dma_to_rst_task
);
2495 if (status
& ISR_GPHY
) {
2496 adapter
->soft_stats
.tx_carrier_errors
++;
2497 atl1_check_for_link(adapter
);
2500 /* transmit event */
2501 if (status
& ISR_CMB_TX
)
2502 atl1_intr_tx(adapter
);
2505 if (unlikely(status
& (ISR_RXF_OV
| ISR_RFD_UNRUN
|
2506 ISR_RRD_OV
| ISR_HOST_RFD_UNRUN
|
2507 ISR_HOST_RRD_OV
| ISR_CMB_RX
))) {
2508 if (status
& (ISR_RXF_OV
| ISR_RFD_UNRUN
|
2509 ISR_RRD_OV
| ISR_HOST_RFD_UNRUN
|
2511 if (netif_msg_intr(adapter
))
2512 dev_printk(KERN_DEBUG
,
2513 &adapter
->pdev
->dev
,
2514 "rx exception, ISR = 0x%x\n",
2516 atl1_intr_rx(adapter
);
2522 } while ((status
= adapter
->cmb
.cmb
->int_stats
));
2524 /* re-enable Interrupt */
2525 iowrite32(ISR_DIS_SMB
| ISR_DIS_DMA
, adapter
->hw
.hw_addr
+ REG_ISR
);
2531 * atl1_phy_config - Timer Call-back
2532 * @data: pointer to netdev cast into an unsigned long
2534 static void atl1_phy_config(unsigned long data
)
2536 struct atl1_adapter
*adapter
= (struct atl1_adapter
*)data
;
2537 struct atl1_hw
*hw
= &adapter
->hw
;
2538 unsigned long flags
;
2540 spin_lock_irqsave(&adapter
->lock
, flags
);
2541 adapter
->phy_timer_pending
= false;
2542 atl1_write_phy_reg(hw
, MII_ADVERTISE
, hw
->mii_autoneg_adv_reg
);
2543 atl1_write_phy_reg(hw
, MII_ATLX_CR
, hw
->mii_1000t_ctrl_reg
);
2544 atl1_write_phy_reg(hw
, MII_BMCR
, MII_CR_RESET
| MII_CR_AUTO_NEG_EN
);
2545 spin_unlock_irqrestore(&adapter
->lock
, flags
);
2549 * Orphaned vendor comment left intact here:
2551 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2552 * will assert. We do soft reset <0x1400=1> according
2553 * with the SPEC. BUT, it seemes that PCIE or DMA
2554 * state-machine will not be reset. DMAR_TO_INT will
2555 * assert again and again.
2559 static int atl1_reset(struct atl1_adapter
*adapter
)
2562 ret
= atl1_reset_hw(&adapter
->hw
);
2565 return atl1_init_hw(&adapter
->hw
);
2568 static s32
atl1_up(struct atl1_adapter
*adapter
)
2570 struct net_device
*netdev
= adapter
->netdev
;
2572 int irq_flags
= IRQF_SAMPLE_RANDOM
;
2574 /* hardware has been reset, we need to reload some things */
2575 atlx_set_multi(netdev
);
2576 atl1_init_ring_ptrs(adapter
);
2577 atlx_restore_vlan(adapter
);
2578 err
= atl1_alloc_rx_buffers(adapter
);
2580 /* no RX BUFFER allocated */
2583 if (unlikely(atl1_configure(adapter
))) {
2588 err
= pci_enable_msi(adapter
->pdev
);
2590 if (netif_msg_ifup(adapter
))
2591 dev_info(&adapter
->pdev
->dev
,
2592 "Unable to enable MSI: %d\n", err
);
2593 irq_flags
|= IRQF_SHARED
;
2596 err
= request_irq(adapter
->pdev
->irq
, atl1_intr
, irq_flags
,
2597 netdev
->name
, netdev
);
2601 atlx_irq_enable(adapter
);
2602 atl1_check_link(adapter
);
2603 netif_start_queue(netdev
);
2607 pci_disable_msi(adapter
->pdev
);
2608 /* free rx_buffers */
2609 atl1_clean_rx_ring(adapter
);
2613 static void atl1_down(struct atl1_adapter
*adapter
)
2615 struct net_device
*netdev
= adapter
->netdev
;
2617 netif_stop_queue(netdev
);
2618 del_timer_sync(&adapter
->phy_config_timer
);
2619 adapter
->phy_timer_pending
= false;
2621 atlx_irq_disable(adapter
);
2622 free_irq(adapter
->pdev
->irq
, netdev
);
2623 pci_disable_msi(adapter
->pdev
);
2624 atl1_reset_hw(&adapter
->hw
);
2625 adapter
->cmb
.cmb
->int_stats
= 0;
2627 adapter
->link_speed
= SPEED_0
;
2628 adapter
->link_duplex
= -1;
2629 netif_carrier_off(netdev
);
2631 atl1_clean_tx_ring(adapter
);
2632 atl1_clean_rx_ring(adapter
);
2635 static void atl1_tx_timeout_task(struct work_struct
*work
)
2637 struct atl1_adapter
*adapter
=
2638 container_of(work
, struct atl1_adapter
, tx_timeout_task
);
2639 struct net_device
*netdev
= adapter
->netdev
;
2641 netif_device_detach(netdev
);
2644 netif_device_attach(netdev
);
2648 * atl1_change_mtu - Change the Maximum Transfer Unit
2649 * @netdev: network interface device structure
2650 * @new_mtu: new value for maximum frame size
2652 * Returns 0 on success, negative on failure
2654 static int atl1_change_mtu(struct net_device
*netdev
, int new_mtu
)
2656 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2657 int old_mtu
= netdev
->mtu
;
2658 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
2660 if ((max_frame
< ETH_ZLEN
+ ETH_FCS_LEN
) ||
2661 (max_frame
> MAX_JUMBO_FRAME_SIZE
)) {
2662 if (netif_msg_link(adapter
))
2663 dev_warn(&adapter
->pdev
->dev
, "invalid MTU setting\n");
2667 adapter
->hw
.max_frame_size
= max_frame
;
2668 adapter
->hw
.tx_jumbo_task_th
= (max_frame
+ 7) >> 3;
2669 adapter
->rx_buffer_len
= (max_frame
+ 7) & ~7;
2670 adapter
->hw
.rx_jumbo_th
= adapter
->rx_buffer_len
/ 8;
2672 netdev
->mtu
= new_mtu
;
2673 if ((old_mtu
!= new_mtu
) && netif_running(netdev
)) {
2682 * atl1_open - Called when a network interface is made active
2683 * @netdev: network interface device structure
2685 * Returns 0 on success, negative value on failure
2687 * The open entry point is called when a network interface is made
2688 * active by the system (IFF_UP). At this point all resources needed
2689 * for transmit and receive operations are allocated, the interrupt
2690 * handler is registered with the OS, the watchdog timer is started,
2691 * and the stack is notified that the interface is ready.
2693 static int atl1_open(struct net_device
*netdev
)
2695 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2698 netif_carrier_off(netdev
);
2700 /* allocate transmit descriptors */
2701 err
= atl1_setup_ring_resources(adapter
);
2705 err
= atl1_up(adapter
);
2712 atl1_reset(adapter
);
2717 * atl1_close - Disables a network interface
2718 * @netdev: network interface device structure
2720 * Returns 0, this is not allowed to fail
2722 * The close entry point is called when an interface is de-activated
2723 * by the OS. The hardware is still under the drivers control, but
2724 * needs to be disabled. A global MAC reset is issued to stop the
2725 * hardware, and all transmit and receive resources are freed.
2727 static int atl1_close(struct net_device
*netdev
)
2729 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2731 atl1_free_ring_resources(adapter
);
2736 static int atl1_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2738 struct net_device
*netdev
= pci_get_drvdata(pdev
);
2739 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2740 struct atl1_hw
*hw
= &adapter
->hw
;
2742 u32 wufc
= adapter
->wol
;
2748 netif_device_detach(netdev
);
2749 if (netif_running(netdev
))
2752 retval
= pci_save_state(pdev
);
2756 atl1_read_phy_reg(hw
, MII_BMSR
, (u16
*) & ctrl
);
2757 atl1_read_phy_reg(hw
, MII_BMSR
, (u16
*) & ctrl
);
2758 val
= ctrl
& BMSR_LSTATUS
;
2760 wufc
&= ~ATLX_WUFC_LNKC
;
2763 val
= atl1_get_speed_and_duplex(hw
, &speed
, &duplex
);
2765 if (netif_msg_ifdown(adapter
))
2766 dev_printk(KERN_DEBUG
, &pdev
->dev
,
2767 "error getting speed/duplex\n");
2773 /* enable magic packet WOL */
2774 if (wufc
& ATLX_WUFC_MAG
)
2775 ctrl
|= (WOL_MAGIC_EN
| WOL_MAGIC_PME_EN
);
2776 iowrite32(ctrl
, hw
->hw_addr
+ REG_WOL_CTRL
);
2777 ioread32(hw
->hw_addr
+ REG_WOL_CTRL
);
2779 /* configure the mac */
2780 ctrl
= MAC_CTRL_RX_EN
;
2781 ctrl
|= ((u32
)((speed
== SPEED_1000
) ? MAC_CTRL_SPEED_1000
:
2782 MAC_CTRL_SPEED_10_100
) << MAC_CTRL_SPEED_SHIFT
);
2783 if (duplex
== FULL_DUPLEX
)
2784 ctrl
|= MAC_CTRL_DUPLX
;
2785 ctrl
|= (((u32
)adapter
->hw
.preamble_len
&
2786 MAC_CTRL_PRMLEN_MASK
) << MAC_CTRL_PRMLEN_SHIFT
);
2788 ctrl
|= MAC_CTRL_RMV_VLAN
;
2789 if (wufc
& ATLX_WUFC_MAG
)
2790 ctrl
|= MAC_CTRL_BC_EN
;
2791 iowrite32(ctrl
, hw
->hw_addr
+ REG_MAC_CTRL
);
2792 ioread32(hw
->hw_addr
+ REG_MAC_CTRL
);
2795 ctrl
= ioread32(hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2796 ctrl
|= PCIE_PHYMISC_FORCE_RCV_DET
;
2797 iowrite32(ctrl
, hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2798 ioread32(hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2800 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), 1);
2805 ctrl
|= (WOL_LINK_CHG_EN
| WOL_LINK_CHG_PME_EN
);
2806 iowrite32(ctrl
, hw
->hw_addr
+ REG_WOL_CTRL
);
2807 ioread32(hw
->hw_addr
+ REG_WOL_CTRL
);
2808 iowrite32(0, hw
->hw_addr
+ REG_MAC_CTRL
);
2809 ioread32(hw
->hw_addr
+ REG_MAC_CTRL
);
2810 hw
->phy_configured
= false;
2811 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), 1);
2816 iowrite32(0, hw
->hw_addr
+ REG_WOL_CTRL
);
2817 ioread32(hw
->hw_addr
+ REG_WOL_CTRL
);
2818 ctrl
= ioread32(hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2819 ctrl
|= PCIE_PHYMISC_FORCE_RCV_DET
;
2820 iowrite32(ctrl
, hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2821 ioread32(hw
->hw_addr
+ REG_PCIE_PHYMISC
);
2822 hw
->phy_configured
= false;
2823 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), 0);
2825 if (netif_running(netdev
))
2826 pci_disable_msi(adapter
->pdev
);
2827 pci_disable_device(pdev
);
2828 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2833 static int atl1_resume(struct pci_dev
*pdev
)
2835 struct net_device
*netdev
= pci_get_drvdata(pdev
);
2836 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
2839 pci_set_power_state(pdev
, PCI_D0
);
2840 pci_restore_state(pdev
);
2842 err
= pci_enable_device(pdev
);
2844 if (netif_msg_ifup(adapter
))
2845 dev_printk(KERN_DEBUG
, &pdev
->dev
,
2846 "error enabling pci device\n");
2850 pci_set_master(pdev
);
2851 iowrite32(0, adapter
->hw
.hw_addr
+ REG_WOL_CTRL
);
2852 pci_enable_wake(pdev
, PCI_D3hot
, 0);
2853 pci_enable_wake(pdev
, PCI_D3cold
, 0);
2855 atl1_reset_hw(&adapter
->hw
);
2857 if (netif_running(netdev
)) {
2858 adapter
->cmb
.cmb
->int_stats
= 0;
2861 netif_device_attach(netdev
);
2866 #define atl1_suspend NULL
2867 #define atl1_resume NULL
2870 static void atl1_shutdown(struct pci_dev
*pdev
)
2873 atl1_suspend(pdev
, PMSG_SUSPEND
);
2877 #ifdef CONFIG_NET_POLL_CONTROLLER
2878 static void atl1_poll_controller(struct net_device
*netdev
)
2880 disable_irq(netdev
->irq
);
2881 atl1_intr(netdev
->irq
, netdev
);
2882 enable_irq(netdev
->irq
);
2886 static const struct net_device_ops atl1_netdev_ops
= {
2887 .ndo_open
= atl1_open
,
2888 .ndo_stop
= atl1_close
,
2889 .ndo_start_xmit
= atl1_xmit_frame
,
2890 .ndo_set_multicast_list
= atlx_set_multi
,
2891 .ndo_validate_addr
= eth_validate_addr
,
2892 .ndo_set_mac_address
= atl1_set_mac
,
2893 .ndo_change_mtu
= atl1_change_mtu
,
2894 .ndo_do_ioctl
= atlx_ioctl
,
2895 .ndo_tx_timeout
= atlx_tx_timeout
,
2896 .ndo_vlan_rx_register
= atlx_vlan_rx_register
,
2897 #ifdef CONFIG_NET_POLL_CONTROLLER
2898 .ndo_poll_controller
= atl1_poll_controller
,
2903 * atl1_probe - Device Initialization Routine
2904 * @pdev: PCI device information struct
2905 * @ent: entry in atl1_pci_tbl
2907 * Returns 0 on success, negative on failure
2909 * atl1_probe initializes an adapter identified by a pci_dev structure.
2910 * The OS initialization, configuring of the adapter private structure,
2911 * and a hardware reset occur.
2913 static int __devinit
atl1_probe(struct pci_dev
*pdev
,
2914 const struct pci_device_id
*ent
)
2916 struct net_device
*netdev
;
2917 struct atl1_adapter
*adapter
;
2918 static int cards_found
= 0;
2921 err
= pci_enable_device(pdev
);
2926 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2927 * shared register for the high 32 bits, so only a single, aligned,
2928 * 4 GB physical address range can be used at a time.
2930 * Supporting 64-bit DMA on this hardware is more trouble than it's
2931 * worth. It is far easier to limit to 32-bit DMA than update
2932 * various kernel subsystems to support the mechanics required by a
2933 * fixed-high-32-bit system.
2935 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2937 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
2941 * Mark all PCI regions associated with PCI device
2942 * pdev as being reserved by owner atl1_driver_name
2944 err
= pci_request_regions(pdev
, ATLX_DRIVER_NAME
);
2946 goto err_request_regions
;
2949 * Enables bus-mastering on the device and calls
2950 * pcibios_set_master to do the needed arch specific settings
2952 pci_set_master(pdev
);
2954 netdev
= alloc_etherdev(sizeof(struct atl1_adapter
));
2957 goto err_alloc_etherdev
;
2959 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
2961 pci_set_drvdata(pdev
, netdev
);
2962 adapter
= netdev_priv(netdev
);
2963 adapter
->netdev
= netdev
;
2964 adapter
->pdev
= pdev
;
2965 adapter
->hw
.back
= adapter
;
2966 adapter
->msg_enable
= netif_msg_init(debug
, atl1_default_msg
);
2968 adapter
->hw
.hw_addr
= pci_iomap(pdev
, 0, 0);
2969 if (!adapter
->hw
.hw_addr
) {
2973 /* get device revision number */
2974 adapter
->hw
.dev_rev
= ioread16(adapter
->hw
.hw_addr
+
2975 (REG_MASTER_CTRL
+ 2));
2976 if (netif_msg_probe(adapter
))
2977 dev_info(&pdev
->dev
, "version %s\n", ATLX_DRIVER_VERSION
);
2979 /* set default ring resource counts */
2980 adapter
->rfd_ring
.count
= adapter
->rrd_ring
.count
= ATL1_DEFAULT_RFD
;
2981 adapter
->tpd_ring
.count
= ATL1_DEFAULT_TPD
;
2983 adapter
->mii
.dev
= netdev
;
2984 adapter
->mii
.mdio_read
= mdio_read
;
2985 adapter
->mii
.mdio_write
= mdio_write
;
2986 adapter
->mii
.phy_id_mask
= 0x1f;
2987 adapter
->mii
.reg_num_mask
= 0x1f;
2989 netdev
->netdev_ops
= &atl1_netdev_ops
;
2990 netdev
->watchdog_timeo
= 5 * HZ
;
2992 netdev
->ethtool_ops
= &atl1_ethtool_ops
;
2993 adapter
->bd_number
= cards_found
;
2995 /* setup the private structure */
2996 err
= atl1_sw_init(adapter
);
3000 netdev
->features
= NETIF_F_HW_CSUM
;
3001 netdev
->features
|= NETIF_F_SG
;
3002 netdev
->features
|= (NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
);
3005 * patch for some L1 of old version,
3006 * the final version of L1 may not need these
3009 /* atl1_pcie_patch(adapter); */
3011 /* really reset GPHY core */
3012 iowrite16(0, adapter
->hw
.hw_addr
+ REG_PHY_ENABLE
);
3015 * reset the controller to
3016 * put the device in a known good starting state
3018 if (atl1_reset_hw(&adapter
->hw
)) {
3023 /* copy the MAC address out of the EEPROM */
3024 atl1_read_mac_addr(&adapter
->hw
);
3025 memcpy(netdev
->dev_addr
, adapter
->hw
.mac_addr
, netdev
->addr_len
);
3027 if (!is_valid_ether_addr(netdev
->dev_addr
)) {
3032 atl1_check_options(adapter
);
3034 /* pre-init the MAC, and setup link */
3035 err
= atl1_init_hw(&adapter
->hw
);
3041 atl1_pcie_patch(adapter
);
3042 /* assume we have no link for now */
3043 netif_carrier_off(netdev
);
3044 netif_stop_queue(netdev
);
3046 setup_timer(&adapter
->phy_config_timer
, atl1_phy_config
,
3047 (unsigned long)adapter
);
3048 adapter
->phy_timer_pending
= false;
3050 INIT_WORK(&adapter
->tx_timeout_task
, atl1_tx_timeout_task
);
3052 INIT_WORK(&adapter
->link_chg_task
, atlx_link_chg_task
);
3054 INIT_WORK(&adapter
->pcie_dma_to_rst_task
, atl1_tx_timeout_task
);
3056 err
= register_netdev(netdev
);
3061 atl1_via_workaround(adapter
);
3065 pci_iounmap(pdev
, adapter
->hw
.hw_addr
);
3067 free_netdev(netdev
);
3069 pci_release_regions(pdev
);
3071 err_request_regions
:
3072 pci_disable_device(pdev
);
3077 * atl1_remove - Device Removal Routine
3078 * @pdev: PCI device information struct
3080 * atl1_remove is called by the PCI subsystem to alert the driver
3081 * that it should release a PCI device. The could be caused by a
3082 * Hot-Plug event, or because the driver is going to be removed from
3085 static void __devexit
atl1_remove(struct pci_dev
*pdev
)
3087 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3088 struct atl1_adapter
*adapter
;
3089 /* Device not available. Return. */
3093 adapter
= netdev_priv(netdev
);
3096 * Some atl1 boards lack persistent storage for their MAC, and get it
3097 * from the BIOS during POST. If we've been messing with the MAC
3098 * address, we need to save the permanent one.
3100 if (memcmp(adapter
->hw
.mac_addr
, adapter
->hw
.perm_mac_addr
, ETH_ALEN
)) {
3101 memcpy(adapter
->hw
.mac_addr
, adapter
->hw
.perm_mac_addr
,
3103 atl1_set_mac_addr(&adapter
->hw
);
3106 iowrite16(0, adapter
->hw
.hw_addr
+ REG_PHY_ENABLE
);
3107 unregister_netdev(netdev
);
3108 pci_iounmap(pdev
, adapter
->hw
.hw_addr
);
3109 pci_release_regions(pdev
);
3110 free_netdev(netdev
);
3111 pci_disable_device(pdev
);
3114 static struct pci_driver atl1_driver
= {
3115 .name
= ATLX_DRIVER_NAME
,
3116 .id_table
= atl1_pci_tbl
,
3117 .probe
= atl1_probe
,
3118 .remove
= __devexit_p(atl1_remove
),
3119 .suspend
= atl1_suspend
,
3120 .resume
= atl1_resume
,
3121 .shutdown
= atl1_shutdown
3125 * atl1_exit_module - Driver Exit Cleanup Routine
3127 * atl1_exit_module is called just before the driver is removed
3130 static void __exit
atl1_exit_module(void)
3132 pci_unregister_driver(&atl1_driver
);
3136 * atl1_init_module - Driver Registration Routine
3138 * atl1_init_module is the first routine called when the driver is
3139 * loaded. All it does is register with the PCI subsystem.
3141 static int __init
atl1_init_module(void)
3143 return pci_register_driver(&atl1_driver
);
3146 module_init(atl1_init_module
);
3147 module_exit(atl1_exit_module
);
3150 char stat_string
[ETH_GSTRING_LEN
];
3155 #define ATL1_STAT(m) \
3156 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3158 static struct atl1_stats atl1_gstrings_stats
[] = {
3159 {"rx_packets", ATL1_STAT(soft_stats
.rx_packets
)},
3160 {"tx_packets", ATL1_STAT(soft_stats
.tx_packets
)},
3161 {"rx_bytes", ATL1_STAT(soft_stats
.rx_bytes
)},
3162 {"tx_bytes", ATL1_STAT(soft_stats
.tx_bytes
)},
3163 {"rx_errors", ATL1_STAT(soft_stats
.rx_errors
)},
3164 {"tx_errors", ATL1_STAT(soft_stats
.tx_errors
)},
3165 {"multicast", ATL1_STAT(soft_stats
.multicast
)},
3166 {"collisions", ATL1_STAT(soft_stats
.collisions
)},
3167 {"rx_length_errors", ATL1_STAT(soft_stats
.rx_length_errors
)},
3168 {"rx_over_errors", ATL1_STAT(soft_stats
.rx_missed_errors
)},
3169 {"rx_crc_errors", ATL1_STAT(soft_stats
.rx_crc_errors
)},
3170 {"rx_frame_errors", ATL1_STAT(soft_stats
.rx_frame_errors
)},
3171 {"rx_fifo_errors", ATL1_STAT(soft_stats
.rx_fifo_errors
)},
3172 {"rx_missed_errors", ATL1_STAT(soft_stats
.rx_missed_errors
)},
3173 {"tx_aborted_errors", ATL1_STAT(soft_stats
.tx_aborted_errors
)},
3174 {"tx_carrier_errors", ATL1_STAT(soft_stats
.tx_carrier_errors
)},
3175 {"tx_fifo_errors", ATL1_STAT(soft_stats
.tx_fifo_errors
)},
3176 {"tx_window_errors", ATL1_STAT(soft_stats
.tx_window_errors
)},
3177 {"tx_abort_exce_coll", ATL1_STAT(soft_stats
.excecol
)},
3178 {"tx_abort_late_coll", ATL1_STAT(soft_stats
.latecol
)},
3179 {"tx_deferred_ok", ATL1_STAT(soft_stats
.deffer
)},
3180 {"tx_single_coll_ok", ATL1_STAT(soft_stats
.scc
)},
3181 {"tx_multi_coll_ok", ATL1_STAT(soft_stats
.mcc
)},
3182 {"tx_underun", ATL1_STAT(soft_stats
.tx_underun
)},
3183 {"tx_trunc", ATL1_STAT(soft_stats
.tx_trunc
)},
3184 {"tx_pause", ATL1_STAT(soft_stats
.tx_pause
)},
3185 {"rx_pause", ATL1_STAT(soft_stats
.rx_pause
)},
3186 {"rx_rrd_ov", ATL1_STAT(soft_stats
.rx_rrd_ov
)},
3187 {"rx_trunc", ATL1_STAT(soft_stats
.rx_trunc
)}
3190 static void atl1_get_ethtool_stats(struct net_device
*netdev
,
3191 struct ethtool_stats
*stats
, u64
*data
)
3193 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3197 for (i
= 0; i
< ARRAY_SIZE(atl1_gstrings_stats
); i
++) {
3198 p
= (char *)adapter
+atl1_gstrings_stats
[i
].stat_offset
;
3199 data
[i
] = (atl1_gstrings_stats
[i
].sizeof_stat
==
3200 sizeof(u64
)) ? *(u64
*)p
: *(u32
*)p
;
3205 static int atl1_get_sset_count(struct net_device
*netdev
, int sset
)
3209 return ARRAY_SIZE(atl1_gstrings_stats
);
3215 static int atl1_get_settings(struct net_device
*netdev
,
3216 struct ethtool_cmd
*ecmd
)
3218 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3219 struct atl1_hw
*hw
= &adapter
->hw
;
3221 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3222 SUPPORTED_10baseT_Full
|
3223 SUPPORTED_100baseT_Half
|
3224 SUPPORTED_100baseT_Full
|
3225 SUPPORTED_1000baseT_Full
|
3226 SUPPORTED_Autoneg
| SUPPORTED_TP
);
3227 ecmd
->advertising
= ADVERTISED_TP
;
3228 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3229 hw
->media_type
== MEDIA_TYPE_1000M_FULL
) {
3230 ecmd
->advertising
|= ADVERTISED_Autoneg
;
3231 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
) {
3232 ecmd
->advertising
|= ADVERTISED_Autoneg
;
3233 ecmd
->advertising
|=
3234 (ADVERTISED_10baseT_Half
|
3235 ADVERTISED_10baseT_Full
|
3236 ADVERTISED_100baseT_Half
|
3237 ADVERTISED_100baseT_Full
|
3238 ADVERTISED_1000baseT_Full
);
3240 ecmd
->advertising
|= (ADVERTISED_1000baseT_Full
);
3242 ecmd
->port
= PORT_TP
;
3243 ecmd
->phy_address
= 0;
3244 ecmd
->transceiver
= XCVR_INTERNAL
;
3246 if (netif_carrier_ok(adapter
->netdev
)) {
3247 u16 link_speed
, link_duplex
;
3248 atl1_get_speed_and_duplex(hw
, &link_speed
, &link_duplex
);
3249 ecmd
->speed
= link_speed
;
3250 if (link_duplex
== FULL_DUPLEX
)
3251 ecmd
->duplex
= DUPLEX_FULL
;
3253 ecmd
->duplex
= DUPLEX_HALF
;
3258 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3259 hw
->media_type
== MEDIA_TYPE_1000M_FULL
)
3260 ecmd
->autoneg
= AUTONEG_ENABLE
;
3262 ecmd
->autoneg
= AUTONEG_DISABLE
;
3267 static int atl1_set_settings(struct net_device
*netdev
,
3268 struct ethtool_cmd
*ecmd
)
3270 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3271 struct atl1_hw
*hw
= &adapter
->hw
;
3274 u16 old_media_type
= hw
->media_type
;
3276 if (netif_running(adapter
->netdev
)) {
3277 if (netif_msg_link(adapter
))
3278 dev_dbg(&adapter
->pdev
->dev
,
3279 "ethtool shutting down adapter\n");
3283 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3284 hw
->media_type
= MEDIA_TYPE_AUTO_SENSOR
;
3286 if (ecmd
->speed
== SPEED_1000
) {
3287 if (ecmd
->duplex
!= DUPLEX_FULL
) {
3288 if (netif_msg_link(adapter
))
3289 dev_warn(&adapter
->pdev
->dev
,
3290 "1000M half is invalid\n");
3294 hw
->media_type
= MEDIA_TYPE_1000M_FULL
;
3295 } else if (ecmd
->speed
== SPEED_100
) {
3296 if (ecmd
->duplex
== DUPLEX_FULL
)
3297 hw
->media_type
= MEDIA_TYPE_100M_FULL
;
3299 hw
->media_type
= MEDIA_TYPE_100M_HALF
;
3301 if (ecmd
->duplex
== DUPLEX_FULL
)
3302 hw
->media_type
= MEDIA_TYPE_10M_FULL
;
3304 hw
->media_type
= MEDIA_TYPE_10M_HALF
;
3307 switch (hw
->media_type
) {
3308 case MEDIA_TYPE_AUTO_SENSOR
:
3310 ADVERTISED_10baseT_Half
|
3311 ADVERTISED_10baseT_Full
|
3312 ADVERTISED_100baseT_Half
|
3313 ADVERTISED_100baseT_Full
|
3314 ADVERTISED_1000baseT_Full
|
3315 ADVERTISED_Autoneg
| ADVERTISED_TP
;
3317 case MEDIA_TYPE_1000M_FULL
:
3319 ADVERTISED_1000baseT_Full
|
3320 ADVERTISED_Autoneg
| ADVERTISED_TP
;
3323 ecmd
->advertising
= 0;
3326 if (atl1_phy_setup_autoneg_adv(hw
)) {
3328 if (netif_msg_link(adapter
))
3329 dev_warn(&adapter
->pdev
->dev
,
3330 "invalid ethtool speed/duplex setting\n");
3333 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3334 hw
->media_type
== MEDIA_TYPE_1000M_FULL
)
3335 phy_data
= MII_CR_RESET
| MII_CR_AUTO_NEG_EN
;
3337 switch (hw
->media_type
) {
3338 case MEDIA_TYPE_100M_FULL
:
3340 MII_CR_FULL_DUPLEX
| MII_CR_SPEED_100
|
3343 case MEDIA_TYPE_100M_HALF
:
3344 phy_data
= MII_CR_SPEED_100
| MII_CR_RESET
;
3346 case MEDIA_TYPE_10M_FULL
:
3348 MII_CR_FULL_DUPLEX
| MII_CR_SPEED_10
| MII_CR_RESET
;
3351 /* MEDIA_TYPE_10M_HALF: */
3352 phy_data
= MII_CR_SPEED_10
| MII_CR_RESET
;
3356 atl1_write_phy_reg(hw
, MII_BMCR
, phy_data
);
3359 hw
->media_type
= old_media_type
;
3361 if (netif_running(adapter
->netdev
)) {
3362 if (netif_msg_link(adapter
))
3363 dev_dbg(&adapter
->pdev
->dev
,
3364 "ethtool starting adapter\n");
3366 } else if (!ret_val
) {
3367 if (netif_msg_link(adapter
))
3368 dev_dbg(&adapter
->pdev
->dev
,
3369 "ethtool resetting adapter\n");
3370 atl1_reset(adapter
);
3375 static void atl1_get_drvinfo(struct net_device
*netdev
,
3376 struct ethtool_drvinfo
*drvinfo
)
3378 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3380 strlcpy(drvinfo
->driver
, ATLX_DRIVER_NAME
, sizeof(drvinfo
->driver
));
3381 strlcpy(drvinfo
->version
, ATLX_DRIVER_VERSION
,
3382 sizeof(drvinfo
->version
));
3383 strlcpy(drvinfo
->fw_version
, "N/A", sizeof(drvinfo
->fw_version
));
3384 strlcpy(drvinfo
->bus_info
, pci_name(adapter
->pdev
),
3385 sizeof(drvinfo
->bus_info
));
3386 drvinfo
->eedump_len
= ATL1_EEDUMP_LEN
;
3389 static void atl1_get_wol(struct net_device
*netdev
,
3390 struct ethtool_wolinfo
*wol
)
3392 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3394 wol
->supported
= WAKE_MAGIC
;
3396 if (adapter
->wol
& ATLX_WUFC_MAG
)
3397 wol
->wolopts
|= WAKE_MAGIC
;
3400 static int atl1_set_wol(struct net_device
*netdev
,
3401 struct ethtool_wolinfo
*wol
)
3403 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3405 if (wol
->wolopts
& (WAKE_PHY
| WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
|
3406 WAKE_ARP
| WAKE_MAGICSECURE
))
3409 if (wol
->wolopts
& WAKE_MAGIC
)
3410 adapter
->wol
|= ATLX_WUFC_MAG
;
3414 static u32
atl1_get_msglevel(struct net_device
*netdev
)
3416 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3417 return adapter
->msg_enable
;
3420 static void atl1_set_msglevel(struct net_device
*netdev
, u32 value
)
3422 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3423 adapter
->msg_enable
= value
;
3426 static int atl1_get_regs_len(struct net_device
*netdev
)
3428 return ATL1_REG_COUNT
* sizeof(u32
);
3431 static void atl1_get_regs(struct net_device
*netdev
, struct ethtool_regs
*regs
,
3434 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3435 struct atl1_hw
*hw
= &adapter
->hw
;
3439 for (i
= 0; i
< ATL1_REG_COUNT
; i
++) {
3441 * This switch statement avoids reserved regions
3442 * of register space.
3467 /* reserved region; don't read it */
3471 /* unreserved region */
3472 regbuf
[i
] = ioread32(hw
->hw_addr
+ (i
* sizeof(u32
)));
3477 static void atl1_get_ringparam(struct net_device
*netdev
,
3478 struct ethtool_ringparam
*ring
)
3480 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3481 struct atl1_tpd_ring
*txdr
= &adapter
->tpd_ring
;
3482 struct atl1_rfd_ring
*rxdr
= &adapter
->rfd_ring
;
3484 ring
->rx_max_pending
= ATL1_MAX_RFD
;
3485 ring
->tx_max_pending
= ATL1_MAX_TPD
;
3486 ring
->rx_mini_max_pending
= 0;
3487 ring
->rx_jumbo_max_pending
= 0;
3488 ring
->rx_pending
= rxdr
->count
;
3489 ring
->tx_pending
= txdr
->count
;
3490 ring
->rx_mini_pending
= 0;
3491 ring
->rx_jumbo_pending
= 0;
3494 static int atl1_set_ringparam(struct net_device
*netdev
,
3495 struct ethtool_ringparam
*ring
)
3497 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3498 struct atl1_tpd_ring
*tpdr
= &adapter
->tpd_ring
;
3499 struct atl1_rrd_ring
*rrdr
= &adapter
->rrd_ring
;
3500 struct atl1_rfd_ring
*rfdr
= &adapter
->rfd_ring
;
3502 struct atl1_tpd_ring tpd_old
, tpd_new
;
3503 struct atl1_rfd_ring rfd_old
, rfd_new
;
3504 struct atl1_rrd_ring rrd_old
, rrd_new
;
3505 struct atl1_ring_header rhdr_old
, rhdr_new
;
3508 tpd_old
= adapter
->tpd_ring
;
3509 rfd_old
= adapter
->rfd_ring
;
3510 rrd_old
= adapter
->rrd_ring
;
3511 rhdr_old
= adapter
->ring_header
;
3513 if (netif_running(adapter
->netdev
))
3516 rfdr
->count
= (u16
) max(ring
->rx_pending
, (u32
) ATL1_MIN_RFD
);
3517 rfdr
->count
= rfdr
->count
> ATL1_MAX_RFD
? ATL1_MAX_RFD
:
3519 rfdr
->count
= (rfdr
->count
+ 3) & ~3;
3520 rrdr
->count
= rfdr
->count
;
3522 tpdr
->count
= (u16
) max(ring
->tx_pending
, (u32
) ATL1_MIN_TPD
);
3523 tpdr
->count
= tpdr
->count
> ATL1_MAX_TPD
? ATL1_MAX_TPD
:
3525 tpdr
->count
= (tpdr
->count
+ 3) & ~3;
3527 if (netif_running(adapter
->netdev
)) {
3528 /* try to get new resources before deleting old */
3529 err
= atl1_setup_ring_resources(adapter
);
3531 goto err_setup_ring
;
3534 * save the new, restore the old in order to free it,
3535 * then restore the new back again
3538 rfd_new
= adapter
->rfd_ring
;
3539 rrd_new
= adapter
->rrd_ring
;
3540 tpd_new
= adapter
->tpd_ring
;
3541 rhdr_new
= adapter
->ring_header
;
3542 adapter
->rfd_ring
= rfd_old
;
3543 adapter
->rrd_ring
= rrd_old
;
3544 adapter
->tpd_ring
= tpd_old
;
3545 adapter
->ring_header
= rhdr_old
;
3546 atl1_free_ring_resources(adapter
);
3547 adapter
->rfd_ring
= rfd_new
;
3548 adapter
->rrd_ring
= rrd_new
;
3549 adapter
->tpd_ring
= tpd_new
;
3550 adapter
->ring_header
= rhdr_new
;
3552 err
= atl1_up(adapter
);
3559 adapter
->rfd_ring
= rfd_old
;
3560 adapter
->rrd_ring
= rrd_old
;
3561 adapter
->tpd_ring
= tpd_old
;
3562 adapter
->ring_header
= rhdr_old
;
3567 static void atl1_get_pauseparam(struct net_device
*netdev
,
3568 struct ethtool_pauseparam
*epause
)
3570 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3571 struct atl1_hw
*hw
= &adapter
->hw
;
3573 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3574 hw
->media_type
== MEDIA_TYPE_1000M_FULL
) {
3575 epause
->autoneg
= AUTONEG_ENABLE
;
3577 epause
->autoneg
= AUTONEG_DISABLE
;
3579 epause
->rx_pause
= 1;
3580 epause
->tx_pause
= 1;
3583 static int atl1_set_pauseparam(struct net_device
*netdev
,
3584 struct ethtool_pauseparam
*epause
)
3586 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3587 struct atl1_hw
*hw
= &adapter
->hw
;
3589 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3590 hw
->media_type
== MEDIA_TYPE_1000M_FULL
) {
3591 epause
->autoneg
= AUTONEG_ENABLE
;
3593 epause
->autoneg
= AUTONEG_DISABLE
;
3596 epause
->rx_pause
= 1;
3597 epause
->tx_pause
= 1;
3602 /* FIXME: is this right? -- CHS */
3603 static u32
atl1_get_rx_csum(struct net_device
*netdev
)
3608 static void atl1_get_strings(struct net_device
*netdev
, u32 stringset
,
3614 switch (stringset
) {
3616 for (i
= 0; i
< ARRAY_SIZE(atl1_gstrings_stats
); i
++) {
3617 memcpy(p
, atl1_gstrings_stats
[i
].stat_string
,
3619 p
+= ETH_GSTRING_LEN
;
3625 static int atl1_nway_reset(struct net_device
*netdev
)
3627 struct atl1_adapter
*adapter
= netdev_priv(netdev
);
3628 struct atl1_hw
*hw
= &adapter
->hw
;
3630 if (netif_running(netdev
)) {
3634 if (hw
->media_type
== MEDIA_TYPE_AUTO_SENSOR
||
3635 hw
->media_type
== MEDIA_TYPE_1000M_FULL
) {
3636 phy_data
= MII_CR_RESET
| MII_CR_AUTO_NEG_EN
;
3638 switch (hw
->media_type
) {
3639 case MEDIA_TYPE_100M_FULL
:
3640 phy_data
= MII_CR_FULL_DUPLEX
|
3641 MII_CR_SPEED_100
| MII_CR_RESET
;
3643 case MEDIA_TYPE_100M_HALF
:
3644 phy_data
= MII_CR_SPEED_100
| MII_CR_RESET
;
3646 case MEDIA_TYPE_10M_FULL
:
3647 phy_data
= MII_CR_FULL_DUPLEX
|
3648 MII_CR_SPEED_10
| MII_CR_RESET
;
3651 /* MEDIA_TYPE_10M_HALF */
3652 phy_data
= MII_CR_SPEED_10
| MII_CR_RESET
;
3655 atl1_write_phy_reg(hw
, MII_BMCR
, phy_data
);
3661 const struct ethtool_ops atl1_ethtool_ops
= {
3662 .get_settings
= atl1_get_settings
,
3663 .set_settings
= atl1_set_settings
,
3664 .get_drvinfo
= atl1_get_drvinfo
,
3665 .get_wol
= atl1_get_wol
,
3666 .set_wol
= atl1_set_wol
,
3667 .get_msglevel
= atl1_get_msglevel
,
3668 .set_msglevel
= atl1_set_msglevel
,
3669 .get_regs_len
= atl1_get_regs_len
,
3670 .get_regs
= atl1_get_regs
,
3671 .get_ringparam
= atl1_get_ringparam
,
3672 .set_ringparam
= atl1_set_ringparam
,
3673 .get_pauseparam
= atl1_get_pauseparam
,
3674 .set_pauseparam
= atl1_set_pauseparam
,
3675 .get_rx_csum
= atl1_get_rx_csum
,
3676 .set_tx_csum
= ethtool_op_set_tx_hw_csum
,
3677 .get_link
= ethtool_op_get_link
,
3678 .set_sg
= ethtool_op_set_sg
,
3679 .get_strings
= atl1_get_strings
,
3680 .nway_reset
= atl1_nway_reset
,
3681 .get_ethtool_stats
= atl1_get_ethtool_stats
,
3682 .get_sset_count
= atl1_get_sset_count
,
3683 .set_tso
= ethtool_op_set_tso
,