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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / atlx / atl2.c
1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <asm/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/string.h>
45 #include <linux/tcp.h>
46 #include <linux/timer.h>
47 #include <linux/types.h>
48 #include <linux/workqueue.h>
49
50 #include "atl2.h"
51
52 #define ATL2_DRV_VERSION "2.2.3"
53
54 static const char atl2_driver_name[] = "atl2";
55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57 static const char atl2_driver_version[] = ATL2_DRV_VERSION;
58
59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61 MODULE_LICENSE("GPL");
62 MODULE_VERSION(ATL2_DRV_VERSION);
63
64 /*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71 };
72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74 static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76 static void atl2_check_options(struct atl2_adapter *adapter);
77
78 /*
79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86 static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87 {
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
96 hw->revision_id = pdev->revision;
97
98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124 }
125
126 /*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135 static void atl2_set_multi(struct net_device *netdev)
136 {
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct netdev_hw_addr *ha;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 netdev_for_each_mc_addr(ha, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, ha->addr);
163 atl2_hash_set(hw, hash_value);
164 }
165 }
166
167 static void init_ring_ptrs(struct atl2_adapter *adapter)
168 {
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178 }
179
180 /*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186 static int atl2_configure(struct atl2_adapter *adapter)
187 {
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222 /*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225 */
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284 }
285
286 /*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293 {
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = adapter->ring_vir_addr + offset;
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336 /*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341 }
342
343 /*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348 {
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351 }
352
353 /*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358 {
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362 }
363
364 #ifdef NETIF_F_HW_VLAN_TX
365 static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367 {
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387 }
388
389 static void atl2_restore_vlan(struct atl2_adapter *adapter)
390 {
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392 }
393 #endif
394
395 static void atl2_intr_rx(struct atl2_adapter *adapter)
396 {
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
412 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
421 netdev->stats.rx_dropped++;
422 break;
423 }
424 memcpy(skb->data, rxd->packet, rx_size);
425 skb_put(skb, rx_size);
426 skb->protocol = eth_type_trans(skb, netdev);
427 #ifdef NETIF_F_HW_VLAN_TX
428 if (adapter->vlgrp && (rxd->status.vlan)) {
429 u16 vlan_tag = (rxd->status.vtag>>4) |
430 ((rxd->status.vtag&7) << 13) |
431 ((rxd->status.vtag&8) << 9);
432 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
433 } else
434 #endif
435 netif_rx(skb);
436 netdev->stats.rx_bytes += rx_size;
437 netdev->stats.rx_packets++;
438 } else {
439 netdev->stats.rx_errors++;
440
441 if (rxd->status.ok && rxd->status.pkt_size <= 60)
442 netdev->stats.rx_length_errors++;
443 if (rxd->status.mcast)
444 netdev->stats.multicast++;
445 if (rxd->status.crc)
446 netdev->stats.rx_crc_errors++;
447 if (rxd->status.align)
448 netdev->stats.rx_frame_errors++;
449 }
450
451 /* advance write ptr */
452 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
453 adapter->rxd_write_ptr = 0;
454 } while (1);
455
456 /* update mailbox? */
457 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
458 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
459 }
460
461 static void atl2_intr_tx(struct atl2_adapter *adapter)
462 {
463 struct net_device *netdev = adapter->netdev;
464 u32 txd_read_ptr;
465 u32 txs_write_ptr;
466 struct tx_pkt_status *txs;
467 struct tx_pkt_header *txph;
468 int free_hole = 0;
469
470 do {
471 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
472 txs = adapter->txs_ring + txs_write_ptr;
473 if (!txs->update)
474 break; /* tx stop here */
475
476 free_hole = 1;
477 txs->update = 0;
478
479 if (++txs_write_ptr == adapter->txs_ring_size)
480 txs_write_ptr = 0;
481 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
482
483 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
484 txph = (struct tx_pkt_header *)
485 (((u8 *)adapter->txd_ring) + txd_read_ptr);
486
487 if (txph->pkt_size != txs->pkt_size) {
488 struct tx_pkt_status *old_txs = txs;
489 printk(KERN_WARNING
490 "%s: txs packet size not consistent with txd"
491 " txd_:0x%08x, txs_:0x%08x!\n",
492 adapter->netdev->name,
493 *(u32 *)txph, *(u32 *)txs);
494 printk(KERN_WARNING
495 "txd read ptr: 0x%x\n",
496 txd_read_ptr);
497 txs = adapter->txs_ring + txs_write_ptr;
498 printk(KERN_WARNING
499 "txs-behind:0x%08x\n",
500 *(u32 *)txs);
501 if (txs_write_ptr < 2) {
502 txs = adapter->txs_ring +
503 (adapter->txs_ring_size +
504 txs_write_ptr - 2);
505 } else {
506 txs = adapter->txs_ring + (txs_write_ptr - 2);
507 }
508 printk(KERN_WARNING
509 "txs-before:0x%08x\n",
510 *(u32 *)txs);
511 txs = old_txs;
512 }
513
514 /* 4for TPH */
515 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
516 if (txd_read_ptr >= adapter->txd_ring_size)
517 txd_read_ptr -= adapter->txd_ring_size;
518
519 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
520
521 /* tx statistics: */
522 if (txs->ok) {
523 netdev->stats.tx_bytes += txs->pkt_size;
524 netdev->stats.tx_packets++;
525 }
526 else
527 netdev->stats.tx_errors++;
528
529 if (txs->defer)
530 netdev->stats.collisions++;
531 if (txs->abort_col)
532 netdev->stats.tx_aborted_errors++;
533 if (txs->late_col)
534 netdev->stats.tx_window_errors++;
535 if (txs->underun)
536 netdev->stats.tx_fifo_errors++;
537 } while (1);
538
539 if (free_hole) {
540 if (netif_queue_stopped(adapter->netdev) &&
541 netif_carrier_ok(adapter->netdev))
542 netif_wake_queue(adapter->netdev);
543 }
544 }
545
546 static void atl2_check_for_link(struct atl2_adapter *adapter)
547 {
548 struct net_device *netdev = adapter->netdev;
549 u16 phy_data = 0;
550
551 spin_lock(&adapter->stats_lock);
552 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
554 spin_unlock(&adapter->stats_lock);
555
556 /* notify upper layer link down ASAP */
557 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
558 if (netif_carrier_ok(netdev)) { /* old link state: Up */
559 printk(KERN_INFO "%s: %s NIC Link is Down\n",
560 atl2_driver_name, netdev->name);
561 adapter->link_speed = SPEED_0;
562 netif_carrier_off(netdev);
563 netif_stop_queue(netdev);
564 }
565 }
566 schedule_work(&adapter->link_chg_task);
567 }
568
569 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
570 {
571 u16 phy_data;
572 spin_lock(&adapter->stats_lock);
573 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
574 spin_unlock(&adapter->stats_lock);
575 }
576
577 /*
578 * atl2_intr - Interrupt Handler
579 * @irq: interrupt number
580 * @data: pointer to a network interface device structure
581 * @pt_regs: CPU registers structure
582 */
583 static irqreturn_t atl2_intr(int irq, void *data)
584 {
585 struct atl2_adapter *adapter = netdev_priv(data);
586 struct atl2_hw *hw = &adapter->hw;
587 u32 status;
588
589 status = ATL2_READ_REG(hw, REG_ISR);
590 if (0 == status)
591 return IRQ_NONE;
592
593 /* link event */
594 if (status & ISR_PHY)
595 atl2_clear_phy_int(adapter);
596
597 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
598 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
599
600 /* check if PCIE PHY Link down */
601 if (status & ISR_PHY_LINKDOWN) {
602 if (netif_running(adapter->netdev)) { /* reset MAC */
603 ATL2_WRITE_REG(hw, REG_ISR, 0);
604 ATL2_WRITE_REG(hw, REG_IMR, 0);
605 ATL2_WRITE_FLUSH(hw);
606 schedule_work(&adapter->reset_task);
607 return IRQ_HANDLED;
608 }
609 }
610
611 /* check if DMA read/write error? */
612 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
613 ATL2_WRITE_REG(hw, REG_ISR, 0);
614 ATL2_WRITE_REG(hw, REG_IMR, 0);
615 ATL2_WRITE_FLUSH(hw);
616 schedule_work(&adapter->reset_task);
617 return IRQ_HANDLED;
618 }
619
620 /* link event */
621 if (status & (ISR_PHY | ISR_MANUAL)) {
622 adapter->netdev->stats.tx_carrier_errors++;
623 atl2_check_for_link(adapter);
624 }
625
626 /* transmit event */
627 if (status & ISR_TX_EVENT)
628 atl2_intr_tx(adapter);
629
630 /* rx exception */
631 if (status & ISR_RX_EVENT)
632 atl2_intr_rx(adapter);
633
634 /* re-enable Interrupt */
635 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
636 return IRQ_HANDLED;
637 }
638
639 static int atl2_request_irq(struct atl2_adapter *adapter)
640 {
641 struct net_device *netdev = adapter->netdev;
642 int flags, err = 0;
643
644 flags = IRQF_SHARED;
645 adapter->have_msi = true;
646 err = pci_enable_msi(adapter->pdev);
647 if (err)
648 adapter->have_msi = false;
649
650 if (adapter->have_msi)
651 flags &= ~IRQF_SHARED;
652
653 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
654 netdev);
655 }
656
657 /*
658 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
659 * @adapter: board private structure
660 *
661 * Free all transmit software resources
662 */
663 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
664 {
665 struct pci_dev *pdev = adapter->pdev;
666 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
667 adapter->ring_dma);
668 }
669
670 /*
671 * atl2_open - Called when a network interface is made active
672 * @netdev: network interface device structure
673 *
674 * Returns 0 on success, negative value on failure
675 *
676 * The open entry point is called when a network interface is made
677 * active by the system (IFF_UP). At this point all resources needed
678 * for transmit and receive operations are allocated, the interrupt
679 * handler is registered with the OS, the watchdog timer is started,
680 * and the stack is notified that the interface is ready.
681 */
682 static int atl2_open(struct net_device *netdev)
683 {
684 struct atl2_adapter *adapter = netdev_priv(netdev);
685 int err;
686 u32 val;
687
688 /* disallow open during test */
689 if (test_bit(__ATL2_TESTING, &adapter->flags))
690 return -EBUSY;
691
692 /* allocate transmit descriptors */
693 err = atl2_setup_ring_resources(adapter);
694 if (err)
695 return err;
696
697 err = atl2_init_hw(&adapter->hw);
698 if (err) {
699 err = -EIO;
700 goto err_init_hw;
701 }
702
703 /* hardware has been reset, we need to reload some things */
704 atl2_set_multi(netdev);
705 init_ring_ptrs(adapter);
706
707 #ifdef NETIF_F_HW_VLAN_TX
708 atl2_restore_vlan(adapter);
709 #endif
710
711 if (atl2_configure(adapter)) {
712 err = -EIO;
713 goto err_config;
714 }
715
716 err = atl2_request_irq(adapter);
717 if (err)
718 goto err_req_irq;
719
720 clear_bit(__ATL2_DOWN, &adapter->flags);
721
722 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
723
724 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
725 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
726 val | MASTER_CTRL_MANUAL_INT);
727
728 atl2_irq_enable(adapter);
729
730 return 0;
731
732 err_init_hw:
733 err_req_irq:
734 err_config:
735 atl2_free_ring_resources(adapter);
736 atl2_reset_hw(&adapter->hw);
737
738 return err;
739 }
740
741 static void atl2_down(struct atl2_adapter *adapter)
742 {
743 struct net_device *netdev = adapter->netdev;
744
745 /* signal that we're down so the interrupt handler does not
746 * reschedule our watchdog timer */
747 set_bit(__ATL2_DOWN, &adapter->flags);
748
749 netif_tx_disable(netdev);
750
751 /* reset MAC to disable all RX/TX */
752 atl2_reset_hw(&adapter->hw);
753 msleep(1);
754
755 atl2_irq_disable(adapter);
756
757 del_timer_sync(&adapter->watchdog_timer);
758 del_timer_sync(&adapter->phy_config_timer);
759 clear_bit(0, &adapter->cfg_phy);
760
761 netif_carrier_off(netdev);
762 adapter->link_speed = SPEED_0;
763 adapter->link_duplex = -1;
764 }
765
766 static void atl2_free_irq(struct atl2_adapter *adapter)
767 {
768 struct net_device *netdev = adapter->netdev;
769
770 free_irq(adapter->pdev->irq, netdev);
771
772 #ifdef CONFIG_PCI_MSI
773 if (adapter->have_msi)
774 pci_disable_msi(adapter->pdev);
775 #endif
776 }
777
778 /*
779 * atl2_close - Disables a network interface
780 * @netdev: network interface device structure
781 *
782 * Returns 0, this is not allowed to fail
783 *
784 * The close entry point is called when an interface is de-activated
785 * by the OS. The hardware is still under the drivers control, but
786 * needs to be disabled. A global MAC reset is issued to stop the
787 * hardware, and all transmit and receive resources are freed.
788 */
789 static int atl2_close(struct net_device *netdev)
790 {
791 struct atl2_adapter *adapter = netdev_priv(netdev);
792
793 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
794
795 atl2_down(adapter);
796 atl2_free_irq(adapter);
797 atl2_free_ring_resources(adapter);
798
799 return 0;
800 }
801
802 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
803 {
804 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
805
806 return (adapter->txs_next_clear >= txs_write_ptr) ?
807 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
808 txs_write_ptr - 1) :
809 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
810 }
811
812 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
813 {
814 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
815
816 return (adapter->txd_write_ptr >= txd_read_ptr) ?
817 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
818 txd_read_ptr - 1) :
819 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
820 }
821
822 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
823 struct net_device *netdev)
824 {
825 struct atl2_adapter *adapter = netdev_priv(netdev);
826 struct tx_pkt_header *txph;
827 u32 offset, copy_len;
828 int txs_unused;
829 int txbuf_unused;
830
831 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
832 dev_kfree_skb_any(skb);
833 return NETDEV_TX_OK;
834 }
835
836 if (unlikely(skb->len <= 0)) {
837 dev_kfree_skb_any(skb);
838 return NETDEV_TX_OK;
839 }
840
841 txs_unused = TxsFreeUnit(adapter);
842 txbuf_unused = TxdFreeBytes(adapter);
843
844 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
845 txs_unused < 1) {
846 /* not enough resources */
847 netif_stop_queue(netdev);
848 return NETDEV_TX_BUSY;
849 }
850
851 offset = adapter->txd_write_ptr;
852
853 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
854
855 *(u32 *)txph = 0;
856 txph->pkt_size = skb->len;
857
858 offset += 4;
859 if (offset >= adapter->txd_ring_size)
860 offset -= adapter->txd_ring_size;
861 copy_len = adapter->txd_ring_size - offset;
862 if (copy_len >= skb->len) {
863 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
864 offset += ((u32)(skb->len + 3) & ~3);
865 } else {
866 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
867 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
868 skb->len-copy_len);
869 offset = ((u32)(skb->len-copy_len + 3) & ~3);
870 }
871 #ifdef NETIF_F_HW_VLAN_TX
872 if (vlan_tx_tag_present(skb)) {
873 u16 vlan_tag = vlan_tx_tag_get(skb);
874 vlan_tag = (vlan_tag << 4) |
875 (vlan_tag >> 13) |
876 ((vlan_tag >> 9) & 0x8);
877 txph->ins_vlan = 1;
878 txph->vlan = vlan_tag;
879 }
880 #endif
881 if (offset >= adapter->txd_ring_size)
882 offset -= adapter->txd_ring_size;
883 adapter->txd_write_ptr = offset;
884
885 /* clear txs before send */
886 adapter->txs_ring[adapter->txs_next_clear].update = 0;
887 if (++adapter->txs_next_clear == adapter->txs_ring_size)
888 adapter->txs_next_clear = 0;
889
890 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
891 (adapter->txd_write_ptr >> 2));
892
893 mmiowb();
894 dev_kfree_skb_any(skb);
895 return NETDEV_TX_OK;
896 }
897
898 /*
899 * atl2_change_mtu - Change the Maximum Transfer Unit
900 * @netdev: network interface device structure
901 * @new_mtu: new value for maximum frame size
902 *
903 * Returns 0 on success, negative on failure
904 */
905 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
906 {
907 struct atl2_adapter *adapter = netdev_priv(netdev);
908 struct atl2_hw *hw = &adapter->hw;
909
910 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
911 return -EINVAL;
912
913 /* set MTU */
914 if (hw->max_frame_size != new_mtu) {
915 netdev->mtu = new_mtu;
916 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
917 VLAN_SIZE + ETHERNET_FCS_SIZE);
918 }
919
920 return 0;
921 }
922
923 /*
924 * atl2_set_mac - Change the Ethernet Address of the NIC
925 * @netdev: network interface device structure
926 * @p: pointer to an address structure
927 *
928 * Returns 0 on success, negative on failure
929 */
930 static int atl2_set_mac(struct net_device *netdev, void *p)
931 {
932 struct atl2_adapter *adapter = netdev_priv(netdev);
933 struct sockaddr *addr = p;
934
935 if (!is_valid_ether_addr(addr->sa_data))
936 return -EADDRNOTAVAIL;
937
938 if (netif_running(netdev))
939 return -EBUSY;
940
941 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
942 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
943
944 atl2_set_mac_addr(&adapter->hw);
945
946 return 0;
947 }
948
949 /*
950 * atl2_mii_ioctl -
951 * @netdev:
952 * @ifreq:
953 * @cmd:
954 */
955 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
956 {
957 struct atl2_adapter *adapter = netdev_priv(netdev);
958 struct mii_ioctl_data *data = if_mii(ifr);
959 unsigned long flags;
960
961 switch (cmd) {
962 case SIOCGMIIPHY:
963 data->phy_id = 0;
964 break;
965 case SIOCGMIIREG:
966 spin_lock_irqsave(&adapter->stats_lock, flags);
967 if (atl2_read_phy_reg(&adapter->hw,
968 data->reg_num & 0x1F, &data->val_out)) {
969 spin_unlock_irqrestore(&adapter->stats_lock, flags);
970 return -EIO;
971 }
972 spin_unlock_irqrestore(&adapter->stats_lock, flags);
973 break;
974 case SIOCSMIIREG:
975 if (data->reg_num & ~(0x1F))
976 return -EFAULT;
977 spin_lock_irqsave(&adapter->stats_lock, flags);
978 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
979 data->val_in)) {
980 spin_unlock_irqrestore(&adapter->stats_lock, flags);
981 return -EIO;
982 }
983 spin_unlock_irqrestore(&adapter->stats_lock, flags);
984 break;
985 default:
986 return -EOPNOTSUPP;
987 }
988 return 0;
989 }
990
991 /*
992 * atl2_ioctl -
993 * @netdev:
994 * @ifreq:
995 * @cmd:
996 */
997 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
998 {
999 switch (cmd) {
1000 case SIOCGMIIPHY:
1001 case SIOCGMIIREG:
1002 case SIOCSMIIREG:
1003 return atl2_mii_ioctl(netdev, ifr, cmd);
1004 #ifdef ETHTOOL_OPS_COMPAT
1005 case SIOCETHTOOL:
1006 return ethtool_ioctl(ifr);
1007 #endif
1008 default:
1009 return -EOPNOTSUPP;
1010 }
1011 }
1012
1013 /*
1014 * atl2_tx_timeout - Respond to a Tx Hang
1015 * @netdev: network interface device structure
1016 */
1017 static void atl2_tx_timeout(struct net_device *netdev)
1018 {
1019 struct atl2_adapter *adapter = netdev_priv(netdev);
1020
1021 /* Do the reset outside of interrupt context */
1022 schedule_work(&adapter->reset_task);
1023 }
1024
1025 /*
1026 * atl2_watchdog - Timer Call-back
1027 * @data: pointer to netdev cast into an unsigned long
1028 */
1029 static void atl2_watchdog(unsigned long data)
1030 {
1031 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1032
1033 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1034 u32 drop_rxd, drop_rxs;
1035 unsigned long flags;
1036
1037 spin_lock_irqsave(&adapter->stats_lock, flags);
1038 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1039 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1040 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1041
1042 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1043
1044 /* Reset the timer */
1045 mod_timer(&adapter->watchdog_timer,
1046 round_jiffies(jiffies + 4 * HZ));
1047 }
1048 }
1049
1050 /*
1051 * atl2_phy_config - Timer Call-back
1052 * @data: pointer to netdev cast into an unsigned long
1053 */
1054 static void atl2_phy_config(unsigned long data)
1055 {
1056 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1057 struct atl2_hw *hw = &adapter->hw;
1058 unsigned long flags;
1059
1060 spin_lock_irqsave(&adapter->stats_lock, flags);
1061 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1062 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1063 MII_CR_RESTART_AUTO_NEG);
1064 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1065 clear_bit(0, &adapter->cfg_phy);
1066 }
1067
1068 static int atl2_up(struct atl2_adapter *adapter)
1069 {
1070 struct net_device *netdev = adapter->netdev;
1071 int err = 0;
1072 u32 val;
1073
1074 /* hardware has been reset, we need to reload some things */
1075
1076 err = atl2_init_hw(&adapter->hw);
1077 if (err) {
1078 err = -EIO;
1079 return err;
1080 }
1081
1082 atl2_set_multi(netdev);
1083 init_ring_ptrs(adapter);
1084
1085 #ifdef NETIF_F_HW_VLAN_TX
1086 atl2_restore_vlan(adapter);
1087 #endif
1088
1089 if (atl2_configure(adapter)) {
1090 err = -EIO;
1091 goto err_up;
1092 }
1093
1094 clear_bit(__ATL2_DOWN, &adapter->flags);
1095
1096 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1097 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1098 MASTER_CTRL_MANUAL_INT);
1099
1100 atl2_irq_enable(adapter);
1101
1102 err_up:
1103 return err;
1104 }
1105
1106 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1107 {
1108 WARN_ON(in_interrupt());
1109 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1110 msleep(1);
1111 atl2_down(adapter);
1112 atl2_up(adapter);
1113 clear_bit(__ATL2_RESETTING, &adapter->flags);
1114 }
1115
1116 static void atl2_reset_task(struct work_struct *work)
1117 {
1118 struct atl2_adapter *adapter;
1119 adapter = container_of(work, struct atl2_adapter, reset_task);
1120
1121 atl2_reinit_locked(adapter);
1122 }
1123
1124 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1125 {
1126 u32 value;
1127 struct atl2_hw *hw = &adapter->hw;
1128 struct net_device *netdev = adapter->netdev;
1129
1130 /* Config MAC CTRL Register */
1131 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1132
1133 /* duplex */
1134 if (FULL_DUPLEX == adapter->link_duplex)
1135 value |= MAC_CTRL_DUPLX;
1136
1137 /* flow control */
1138 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1139
1140 /* PAD & CRC */
1141 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1142
1143 /* preamble length */
1144 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1145 MAC_CTRL_PRMLEN_SHIFT);
1146
1147 /* vlan */
1148 if (adapter->vlgrp)
1149 value |= MAC_CTRL_RMV_VLAN;
1150
1151 /* filter mode */
1152 value |= MAC_CTRL_BC_EN;
1153 if (netdev->flags & IFF_PROMISC)
1154 value |= MAC_CTRL_PROMIS_EN;
1155 else if (netdev->flags & IFF_ALLMULTI)
1156 value |= MAC_CTRL_MC_ALL_EN;
1157
1158 /* half retry buffer */
1159 value |= (((u32)(adapter->hw.retry_buf &
1160 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1161
1162 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1163 }
1164
1165 static int atl2_check_link(struct atl2_adapter *adapter)
1166 {
1167 struct atl2_hw *hw = &adapter->hw;
1168 struct net_device *netdev = adapter->netdev;
1169 int ret_val;
1170 u16 speed, duplex, phy_data;
1171 int reconfig = 0;
1172
1173 /* MII_BMSR must read twise */
1174 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1175 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1176 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1177 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1178 u32 value;
1179 /* disable rx */
1180 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1181 value &= ~MAC_CTRL_RX_EN;
1182 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1183 adapter->link_speed = SPEED_0;
1184 netif_carrier_off(netdev);
1185 netif_stop_queue(netdev);
1186 }
1187 return 0;
1188 }
1189
1190 /* Link Up */
1191 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1192 if (ret_val)
1193 return ret_val;
1194 switch (hw->MediaType) {
1195 case MEDIA_TYPE_100M_FULL:
1196 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1197 reconfig = 1;
1198 break;
1199 case MEDIA_TYPE_100M_HALF:
1200 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1201 reconfig = 1;
1202 break;
1203 case MEDIA_TYPE_10M_FULL:
1204 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1205 reconfig = 1;
1206 break;
1207 case MEDIA_TYPE_10M_HALF:
1208 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1209 reconfig = 1;
1210 break;
1211 }
1212 /* link result is our setting */
1213 if (reconfig == 0) {
1214 if (adapter->link_speed != speed ||
1215 adapter->link_duplex != duplex) {
1216 adapter->link_speed = speed;
1217 adapter->link_duplex = duplex;
1218 atl2_setup_mac_ctrl(adapter);
1219 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1220 atl2_driver_name, netdev->name,
1221 adapter->link_speed,
1222 adapter->link_duplex == FULL_DUPLEX ?
1223 "Full Duplex" : "Half Duplex");
1224 }
1225
1226 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1227 netif_carrier_on(netdev);
1228 netif_wake_queue(netdev);
1229 }
1230 return 0;
1231 }
1232
1233 /* change original link status */
1234 if (netif_carrier_ok(netdev)) {
1235 u32 value;
1236 /* disable rx */
1237 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1238 value &= ~MAC_CTRL_RX_EN;
1239 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1240
1241 adapter->link_speed = SPEED_0;
1242 netif_carrier_off(netdev);
1243 netif_stop_queue(netdev);
1244 }
1245
1246 /* auto-neg, insert timer to re-config phy
1247 * (if interval smaller than 5 seconds, something strange) */
1248 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1249 if (!test_and_set_bit(0, &adapter->cfg_phy))
1250 mod_timer(&adapter->phy_config_timer,
1251 round_jiffies(jiffies + 5 * HZ));
1252 }
1253
1254 return 0;
1255 }
1256
1257 /*
1258 * atl2_link_chg_task - deal with link change event Out of interrupt context
1259 * @netdev: network interface device structure
1260 */
1261 static void atl2_link_chg_task(struct work_struct *work)
1262 {
1263 struct atl2_adapter *adapter;
1264 unsigned long flags;
1265
1266 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1267
1268 spin_lock_irqsave(&adapter->stats_lock, flags);
1269 atl2_check_link(adapter);
1270 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1271 }
1272
1273 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1274 {
1275 u16 cmd;
1276
1277 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1278
1279 if (cmd & PCI_COMMAND_INTX_DISABLE)
1280 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1281 if (cmd & PCI_COMMAND_IO)
1282 cmd &= ~PCI_COMMAND_IO;
1283 if (0 == (cmd & PCI_COMMAND_MEMORY))
1284 cmd |= PCI_COMMAND_MEMORY;
1285 if (0 == (cmd & PCI_COMMAND_MASTER))
1286 cmd |= PCI_COMMAND_MASTER;
1287 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1288
1289 /*
1290 * some motherboards BIOS(PXE/EFI) driver may set PME
1291 * while they transfer control to OS (Windows/Linux)
1292 * so we should clear this bit before NIC work normally
1293 */
1294 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1295 }
1296
1297 #ifdef CONFIG_NET_POLL_CONTROLLER
1298 static void atl2_poll_controller(struct net_device *netdev)
1299 {
1300 disable_irq(netdev->irq);
1301 atl2_intr(netdev->irq, netdev);
1302 enable_irq(netdev->irq);
1303 }
1304 #endif
1305
1306
1307 static const struct net_device_ops atl2_netdev_ops = {
1308 .ndo_open = atl2_open,
1309 .ndo_stop = atl2_close,
1310 .ndo_start_xmit = atl2_xmit_frame,
1311 .ndo_set_multicast_list = atl2_set_multi,
1312 .ndo_validate_addr = eth_validate_addr,
1313 .ndo_set_mac_address = atl2_set_mac,
1314 .ndo_change_mtu = atl2_change_mtu,
1315 .ndo_do_ioctl = atl2_ioctl,
1316 .ndo_tx_timeout = atl2_tx_timeout,
1317 .ndo_vlan_rx_register = atl2_vlan_rx_register,
1318 #ifdef CONFIG_NET_POLL_CONTROLLER
1319 .ndo_poll_controller = atl2_poll_controller,
1320 #endif
1321 };
1322
1323 /*
1324 * atl2_probe - Device Initialization Routine
1325 * @pdev: PCI device information struct
1326 * @ent: entry in atl2_pci_tbl
1327 *
1328 * Returns 0 on success, negative on failure
1329 *
1330 * atl2_probe initializes an adapter identified by a pci_dev structure.
1331 * The OS initialization, configuring of the adapter private structure,
1332 * and a hardware reset occur.
1333 */
1334 static int __devinit atl2_probe(struct pci_dev *pdev,
1335 const struct pci_device_id *ent)
1336 {
1337 struct net_device *netdev;
1338 struct atl2_adapter *adapter;
1339 static int cards_found;
1340 unsigned long mmio_start;
1341 int mmio_len;
1342 int err;
1343
1344 cards_found = 0;
1345
1346 err = pci_enable_device(pdev);
1347 if (err)
1348 return err;
1349
1350 /*
1351 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1352 * until the kernel has the proper infrastructure to support 64-bit DMA
1353 * on these devices.
1354 */
1355 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1356 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1357 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1358 goto err_dma;
1359 }
1360
1361 /* Mark all PCI regions associated with PCI device
1362 * pdev as being reserved by owner atl2_driver_name */
1363 err = pci_request_regions(pdev, atl2_driver_name);
1364 if (err)
1365 goto err_pci_reg;
1366
1367 /* Enables bus-mastering on the device and calls
1368 * pcibios_set_master to do the needed arch specific settings */
1369 pci_set_master(pdev);
1370
1371 err = -ENOMEM;
1372 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1373 if (!netdev)
1374 goto err_alloc_etherdev;
1375
1376 SET_NETDEV_DEV(netdev, &pdev->dev);
1377
1378 pci_set_drvdata(pdev, netdev);
1379 adapter = netdev_priv(netdev);
1380 adapter->netdev = netdev;
1381 adapter->pdev = pdev;
1382 adapter->hw.back = adapter;
1383
1384 mmio_start = pci_resource_start(pdev, 0x0);
1385 mmio_len = pci_resource_len(pdev, 0x0);
1386
1387 adapter->hw.mem_rang = (u32)mmio_len;
1388 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1389 if (!adapter->hw.hw_addr) {
1390 err = -EIO;
1391 goto err_ioremap;
1392 }
1393
1394 atl2_setup_pcicmd(pdev);
1395
1396 netdev->netdev_ops = &atl2_netdev_ops;
1397 atl2_set_ethtool_ops(netdev);
1398 netdev->watchdog_timeo = 5 * HZ;
1399 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1400
1401 netdev->mem_start = mmio_start;
1402 netdev->mem_end = mmio_start + mmio_len;
1403 adapter->bd_number = cards_found;
1404 adapter->pci_using_64 = false;
1405
1406 /* setup the private structure */
1407 err = atl2_sw_init(adapter);
1408 if (err)
1409 goto err_sw_init;
1410
1411 err = -EIO;
1412
1413 netdev->hw_features = NETIF_F_SG;
1414 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1415
1416 /* Init PHY as early as possible due to power saving issue */
1417 atl2_phy_init(&adapter->hw);
1418
1419 /* reset the controller to
1420 * put the device in a known good starting state */
1421
1422 if (atl2_reset_hw(&adapter->hw)) {
1423 err = -EIO;
1424 goto err_reset;
1425 }
1426
1427 /* copy the MAC address out of the EEPROM */
1428 atl2_read_mac_addr(&adapter->hw);
1429 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1430 /* FIXME: do we still need this? */
1431 #ifdef ETHTOOL_GPERMADDR
1432 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1433
1434 if (!is_valid_ether_addr(netdev->perm_addr)) {
1435 #else
1436 if (!is_valid_ether_addr(netdev->dev_addr)) {
1437 #endif
1438 err = -EIO;
1439 goto err_eeprom;
1440 }
1441
1442 atl2_check_options(adapter);
1443
1444 init_timer(&adapter->watchdog_timer);
1445 adapter->watchdog_timer.function = atl2_watchdog;
1446 adapter->watchdog_timer.data = (unsigned long) adapter;
1447
1448 init_timer(&adapter->phy_config_timer);
1449 adapter->phy_config_timer.function = atl2_phy_config;
1450 adapter->phy_config_timer.data = (unsigned long) adapter;
1451
1452 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1453 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1454
1455 strcpy(netdev->name, "eth%d"); /* ?? */
1456 err = register_netdev(netdev);
1457 if (err)
1458 goto err_register;
1459
1460 /* assume we have no link for now */
1461 netif_carrier_off(netdev);
1462 netif_stop_queue(netdev);
1463
1464 cards_found++;
1465
1466 return 0;
1467
1468 err_reset:
1469 err_register:
1470 err_sw_init:
1471 err_eeprom:
1472 iounmap(adapter->hw.hw_addr);
1473 err_ioremap:
1474 free_netdev(netdev);
1475 err_alloc_etherdev:
1476 pci_release_regions(pdev);
1477 err_pci_reg:
1478 err_dma:
1479 pci_disable_device(pdev);
1480 return err;
1481 }
1482
1483 /*
1484 * atl2_remove - Device Removal Routine
1485 * @pdev: PCI device information struct
1486 *
1487 * atl2_remove is called by the PCI subsystem to alert the driver
1488 * that it should release a PCI device. The could be caused by a
1489 * Hot-Plug event, or because the driver is going to be removed from
1490 * memory.
1491 */
1492 /* FIXME: write the original MAC address back in case it was changed from a
1493 * BIOS-set value, as in atl1 -- CHS */
1494 static void __devexit atl2_remove(struct pci_dev *pdev)
1495 {
1496 struct net_device *netdev = pci_get_drvdata(pdev);
1497 struct atl2_adapter *adapter = netdev_priv(netdev);
1498
1499 /* flush_scheduled work may reschedule our watchdog task, so
1500 * explicitly disable watchdog tasks from being rescheduled */
1501 set_bit(__ATL2_DOWN, &adapter->flags);
1502
1503 del_timer_sync(&adapter->watchdog_timer);
1504 del_timer_sync(&adapter->phy_config_timer);
1505 cancel_work_sync(&adapter->reset_task);
1506 cancel_work_sync(&adapter->link_chg_task);
1507
1508 unregister_netdev(netdev);
1509
1510 atl2_force_ps(&adapter->hw);
1511
1512 iounmap(adapter->hw.hw_addr);
1513 pci_release_regions(pdev);
1514
1515 free_netdev(netdev);
1516
1517 pci_disable_device(pdev);
1518 }
1519
1520 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1521 {
1522 struct net_device *netdev = pci_get_drvdata(pdev);
1523 struct atl2_adapter *adapter = netdev_priv(netdev);
1524 struct atl2_hw *hw = &adapter->hw;
1525 u16 speed, duplex;
1526 u32 ctrl = 0;
1527 u32 wufc = adapter->wol;
1528
1529 #ifdef CONFIG_PM
1530 int retval = 0;
1531 #endif
1532
1533 netif_device_detach(netdev);
1534
1535 if (netif_running(netdev)) {
1536 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1537 atl2_down(adapter);
1538 }
1539
1540 #ifdef CONFIG_PM
1541 retval = pci_save_state(pdev);
1542 if (retval)
1543 return retval;
1544 #endif
1545
1546 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1547 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1548 if (ctrl & BMSR_LSTATUS)
1549 wufc &= ~ATLX_WUFC_LNKC;
1550
1551 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1552 u32 ret_val;
1553 /* get current link speed & duplex */
1554 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1555 if (ret_val) {
1556 printk(KERN_DEBUG
1557 "%s: get speed&duplex error while suspend\n",
1558 atl2_driver_name);
1559 goto wol_dis;
1560 }
1561
1562 ctrl = 0;
1563
1564 /* turn on magic packet wol */
1565 if (wufc & ATLX_WUFC_MAG)
1566 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1567
1568 /* ignore Link Chg event when Link is up */
1569 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1570
1571 /* Config MAC CTRL Register */
1572 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1573 if (FULL_DUPLEX == adapter->link_duplex)
1574 ctrl |= MAC_CTRL_DUPLX;
1575 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1576 ctrl |= (((u32)adapter->hw.preamble_len &
1577 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1578 ctrl |= (((u32)(adapter->hw.retry_buf &
1579 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1580 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1581 if (wufc & ATLX_WUFC_MAG) {
1582 /* magic packet maybe Broadcast&multicast&Unicast */
1583 ctrl |= MAC_CTRL_BC_EN;
1584 }
1585
1586 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1587
1588 /* pcie patch */
1589 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1590 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1591 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1592 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1593 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1594 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1595
1596 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1597 goto suspend_exit;
1598 }
1599
1600 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1601 /* link is down, so only LINK CHG WOL event enable */
1602 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1603 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1604 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1605
1606 /* pcie patch */
1607 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1608 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1609 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1611 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1612 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1613
1614 hw->phy_configured = false; /* re-init PHY when resume */
1615
1616 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1617
1618 goto suspend_exit;
1619 }
1620
1621 wol_dis:
1622 /* WOL disabled */
1623 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1624
1625 /* pcie patch */
1626 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1627 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1628 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1629 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1630 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1631 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1632
1633 atl2_force_ps(hw);
1634 hw->phy_configured = false; /* re-init PHY when resume */
1635
1636 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1637
1638 suspend_exit:
1639 if (netif_running(netdev))
1640 atl2_free_irq(adapter);
1641
1642 pci_disable_device(pdev);
1643
1644 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1645
1646 return 0;
1647 }
1648
1649 #ifdef CONFIG_PM
1650 static int atl2_resume(struct pci_dev *pdev)
1651 {
1652 struct net_device *netdev = pci_get_drvdata(pdev);
1653 struct atl2_adapter *adapter = netdev_priv(netdev);
1654 u32 err;
1655
1656 pci_set_power_state(pdev, PCI_D0);
1657 pci_restore_state(pdev);
1658
1659 err = pci_enable_device(pdev);
1660 if (err) {
1661 printk(KERN_ERR
1662 "atl2: Cannot enable PCI device from suspend\n");
1663 return err;
1664 }
1665
1666 pci_set_master(pdev);
1667
1668 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1669
1670 pci_enable_wake(pdev, PCI_D3hot, 0);
1671 pci_enable_wake(pdev, PCI_D3cold, 0);
1672
1673 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1674
1675 if (netif_running(netdev)) {
1676 err = atl2_request_irq(adapter);
1677 if (err)
1678 return err;
1679 }
1680
1681 atl2_reset_hw(&adapter->hw);
1682
1683 if (netif_running(netdev))
1684 atl2_up(adapter);
1685
1686 netif_device_attach(netdev);
1687
1688 return 0;
1689 }
1690 #endif
1691
1692 static void atl2_shutdown(struct pci_dev *pdev)
1693 {
1694 atl2_suspend(pdev, PMSG_SUSPEND);
1695 }
1696
1697 static struct pci_driver atl2_driver = {
1698 .name = atl2_driver_name,
1699 .id_table = atl2_pci_tbl,
1700 .probe = atl2_probe,
1701 .remove = __devexit_p(atl2_remove),
1702 /* Power Management Hooks */
1703 .suspend = atl2_suspend,
1704 #ifdef CONFIG_PM
1705 .resume = atl2_resume,
1706 #endif
1707 .shutdown = atl2_shutdown,
1708 };
1709
1710 /*
1711 * atl2_init_module - Driver Registration Routine
1712 *
1713 * atl2_init_module is the first routine called when the driver is
1714 * loaded. All it does is register with the PCI subsystem.
1715 */
1716 static int __init atl2_init_module(void)
1717 {
1718 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1719 atl2_driver_version);
1720 printk(KERN_INFO "%s\n", atl2_copyright);
1721 return pci_register_driver(&atl2_driver);
1722 }
1723 module_init(atl2_init_module);
1724
1725 /*
1726 * atl2_exit_module - Driver Exit Cleanup Routine
1727 *
1728 * atl2_exit_module is called just before the driver is removed
1729 * from memory.
1730 */
1731 static void __exit atl2_exit_module(void)
1732 {
1733 pci_unregister_driver(&atl2_driver);
1734 }
1735 module_exit(atl2_exit_module);
1736
1737 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1738 {
1739 struct atl2_adapter *adapter = hw->back;
1740 pci_read_config_word(adapter->pdev, reg, value);
1741 }
1742
1743 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1744 {
1745 struct atl2_adapter *adapter = hw->back;
1746 pci_write_config_word(adapter->pdev, reg, *value);
1747 }
1748
1749 static int atl2_get_settings(struct net_device *netdev,
1750 struct ethtool_cmd *ecmd)
1751 {
1752 struct atl2_adapter *adapter = netdev_priv(netdev);
1753 struct atl2_hw *hw = &adapter->hw;
1754
1755 ecmd->supported = (SUPPORTED_10baseT_Half |
1756 SUPPORTED_10baseT_Full |
1757 SUPPORTED_100baseT_Half |
1758 SUPPORTED_100baseT_Full |
1759 SUPPORTED_Autoneg |
1760 SUPPORTED_TP);
1761 ecmd->advertising = ADVERTISED_TP;
1762
1763 ecmd->advertising |= ADVERTISED_Autoneg;
1764 ecmd->advertising |= hw->autoneg_advertised;
1765
1766 ecmd->port = PORT_TP;
1767 ecmd->phy_address = 0;
1768 ecmd->transceiver = XCVR_INTERNAL;
1769
1770 if (adapter->link_speed != SPEED_0) {
1771 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
1772 if (adapter->link_duplex == FULL_DUPLEX)
1773 ecmd->duplex = DUPLEX_FULL;
1774 else
1775 ecmd->duplex = DUPLEX_HALF;
1776 } else {
1777 ethtool_cmd_speed_set(ecmd, -1);
1778 ecmd->duplex = -1;
1779 }
1780
1781 ecmd->autoneg = AUTONEG_ENABLE;
1782 return 0;
1783 }
1784
1785 static int atl2_set_settings(struct net_device *netdev,
1786 struct ethtool_cmd *ecmd)
1787 {
1788 struct atl2_adapter *adapter = netdev_priv(netdev);
1789 struct atl2_hw *hw = &adapter->hw;
1790
1791 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1792 msleep(1);
1793
1794 if (ecmd->autoneg == AUTONEG_ENABLE) {
1795 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1796 ADVERTISE_10_FULL | \
1797 ADVERTISE_100_HALF| \
1798 ADVERTISE_100_FULL)
1799
1800 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1801 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1802 hw->autoneg_advertised = MY_ADV_MASK;
1803 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1804 ADVERTISE_100_FULL) {
1805 hw->MediaType = MEDIA_TYPE_100M_FULL;
1806 hw->autoneg_advertised = ADVERTISE_100_FULL;
1807 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1808 ADVERTISE_100_HALF) {
1809 hw->MediaType = MEDIA_TYPE_100M_HALF;
1810 hw->autoneg_advertised = ADVERTISE_100_HALF;
1811 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1812 ADVERTISE_10_FULL) {
1813 hw->MediaType = MEDIA_TYPE_10M_FULL;
1814 hw->autoneg_advertised = ADVERTISE_10_FULL;
1815 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1816 ADVERTISE_10_HALF) {
1817 hw->MediaType = MEDIA_TYPE_10M_HALF;
1818 hw->autoneg_advertised = ADVERTISE_10_HALF;
1819 } else {
1820 clear_bit(__ATL2_RESETTING, &adapter->flags);
1821 return -EINVAL;
1822 }
1823 ecmd->advertising = hw->autoneg_advertised |
1824 ADVERTISED_TP | ADVERTISED_Autoneg;
1825 } else {
1826 clear_bit(__ATL2_RESETTING, &adapter->flags);
1827 return -EINVAL;
1828 }
1829
1830 /* reset the link */
1831 if (netif_running(adapter->netdev)) {
1832 atl2_down(adapter);
1833 atl2_up(adapter);
1834 } else
1835 atl2_reset_hw(&adapter->hw);
1836
1837 clear_bit(__ATL2_RESETTING, &adapter->flags);
1838 return 0;
1839 }
1840
1841 static u32 atl2_get_msglevel(struct net_device *netdev)
1842 {
1843 return 0;
1844 }
1845
1846 /*
1847 * It's sane for this to be empty, but we might want to take advantage of this.
1848 */
1849 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1850 {
1851 }
1852
1853 static int atl2_get_regs_len(struct net_device *netdev)
1854 {
1855 #define ATL2_REGS_LEN 42
1856 return sizeof(u32) * ATL2_REGS_LEN;
1857 }
1858
1859 static void atl2_get_regs(struct net_device *netdev,
1860 struct ethtool_regs *regs, void *p)
1861 {
1862 struct atl2_adapter *adapter = netdev_priv(netdev);
1863 struct atl2_hw *hw = &adapter->hw;
1864 u32 *regs_buff = p;
1865 u16 phy_data;
1866
1867 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1868
1869 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1870
1871 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1872 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1873 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1874 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1875 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1876 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1877 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1878 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1879 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1880 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1881 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1882 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1883 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1884 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1885 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1886 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1887 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1888 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1889 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1890 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1891 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1892 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1893 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1894 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1895 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1896 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1897 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1898 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1899 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1900 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1901 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1902 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1903 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1904 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1905 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1906 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1907 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1908 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1909 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1910
1911 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1912 regs_buff[40] = (u32)phy_data;
1913 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1914 regs_buff[41] = (u32)phy_data;
1915 }
1916
1917 static int atl2_get_eeprom_len(struct net_device *netdev)
1918 {
1919 struct atl2_adapter *adapter = netdev_priv(netdev);
1920
1921 if (!atl2_check_eeprom_exist(&adapter->hw))
1922 return 512;
1923 else
1924 return 0;
1925 }
1926
1927 static int atl2_get_eeprom(struct net_device *netdev,
1928 struct ethtool_eeprom *eeprom, u8 *bytes)
1929 {
1930 struct atl2_adapter *adapter = netdev_priv(netdev);
1931 struct atl2_hw *hw = &adapter->hw;
1932 u32 *eeprom_buff;
1933 int first_dword, last_dword;
1934 int ret_val = 0;
1935 int i;
1936
1937 if (eeprom->len == 0)
1938 return -EINVAL;
1939
1940 if (atl2_check_eeprom_exist(hw))
1941 return -EINVAL;
1942
1943 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1944
1945 first_dword = eeprom->offset >> 2;
1946 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1947
1948 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1949 GFP_KERNEL);
1950 if (!eeprom_buff)
1951 return -ENOMEM;
1952
1953 for (i = first_dword; i < last_dword; i++) {
1954 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1955 ret_val = -EIO;
1956 goto free;
1957 }
1958 }
1959
1960 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1961 eeprom->len);
1962 free:
1963 kfree(eeprom_buff);
1964
1965 return ret_val;
1966 }
1967
1968 static int atl2_set_eeprom(struct net_device *netdev,
1969 struct ethtool_eeprom *eeprom, u8 *bytes)
1970 {
1971 struct atl2_adapter *adapter = netdev_priv(netdev);
1972 struct atl2_hw *hw = &adapter->hw;
1973 u32 *eeprom_buff;
1974 u32 *ptr;
1975 int max_len, first_dword, last_dword, ret_val = 0;
1976 int i;
1977
1978 if (eeprom->len == 0)
1979 return -EOPNOTSUPP;
1980
1981 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1982 return -EFAULT;
1983
1984 max_len = 512;
1985
1986 first_dword = eeprom->offset >> 2;
1987 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1988 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1989 if (!eeprom_buff)
1990 return -ENOMEM;
1991
1992 ptr = eeprom_buff;
1993
1994 if (eeprom->offset & 3) {
1995 /* need read/modify/write of first changed EEPROM word */
1996 /* only the second byte of the word is being modified */
1997 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
1998 ret_val = -EIO;
1999 goto out;
2000 }
2001 ptr++;
2002 }
2003 if (((eeprom->offset + eeprom->len) & 3)) {
2004 /*
2005 * need read/modify/write of last changed EEPROM word
2006 * only the first byte of the word is being modified
2007 */
2008 if (!atl2_read_eeprom(hw, last_dword * 4,
2009 &(eeprom_buff[last_dword - first_dword]))) {
2010 ret_val = -EIO;
2011 goto out;
2012 }
2013 }
2014
2015 /* Device's eeprom is always little-endian, word addressable */
2016 memcpy(ptr, bytes, eeprom->len);
2017
2018 for (i = 0; i < last_dword - first_dword + 1; i++) {
2019 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2020 ret_val = -EIO;
2021 goto out;
2022 }
2023 }
2024 out:
2025 kfree(eeprom_buff);
2026 return ret_val;
2027 }
2028
2029 static void atl2_get_drvinfo(struct net_device *netdev,
2030 struct ethtool_drvinfo *drvinfo)
2031 {
2032 struct atl2_adapter *adapter = netdev_priv(netdev);
2033
2034 strncpy(drvinfo->driver, atl2_driver_name, 32);
2035 strncpy(drvinfo->version, atl2_driver_version, 32);
2036 strncpy(drvinfo->fw_version, "L2", 32);
2037 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2038 drvinfo->n_stats = 0;
2039 drvinfo->testinfo_len = 0;
2040 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2041 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2042 }
2043
2044 static void atl2_get_wol(struct net_device *netdev,
2045 struct ethtool_wolinfo *wol)
2046 {
2047 struct atl2_adapter *adapter = netdev_priv(netdev);
2048
2049 wol->supported = WAKE_MAGIC;
2050 wol->wolopts = 0;
2051
2052 if (adapter->wol & ATLX_WUFC_EX)
2053 wol->wolopts |= WAKE_UCAST;
2054 if (adapter->wol & ATLX_WUFC_MC)
2055 wol->wolopts |= WAKE_MCAST;
2056 if (adapter->wol & ATLX_WUFC_BC)
2057 wol->wolopts |= WAKE_BCAST;
2058 if (adapter->wol & ATLX_WUFC_MAG)
2059 wol->wolopts |= WAKE_MAGIC;
2060 if (adapter->wol & ATLX_WUFC_LNKC)
2061 wol->wolopts |= WAKE_PHY;
2062 }
2063
2064 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2065 {
2066 struct atl2_adapter *adapter = netdev_priv(netdev);
2067
2068 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2069 return -EOPNOTSUPP;
2070
2071 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
2072 return -EOPNOTSUPP;
2073
2074 /* these settings will always override what we currently have */
2075 adapter->wol = 0;
2076
2077 if (wol->wolopts & WAKE_MAGIC)
2078 adapter->wol |= ATLX_WUFC_MAG;
2079 if (wol->wolopts & WAKE_PHY)
2080 adapter->wol |= ATLX_WUFC_LNKC;
2081
2082 return 0;
2083 }
2084
2085 static int atl2_nway_reset(struct net_device *netdev)
2086 {
2087 struct atl2_adapter *adapter = netdev_priv(netdev);
2088 if (netif_running(netdev))
2089 atl2_reinit_locked(adapter);
2090 return 0;
2091 }
2092
2093 static const struct ethtool_ops atl2_ethtool_ops = {
2094 .get_settings = atl2_get_settings,
2095 .set_settings = atl2_set_settings,
2096 .get_drvinfo = atl2_get_drvinfo,
2097 .get_regs_len = atl2_get_regs_len,
2098 .get_regs = atl2_get_regs,
2099 .get_wol = atl2_get_wol,
2100 .set_wol = atl2_set_wol,
2101 .get_msglevel = atl2_get_msglevel,
2102 .set_msglevel = atl2_set_msglevel,
2103 .nway_reset = atl2_nway_reset,
2104 .get_link = ethtool_op_get_link,
2105 .get_eeprom_len = atl2_get_eeprom_len,
2106 .get_eeprom = atl2_get_eeprom,
2107 .set_eeprom = atl2_set_eeprom,
2108 };
2109
2110 static void atl2_set_ethtool_ops(struct net_device *netdev)
2111 {
2112 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2113 }
2114
2115 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2116 (((a) & 0xff00ff00) >> 8))
2117 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2118 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2119
2120 /*
2121 * Reset the transmit and receive units; mask and clear all interrupts.
2122 *
2123 * hw - Struct containing variables accessed by shared code
2124 * return : 0 or idle status (if error)
2125 */
2126 static s32 atl2_reset_hw(struct atl2_hw *hw)
2127 {
2128 u32 icr;
2129 u16 pci_cfg_cmd_word;
2130 int i;
2131
2132 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2133 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2134 if ((pci_cfg_cmd_word &
2135 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2136 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2137 pci_cfg_cmd_word |=
2138 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2139 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2140 }
2141
2142 /* Clear Interrupt mask to stop board from generating
2143 * interrupts & Clear any pending interrupt events
2144 */
2145 /* FIXME */
2146 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2147 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2148
2149 /* Issue Soft Reset to the MAC. This will reset the chip's
2150 * transmit, receive, DMA. It will not effect
2151 * the current PCI configuration. The global reset bit is self-
2152 * clearing, and should clear within a microsecond.
2153 */
2154 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2155 wmb();
2156 msleep(1); /* delay about 1ms */
2157
2158 /* Wait at least 10ms for All module to be Idle */
2159 for (i = 0; i < 10; i++) {
2160 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2161 if (!icr)
2162 break;
2163 msleep(1); /* delay 1 ms */
2164 cpu_relax();
2165 }
2166
2167 if (icr)
2168 return icr;
2169
2170 return 0;
2171 }
2172
2173 #define CUSTOM_SPI_CS_SETUP 2
2174 #define CUSTOM_SPI_CLK_HI 2
2175 #define CUSTOM_SPI_CLK_LO 2
2176 #define CUSTOM_SPI_CS_HOLD 2
2177 #define CUSTOM_SPI_CS_HI 3
2178
2179 static struct atl2_spi_flash_dev flash_table[] =
2180 {
2181 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2182 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2183 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2184 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2185 };
2186
2187 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2188 {
2189 int i;
2190 u32 value;
2191
2192 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2193 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2194
2195 value = SPI_FLASH_CTRL_WAIT_READY |
2196 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2197 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2198 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2199 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2200 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2201 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2202 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2203 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2204 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2205 SPI_FLASH_CTRL_CS_HI_SHIFT |
2206 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2207
2208 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2209
2210 value |= SPI_FLASH_CTRL_START;
2211
2212 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2213
2214 for (i = 0; i < 10; i++) {
2215 msleep(1);
2216 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2217 if (!(value & SPI_FLASH_CTRL_START))
2218 break;
2219 }
2220
2221 if (value & SPI_FLASH_CTRL_START)
2222 return false;
2223
2224 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2225
2226 return true;
2227 }
2228
2229 /*
2230 * get_permanent_address
2231 * return 0 if get valid mac address,
2232 */
2233 static int get_permanent_address(struct atl2_hw *hw)
2234 {
2235 u32 Addr[2];
2236 u32 i, Control;
2237 u16 Register;
2238 u8 EthAddr[NODE_ADDRESS_SIZE];
2239 bool KeyValid;
2240
2241 if (is_valid_ether_addr(hw->perm_mac_addr))
2242 return 0;
2243
2244 Addr[0] = 0;
2245 Addr[1] = 0;
2246
2247 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2248 Register = 0;
2249 KeyValid = false;
2250
2251 /* Read out all EEPROM content */
2252 i = 0;
2253 while (1) {
2254 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2255 if (KeyValid) {
2256 if (Register == REG_MAC_STA_ADDR)
2257 Addr[0] = Control;
2258 else if (Register ==
2259 (REG_MAC_STA_ADDR + 4))
2260 Addr[1] = Control;
2261 KeyValid = false;
2262 } else if ((Control & 0xff) == 0x5A) {
2263 KeyValid = true;
2264 Register = (u16) (Control >> 16);
2265 } else {
2266 /* assume data end while encount an invalid KEYWORD */
2267 break;
2268 }
2269 } else {
2270 break; /* read error */
2271 }
2272 i += 4;
2273 }
2274
2275 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2276 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2277
2278 if (is_valid_ether_addr(EthAddr)) {
2279 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2280 return 0;
2281 }
2282 return 1;
2283 }
2284
2285 /* see if SPI flash exists? */
2286 Addr[0] = 0;
2287 Addr[1] = 0;
2288 Register = 0;
2289 KeyValid = false;
2290 i = 0;
2291 while (1) {
2292 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2293 if (KeyValid) {
2294 if (Register == REG_MAC_STA_ADDR)
2295 Addr[0] = Control;
2296 else if (Register == (REG_MAC_STA_ADDR + 4))
2297 Addr[1] = Control;
2298 KeyValid = false;
2299 } else if ((Control & 0xff) == 0x5A) {
2300 KeyValid = true;
2301 Register = (u16) (Control >> 16);
2302 } else {
2303 break; /* data end */
2304 }
2305 } else {
2306 break; /* read error */
2307 }
2308 i += 4;
2309 }
2310
2311 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2312 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2313 if (is_valid_ether_addr(EthAddr)) {
2314 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2315 return 0;
2316 }
2317 /* maybe MAC-address is from BIOS */
2318 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2319 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2320 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2321 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2322
2323 if (is_valid_ether_addr(EthAddr)) {
2324 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2325 return 0;
2326 }
2327
2328 return 1;
2329 }
2330
2331 /*
2332 * Reads the adapter's MAC address from the EEPROM
2333 *
2334 * hw - Struct containing variables accessed by shared code
2335 */
2336 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2337 {
2338 u16 i;
2339
2340 if (get_permanent_address(hw)) {
2341 /* for test */
2342 /* FIXME: shouldn't we use random_ether_addr() here? */
2343 hw->perm_mac_addr[0] = 0x00;
2344 hw->perm_mac_addr[1] = 0x13;
2345 hw->perm_mac_addr[2] = 0x74;
2346 hw->perm_mac_addr[3] = 0x00;
2347 hw->perm_mac_addr[4] = 0x5c;
2348 hw->perm_mac_addr[5] = 0x38;
2349 }
2350
2351 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2352 hw->mac_addr[i] = hw->perm_mac_addr[i];
2353
2354 return 0;
2355 }
2356
2357 /*
2358 * Hashes an address to determine its location in the multicast table
2359 *
2360 * hw - Struct containing variables accessed by shared code
2361 * mc_addr - the multicast address to hash
2362 *
2363 * atl2_hash_mc_addr
2364 * purpose
2365 * set hash value for a multicast address
2366 * hash calcu processing :
2367 * 1. calcu 32bit CRC for multicast address
2368 * 2. reverse crc with MSB to LSB
2369 */
2370 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2371 {
2372 u32 crc32, value;
2373 int i;
2374
2375 value = 0;
2376 crc32 = ether_crc_le(6, mc_addr);
2377
2378 for (i = 0; i < 32; i++)
2379 value |= (((crc32 >> i) & 1) << (31 - i));
2380
2381 return value;
2382 }
2383
2384 /*
2385 * Sets the bit in the multicast table corresponding to the hash value.
2386 *
2387 * hw - Struct containing variables accessed by shared code
2388 * hash_value - Multicast address hash value
2389 */
2390 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2391 {
2392 u32 hash_bit, hash_reg;
2393 u32 mta;
2394
2395 /* The HASH Table is a register array of 2 32-bit registers.
2396 * It is treated like an array of 64 bits. We want to set
2397 * bit BitArray[hash_value]. So we figure out what register
2398 * the bit is in, read it, OR in the new bit, then write
2399 * back the new value. The register is determined by the
2400 * upper 7 bits of the hash value and the bit within that
2401 * register are determined by the lower 5 bits of the value.
2402 */
2403 hash_reg = (hash_value >> 31) & 0x1;
2404 hash_bit = (hash_value >> 26) & 0x1F;
2405
2406 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2407
2408 mta |= (1 << hash_bit);
2409
2410 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2411 }
2412
2413 /*
2414 * atl2_init_pcie - init PCIE module
2415 */
2416 static void atl2_init_pcie(struct atl2_hw *hw)
2417 {
2418 u32 value;
2419 value = LTSSM_TEST_MODE_DEF;
2420 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2421
2422 value = PCIE_DLL_TX_CTRL1_DEF;
2423 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2424 }
2425
2426 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2427 {
2428 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2429 hw->flash_vendor = 0; /* ATMEL */
2430
2431 /* Init OP table */
2432 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2433 flash_table[hw->flash_vendor].cmdPROGRAM);
2434 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2435 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2436 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2437 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2438 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2439 flash_table[hw->flash_vendor].cmdRDID);
2440 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2441 flash_table[hw->flash_vendor].cmdWREN);
2442 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2443 flash_table[hw->flash_vendor].cmdRDSR);
2444 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2445 flash_table[hw->flash_vendor].cmdWRSR);
2446 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2447 flash_table[hw->flash_vendor].cmdREAD);
2448 }
2449
2450 /********************************************************************
2451 * Performs basic configuration of the adapter.
2452 *
2453 * hw - Struct containing variables accessed by shared code
2454 * Assumes that the controller has previously been reset and is in a
2455 * post-reset uninitialized state. Initializes multicast table,
2456 * and Calls routines to setup link
2457 * Leaves the transmit and receive units disabled and uninitialized.
2458 ********************************************************************/
2459 static s32 atl2_init_hw(struct atl2_hw *hw)
2460 {
2461 u32 ret_val = 0;
2462
2463 atl2_init_pcie(hw);
2464
2465 /* Zero out the Multicast HASH table */
2466 /* clear the old settings from the multicast hash table */
2467 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2468 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2469
2470 atl2_init_flash_opcode(hw);
2471
2472 ret_val = atl2_phy_init(hw);
2473
2474 return ret_val;
2475 }
2476
2477 /*
2478 * Detects the current speed and duplex settings of the hardware.
2479 *
2480 * hw - Struct containing variables accessed by shared code
2481 * speed - Speed of the connection
2482 * duplex - Duplex setting of the connection
2483 */
2484 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2485 u16 *duplex)
2486 {
2487 s32 ret_val;
2488 u16 phy_data;
2489
2490 /* Read PHY Specific Status Register (17) */
2491 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2492 if (ret_val)
2493 return ret_val;
2494
2495 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2496 return ATLX_ERR_PHY_RES;
2497
2498 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2499 case MII_ATLX_PSSR_100MBS:
2500 *speed = SPEED_100;
2501 break;
2502 case MII_ATLX_PSSR_10MBS:
2503 *speed = SPEED_10;
2504 break;
2505 default:
2506 return ATLX_ERR_PHY_SPEED;
2507 break;
2508 }
2509
2510 if (phy_data & MII_ATLX_PSSR_DPLX)
2511 *duplex = FULL_DUPLEX;
2512 else
2513 *duplex = HALF_DUPLEX;
2514
2515 return 0;
2516 }
2517
2518 /*
2519 * Reads the value from a PHY register
2520 * hw - Struct containing variables accessed by shared code
2521 * reg_addr - address of the PHY register to read
2522 */
2523 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2524 {
2525 u32 val;
2526 int i;
2527
2528 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2529 MDIO_START |
2530 MDIO_SUP_PREAMBLE |
2531 MDIO_RW |
2532 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2533 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2534
2535 wmb();
2536
2537 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2538 udelay(2);
2539 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2540 if (!(val & (MDIO_START | MDIO_BUSY)))
2541 break;
2542 wmb();
2543 }
2544 if (!(val & (MDIO_START | MDIO_BUSY))) {
2545 *phy_data = (u16)val;
2546 return 0;
2547 }
2548
2549 return ATLX_ERR_PHY;
2550 }
2551
2552 /*
2553 * Writes a value to a PHY register
2554 * hw - Struct containing variables accessed by shared code
2555 * reg_addr - address of the PHY register to write
2556 * data - data to write to the PHY
2557 */
2558 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2559 {
2560 int i;
2561 u32 val;
2562
2563 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2564 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2565 MDIO_SUP_PREAMBLE |
2566 MDIO_START |
2567 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2568 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2569
2570 wmb();
2571
2572 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2573 udelay(2);
2574 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2575 if (!(val & (MDIO_START | MDIO_BUSY)))
2576 break;
2577
2578 wmb();
2579 }
2580
2581 if (!(val & (MDIO_START | MDIO_BUSY)))
2582 return 0;
2583
2584 return ATLX_ERR_PHY;
2585 }
2586
2587 /*
2588 * Configures PHY autoneg and flow control advertisement settings
2589 *
2590 * hw - Struct containing variables accessed by shared code
2591 */
2592 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2593 {
2594 s32 ret_val;
2595 s16 mii_autoneg_adv_reg;
2596
2597 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2598 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2599
2600 /* Need to parse autoneg_advertised and set up
2601 * the appropriate PHY registers. First we will parse for
2602 * autoneg_advertised software override. Since we can advertise
2603 * a plethora of combinations, we need to check each bit
2604 * individually.
2605 */
2606
2607 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2608 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2609 * the 1000Base-T Control Register (Address 9). */
2610 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2611
2612 /* Need to parse MediaType and setup the
2613 * appropriate PHY registers. */
2614 switch (hw->MediaType) {
2615 case MEDIA_TYPE_AUTO_SENSOR:
2616 mii_autoneg_adv_reg |=
2617 (MII_AR_10T_HD_CAPS |
2618 MII_AR_10T_FD_CAPS |
2619 MII_AR_100TX_HD_CAPS|
2620 MII_AR_100TX_FD_CAPS);
2621 hw->autoneg_advertised =
2622 ADVERTISE_10_HALF |
2623 ADVERTISE_10_FULL |
2624 ADVERTISE_100_HALF|
2625 ADVERTISE_100_FULL;
2626 break;
2627 case MEDIA_TYPE_100M_FULL:
2628 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2629 hw->autoneg_advertised = ADVERTISE_100_FULL;
2630 break;
2631 case MEDIA_TYPE_100M_HALF:
2632 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2633 hw->autoneg_advertised = ADVERTISE_100_HALF;
2634 break;
2635 case MEDIA_TYPE_10M_FULL:
2636 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2637 hw->autoneg_advertised = ADVERTISE_10_FULL;
2638 break;
2639 default:
2640 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2641 hw->autoneg_advertised = ADVERTISE_10_HALF;
2642 break;
2643 }
2644
2645 /* flow control fixed to enable all */
2646 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2647
2648 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2649
2650 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2651
2652 if (ret_val)
2653 return ret_val;
2654
2655 return 0;
2656 }
2657
2658 /*
2659 * Resets the PHY and make all config validate
2660 *
2661 * hw - Struct containing variables accessed by shared code
2662 *
2663 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2664 */
2665 static s32 atl2_phy_commit(struct atl2_hw *hw)
2666 {
2667 s32 ret_val;
2668 u16 phy_data;
2669
2670 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2671 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2672 if (ret_val) {
2673 u32 val;
2674 int i;
2675 /* pcie serdes link may be down ! */
2676 for (i = 0; i < 25; i++) {
2677 msleep(1);
2678 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2679 if (!(val & (MDIO_START | MDIO_BUSY)))
2680 break;
2681 }
2682
2683 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2684 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2685 return ret_val;
2686 }
2687 }
2688 return 0;
2689 }
2690
2691 static s32 atl2_phy_init(struct atl2_hw *hw)
2692 {
2693 s32 ret_val;
2694 u16 phy_val;
2695
2696 if (hw->phy_configured)
2697 return 0;
2698
2699 /* Enable PHY */
2700 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2701 ATL2_WRITE_FLUSH(hw);
2702 msleep(1);
2703
2704 /* check if the PHY is in powersaving mode */
2705 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2706 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2707
2708 /* 024E / 124E 0r 0274 / 1274 ? */
2709 if (phy_val & 0x1000) {
2710 phy_val &= ~0x1000;
2711 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2712 }
2713
2714 msleep(1);
2715
2716 /*Enable PHY LinkChange Interrupt */
2717 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2718 if (ret_val)
2719 return ret_val;
2720
2721 /* setup AutoNeg parameters */
2722 ret_val = atl2_phy_setup_autoneg_adv(hw);
2723 if (ret_val)
2724 return ret_val;
2725
2726 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2727 ret_val = atl2_phy_commit(hw);
2728 if (ret_val)
2729 return ret_val;
2730
2731 hw->phy_configured = true;
2732
2733 return ret_val;
2734 }
2735
2736 static void atl2_set_mac_addr(struct atl2_hw *hw)
2737 {
2738 u32 value;
2739 /* 00-0B-6A-F6-00-DC
2740 * 0: 6AF600DC 1: 000B
2741 * low dword */
2742 value = (((u32)hw->mac_addr[2]) << 24) |
2743 (((u32)hw->mac_addr[3]) << 16) |
2744 (((u32)hw->mac_addr[4]) << 8) |
2745 (((u32)hw->mac_addr[5]));
2746 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2747 /* hight dword */
2748 value = (((u32)hw->mac_addr[0]) << 8) |
2749 (((u32)hw->mac_addr[1]));
2750 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2751 }
2752
2753 /*
2754 * check_eeprom_exist
2755 * return 0 if eeprom exist
2756 */
2757 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2758 {
2759 u32 value;
2760
2761 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2762 if (value & SPI_FLASH_CTRL_EN_VPD) {
2763 value &= ~SPI_FLASH_CTRL_EN_VPD;
2764 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2765 }
2766 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2767 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2768 }
2769
2770 /* FIXME: This doesn't look right. -- CHS */
2771 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2772 {
2773 return true;
2774 }
2775
2776 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2777 {
2778 int i;
2779 u32 Control;
2780
2781 if (Offset & 0x3)
2782 return false; /* address do not align */
2783
2784 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2785 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2786 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2787
2788 for (i = 0; i < 10; i++) {
2789 msleep(2);
2790 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2791 if (Control & VPD_CAP_VPD_FLAG)
2792 break;
2793 }
2794
2795 if (Control & VPD_CAP_VPD_FLAG) {
2796 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2797 return true;
2798 }
2799 return false; /* timeout */
2800 }
2801
2802 static void atl2_force_ps(struct atl2_hw *hw)
2803 {
2804 u16 phy_val;
2805
2806 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2807 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2808 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2809
2810 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2811 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2812 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2813 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2814 }
2815
2816 /* This is the only thing that needs to be changed to adjust the
2817 * maximum number of ports that the driver can manage.
2818 */
2819 #define ATL2_MAX_NIC 4
2820
2821 #define OPTION_UNSET -1
2822 #define OPTION_DISABLED 0
2823 #define OPTION_ENABLED 1
2824
2825 /* All parameters are treated the same, as an integer array of values.
2826 * This macro just reduces the need to repeat the same declaration code
2827 * over and over (plus this helps to avoid typo bugs).
2828 */
2829 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2830 #ifndef module_param_array
2831 /* Module Parameters are always initialized to -1, so that the driver
2832 * can tell the difference between no user specified value or the
2833 * user asking for the default value.
2834 * The true default values are loaded in when atl2_check_options is called.
2835 *
2836 * This is a GCC extension to ANSI C.
2837 * See the item "Labeled Elements in Initializers" in the section
2838 * "Extensions to the C Language Family" of the GCC documentation.
2839 */
2840
2841 #define ATL2_PARAM(X, desc) \
2842 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2843 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2844 MODULE_PARM_DESC(X, desc);
2845 #else
2846 #define ATL2_PARAM(X, desc) \
2847 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2848 static unsigned int num_##X; \
2849 module_param_array_named(X, X, int, &num_##X, 0); \
2850 MODULE_PARM_DESC(X, desc);
2851 #endif
2852
2853 /*
2854 * Transmit Memory Size
2855 * Valid Range: 64-2048
2856 * Default Value: 128
2857 */
2858 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2859 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2860 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2861 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2862
2863 /*
2864 * Receive Memory Block Count
2865 * Valid Range: 16-512
2866 * Default Value: 128
2867 */
2868 #define ATL2_MIN_RXD_COUNT 16
2869 #define ATL2_MAX_RXD_COUNT 512
2870 #define ATL2_DEFAULT_RXD_COUNT 64
2871 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2872
2873 /*
2874 * User Specified MediaType Override
2875 *
2876 * Valid Range: 0-5
2877 * - 0 - auto-negotiate at all supported speeds
2878 * - 1 - only link at 1000Mbps Full Duplex
2879 * - 2 - only link at 100Mbps Full Duplex
2880 * - 3 - only link at 100Mbps Half Duplex
2881 * - 4 - only link at 10Mbps Full Duplex
2882 * - 5 - only link at 10Mbps Half Duplex
2883 * Default Value: 0
2884 */
2885 ATL2_PARAM(MediaType, "MediaType Select");
2886
2887 /*
2888 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2889 * Valid Range: 10-65535
2890 * Default Value: 45000(90ms)
2891 */
2892 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2893 #define INT_MOD_MAX_CNT 65000
2894 #define INT_MOD_MIN_CNT 50
2895 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2896
2897 /*
2898 * FlashVendor
2899 * Valid Range: 0-2
2900 * 0 - Atmel
2901 * 1 - SST
2902 * 2 - ST
2903 */
2904 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2905
2906 #define AUTONEG_ADV_DEFAULT 0x2F
2907 #define AUTONEG_ADV_MASK 0x2F
2908 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2909
2910 #define FLASH_VENDOR_DEFAULT 0
2911 #define FLASH_VENDOR_MIN 0
2912 #define FLASH_VENDOR_MAX 2
2913
2914 struct atl2_option {
2915 enum { enable_option, range_option, list_option } type;
2916 char *name;
2917 char *err;
2918 int def;
2919 union {
2920 struct { /* range_option info */
2921 int min;
2922 int max;
2923 } r;
2924 struct { /* list_option info */
2925 int nr;
2926 struct atl2_opt_list { int i; char *str; } *p;
2927 } l;
2928 } arg;
2929 };
2930
2931 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2932 {
2933 int i;
2934 struct atl2_opt_list *ent;
2935
2936 if (*value == OPTION_UNSET) {
2937 *value = opt->def;
2938 return 0;
2939 }
2940
2941 switch (opt->type) {
2942 case enable_option:
2943 switch (*value) {
2944 case OPTION_ENABLED:
2945 printk(KERN_INFO "%s Enabled\n", opt->name);
2946 return 0;
2947 break;
2948 case OPTION_DISABLED:
2949 printk(KERN_INFO "%s Disabled\n", opt->name);
2950 return 0;
2951 break;
2952 }
2953 break;
2954 case range_option:
2955 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2956 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2957 return 0;
2958 }
2959 break;
2960 case list_option:
2961 for (i = 0; i < opt->arg.l.nr; i++) {
2962 ent = &opt->arg.l.p[i];
2963 if (*value == ent->i) {
2964 if (ent->str[0] != '\0')
2965 printk(KERN_INFO "%s\n", ent->str);
2966 return 0;
2967 }
2968 }
2969 break;
2970 default:
2971 BUG();
2972 }
2973
2974 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2975 opt->name, *value, opt->err);
2976 *value = opt->def;
2977 return -1;
2978 }
2979
2980 /*
2981 * atl2_check_options - Range Checking for Command Line Parameters
2982 * @adapter: board private structure
2983 *
2984 * This routine checks all command line parameters for valid user
2985 * input. If an invalid value is given, or if no user specified
2986 * value exists, a default value is used. The final value is stored
2987 * in a variable in the adapter structure.
2988 */
2989 static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2990 {
2991 int val;
2992 struct atl2_option opt;
2993 int bd = adapter->bd_number;
2994 if (bd >= ATL2_MAX_NIC) {
2995 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
2996 bd);
2997 printk(KERN_NOTICE "Using defaults for all values\n");
2998 #ifndef module_param_array
2999 bd = ATL2_MAX_NIC;
3000 #endif
3001 }
3002
3003 /* Bytes of Transmit Memory */
3004 opt.type = range_option;
3005 opt.name = "Bytes of Transmit Memory";
3006 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3007 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3008 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3009 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3010 #ifdef module_param_array
3011 if (num_TxMemSize > bd) {
3012 #endif
3013 val = TxMemSize[bd];
3014 atl2_validate_option(&val, &opt);
3015 adapter->txd_ring_size = ((u32) val) * 1024;
3016 #ifdef module_param_array
3017 } else
3018 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3019 #endif
3020 /* txs ring size: */
3021 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3022 if (adapter->txs_ring_size > 160)
3023 adapter->txs_ring_size = 160;
3024
3025 /* Receive Memory Block Count */
3026 opt.type = range_option;
3027 opt.name = "Number of receive memory block";
3028 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3029 opt.def = ATL2_DEFAULT_RXD_COUNT;
3030 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3031 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3032 #ifdef module_param_array
3033 if (num_RxMemBlock > bd) {
3034 #endif
3035 val = RxMemBlock[bd];
3036 atl2_validate_option(&val, &opt);
3037 adapter->rxd_ring_size = (u32)val;
3038 /* FIXME */
3039 /* ((u16)val)&~1; */ /* even number */
3040 #ifdef module_param_array
3041 } else
3042 adapter->rxd_ring_size = (u32)opt.def;
3043 #endif
3044 /* init RXD Flow control value */
3045 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3046 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3047 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3048 (adapter->rxd_ring_size / 12);
3049
3050 /* Interrupt Moderate Timer */
3051 opt.type = range_option;
3052 opt.name = "Interrupt Moderate Timer";
3053 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3054 opt.def = INT_MOD_DEFAULT_CNT;
3055 opt.arg.r.min = INT_MOD_MIN_CNT;
3056 opt.arg.r.max = INT_MOD_MAX_CNT;
3057 #ifdef module_param_array
3058 if (num_IntModTimer > bd) {
3059 #endif
3060 val = IntModTimer[bd];
3061 atl2_validate_option(&val, &opt);
3062 adapter->imt = (u16) val;
3063 #ifdef module_param_array
3064 } else
3065 adapter->imt = (u16)(opt.def);
3066 #endif
3067 /* Flash Vendor */
3068 opt.type = range_option;
3069 opt.name = "SPI Flash Vendor";
3070 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3071 opt.def = FLASH_VENDOR_DEFAULT;
3072 opt.arg.r.min = FLASH_VENDOR_MIN;
3073 opt.arg.r.max = FLASH_VENDOR_MAX;
3074 #ifdef module_param_array
3075 if (num_FlashVendor > bd) {
3076 #endif
3077 val = FlashVendor[bd];
3078 atl2_validate_option(&val, &opt);
3079 adapter->hw.flash_vendor = (u8) val;
3080 #ifdef module_param_array
3081 } else
3082 adapter->hw.flash_vendor = (u8)(opt.def);
3083 #endif
3084 /* MediaType */
3085 opt.type = range_option;
3086 opt.name = "Speed/Duplex Selection";
3087 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3088 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3089 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3090 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3091 #ifdef module_param_array
3092 if (num_MediaType > bd) {
3093 #endif
3094 val = MediaType[bd];
3095 atl2_validate_option(&val, &opt);
3096 adapter->hw.MediaType = (u16) val;
3097 #ifdef module_param_array
3098 } else
3099 adapter->hw.MediaType = (u16)(opt.def);
3100 #endif
3101 }
Linux kernel - Deliverables
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