drivers/net/benet/be.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #ifndef BE_H
  19 #define BE_H
  20
  21 #include <linux/pci.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/version.h>
  24 #include <linux/delay.h>
  25 #include <net/tcp.h>
  26 #include <net/ip.h>
  27 #include <net/ipv6.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/firmware.h>
  32 #include <linux/slab.h>
  33
  34 #include "be_hw.h"
  35
  36 #define DRV_VER                 "2.102.147u"
  37 #define DRV_NAME                "be2net"
  38 #define BE_NAME                 "ServerEngines BladeEngine2 10Gbps NIC"
  39 #define BE3_NAME                "ServerEngines BladeEngine3 10Gbps NIC"
  40 #define OC_NAME                 "Emulex OneConnect 10Gbps NIC"
  41 #define OC_NAME1                "Emulex OneConnect 10Gbps NIC (be3)"
  42 #define DRV_DESC                "ServerEngines BladeEngine 10Gbps NIC Driver"
  43
  44 #define BE_VENDOR_ID            0x19a2
  45 #define BE_DEVICE_ID1           0x211
  46 #define BE_DEVICE_ID2           0x221
  47 #define OC_DEVICE_ID1           0x700
  48 #define OC_DEVICE_ID2           0x710
  49
  50 static inline char *nic_name(struct pci_dev *pdev)
  51 {
  52         switch (pdev->device) {
  53         case OC_DEVICE_ID1:
  54                 return OC_NAME;
  55         case OC_DEVICE_ID2:
  56                 return OC_NAME1;
  57         case BE_DEVICE_ID2:
  58                 return BE3_NAME;
  59         default:
  60                 return BE_NAME;
  61         }
  62 }
  63
  64 /* Number of bytes of an RX frame that are copied to skb->data */
  65 #define BE_HDR_LEN              64
  66 #define BE_MAX_JUMBO_FRAME_SIZE 9018
  67 #define BE_MIN_MTU              256
  68
  69 #define BE_NUM_VLANS_SUPPORTED  64
  70 #define BE_MAX_EQD              96
  71 #define BE_MAX_TX_FRAG_COUNT    30
  72
  73 #define EVNT_Q_LEN              1024
  74 #define TX_Q_LEN                2048
  75 #define TX_CQ_LEN               1024
  76 #define RX_Q_LEN                1024    /* Does not support any other value */
  77 #define RX_CQ_LEN               1024
  78 #define MCC_Q_LEN               128     /* total size not to exceed 8 pages */
  79 #define MCC_CQ_LEN              256
  80
  81 #define BE_NAPI_WEIGHT          64
  82 #define MAX_RX_POST             BE_NAPI_WEIGHT /* Frags posted at a time */
  83 #define RX_FRAGS_REFILL_WM      (RX_Q_LEN - MAX_RX_POST)
  84
  85 #define FW_VER_LEN              32
  86
  87 struct be_dma_mem {
  88         void *va;
  89         dma_addr_t dma;
  90         u32 size;
  91 };
  92
  93 struct be_queue_info {
  94         struct be_dma_mem dma_mem;
  95         u16 len;
  96         u16 entry_size; /* Size of an element in the queue */
  97         u16 id;
  98         u16 tail, head;
  99         bool created;
 100         atomic_t used;  /* Number of valid elements in the queue */
 101 };
 102
 103 static inline u32 MODULO(u16 val, u16 limit)
 104 {
 105         BUG_ON(limit & (limit - 1));
 106         return val & (limit - 1);
 107 }
 108
 109 static inline void index_adv(u16 *index, u16 val, u16 limit)
 110 {
 111         *index = MODULO((*index + val), limit);
 112 }
 113
 114 static inline void index_inc(u16 *index, u16 limit)
 115 {
 116         *index = MODULO((*index + 1), limit);
 117 }
 118
 119 static inline void *queue_head_node(struct be_queue_info *q)
 120 {
 121         return q->dma_mem.va + q->head * q->entry_size;
 122 }
 123
 124 static inline void *queue_tail_node(struct be_queue_info *q)
 125 {
 126         return q->dma_mem.va + q->tail * q->entry_size;
 127 }
 128
 129 static inline void queue_head_inc(struct be_queue_info *q)
 130 {
 131         index_inc(&q->head, q->len);
 132 }
 133
 134 static inline void queue_tail_inc(struct be_queue_info *q)
 135 {
 136         index_inc(&q->tail, q->len);
 137 }
 138
 139 struct be_eq_obj {
 140         struct be_queue_info q;
 141         char desc[32];
 142
 143         /* Adaptive interrupt coalescing (AIC) info */
 144         bool enable_aic;
 145         u16 min_eqd;            /* in usecs */
 146         u16 max_eqd;            /* in usecs */
 147         u16 cur_eqd;            /* in usecs */
 148
 149         struct napi_struct napi;
 150 };
 151
 152 struct be_mcc_obj {
 153         struct be_queue_info q;
 154         struct be_queue_info cq;
 155         bool rearm_cq;
 156 };
 157
 158 struct be_drvr_stats {
 159         u32 be_tx_reqs;         /* number of TX requests initiated */
 160         u32 be_tx_stops;        /* number of times TX Q was stopped */
 161         u32 be_fwd_reqs;        /* number of send reqs through forwarding i/f */
 162         u32 be_tx_wrbs;         /* number of tx WRBs used */
 163         u32 be_tx_events;       /* number of tx completion events  */
 164         u32 be_tx_compl;        /* number of tx completion entries processed */
 165         ulong be_tx_jiffies;
 166         u64 be_tx_bytes;
 167         u64 be_tx_bytes_prev;
 168         u64 be_tx_pkts;
 169         u32 be_tx_rate;
 170
 171         u32 cache_barrier[16];
 172
 173         u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
 174         u32 be_rx_polls;        /* number of times NAPI called poll function */
 175         u32 be_rx_events;       /* number of ucast rx completion events  */
 176         u32 be_rx_compl;        /* number of rx completion entries processed */
 177         ulong be_rx_jiffies;
 178         u64 be_rx_bytes;
 179         u64 be_rx_bytes_prev;
 180         u64 be_rx_pkts;
 181         u32 be_rx_rate;
 182         /* number of non ether type II frames dropped where
 183          * frame len > length field of Mac Hdr */
 184         u32 be_802_3_dropped_frames;
 185         /* number of non ether type II frames malformed where
 186          * in frame len < length field of Mac Hdr */
 187         u32 be_802_3_malformed_frames;
 188         u32 be_rxcp_err;        /* Num rx completion entries w/ err set. */
 189         ulong rx_fps_jiffies;   /* jiffies at last FPS calc */
 190         u32 be_rx_frags;
 191         u32 be_prev_rx_frags;
 192         u32 be_rx_fps;          /* Rx frags per second */
 193 };
 194
 195 struct be_stats_obj {
 196         struct be_drvr_stats drvr_stats;
 197         struct be_dma_mem cmd;
 198 };
 199
 200 struct be_tx_obj {
 201         struct be_queue_info q;
 202         struct be_queue_info cq;
 203         /* Remember the skbs that were transmitted */
 204         struct sk_buff *sent_skb_list[TX_Q_LEN];
 205 };
 206
 207 /* Struct to remember the pages posted for rx frags */
 208 struct be_rx_page_info {
 209         struct page *page;
 210         dma_addr_t bus;
 211         u16 page_offset;
 212         bool last_page_user;
 213 };
 214
 215 struct be_rx_obj {
 216         struct be_queue_info q;
 217         struct be_queue_info cq;
 218         struct be_rx_page_info page_info_tbl[RX_Q_LEN];
 219 };
 220
 221 #define BE_NUM_MSIX_VECTORS             2       /* 1 each for Tx and Rx */
 222 struct be_adapter {
 223         struct pci_dev *pdev;
 224         struct net_device *netdev;
 225
 226         u8 __iomem *csr;
 227         u8 __iomem *db;         /* Door Bell */
 228         u8 __iomem *pcicfg;     /* PCI config space */
 229
 230         spinlock_t mbox_lock;   /* For serializing mbox cmds to BE card */
 231         struct be_dma_mem mbox_mem;
 232         /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
 233          * is stored for freeing purpose */
 234         struct be_dma_mem mbox_mem_alloced;
 235
 236         struct be_mcc_obj mcc_obj;
 237         spinlock_t mcc_lock;    /* For serializing mcc cmds to BE card */
 238         spinlock_t mcc_cq_lock;
 239
 240         struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
 241         bool msix_enabled;
 242         bool isr_registered;
 243
 244         /* TX Rings */
 245         struct be_eq_obj tx_eq;
 246         struct be_tx_obj tx_obj;
 247
 248         u32 cache_line_break[8];
 249
 250         /* Rx rings */
 251         struct be_eq_obj rx_eq;
 252         struct be_rx_obj rx_obj;
 253         u32 big_page_size;      /* Compounded page size shared by rx wrbs */
 254         bool rx_post_starved;   /* Zero rx frags have been posted to BE */
 255
 256         struct vlan_group *vlan_grp;
 257         u16 vlans_added;
 258         u16 max_vlans;  /* Number of vlans supported */
 259         u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
 260         struct be_dma_mem mc_cmd_mem;
 261
 262         struct be_stats_obj stats;
 263         /* Work queue used to perform periodic tasks like getting statistics */
 264         struct delayed_work work;
 265
 266         /* Ethtool knobs and info */
 267         bool rx_csum;           /* BE card must perform rx-checksumming */
 268         char fw_ver[FW_VER_LEN];
 269         u32 if_handle;          /* Used to configure filtering */
 270         u32 pmac_id;            /* MAC addr handle used by BE card */
 271
 272         bool eeh_err;
 273         bool link_up;
 274         u32 port_num;
 275         bool promiscuous;
 276         bool wol;
 277         u32 cap;
 278         u32 rx_fc;              /* Rx flow control */
 279         u32 tx_fc;              /* Tx flow control */
 280         int link_speed;
 281         u8 port_type;
 282         u8 transceiver;
 283         u8 generation;          /* BladeEngine ASIC generation */
 284 };
 285
 286 /* BladeEngine Generation numbers */
 287 #define BE_GEN2 2
 288 #define BE_GEN3 3
 289
 290 extern const struct ethtool_ops be_ethtool_ops;
 291
 292 #define drvr_stats(adapter)             (&adapter->stats.drvr_stats)
 293
 294 #define BE_SET_NETDEV_OPS(netdev, ops)  (netdev->netdev_ops = ops)
 295
 296 #define PAGE_SHIFT_4K           12
 297 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 298
 299 /* Returns number of pages spanned by the data starting at the given addr */
 300 #define PAGES_4K_SPANNED(_address, size)                                \
 301                 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 302                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 303
 304 /* Byte offset into the page corresponding to given address */
 305 #define OFFSET_IN_PAGE(addr)                                            \
 306                  ((size_t)(addr) & (PAGE_SIZE_4K-1))
 307
 308 /* Returns bit offset within a DWORD of a bitfield */
 309 #define AMAP_BIT_OFFSET(_struct, field)                                 \
 310                 (((size_t)&(((_struct *)0)->field))%32)
 311
 312 /* Returns the bit mask of the field that is NOT shifted into location. */
 313 static inline u32 amap_mask(u32 bitsize)
 314 {
 315         return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
 316 }
 317
 318 static inline void
 319 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
 320 {
 321         u32 *dw = (u32 *) ptr + dw_offset;
 322         *dw &= ~(mask << offset);
 323         *dw |= (mask & value) << offset;
 324 }
 325
 326 #define AMAP_SET_BITS(_struct, field, ptr, val)                         \
 327                 amap_set(ptr,                                           \
 328                         offsetof(_struct, field)/32,                    \
 329                         amap_mask(sizeof(((_struct *)0)->field)),       \
 330                         AMAP_BIT_OFFSET(_struct, field),                \
 331                         val)
 332
 333 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
 334 {
 335         u32 *dw = (u32 *) ptr;
 336         return mask & (*(dw + dw_offset) >> offset);
 337 }
 338
 339 #define AMAP_GET_BITS(_struct, field, ptr)                              \
 340                 amap_get(ptr,                                           \
 341                         offsetof(_struct, field)/32,                    \
 342                         amap_mask(sizeof(((_struct *)0)->field)),       \
 343                         AMAP_BIT_OFFSET(_struct, field))
 344
 345 #define be_dws_cpu_to_le(wrb, len)      swap_dws(wrb, len)
 346 #define be_dws_le_to_cpu(wrb, len)      swap_dws(wrb, len)
 347 static inline void swap_dws(void *wrb, int len)
 348 {
 349 #ifdef __BIG_ENDIAN
 350         u32 *dw = wrb;
 351         BUG_ON(len % 4);
 352         do {
 353                 *dw = cpu_to_le32(*dw);
 354                 dw++;
 355                 len -= 4;
 356         } while (len);
 357 #endif                          /* __BIG_ENDIAN */
 358 }
 359
 360 static inline u8 is_tcp_pkt(struct sk_buff *skb)
 361 {
 362         u8 val = 0;
 363
 364         if (ip_hdr(skb)->version == 4)
 365                 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
 366         else if (ip_hdr(skb)->version == 6)
 367                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
 368
 369         return val;
 370 }
 371
 372 static inline u8 is_udp_pkt(struct sk_buff *skb)
 373 {
 374         u8 val = 0;
 375
 376         if (ip_hdr(skb)->version == 4)
 377                 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
 378         else if (ip_hdr(skb)->version == 6)
 379                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
 380
 381         return val;
 382 }
 383
 384 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
 385                 u16 num_popped);
 386 extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
 387 extern void netdev_stats_update(struct be_adapter *adapter);
 388 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
 389 #endif                          /* BE_H */