2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/version.h>
24 #include <linux/delay.h>
28 #include <linux/if_vlan.h>
29 #include <linux/workqueue.h>
30 #include <linux/interrupt.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
36 #define DRV_VER "2.103.175u"
37 #define DRV_NAME "be2net"
38 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
39 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
40 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
41 #define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
42 #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
44 #define BE_VENDOR_ID 0x19a2
45 #define BE_DEVICE_ID1 0x211
46 #define BE_DEVICE_ID2 0x221
47 #define OC_DEVICE_ID1 0x700
48 #define OC_DEVICE_ID2 0x710
50 static inline char *nic_name(struct pci_dev
*pdev
)
52 switch (pdev
->device
) {
64 /* Number of bytes of an RX frame that are copied to skb->data */
66 #define BE_MAX_JUMBO_FRAME_SIZE 9018
67 #define BE_MIN_MTU 256
69 #define BE_NUM_VLANS_SUPPORTED 64
71 #define BE_MAX_TX_FRAG_COUNT 30
73 #define EVNT_Q_LEN 1024
75 #define TX_CQ_LEN 1024
76 #define RX_Q_LEN 1024 /* Does not support any other value */
77 #define RX_CQ_LEN 1024
78 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
79 #define MCC_CQ_LEN 256
81 #define BE_NAPI_WEIGHT 64
82 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
83 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
95 struct be_queue_info
{
96 struct be_dma_mem dma_mem
;
98 u16 entry_size
; /* Size of an element in the queue */
102 atomic_t used
; /* Number of valid elements in the queue */
105 static inline u32
MODULO(u16 val
, u16 limit
)
107 BUG_ON(limit
& (limit
- 1));
108 return val
& (limit
- 1);
111 static inline void index_adv(u16
*index
, u16 val
, u16 limit
)
113 *index
= MODULO((*index
+ val
), limit
);
116 static inline void index_inc(u16
*index
, u16 limit
)
118 *index
= MODULO((*index
+ 1), limit
);
121 static inline void *queue_head_node(struct be_queue_info
*q
)
123 return q
->dma_mem
.va
+ q
->head
* q
->entry_size
;
126 static inline void *queue_tail_node(struct be_queue_info
*q
)
128 return q
->dma_mem
.va
+ q
->tail
* q
->entry_size
;
131 static inline void queue_head_inc(struct be_queue_info
*q
)
133 index_inc(&q
->head
, q
->len
);
136 static inline void queue_tail_inc(struct be_queue_info
*q
)
138 index_inc(&q
->tail
, q
->len
);
142 struct be_queue_info q
;
145 /* Adaptive interrupt coalescing (AIC) info */
147 u16 min_eqd
; /* in usecs */
148 u16 max_eqd
; /* in usecs */
149 u16 cur_eqd
; /* in usecs */
151 struct napi_struct napi
;
155 struct be_queue_info q
;
156 struct be_queue_info cq
;
160 struct be_drvr_stats
{
161 u32 be_tx_reqs
; /* number of TX requests initiated */
162 u32 be_tx_stops
; /* number of times TX Q was stopped */
163 u32 be_fwd_reqs
; /* number of send reqs through forwarding i/f */
164 u32 be_tx_wrbs
; /* number of tx WRBs used */
165 u32 be_tx_events
; /* number of tx completion events */
166 u32 be_tx_compl
; /* number of tx completion entries processed */
169 u64 be_tx_bytes_prev
;
173 u32 cache_barrier
[16];
175 u32 be_ethrx_post_fail
;/* number of ethrx buffer alloc failures */
176 u32 be_rx_polls
; /* number of times NAPI called poll function */
177 u32 be_rx_events
; /* number of ucast rx completion events */
178 u32 be_rx_compl
; /* number of rx completion entries processed */
181 u64 be_rx_bytes_prev
;
185 /* number of non ether type II frames dropped where
186 * frame len > length field of Mac Hdr */
187 u32 be_802_3_dropped_frames
;
188 /* number of non ether type II frames malformed where
189 * in frame len < length field of Mac Hdr */
190 u32 be_802_3_malformed_frames
;
191 u32 be_rxcp_err
; /* Num rx completion entries w/ err set. */
192 ulong rx_fps_jiffies
; /* jiffies at last FPS calc */
194 u32 be_prev_rx_frags
;
195 u32 be_rx_fps
; /* Rx frags per second */
198 struct be_stats_obj
{
199 struct be_drvr_stats drvr_stats
;
200 struct be_dma_mem cmd
;
204 struct be_queue_info q
;
205 struct be_queue_info cq
;
206 /* Remember the skbs that were transmitted */
207 struct sk_buff
*sent_skb_list
[TX_Q_LEN
];
210 /* Struct to remember the pages posted for rx frags */
211 struct be_rx_page_info
{
213 DEFINE_DMA_UNMAP_ADDR(bus
);
219 struct be_queue_info q
;
220 struct be_queue_info cq
;
221 struct be_rx_page_info page_info_tbl
[RX_Q_LEN
];
225 unsigned char vf_mac_addr
[ETH_ALEN
];
232 #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
233 #define BE_INVALID_PMAC_ID 0xffffffff
235 struct pci_dev
*pdev
;
236 struct net_device
*netdev
;
239 u8 __iomem
*db
; /* Door Bell */
240 u8 __iomem
*pcicfg
; /* PCI config space */
242 spinlock_t mbox_lock
; /* For serializing mbox cmds to BE card */
243 struct be_dma_mem mbox_mem
;
244 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
245 * is stored for freeing purpose */
246 struct be_dma_mem mbox_mem_alloced
;
248 struct be_mcc_obj mcc_obj
;
249 spinlock_t mcc_lock
; /* For serializing mcc cmds to BE card */
250 spinlock_t mcc_cq_lock
;
252 struct msix_entry msix_entries
[BE_NUM_MSIX_VECTORS
];
257 struct be_eq_obj tx_eq
;
258 struct be_tx_obj tx_obj
;
260 u32 cache_line_break
[8];
263 struct be_eq_obj rx_eq
;
264 struct be_rx_obj rx_obj
;
265 u32 big_page_size
; /* Compounded page size shared by rx wrbs */
266 bool rx_post_starved
; /* Zero rx frags have been posted to BE */
268 struct vlan_group
*vlan_grp
;
270 u16 max_vlans
; /* Number of vlans supported */
271 u8 vlan_tag
[VLAN_GROUP_ARRAY_LEN
];
272 struct be_dma_mem mc_cmd_mem
;
274 struct be_stats_obj stats
;
275 /* Work queue used to perform periodic tasks like getting statistics */
276 struct delayed_work work
;
278 /* Ethtool knobs and info */
279 bool rx_csum
; /* BE card must perform rx-checksumming */
280 char fw_ver
[FW_VER_LEN
];
281 u32 if_handle
; /* Used to configure filtering */
282 u32 pmac_id
; /* MAC addr handle used by BE card */
290 u32 rx_fc
; /* Rx flow control */
291 u32 tx_fc
; /* Tx flow control */
293 bool stats_ioctl_sent
;
298 u8 generation
; /* BladeEngine ASIC generation */
300 struct completion flash_compl
;
303 struct be_vf_cfg vf_cfg
[BE_MAX_VF
];
308 #define be_physfn(adapter) (!adapter->is_virtfn)
310 /* BladeEngine Generation numbers */
314 extern const struct ethtool_ops be_ethtool_ops
;
316 #define drvr_stats(adapter) (&adapter->stats.drvr_stats)
318 #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
320 #define PAGE_SHIFT_4K 12
321 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
323 /* Returns number of pages spanned by the data starting at the given addr */
324 #define PAGES_4K_SPANNED(_address, size) \
325 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
326 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
328 /* Byte offset into the page corresponding to given address */
329 #define OFFSET_IN_PAGE(addr) \
330 ((size_t)(addr) & (PAGE_SIZE_4K-1))
332 /* Returns bit offset within a DWORD of a bitfield */
333 #define AMAP_BIT_OFFSET(_struct, field) \
334 (((size_t)&(((_struct *)0)->field))%32)
336 /* Returns the bit mask of the field that is NOT shifted into location. */
337 static inline u32
amap_mask(u32 bitsize
)
339 return (bitsize
== 32 ? 0xFFFFFFFF : (1 << bitsize
) - 1);
343 amap_set(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
, u32 value
)
345 u32
*dw
= (u32
*) ptr
+ dw_offset
;
346 *dw
&= ~(mask
<< offset
);
347 *dw
|= (mask
& value
) << offset
;
350 #define AMAP_SET_BITS(_struct, field, ptr, val) \
352 offsetof(_struct, field)/32, \
353 amap_mask(sizeof(((_struct *)0)->field)), \
354 AMAP_BIT_OFFSET(_struct, field), \
357 static inline u32
amap_get(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
)
359 u32
*dw
= (u32
*) ptr
;
360 return mask
& (*(dw
+ dw_offset
) >> offset
);
363 #define AMAP_GET_BITS(_struct, field, ptr) \
365 offsetof(_struct, field)/32, \
366 amap_mask(sizeof(((_struct *)0)->field)), \
367 AMAP_BIT_OFFSET(_struct, field))
369 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
370 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
371 static inline void swap_dws(void *wrb
, int len
)
377 *dw
= cpu_to_le32(*dw
);
381 #endif /* __BIG_ENDIAN */
384 static inline u8
is_tcp_pkt(struct sk_buff
*skb
)
388 if (ip_hdr(skb
)->version
== 4)
389 val
= (ip_hdr(skb
)->protocol
== IPPROTO_TCP
);
390 else if (ip_hdr(skb
)->version
== 6)
391 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_TCP
);
396 static inline u8
is_udp_pkt(struct sk_buff
*skb
)
400 if (ip_hdr(skb
)->version
== 4)
401 val
= (ip_hdr(skb
)->protocol
== IPPROTO_UDP
);
402 else if (ip_hdr(skb
)->version
== 6)
403 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_UDP
);
408 static inline void be_check_sriov_fn_type(struct be_adapter
*adapter
)
412 pci_write_config_byte(adapter
->pdev
, 0xFE, 0xAA);
413 pci_read_config_byte(adapter
->pdev
, 0xFE, &data
);
414 adapter
->is_virtfn
= (data
!= 0xAA);
417 extern void be_cq_notify(struct be_adapter
*adapter
, u16 qid
, bool arm
,
419 extern void be_link_status_update(struct be_adapter
*adapter
, bool link_up
);
420 extern void netdev_stats_update(struct be_adapter
*adapter
);
421 extern int be_load_fw(struct be_adapter
*adapter
, u8
*func
);