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be2net: Support for version 1 of stats for BE3
[deliverable/linux.git] / drivers / net / benet / be_cmds.c
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 32;
23
24 static void be_mcc_notify(struct be_adapter *adapter)
25 {
26 struct be_queue_info *mccq = &adapter->mcc_obj.q;
27 u32 val = 0;
28
29 if (adapter->eeh_err) {
30 dev_info(&adapter->pdev->dev,
31 "Error in Card Detected! Cannot issue commands\n");
32 return;
33 }
34
35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
37
38 wmb();
39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
40 }
41
42 /* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
46 {
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54 }
55
56 /* Need to reset the entire word that houses the valid bit */
57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
58 {
59 compl->flags = 0;
60 }
61
62 static int be_mcc_compl_process(struct be_adapter *adapter,
63 struct be_mcc_compl *compl)
64 {
65 u16 compl_status, extd_status;
66
67 /* Just swap the status to host endian; mcc tag is opaquely copied
68 * from mcc_wrb */
69 be_dws_le_to_cpu(compl, 4);
70
71 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
72 CQE_STATUS_COMPL_MASK;
73
74 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
75 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
76 adapter->flash_status = compl_status;
77 complete(&adapter->flash_compl);
78 }
79
80 if (compl_status == MCC_STATUS_SUCCESS) {
81 if ((compl->tag0 == OPCODE_ETH_GET_STATISTICS) &&
82 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
83 if (adapter->generation == BE_GEN3) {
84 struct be_cmd_resp_get_stats_v1 *resp =
85 adapter->stats_cmd.va;
86
87 be_dws_le_to_cpu(&resp->hw_stats,
88 sizeof(resp->hw_stats));
89 } else {
90 struct be_cmd_resp_get_stats_v0 *resp =
91 adapter->stats_cmd.va;
92
93 be_dws_le_to_cpu(&resp->hw_stats,
94 sizeof(resp->hw_stats));
95 }
96 be_parse_stats(adapter);
97 netdev_stats_update(adapter);
98 adapter->stats_cmd_sent = false;
99 }
100 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
101 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
102 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
103 CQE_STATUS_EXTD_MASK;
104 dev_warn(&adapter->pdev->dev,
105 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
106 compl->tag0, compl_status, extd_status);
107 }
108 return compl_status;
109 }
110
111 /* Link state evt is a string of bytes; no need for endian swapping */
112 static void be_async_link_state_process(struct be_adapter *adapter,
113 struct be_async_event_link_state *evt)
114 {
115 be_link_status_update(adapter,
116 evt->port_link_status == ASYNC_EVENT_LINK_UP);
117 }
118
119 /* Grp5 CoS Priority evt */
120 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
121 struct be_async_event_grp5_cos_priority *evt)
122 {
123 if (evt->valid) {
124 adapter->vlan_prio_bmap = evt->available_priority_bmap;
125 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
126 adapter->recommended_prio =
127 evt->reco_default_priority << VLAN_PRIO_SHIFT;
128 }
129 }
130
131 /* Grp5 QOS Speed evt */
132 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
133 struct be_async_event_grp5_qos_link_speed *evt)
134 {
135 if (evt->physical_port == adapter->port_num) {
136 /* qos_link_speed is in units of 10 Mbps */
137 adapter->link_speed = evt->qos_link_speed * 10;
138 }
139 }
140
141 /*Grp5 PVID evt*/
142 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
143 struct be_async_event_grp5_pvid_state *evt)
144 {
145 if (evt->enabled)
146 adapter->pvid = le16_to_cpu(evt->tag);
147 else
148 adapter->pvid = 0;
149 }
150
151 static void be_async_grp5_evt_process(struct be_adapter *adapter,
152 u32 trailer, struct be_mcc_compl *evt)
153 {
154 u8 event_type = 0;
155
156 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
157 ASYNC_TRAILER_EVENT_TYPE_MASK;
158
159 switch (event_type) {
160 case ASYNC_EVENT_COS_PRIORITY:
161 be_async_grp5_cos_priority_process(adapter,
162 (struct be_async_event_grp5_cos_priority *)evt);
163 break;
164 case ASYNC_EVENT_QOS_SPEED:
165 be_async_grp5_qos_speed_process(adapter,
166 (struct be_async_event_grp5_qos_link_speed *)evt);
167 break;
168 case ASYNC_EVENT_PVID_STATE:
169 be_async_grp5_pvid_state_process(adapter,
170 (struct be_async_event_grp5_pvid_state *)evt);
171 break;
172 default:
173 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
174 break;
175 }
176 }
177
178 static inline bool is_link_state_evt(u32 trailer)
179 {
180 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
181 ASYNC_TRAILER_EVENT_CODE_MASK) ==
182 ASYNC_EVENT_CODE_LINK_STATE;
183 }
184
185 static inline bool is_grp5_evt(u32 trailer)
186 {
187 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
188 ASYNC_TRAILER_EVENT_CODE_MASK) ==
189 ASYNC_EVENT_CODE_GRP_5);
190 }
191
192 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
193 {
194 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
195 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
196
197 if (be_mcc_compl_is_new(compl)) {
198 queue_tail_inc(mcc_cq);
199 return compl;
200 }
201 return NULL;
202 }
203
204 void be_async_mcc_enable(struct be_adapter *adapter)
205 {
206 spin_lock_bh(&adapter->mcc_cq_lock);
207
208 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
209 adapter->mcc_obj.rearm_cq = true;
210
211 spin_unlock_bh(&adapter->mcc_cq_lock);
212 }
213
214 void be_async_mcc_disable(struct be_adapter *adapter)
215 {
216 adapter->mcc_obj.rearm_cq = false;
217 }
218
219 int be_process_mcc(struct be_adapter *adapter, int *status)
220 {
221 struct be_mcc_compl *compl;
222 int num = 0;
223 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
224
225 spin_lock_bh(&adapter->mcc_cq_lock);
226 while ((compl = be_mcc_compl_get(adapter))) {
227 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
228 /* Interpret flags as an async trailer */
229 if (is_link_state_evt(compl->flags))
230 be_async_link_state_process(adapter,
231 (struct be_async_event_link_state *) compl);
232 else if (is_grp5_evt(compl->flags))
233 be_async_grp5_evt_process(adapter,
234 compl->flags, compl);
235 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
236 *status = be_mcc_compl_process(adapter, compl);
237 atomic_dec(&mcc_obj->q.used);
238 }
239 be_mcc_compl_use(compl);
240 num++;
241 }
242
243 spin_unlock_bh(&adapter->mcc_cq_lock);
244 return num;
245 }
246
247 /* Wait till no more pending mcc requests are present */
248 static int be_mcc_wait_compl(struct be_adapter *adapter)
249 {
250 #define mcc_timeout 120000 /* 12s timeout */
251 int i, num, status = 0;
252 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
253
254 if (adapter->eeh_err)
255 return -EIO;
256
257 for (i = 0; i < mcc_timeout; i++) {
258 num = be_process_mcc(adapter, &status);
259 if (num)
260 be_cq_notify(adapter, mcc_obj->cq.id,
261 mcc_obj->rearm_cq, num);
262
263 if (atomic_read(&mcc_obj->q.used) == 0)
264 break;
265 udelay(100);
266 }
267 if (i == mcc_timeout) {
268 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
269 return -1;
270 }
271 return status;
272 }
273
274 /* Notify MCC requests and wait for completion */
275 static int be_mcc_notify_wait(struct be_adapter *adapter)
276 {
277 be_mcc_notify(adapter);
278 return be_mcc_wait_compl(adapter);
279 }
280
281 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
282 {
283 int msecs = 0;
284 u32 ready;
285
286 if (adapter->eeh_err) {
287 dev_err(&adapter->pdev->dev,
288 "Error detected in card.Cannot issue commands\n");
289 return -EIO;
290 }
291
292 do {
293 ready = ioread32(db);
294 if (ready == 0xffffffff) {
295 dev_err(&adapter->pdev->dev,
296 "pci slot disconnected\n");
297 return -1;
298 }
299
300 ready &= MPU_MAILBOX_DB_RDY_MASK;
301 if (ready)
302 break;
303
304 if (msecs > 4000) {
305 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
306 if (!lancer_chip(adapter))
307 be_detect_dump_ue(adapter);
308 return -1;
309 }
310
311 msleep(1);
312 msecs++;
313 } while (true);
314
315 return 0;
316 }
317
318 /*
319 * Insert the mailbox address into the doorbell in two steps
320 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
321 */
322 static int be_mbox_notify_wait(struct be_adapter *adapter)
323 {
324 int status;
325 u32 val = 0;
326 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
327 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
328 struct be_mcc_mailbox *mbox = mbox_mem->va;
329 struct be_mcc_compl *compl = &mbox->compl;
330
331 /* wait for ready to be set */
332 status = be_mbox_db_ready_wait(adapter, db);
333 if (status != 0)
334 return status;
335
336 val |= MPU_MAILBOX_DB_HI_MASK;
337 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
338 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
339 iowrite32(val, db);
340
341 /* wait for ready to be set */
342 status = be_mbox_db_ready_wait(adapter, db);
343 if (status != 0)
344 return status;
345
346 val = 0;
347 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
348 val |= (u32)(mbox_mem->dma >> 4) << 2;
349 iowrite32(val, db);
350
351 status = be_mbox_db_ready_wait(adapter, db);
352 if (status != 0)
353 return status;
354
355 /* A cq entry has been made now */
356 if (be_mcc_compl_is_new(compl)) {
357 status = be_mcc_compl_process(adapter, &mbox->compl);
358 be_mcc_compl_use(compl);
359 if (status)
360 return status;
361 } else {
362 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
363 return -1;
364 }
365 return 0;
366 }
367
368 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
369 {
370 u32 sem;
371
372 if (lancer_chip(adapter))
373 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
374 else
375 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
376
377 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
378 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
379 return -1;
380 else
381 return 0;
382 }
383
384 int be_cmd_POST(struct be_adapter *adapter)
385 {
386 u16 stage;
387 int status, timeout = 0;
388 struct device *dev = &adapter->pdev->dev;
389
390 do {
391 status = be_POST_stage_get(adapter, &stage);
392 if (status) {
393 dev_err(dev, "POST error; stage=0x%x\n", stage);
394 return -1;
395 } else if (stage != POST_STAGE_ARMFW_RDY) {
396 if (msleep_interruptible(2000)) {
397 dev_err(dev, "Waiting for POST aborted\n");
398 return -EINTR;
399 }
400 timeout += 2;
401 } else {
402 return 0;
403 }
404 } while (timeout < 40);
405
406 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
407 return -1;
408 }
409
410 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
411 {
412 return wrb->payload.embedded_payload;
413 }
414
415 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
416 {
417 return &wrb->payload.sgl[0];
418 }
419
420 /* Don't touch the hdr after it's prepared */
421 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
422 bool embedded, u8 sge_cnt, u32 opcode)
423 {
424 if (embedded)
425 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
426 else
427 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
428 MCC_WRB_SGE_CNT_SHIFT;
429 wrb->payload_length = payload_len;
430 wrb->tag0 = opcode;
431 be_dws_cpu_to_le(wrb, 8);
432 }
433
434 /* Don't touch the hdr after it's prepared */
435 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
436 u8 subsystem, u8 opcode, int cmd_len)
437 {
438 req_hdr->opcode = opcode;
439 req_hdr->subsystem = subsystem;
440 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
441 req_hdr->version = 0;
442 }
443
444 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
445 struct be_dma_mem *mem)
446 {
447 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
448 u64 dma = (u64)mem->dma;
449
450 for (i = 0; i < buf_pages; i++) {
451 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
452 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
453 dma += PAGE_SIZE_4K;
454 }
455 }
456
457 /* Converts interrupt delay in microseconds to multiplier value */
458 static u32 eq_delay_to_mult(u32 usec_delay)
459 {
460 #define MAX_INTR_RATE 651042
461 const u32 round = 10;
462 u32 multiplier;
463
464 if (usec_delay == 0)
465 multiplier = 0;
466 else {
467 u32 interrupt_rate = 1000000 / usec_delay;
468 /* Max delay, corresponding to the lowest interrupt rate */
469 if (interrupt_rate == 0)
470 multiplier = 1023;
471 else {
472 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
473 multiplier /= interrupt_rate;
474 /* Round the multiplier to the closest value.*/
475 multiplier = (multiplier + round/2) / round;
476 multiplier = min(multiplier, (u32)1023);
477 }
478 }
479 return multiplier;
480 }
481
482 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
483 {
484 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
485 struct be_mcc_wrb *wrb
486 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
487 memset(wrb, 0, sizeof(*wrb));
488 return wrb;
489 }
490
491 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
492 {
493 struct be_queue_info *mccq = &adapter->mcc_obj.q;
494 struct be_mcc_wrb *wrb;
495
496 if (atomic_read(&mccq->used) >= mccq->len) {
497 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
498 return NULL;
499 }
500
501 wrb = queue_head_node(mccq);
502 queue_head_inc(mccq);
503 atomic_inc(&mccq->used);
504 memset(wrb, 0, sizeof(*wrb));
505 return wrb;
506 }
507
508 /* Tell fw we're about to start firing cmds by writing a
509 * special pattern across the wrb hdr; uses mbox
510 */
511 int be_cmd_fw_init(struct be_adapter *adapter)
512 {
513 u8 *wrb;
514 int status;
515
516 if (mutex_lock_interruptible(&adapter->mbox_lock))
517 return -1;
518
519 wrb = (u8 *)wrb_from_mbox(adapter);
520 *wrb++ = 0xFF;
521 *wrb++ = 0x12;
522 *wrb++ = 0x34;
523 *wrb++ = 0xFF;
524 *wrb++ = 0xFF;
525 *wrb++ = 0x56;
526 *wrb++ = 0x78;
527 *wrb = 0xFF;
528
529 status = be_mbox_notify_wait(adapter);
530
531 mutex_unlock(&adapter->mbox_lock);
532 return status;
533 }
534
535 /* Tell fw we're done with firing cmds by writing a
536 * special pattern across the wrb hdr; uses mbox
537 */
538 int be_cmd_fw_clean(struct be_adapter *adapter)
539 {
540 u8 *wrb;
541 int status;
542
543 if (adapter->eeh_err)
544 return -EIO;
545
546 if (mutex_lock_interruptible(&adapter->mbox_lock))
547 return -1;
548
549 wrb = (u8 *)wrb_from_mbox(adapter);
550 *wrb++ = 0xFF;
551 *wrb++ = 0xAA;
552 *wrb++ = 0xBB;
553 *wrb++ = 0xFF;
554 *wrb++ = 0xFF;
555 *wrb++ = 0xCC;
556 *wrb++ = 0xDD;
557 *wrb = 0xFF;
558
559 status = be_mbox_notify_wait(adapter);
560
561 mutex_unlock(&adapter->mbox_lock);
562 return status;
563 }
564 int be_cmd_eq_create(struct be_adapter *adapter,
565 struct be_queue_info *eq, int eq_delay)
566 {
567 struct be_mcc_wrb *wrb;
568 struct be_cmd_req_eq_create *req;
569 struct be_dma_mem *q_mem = &eq->dma_mem;
570 int status;
571
572 if (mutex_lock_interruptible(&adapter->mbox_lock))
573 return -1;
574
575 wrb = wrb_from_mbox(adapter);
576 req = embedded_payload(wrb);
577
578 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
579
580 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
581 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
582
583 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
584
585 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
586 /* 4byte eqe*/
587 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
588 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
589 __ilog2_u32(eq->len/256));
590 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
591 eq_delay_to_mult(eq_delay));
592 be_dws_cpu_to_le(req->context, sizeof(req->context));
593
594 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
595
596 status = be_mbox_notify_wait(adapter);
597 if (!status) {
598 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
599 eq->id = le16_to_cpu(resp->eq_id);
600 eq->created = true;
601 }
602
603 mutex_unlock(&adapter->mbox_lock);
604 return status;
605 }
606
607 /* Uses mbox */
608 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
609 u8 type, bool permanent, u32 if_handle)
610 {
611 struct be_mcc_wrb *wrb;
612 struct be_cmd_req_mac_query *req;
613 int status;
614
615 if (mutex_lock_interruptible(&adapter->mbox_lock))
616 return -1;
617
618 wrb = wrb_from_mbox(adapter);
619 req = embedded_payload(wrb);
620
621 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
622 OPCODE_COMMON_NTWK_MAC_QUERY);
623
624 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
625 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
626
627 req->type = type;
628 if (permanent) {
629 req->permanent = 1;
630 } else {
631 req->if_id = cpu_to_le16((u16) if_handle);
632 req->permanent = 0;
633 }
634
635 status = be_mbox_notify_wait(adapter);
636 if (!status) {
637 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
638 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
639 }
640
641 mutex_unlock(&adapter->mbox_lock);
642 return status;
643 }
644
645 /* Uses synchronous MCCQ */
646 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
647 u32 if_id, u32 *pmac_id, u32 domain)
648 {
649 struct be_mcc_wrb *wrb;
650 struct be_cmd_req_pmac_add *req;
651 int status;
652
653 spin_lock_bh(&adapter->mcc_lock);
654
655 wrb = wrb_from_mccq(adapter);
656 if (!wrb) {
657 status = -EBUSY;
658 goto err;
659 }
660 req = embedded_payload(wrb);
661
662 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
663 OPCODE_COMMON_NTWK_PMAC_ADD);
664
665 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
666 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
667
668 req->hdr.domain = domain;
669 req->if_id = cpu_to_le32(if_id);
670 memcpy(req->mac_address, mac_addr, ETH_ALEN);
671
672 status = be_mcc_notify_wait(adapter);
673 if (!status) {
674 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
675 *pmac_id = le32_to_cpu(resp->pmac_id);
676 }
677
678 err:
679 spin_unlock_bh(&adapter->mcc_lock);
680 return status;
681 }
682
683 /* Uses synchronous MCCQ */
684 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
685 {
686 struct be_mcc_wrb *wrb;
687 struct be_cmd_req_pmac_del *req;
688 int status;
689
690 spin_lock_bh(&adapter->mcc_lock);
691
692 wrb = wrb_from_mccq(adapter);
693 if (!wrb) {
694 status = -EBUSY;
695 goto err;
696 }
697 req = embedded_payload(wrb);
698
699 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
700 OPCODE_COMMON_NTWK_PMAC_DEL);
701
702 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
703 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
704
705 req->hdr.domain = dom;
706 req->if_id = cpu_to_le32(if_id);
707 req->pmac_id = cpu_to_le32(pmac_id);
708
709 status = be_mcc_notify_wait(adapter);
710
711 err:
712 spin_unlock_bh(&adapter->mcc_lock);
713 return status;
714 }
715
716 /* Uses Mbox */
717 int be_cmd_cq_create(struct be_adapter *adapter,
718 struct be_queue_info *cq, struct be_queue_info *eq,
719 bool sol_evts, bool no_delay, int coalesce_wm)
720 {
721 struct be_mcc_wrb *wrb;
722 struct be_cmd_req_cq_create *req;
723 struct be_dma_mem *q_mem = &cq->dma_mem;
724 void *ctxt;
725 int status;
726
727 if (mutex_lock_interruptible(&adapter->mbox_lock))
728 return -1;
729
730 wrb = wrb_from_mbox(adapter);
731 req = embedded_payload(wrb);
732 ctxt = &req->context;
733
734 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
735 OPCODE_COMMON_CQ_CREATE);
736
737 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
738 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
739
740 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
741 if (lancer_chip(adapter)) {
742 req->hdr.version = 2;
743 req->page_size = 1; /* 1 for 4K */
744 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
745 no_delay);
746 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
747 __ilog2_u32(cq->len/256));
748 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
749 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
750 ctxt, 1);
751 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
752 ctxt, eq->id);
753 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
754 } else {
755 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
756 coalesce_wm);
757 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
758 ctxt, no_delay);
759 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
760 __ilog2_u32(cq->len/256));
761 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
762 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
763 ctxt, sol_evts);
764 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
765 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
766 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
767 }
768
769 be_dws_cpu_to_le(ctxt, sizeof(req->context));
770
771 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
772
773 status = be_mbox_notify_wait(adapter);
774 if (!status) {
775 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
776 cq->id = le16_to_cpu(resp->cq_id);
777 cq->created = true;
778 }
779
780 mutex_unlock(&adapter->mbox_lock);
781
782 return status;
783 }
784
785 static u32 be_encoded_q_len(int q_len)
786 {
787 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
788 if (len_encoded == 16)
789 len_encoded = 0;
790 return len_encoded;
791 }
792
793 int be_cmd_mccq_create(struct be_adapter *adapter,
794 struct be_queue_info *mccq,
795 struct be_queue_info *cq)
796 {
797 struct be_mcc_wrb *wrb;
798 struct be_cmd_req_mcc_create *req;
799 struct be_dma_mem *q_mem = &mccq->dma_mem;
800 void *ctxt;
801 int status;
802
803 if (mutex_lock_interruptible(&adapter->mbox_lock))
804 return -1;
805
806 wrb = wrb_from_mbox(adapter);
807 req = embedded_payload(wrb);
808 ctxt = &req->context;
809
810 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
811 OPCODE_COMMON_MCC_CREATE_EXT);
812
813 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
814 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
815
816 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
817 if (lancer_chip(adapter)) {
818 req->hdr.version = 1;
819 req->cq_id = cpu_to_le16(cq->id);
820
821 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
822 be_encoded_q_len(mccq->len));
823 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
824 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
825 ctxt, cq->id);
826 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
827 ctxt, 1);
828
829 } else {
830 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
831 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
832 be_encoded_q_len(mccq->len));
833 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
834 }
835
836 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
837 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
838 be_dws_cpu_to_le(ctxt, sizeof(req->context));
839
840 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
841
842 status = be_mbox_notify_wait(adapter);
843 if (!status) {
844 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
845 mccq->id = le16_to_cpu(resp->id);
846 mccq->created = true;
847 }
848 mutex_unlock(&adapter->mbox_lock);
849
850 return status;
851 }
852
853 int be_cmd_txq_create(struct be_adapter *adapter,
854 struct be_queue_info *txq,
855 struct be_queue_info *cq)
856 {
857 struct be_mcc_wrb *wrb;
858 struct be_cmd_req_eth_tx_create *req;
859 struct be_dma_mem *q_mem = &txq->dma_mem;
860 void *ctxt;
861 int status;
862
863 if (mutex_lock_interruptible(&adapter->mbox_lock))
864 return -1;
865
866 wrb = wrb_from_mbox(adapter);
867 req = embedded_payload(wrb);
868 ctxt = &req->context;
869
870 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
871 OPCODE_ETH_TX_CREATE);
872
873 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
874 sizeof(*req));
875
876 if (lancer_chip(adapter)) {
877 req->hdr.version = 1;
878 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
879 adapter->if_handle);
880 }
881
882 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
883 req->ulp_num = BE_ULP1_NUM;
884 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
885
886 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
887 be_encoded_q_len(txq->len));
888 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
889 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
890
891 be_dws_cpu_to_le(ctxt, sizeof(req->context));
892
893 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
894
895 status = be_mbox_notify_wait(adapter);
896 if (!status) {
897 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
898 txq->id = le16_to_cpu(resp->cid);
899 txq->created = true;
900 }
901
902 mutex_unlock(&adapter->mbox_lock);
903
904 return status;
905 }
906
907 /* Uses mbox */
908 int be_cmd_rxq_create(struct be_adapter *adapter,
909 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
910 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
911 {
912 struct be_mcc_wrb *wrb;
913 struct be_cmd_req_eth_rx_create *req;
914 struct be_dma_mem *q_mem = &rxq->dma_mem;
915 int status;
916
917 if (mutex_lock_interruptible(&adapter->mbox_lock))
918 return -1;
919
920 wrb = wrb_from_mbox(adapter);
921 req = embedded_payload(wrb);
922
923 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
924 OPCODE_ETH_RX_CREATE);
925
926 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
927 sizeof(*req));
928
929 req->cq_id = cpu_to_le16(cq_id);
930 req->frag_size = fls(frag_size) - 1;
931 req->num_pages = 2;
932 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
933 req->interface_id = cpu_to_le32(if_id);
934 req->max_frame_size = cpu_to_le16(max_frame_size);
935 req->rss_queue = cpu_to_le32(rss);
936
937 status = be_mbox_notify_wait(adapter);
938 if (!status) {
939 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
940 rxq->id = le16_to_cpu(resp->id);
941 rxq->created = true;
942 *rss_id = resp->rss_id;
943 }
944
945 mutex_unlock(&adapter->mbox_lock);
946
947 return status;
948 }
949
950 /* Generic destroyer function for all types of queues
951 * Uses Mbox
952 */
953 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
954 int queue_type)
955 {
956 struct be_mcc_wrb *wrb;
957 struct be_cmd_req_q_destroy *req;
958 u8 subsys = 0, opcode = 0;
959 int status;
960
961 if (adapter->eeh_err)
962 return -EIO;
963
964 if (mutex_lock_interruptible(&adapter->mbox_lock))
965 return -1;
966
967 wrb = wrb_from_mbox(adapter);
968 req = embedded_payload(wrb);
969
970 switch (queue_type) {
971 case QTYPE_EQ:
972 subsys = CMD_SUBSYSTEM_COMMON;
973 opcode = OPCODE_COMMON_EQ_DESTROY;
974 break;
975 case QTYPE_CQ:
976 subsys = CMD_SUBSYSTEM_COMMON;
977 opcode = OPCODE_COMMON_CQ_DESTROY;
978 break;
979 case QTYPE_TXQ:
980 subsys = CMD_SUBSYSTEM_ETH;
981 opcode = OPCODE_ETH_TX_DESTROY;
982 break;
983 case QTYPE_RXQ:
984 subsys = CMD_SUBSYSTEM_ETH;
985 opcode = OPCODE_ETH_RX_DESTROY;
986 break;
987 case QTYPE_MCCQ:
988 subsys = CMD_SUBSYSTEM_COMMON;
989 opcode = OPCODE_COMMON_MCC_DESTROY;
990 break;
991 default:
992 BUG();
993 }
994
995 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
996
997 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
998 req->id = cpu_to_le16(q->id);
999
1000 status = be_mbox_notify_wait(adapter);
1001
1002 mutex_unlock(&adapter->mbox_lock);
1003
1004 return status;
1005 }
1006
1007 /* Create an rx filtering policy configuration on an i/f
1008 * Uses mbox
1009 */
1010 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1011 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1012 u32 domain)
1013 {
1014 struct be_mcc_wrb *wrb;
1015 struct be_cmd_req_if_create *req;
1016 int status;
1017
1018 if (mutex_lock_interruptible(&adapter->mbox_lock))
1019 return -1;
1020
1021 wrb = wrb_from_mbox(adapter);
1022 req = embedded_payload(wrb);
1023
1024 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1025 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1026
1027 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1028 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1029
1030 req->hdr.domain = domain;
1031 req->capability_flags = cpu_to_le32(cap_flags);
1032 req->enable_flags = cpu_to_le32(en_flags);
1033 req->pmac_invalid = pmac_invalid;
1034 if (!pmac_invalid)
1035 memcpy(req->mac_addr, mac, ETH_ALEN);
1036
1037 status = be_mbox_notify_wait(adapter);
1038 if (!status) {
1039 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1040 *if_handle = le32_to_cpu(resp->interface_id);
1041 if (!pmac_invalid)
1042 *pmac_id = le32_to_cpu(resp->pmac_id);
1043 }
1044
1045 mutex_unlock(&adapter->mbox_lock);
1046 return status;
1047 }
1048
1049 /* Uses mbox */
1050 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1051 {
1052 struct be_mcc_wrb *wrb;
1053 struct be_cmd_req_if_destroy *req;
1054 int status;
1055
1056 if (adapter->eeh_err)
1057 return -EIO;
1058
1059 if (mutex_lock_interruptible(&adapter->mbox_lock))
1060 return -1;
1061
1062 wrb = wrb_from_mbox(adapter);
1063 req = embedded_payload(wrb);
1064
1065 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1066 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1067
1068 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1069 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1070
1071 req->hdr.domain = domain;
1072 req->interface_id = cpu_to_le32(interface_id);
1073
1074 status = be_mbox_notify_wait(adapter);
1075
1076 mutex_unlock(&adapter->mbox_lock);
1077
1078 return status;
1079 }
1080
1081 /* Get stats is a non embedded command: the request is not embedded inside
1082 * WRB but is a separate dma memory block
1083 * Uses asynchronous MCC
1084 */
1085 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1086 {
1087 struct be_mcc_wrb *wrb;
1088 struct be_cmd_req_hdr *hdr;
1089 struct be_sge *sge;
1090 int status = 0;
1091
1092 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1093 be_cmd_get_die_temperature(adapter);
1094
1095 spin_lock_bh(&adapter->mcc_lock);
1096
1097 wrb = wrb_from_mccq(adapter);
1098 if (!wrb) {
1099 status = -EBUSY;
1100 goto err;
1101 }
1102 hdr = nonemb_cmd->va;
1103 sge = nonembedded_sgl(wrb);
1104
1105 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1106 OPCODE_ETH_GET_STATISTICS);
1107
1108 be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1109 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1110
1111 if (adapter->generation == BE_GEN3)
1112 hdr->version = 1;
1113
1114 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1115 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1116 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1117 sge->len = cpu_to_le32(nonemb_cmd->size);
1118
1119 be_mcc_notify(adapter);
1120 adapter->stats_cmd_sent = true;
1121
1122 err:
1123 spin_unlock_bh(&adapter->mcc_lock);
1124 return status;
1125 }
1126
1127 /* Uses synchronous mcc */
1128 int be_cmd_link_status_query(struct be_adapter *adapter,
1129 bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
1130 {
1131 struct be_mcc_wrb *wrb;
1132 struct be_cmd_req_link_status *req;
1133 int status;
1134
1135 spin_lock_bh(&adapter->mcc_lock);
1136
1137 wrb = wrb_from_mccq(adapter);
1138 if (!wrb) {
1139 status = -EBUSY;
1140 goto err;
1141 }
1142 req = embedded_payload(wrb);
1143
1144 *link_up = false;
1145
1146 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1147 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1148
1149 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1150 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1151
1152 status = be_mcc_notify_wait(adapter);
1153 if (!status) {
1154 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1155 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1156 *link_up = true;
1157 *link_speed = le16_to_cpu(resp->link_speed);
1158 *mac_speed = resp->mac_speed;
1159 }
1160 }
1161
1162 err:
1163 spin_unlock_bh(&adapter->mcc_lock);
1164 return status;
1165 }
1166
1167 /* Uses synchronous mcc */
1168 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1169 {
1170 struct be_mcc_wrb *wrb;
1171 struct be_cmd_req_get_cntl_addnl_attribs *req;
1172 int status;
1173
1174 spin_lock_bh(&adapter->mcc_lock);
1175
1176 wrb = wrb_from_mccq(adapter);
1177 if (!wrb) {
1178 status = -EBUSY;
1179 goto err;
1180 }
1181 req = embedded_payload(wrb);
1182
1183 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1184 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1185
1186 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1187 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1188
1189 status = be_mcc_notify_wait(adapter);
1190 if (!status) {
1191 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1192 embedded_payload(wrb);
1193 adapter->drv_stats.be_on_die_temperature =
1194 resp->on_die_temperature;
1195 }
1196 /* If IOCTL fails once, do not bother issuing it again */
1197 else
1198 be_get_temp_freq = 0;
1199
1200 err:
1201 spin_unlock_bh(&adapter->mcc_lock);
1202 return status;
1203 }
1204
1205 /* Uses synchronous mcc */
1206 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1207 {
1208 struct be_mcc_wrb *wrb;
1209 struct be_cmd_req_get_fat *req;
1210 int status;
1211
1212 spin_lock_bh(&adapter->mcc_lock);
1213
1214 wrb = wrb_from_mccq(adapter);
1215 if (!wrb) {
1216 status = -EBUSY;
1217 goto err;
1218 }
1219 req = embedded_payload(wrb);
1220
1221 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1222 OPCODE_COMMON_MANAGE_FAT);
1223
1224 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1225 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1226 req->fat_operation = cpu_to_le32(QUERY_FAT);
1227 status = be_mcc_notify_wait(adapter);
1228 if (!status) {
1229 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1230 if (log_size && resp->log_size)
1231 *log_size = le32_to_cpu(resp->log_size) -
1232 sizeof(u32);
1233 }
1234 err:
1235 spin_unlock_bh(&adapter->mcc_lock);
1236 return status;
1237 }
1238
1239 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1240 {
1241 struct be_dma_mem get_fat_cmd;
1242 struct be_mcc_wrb *wrb;
1243 struct be_cmd_req_get_fat *req;
1244 struct be_sge *sge;
1245 u32 offset = 0, total_size, buf_size,
1246 log_offset = sizeof(u32), payload_len;
1247 int status;
1248
1249 if (buf_len == 0)
1250 return;
1251
1252 total_size = buf_len;
1253
1254 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1255 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1256 get_fat_cmd.size,
1257 &get_fat_cmd.dma);
1258 if (!get_fat_cmd.va) {
1259 status = -ENOMEM;
1260 dev_err(&adapter->pdev->dev,
1261 "Memory allocation failure while retrieving FAT data\n");
1262 return;
1263 }
1264
1265 spin_lock_bh(&adapter->mcc_lock);
1266
1267 while (total_size) {
1268 buf_size = min(total_size, (u32)60*1024);
1269 total_size -= buf_size;
1270
1271 wrb = wrb_from_mccq(adapter);
1272 if (!wrb) {
1273 status = -EBUSY;
1274 goto err;
1275 }
1276 req = get_fat_cmd.va;
1277 sge = nonembedded_sgl(wrb);
1278
1279 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1280 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1281 OPCODE_COMMON_MANAGE_FAT);
1282
1283 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1284 OPCODE_COMMON_MANAGE_FAT, payload_len);
1285
1286 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1287 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1288 sge->len = cpu_to_le32(get_fat_cmd.size);
1289
1290 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1291 req->read_log_offset = cpu_to_le32(log_offset);
1292 req->read_log_length = cpu_to_le32(buf_size);
1293 req->data_buffer_size = cpu_to_le32(buf_size);
1294
1295 status = be_mcc_notify_wait(adapter);
1296 if (!status) {
1297 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1298 memcpy(buf + offset,
1299 resp->data_buffer,
1300 resp->read_log_length);
1301 } else {
1302 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1303 goto err;
1304 }
1305 offset += buf_size;
1306 log_offset += buf_size;
1307 }
1308 err:
1309 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1310 get_fat_cmd.va,
1311 get_fat_cmd.dma);
1312 spin_unlock_bh(&adapter->mcc_lock);
1313 }
1314
1315 /* Uses Mbox */
1316 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1317 {
1318 struct be_mcc_wrb *wrb;
1319 struct be_cmd_req_get_fw_version *req;
1320 int status;
1321
1322 if (mutex_lock_interruptible(&adapter->mbox_lock))
1323 return -1;
1324
1325 wrb = wrb_from_mbox(adapter);
1326 req = embedded_payload(wrb);
1327
1328 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1329 OPCODE_COMMON_GET_FW_VERSION);
1330
1331 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1332 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1333
1334 status = be_mbox_notify_wait(adapter);
1335 if (!status) {
1336 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1337 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1338 }
1339
1340 mutex_unlock(&adapter->mbox_lock);
1341 return status;
1342 }
1343
1344 /* set the EQ delay interval of an EQ to specified value
1345 * Uses async mcc
1346 */
1347 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1348 {
1349 struct be_mcc_wrb *wrb;
1350 struct be_cmd_req_modify_eq_delay *req;
1351 int status = 0;
1352
1353 spin_lock_bh(&adapter->mcc_lock);
1354
1355 wrb = wrb_from_mccq(adapter);
1356 if (!wrb) {
1357 status = -EBUSY;
1358 goto err;
1359 }
1360 req = embedded_payload(wrb);
1361
1362 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1363 OPCODE_COMMON_MODIFY_EQ_DELAY);
1364
1365 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1366 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1367
1368 req->num_eq = cpu_to_le32(1);
1369 req->delay[0].eq_id = cpu_to_le32(eq_id);
1370 req->delay[0].phase = 0;
1371 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1372
1373 be_mcc_notify(adapter);
1374
1375 err:
1376 spin_unlock_bh(&adapter->mcc_lock);
1377 return status;
1378 }
1379
1380 /* Uses sycnhronous mcc */
1381 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1382 u32 num, bool untagged, bool promiscuous)
1383 {
1384 struct be_mcc_wrb *wrb;
1385 struct be_cmd_req_vlan_config *req;
1386 int status;
1387
1388 spin_lock_bh(&adapter->mcc_lock);
1389
1390 wrb = wrb_from_mccq(adapter);
1391 if (!wrb) {
1392 status = -EBUSY;
1393 goto err;
1394 }
1395 req = embedded_payload(wrb);
1396
1397 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1398 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1399
1400 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1401 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1402
1403 req->interface_id = if_id;
1404 req->promiscuous = promiscuous;
1405 req->untagged = untagged;
1406 req->num_vlan = num;
1407 if (!promiscuous) {
1408 memcpy(req->normal_vlan, vtag_array,
1409 req->num_vlan * sizeof(vtag_array[0]));
1410 }
1411
1412 status = be_mcc_notify_wait(adapter);
1413
1414 err:
1415 spin_unlock_bh(&adapter->mcc_lock);
1416 return status;
1417 }
1418
1419 /* Uses MCC for this command as it may be called in BH context
1420 * Uses synchronous mcc
1421 */
1422 int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
1423 {
1424 struct be_mcc_wrb *wrb;
1425 struct be_cmd_req_rx_filter *req;
1426 struct be_dma_mem promiscous_cmd;
1427 struct be_sge *sge;
1428 int status;
1429
1430 memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
1431 promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
1432 promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
1433 promiscous_cmd.size, &promiscous_cmd.dma);
1434 if (!promiscous_cmd.va) {
1435 dev_err(&adapter->pdev->dev,
1436 "Memory allocation failure\n");
1437 return -ENOMEM;
1438 }
1439
1440 spin_lock_bh(&adapter->mcc_lock);
1441
1442 wrb = wrb_from_mccq(adapter);
1443 if (!wrb) {
1444 status = -EBUSY;
1445 goto err;
1446 }
1447
1448 req = promiscous_cmd.va;
1449 sge = nonembedded_sgl(wrb);
1450
1451 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1452 OPCODE_COMMON_NTWK_RX_FILTER);
1453 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1454 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1455
1456 req->if_id = cpu_to_le32(adapter->if_handle);
1457 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1458 if (en)
1459 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1460
1461 sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
1462 sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
1463 sge->len = cpu_to_le32(promiscous_cmd.size);
1464
1465 status = be_mcc_notify_wait(adapter);
1466
1467 err:
1468 spin_unlock_bh(&adapter->mcc_lock);
1469 pci_free_consistent(adapter->pdev, promiscous_cmd.size,
1470 promiscous_cmd.va, promiscous_cmd.dma);
1471 return status;
1472 }
1473
1474 /*
1475 * Uses MCC for this command as it may be called in BH context
1476 * (mc == NULL) => multicast promiscuous
1477 */
1478 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1479 struct net_device *netdev, struct be_dma_mem *mem)
1480 {
1481 struct be_mcc_wrb *wrb;
1482 struct be_cmd_req_mcast_mac_config *req = mem->va;
1483 struct be_sge *sge;
1484 int status;
1485
1486 spin_lock_bh(&adapter->mcc_lock);
1487
1488 wrb = wrb_from_mccq(adapter);
1489 if (!wrb) {
1490 status = -EBUSY;
1491 goto err;
1492 }
1493 sge = nonembedded_sgl(wrb);
1494 memset(req, 0, sizeof(*req));
1495
1496 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1497 OPCODE_COMMON_NTWK_MULTICAST_SET);
1498 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1499 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1500 sge->len = cpu_to_le32(mem->size);
1501
1502 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1503 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1504
1505 req->interface_id = if_id;
1506 if (netdev) {
1507 int i;
1508 struct netdev_hw_addr *ha;
1509
1510 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1511
1512 i = 0;
1513 netdev_for_each_mc_addr(ha, netdev)
1514 memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1515 } else {
1516 req->promiscuous = 1;
1517 }
1518
1519 status = be_mcc_notify_wait(adapter);
1520
1521 err:
1522 spin_unlock_bh(&adapter->mcc_lock);
1523 return status;
1524 }
1525
1526 /* Uses synchrounous mcc */
1527 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1528 {
1529 struct be_mcc_wrb *wrb;
1530 struct be_cmd_req_set_flow_control *req;
1531 int status;
1532
1533 spin_lock_bh(&adapter->mcc_lock);
1534
1535 wrb = wrb_from_mccq(adapter);
1536 if (!wrb) {
1537 status = -EBUSY;
1538 goto err;
1539 }
1540 req = embedded_payload(wrb);
1541
1542 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1543 OPCODE_COMMON_SET_FLOW_CONTROL);
1544
1545 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1546 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1547
1548 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1549 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1550
1551 status = be_mcc_notify_wait(adapter);
1552
1553 err:
1554 spin_unlock_bh(&adapter->mcc_lock);
1555 return status;
1556 }
1557
1558 /* Uses sycn mcc */
1559 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1560 {
1561 struct be_mcc_wrb *wrb;
1562 struct be_cmd_req_get_flow_control *req;
1563 int status;
1564
1565 spin_lock_bh(&adapter->mcc_lock);
1566
1567 wrb = wrb_from_mccq(adapter);
1568 if (!wrb) {
1569 status = -EBUSY;
1570 goto err;
1571 }
1572 req = embedded_payload(wrb);
1573
1574 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1575 OPCODE_COMMON_GET_FLOW_CONTROL);
1576
1577 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1578 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1579
1580 status = be_mcc_notify_wait(adapter);
1581 if (!status) {
1582 struct be_cmd_resp_get_flow_control *resp =
1583 embedded_payload(wrb);
1584 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1585 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1586 }
1587
1588 err:
1589 spin_unlock_bh(&adapter->mcc_lock);
1590 return status;
1591 }
1592
1593 /* Uses mbox */
1594 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1595 u32 *mode, u32 *caps)
1596 {
1597 struct be_mcc_wrb *wrb;
1598 struct be_cmd_req_query_fw_cfg *req;
1599 int status;
1600
1601 if (mutex_lock_interruptible(&adapter->mbox_lock))
1602 return -1;
1603
1604 wrb = wrb_from_mbox(adapter);
1605 req = embedded_payload(wrb);
1606
1607 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1608 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1609
1610 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1611 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1612
1613 status = be_mbox_notify_wait(adapter);
1614 if (!status) {
1615 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1616 *port_num = le32_to_cpu(resp->phys_port);
1617 *mode = le32_to_cpu(resp->function_mode);
1618 *caps = le32_to_cpu(resp->function_caps);
1619 }
1620
1621 mutex_unlock(&adapter->mbox_lock);
1622 return status;
1623 }
1624
1625 /* Uses mbox */
1626 int be_cmd_reset_function(struct be_adapter *adapter)
1627 {
1628 struct be_mcc_wrb *wrb;
1629 struct be_cmd_req_hdr *req;
1630 int status;
1631
1632 if (mutex_lock_interruptible(&adapter->mbox_lock))
1633 return -1;
1634
1635 wrb = wrb_from_mbox(adapter);
1636 req = embedded_payload(wrb);
1637
1638 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1639 OPCODE_COMMON_FUNCTION_RESET);
1640
1641 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1642 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1643
1644 status = be_mbox_notify_wait(adapter);
1645
1646 mutex_unlock(&adapter->mbox_lock);
1647 return status;
1648 }
1649
1650 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1651 {
1652 struct be_mcc_wrb *wrb;
1653 struct be_cmd_req_rss_config *req;
1654 u32 myhash[10];
1655 int status;
1656
1657 if (mutex_lock_interruptible(&adapter->mbox_lock))
1658 return -1;
1659
1660 wrb = wrb_from_mbox(adapter);
1661 req = embedded_payload(wrb);
1662
1663 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1664 OPCODE_ETH_RSS_CONFIG);
1665
1666 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1667 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1668
1669 req->if_id = cpu_to_le32(adapter->if_handle);
1670 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1671 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1672 memcpy(req->cpu_table, rsstable, table_size);
1673 memcpy(req->hash, myhash, sizeof(myhash));
1674 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1675
1676 status = be_mbox_notify_wait(adapter);
1677
1678 mutex_unlock(&adapter->mbox_lock);
1679 return status;
1680 }
1681
1682 /* Uses sync mcc */
1683 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1684 u8 bcn, u8 sts, u8 state)
1685 {
1686 struct be_mcc_wrb *wrb;
1687 struct be_cmd_req_enable_disable_beacon *req;
1688 int status;
1689
1690 spin_lock_bh(&adapter->mcc_lock);
1691
1692 wrb = wrb_from_mccq(adapter);
1693 if (!wrb) {
1694 status = -EBUSY;
1695 goto err;
1696 }
1697 req = embedded_payload(wrb);
1698
1699 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1700 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1701
1702 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1703 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1704
1705 req->port_num = port_num;
1706 req->beacon_state = state;
1707 req->beacon_duration = bcn;
1708 req->status_duration = sts;
1709
1710 status = be_mcc_notify_wait(adapter);
1711
1712 err:
1713 spin_unlock_bh(&adapter->mcc_lock);
1714 return status;
1715 }
1716
1717 /* Uses sync mcc */
1718 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1719 {
1720 struct be_mcc_wrb *wrb;
1721 struct be_cmd_req_get_beacon_state *req;
1722 int status;
1723
1724 spin_lock_bh(&adapter->mcc_lock);
1725
1726 wrb = wrb_from_mccq(adapter);
1727 if (!wrb) {
1728 status = -EBUSY;
1729 goto err;
1730 }
1731 req = embedded_payload(wrb);
1732
1733 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1734 OPCODE_COMMON_GET_BEACON_STATE);
1735
1736 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1737 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1738
1739 req->port_num = port_num;
1740
1741 status = be_mcc_notify_wait(adapter);
1742 if (!status) {
1743 struct be_cmd_resp_get_beacon_state *resp =
1744 embedded_payload(wrb);
1745 *state = resp->beacon_state;
1746 }
1747
1748 err:
1749 spin_unlock_bh(&adapter->mcc_lock);
1750 return status;
1751 }
1752
1753 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1754 u32 flash_type, u32 flash_opcode, u32 buf_size)
1755 {
1756 struct be_mcc_wrb *wrb;
1757 struct be_cmd_write_flashrom *req;
1758 struct be_sge *sge;
1759 int status;
1760
1761 spin_lock_bh(&adapter->mcc_lock);
1762 adapter->flash_status = 0;
1763
1764 wrb = wrb_from_mccq(adapter);
1765 if (!wrb) {
1766 status = -EBUSY;
1767 goto err_unlock;
1768 }
1769 req = cmd->va;
1770 sge = nonembedded_sgl(wrb);
1771
1772 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1773 OPCODE_COMMON_WRITE_FLASHROM);
1774 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1775
1776 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1777 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1778 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1779 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1780 sge->len = cpu_to_le32(cmd->size);
1781
1782 req->params.op_type = cpu_to_le32(flash_type);
1783 req->params.op_code = cpu_to_le32(flash_opcode);
1784 req->params.data_buf_size = cpu_to_le32(buf_size);
1785
1786 be_mcc_notify(adapter);
1787 spin_unlock_bh(&adapter->mcc_lock);
1788
1789 if (!wait_for_completion_timeout(&adapter->flash_compl,
1790 msecs_to_jiffies(12000)))
1791 status = -1;
1792 else
1793 status = adapter->flash_status;
1794
1795 return status;
1796
1797 err_unlock:
1798 spin_unlock_bh(&adapter->mcc_lock);
1799 return status;
1800 }
1801
1802 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1803 int offset)
1804 {
1805 struct be_mcc_wrb *wrb;
1806 struct be_cmd_write_flashrom *req;
1807 int status;
1808
1809 spin_lock_bh(&adapter->mcc_lock);
1810
1811 wrb = wrb_from_mccq(adapter);
1812 if (!wrb) {
1813 status = -EBUSY;
1814 goto err;
1815 }
1816 req = embedded_payload(wrb);
1817
1818 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1819 OPCODE_COMMON_READ_FLASHROM);
1820
1821 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1822 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1823
1824 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1825 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1826 req->params.offset = cpu_to_le32(offset);
1827 req->params.data_buf_size = cpu_to_le32(0x4);
1828
1829 status = be_mcc_notify_wait(adapter);
1830 if (!status)
1831 memcpy(flashed_crc, req->params.data_buf, 4);
1832
1833 err:
1834 spin_unlock_bh(&adapter->mcc_lock);
1835 return status;
1836 }
1837
1838 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1839 struct be_dma_mem *nonemb_cmd)
1840 {
1841 struct be_mcc_wrb *wrb;
1842 struct be_cmd_req_acpi_wol_magic_config *req;
1843 struct be_sge *sge;
1844 int status;
1845
1846 spin_lock_bh(&adapter->mcc_lock);
1847
1848 wrb = wrb_from_mccq(adapter);
1849 if (!wrb) {
1850 status = -EBUSY;
1851 goto err;
1852 }
1853 req = nonemb_cmd->va;
1854 sge = nonembedded_sgl(wrb);
1855
1856 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1857 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1858
1859 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1860 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1861 memcpy(req->magic_mac, mac, ETH_ALEN);
1862
1863 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1864 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1865 sge->len = cpu_to_le32(nonemb_cmd->size);
1866
1867 status = be_mcc_notify_wait(adapter);
1868
1869 err:
1870 spin_unlock_bh(&adapter->mcc_lock);
1871 return status;
1872 }
1873
1874 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1875 u8 loopback_type, u8 enable)
1876 {
1877 struct be_mcc_wrb *wrb;
1878 struct be_cmd_req_set_lmode *req;
1879 int status;
1880
1881 spin_lock_bh(&adapter->mcc_lock);
1882
1883 wrb = wrb_from_mccq(adapter);
1884 if (!wrb) {
1885 status = -EBUSY;
1886 goto err;
1887 }
1888
1889 req = embedded_payload(wrb);
1890
1891 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1892 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1893
1894 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1895 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1896 sizeof(*req));
1897
1898 req->src_port = port_num;
1899 req->dest_port = port_num;
1900 req->loopback_type = loopback_type;
1901 req->loopback_state = enable;
1902
1903 status = be_mcc_notify_wait(adapter);
1904 err:
1905 spin_unlock_bh(&adapter->mcc_lock);
1906 return status;
1907 }
1908
1909 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1910 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1911 {
1912 struct be_mcc_wrb *wrb;
1913 struct be_cmd_req_loopback_test *req;
1914 int status;
1915
1916 spin_lock_bh(&adapter->mcc_lock);
1917
1918 wrb = wrb_from_mccq(adapter);
1919 if (!wrb) {
1920 status = -EBUSY;
1921 goto err;
1922 }
1923
1924 req = embedded_payload(wrb);
1925
1926 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1927 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1928
1929 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1930 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1931 req->hdr.timeout = cpu_to_le32(4);
1932
1933 req->pattern = cpu_to_le64(pattern);
1934 req->src_port = cpu_to_le32(port_num);
1935 req->dest_port = cpu_to_le32(port_num);
1936 req->pkt_size = cpu_to_le32(pkt_size);
1937 req->num_pkts = cpu_to_le32(num_pkts);
1938 req->loopback_type = cpu_to_le32(loopback_type);
1939
1940 status = be_mcc_notify_wait(adapter);
1941 if (!status) {
1942 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1943 status = le32_to_cpu(resp->status);
1944 }
1945
1946 err:
1947 spin_unlock_bh(&adapter->mcc_lock);
1948 return status;
1949 }
1950
1951 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1952 u32 byte_cnt, struct be_dma_mem *cmd)
1953 {
1954 struct be_mcc_wrb *wrb;
1955 struct be_cmd_req_ddrdma_test *req;
1956 struct be_sge *sge;
1957 int status;
1958 int i, j = 0;
1959
1960 spin_lock_bh(&adapter->mcc_lock);
1961
1962 wrb = wrb_from_mccq(adapter);
1963 if (!wrb) {
1964 status = -EBUSY;
1965 goto err;
1966 }
1967 req = cmd->va;
1968 sge = nonembedded_sgl(wrb);
1969 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1970 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1971 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1972 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1973
1974 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1975 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1976 sge->len = cpu_to_le32(cmd->size);
1977
1978 req->pattern = cpu_to_le64(pattern);
1979 req->byte_count = cpu_to_le32(byte_cnt);
1980 for (i = 0; i < byte_cnt; i++) {
1981 req->snd_buff[i] = (u8)(pattern >> (j*8));
1982 j++;
1983 if (j > 7)
1984 j = 0;
1985 }
1986
1987 status = be_mcc_notify_wait(adapter);
1988
1989 if (!status) {
1990 struct be_cmd_resp_ddrdma_test *resp;
1991 resp = cmd->va;
1992 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1993 resp->snd_err) {
1994 status = -1;
1995 }
1996 }
1997
1998 err:
1999 spin_unlock_bh(&adapter->mcc_lock);
2000 return status;
2001 }
2002
2003 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2004 struct be_dma_mem *nonemb_cmd)
2005 {
2006 struct be_mcc_wrb *wrb;
2007 struct be_cmd_req_seeprom_read *req;
2008 struct be_sge *sge;
2009 int status;
2010
2011 spin_lock_bh(&adapter->mcc_lock);
2012
2013 wrb = wrb_from_mccq(adapter);
2014 if (!wrb) {
2015 status = -EBUSY;
2016 goto err;
2017 }
2018 req = nonemb_cmd->va;
2019 sge = nonembedded_sgl(wrb);
2020
2021 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2022 OPCODE_COMMON_SEEPROM_READ);
2023
2024 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2025 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2026
2027 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2028 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2029 sge->len = cpu_to_le32(nonemb_cmd->size);
2030
2031 status = be_mcc_notify_wait(adapter);
2032
2033 err:
2034 spin_unlock_bh(&adapter->mcc_lock);
2035 return status;
2036 }
2037
2038 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2039 {
2040 struct be_mcc_wrb *wrb;
2041 struct be_cmd_req_get_phy_info *req;
2042 struct be_sge *sge;
2043 int status;
2044
2045 spin_lock_bh(&adapter->mcc_lock);
2046
2047 wrb = wrb_from_mccq(adapter);
2048 if (!wrb) {
2049 status = -EBUSY;
2050 goto err;
2051 }
2052
2053 req = cmd->va;
2054 sge = nonembedded_sgl(wrb);
2055
2056 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2057 OPCODE_COMMON_GET_PHY_DETAILS);
2058
2059 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2060 OPCODE_COMMON_GET_PHY_DETAILS,
2061 sizeof(*req));
2062
2063 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2064 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2065 sge->len = cpu_to_le32(cmd->size);
2066
2067 status = be_mcc_notify_wait(adapter);
2068 err:
2069 spin_unlock_bh(&adapter->mcc_lock);
2070 return status;
2071 }
2072
2073 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2074 {
2075 struct be_mcc_wrb *wrb;
2076 struct be_cmd_req_set_qos *req;
2077 int status;
2078
2079 spin_lock_bh(&adapter->mcc_lock);
2080
2081 wrb = wrb_from_mccq(adapter);
2082 if (!wrb) {
2083 status = -EBUSY;
2084 goto err;
2085 }
2086
2087 req = embedded_payload(wrb);
2088
2089 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2090 OPCODE_COMMON_SET_QOS);
2091
2092 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2093 OPCODE_COMMON_SET_QOS, sizeof(*req));
2094
2095 req->hdr.domain = domain;
2096 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2097 req->max_bps_nic = cpu_to_le32(bps);
2098
2099 status = be_mcc_notify_wait(adapter);
2100
2101 err:
2102 spin_unlock_bh(&adapter->mcc_lock);
2103 return status;
2104 }
2105
2106 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2107 {
2108 struct be_mcc_wrb *wrb;
2109 struct be_cmd_req_cntl_attribs *req;
2110 struct be_cmd_resp_cntl_attribs *resp;
2111 struct be_sge *sge;
2112 int status;
2113 int payload_len = max(sizeof(*req), sizeof(*resp));
2114 struct mgmt_controller_attrib *attribs;
2115 struct be_dma_mem attribs_cmd;
2116
2117 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2118 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2119 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2120 &attribs_cmd.dma);
2121 if (!attribs_cmd.va) {
2122 dev_err(&adapter->pdev->dev,
2123 "Memory allocation failure\n");
2124 return -ENOMEM;
2125 }
2126
2127 if (mutex_lock_interruptible(&adapter->mbox_lock))
2128 return -1;
2129
2130 wrb = wrb_from_mbox(adapter);
2131 if (!wrb) {
2132 status = -EBUSY;
2133 goto err;
2134 }
2135 req = attribs_cmd.va;
2136 sge = nonembedded_sgl(wrb);
2137
2138 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2139 OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2140 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2141 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2142 sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2143 sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2144 sge->len = cpu_to_le32(attribs_cmd.size);
2145
2146 status = be_mbox_notify_wait(adapter);
2147 if (!status) {
2148 attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
2149 sizeof(struct be_cmd_resp_hdr));
2150 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2151 }
2152
2153 err:
2154 mutex_unlock(&adapter->mbox_lock);
2155 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2156 attribs_cmd.dma);
2157 return status;
2158 }
2159
2160 /* Uses mbox */
2161 int be_cmd_check_native_mode(struct be_adapter *adapter)
2162 {
2163 struct be_mcc_wrb *wrb;
2164 struct be_cmd_req_set_func_cap *req;
2165 int status;
2166
2167 if (mutex_lock_interruptible(&adapter->mbox_lock))
2168 return -1;
2169
2170 wrb = wrb_from_mbox(adapter);
2171 if (!wrb) {
2172 status = -EBUSY;
2173 goto err;
2174 }
2175
2176 req = embedded_payload(wrb);
2177
2178 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2179 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2180
2181 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2182 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2183
2184 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2185 CAPABILITY_BE3_NATIVE_ERX_API);
2186 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2187
2188 status = be_mbox_notify_wait(adapter);
2189 if (!status) {
2190 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2191 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2192 CAPABILITY_BE3_NATIVE_ERX_API;
2193 }
2194 err:
2195 mutex_unlock(&adapter->mbox_lock);
2196 return status;
2197 }
Linux kernel - Deliverables
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