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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / benet / be_cmds.c
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 32;
23
24 static void be_mcc_notify(struct be_adapter *adapter)
25 {
26 struct be_queue_info *mccq = &adapter->mcc_obj.q;
27 u32 val = 0;
28
29 if (adapter->eeh_err) {
30 dev_info(&adapter->pdev->dev,
31 "Error in Card Detected! Cannot issue commands\n");
32 return;
33 }
34
35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
37
38 wmb();
39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
40 }
41
42 /* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
46 {
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54 }
55
56 /* Need to reset the entire word that houses the valid bit */
57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
58 {
59 compl->flags = 0;
60 }
61
62 static int be_mcc_compl_process(struct be_adapter *adapter,
63 struct be_mcc_compl *compl)
64 {
65 u16 compl_status, extd_status;
66
67 /* Just swap the status to host endian; mcc tag is opaquely copied
68 * from mcc_wrb */
69 be_dws_le_to_cpu(compl, 4);
70
71 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
72 CQE_STATUS_COMPL_MASK;
73
74 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
75 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
76 adapter->flash_status = compl_status;
77 complete(&adapter->flash_compl);
78 }
79
80 if (compl_status == MCC_STATUS_SUCCESS) {
81 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
82 struct be_cmd_resp_get_stats *resp =
83 adapter->stats_cmd.va;
84 be_dws_le_to_cpu(&resp->hw_stats,
85 sizeof(resp->hw_stats));
86 netdev_stats_update(adapter);
87 adapter->stats_cmd_sent = false;
88 }
89 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
90 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
91 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
92 CQE_STATUS_EXTD_MASK;
93 dev_warn(&adapter->pdev->dev,
94 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
95 compl->tag0, compl_status, extd_status);
96 }
97 return compl_status;
98 }
99
100 /* Link state evt is a string of bytes; no need for endian swapping */
101 static void be_async_link_state_process(struct be_adapter *adapter,
102 struct be_async_event_link_state *evt)
103 {
104 be_link_status_update(adapter,
105 evt->port_link_status == ASYNC_EVENT_LINK_UP);
106 }
107
108 /* Grp5 CoS Priority evt */
109 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
110 struct be_async_event_grp5_cos_priority *evt)
111 {
112 if (evt->valid) {
113 adapter->vlan_prio_bmap = evt->available_priority_bmap;
114 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
115 adapter->recommended_prio =
116 evt->reco_default_priority << VLAN_PRIO_SHIFT;
117 }
118 }
119
120 /* Grp5 QOS Speed evt */
121 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
122 struct be_async_event_grp5_qos_link_speed *evt)
123 {
124 if (evt->physical_port == adapter->port_num) {
125 /* qos_link_speed is in units of 10 Mbps */
126 adapter->link_speed = evt->qos_link_speed * 10;
127 }
128 }
129
130 /*Grp5 PVID evt*/
131 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
132 struct be_async_event_grp5_pvid_state *evt)
133 {
134 if (evt->enabled)
135 adapter->pvid = evt->tag;
136 else
137 adapter->pvid = 0;
138 }
139
140 static void be_async_grp5_evt_process(struct be_adapter *adapter,
141 u32 trailer, struct be_mcc_compl *evt)
142 {
143 u8 event_type = 0;
144
145 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
146 ASYNC_TRAILER_EVENT_TYPE_MASK;
147
148 switch (event_type) {
149 case ASYNC_EVENT_COS_PRIORITY:
150 be_async_grp5_cos_priority_process(adapter,
151 (struct be_async_event_grp5_cos_priority *)evt);
152 break;
153 case ASYNC_EVENT_QOS_SPEED:
154 be_async_grp5_qos_speed_process(adapter,
155 (struct be_async_event_grp5_qos_link_speed *)evt);
156 break;
157 case ASYNC_EVENT_PVID_STATE:
158 be_async_grp5_pvid_state_process(adapter,
159 (struct be_async_event_grp5_pvid_state *)evt);
160 break;
161 default:
162 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
163 break;
164 }
165 }
166
167 static inline bool is_link_state_evt(u32 trailer)
168 {
169 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
170 ASYNC_TRAILER_EVENT_CODE_MASK) ==
171 ASYNC_EVENT_CODE_LINK_STATE;
172 }
173
174 static inline bool is_grp5_evt(u32 trailer)
175 {
176 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
177 ASYNC_TRAILER_EVENT_CODE_MASK) ==
178 ASYNC_EVENT_CODE_GRP_5);
179 }
180
181 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
182 {
183 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
184 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
185
186 if (be_mcc_compl_is_new(compl)) {
187 queue_tail_inc(mcc_cq);
188 return compl;
189 }
190 return NULL;
191 }
192
193 void be_async_mcc_enable(struct be_adapter *adapter)
194 {
195 spin_lock_bh(&adapter->mcc_cq_lock);
196
197 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
198 adapter->mcc_obj.rearm_cq = true;
199
200 spin_unlock_bh(&adapter->mcc_cq_lock);
201 }
202
203 void be_async_mcc_disable(struct be_adapter *adapter)
204 {
205 adapter->mcc_obj.rearm_cq = false;
206 }
207
208 int be_process_mcc(struct be_adapter *adapter, int *status)
209 {
210 struct be_mcc_compl *compl;
211 int num = 0;
212 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
213
214 spin_lock_bh(&adapter->mcc_cq_lock);
215 while ((compl = be_mcc_compl_get(adapter))) {
216 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
217 /* Interpret flags as an async trailer */
218 if (is_link_state_evt(compl->flags))
219 be_async_link_state_process(adapter,
220 (struct be_async_event_link_state *) compl);
221 else if (is_grp5_evt(compl->flags))
222 be_async_grp5_evt_process(adapter,
223 compl->flags, compl);
224 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
225 *status = be_mcc_compl_process(adapter, compl);
226 atomic_dec(&mcc_obj->q.used);
227 }
228 be_mcc_compl_use(compl);
229 num++;
230 }
231
232 spin_unlock_bh(&adapter->mcc_cq_lock);
233 return num;
234 }
235
236 /* Wait till no more pending mcc requests are present */
237 static int be_mcc_wait_compl(struct be_adapter *adapter)
238 {
239 #define mcc_timeout 120000 /* 12s timeout */
240 int i, num, status = 0;
241 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
242
243 if (adapter->eeh_err)
244 return -EIO;
245
246 for (i = 0; i < mcc_timeout; i++) {
247 num = be_process_mcc(adapter, &status);
248 if (num)
249 be_cq_notify(adapter, mcc_obj->cq.id,
250 mcc_obj->rearm_cq, num);
251
252 if (atomic_read(&mcc_obj->q.used) == 0)
253 break;
254 udelay(100);
255 }
256 if (i == mcc_timeout) {
257 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
258 return -1;
259 }
260 return status;
261 }
262
263 /* Notify MCC requests and wait for completion */
264 static int be_mcc_notify_wait(struct be_adapter *adapter)
265 {
266 be_mcc_notify(adapter);
267 return be_mcc_wait_compl(adapter);
268 }
269
270 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
271 {
272 int msecs = 0;
273 u32 ready;
274
275 if (adapter->eeh_err) {
276 dev_err(&adapter->pdev->dev,
277 "Error detected in card.Cannot issue commands\n");
278 return -EIO;
279 }
280
281 do {
282 ready = ioread32(db);
283 if (ready == 0xffffffff) {
284 dev_err(&adapter->pdev->dev,
285 "pci slot disconnected\n");
286 return -1;
287 }
288
289 ready &= MPU_MAILBOX_DB_RDY_MASK;
290 if (ready)
291 break;
292
293 if (msecs > 4000) {
294 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
295 be_detect_dump_ue(adapter);
296 return -1;
297 }
298
299 set_current_state(TASK_INTERRUPTIBLE);
300 schedule_timeout(msecs_to_jiffies(1));
301 msecs++;
302 } while (true);
303
304 return 0;
305 }
306
307 /*
308 * Insert the mailbox address into the doorbell in two steps
309 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
310 */
311 static int be_mbox_notify_wait(struct be_adapter *adapter)
312 {
313 int status;
314 u32 val = 0;
315 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
316 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
317 struct be_mcc_mailbox *mbox = mbox_mem->va;
318 struct be_mcc_compl *compl = &mbox->compl;
319
320 /* wait for ready to be set */
321 status = be_mbox_db_ready_wait(adapter, db);
322 if (status != 0)
323 return status;
324
325 val |= MPU_MAILBOX_DB_HI_MASK;
326 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
327 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
328 iowrite32(val, db);
329
330 /* wait for ready to be set */
331 status = be_mbox_db_ready_wait(adapter, db);
332 if (status != 0)
333 return status;
334
335 val = 0;
336 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
337 val |= (u32)(mbox_mem->dma >> 4) << 2;
338 iowrite32(val, db);
339
340 status = be_mbox_db_ready_wait(adapter, db);
341 if (status != 0)
342 return status;
343
344 /* A cq entry has been made now */
345 if (be_mcc_compl_is_new(compl)) {
346 status = be_mcc_compl_process(adapter, &mbox->compl);
347 be_mcc_compl_use(compl);
348 if (status)
349 return status;
350 } else {
351 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
352 return -1;
353 }
354 return 0;
355 }
356
357 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
358 {
359 u32 sem;
360
361 if (lancer_chip(adapter))
362 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
363 else
364 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
365
366 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
367 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
368 return -1;
369 else
370 return 0;
371 }
372
373 int be_cmd_POST(struct be_adapter *adapter)
374 {
375 u16 stage;
376 int status, timeout = 0;
377
378 do {
379 status = be_POST_stage_get(adapter, &stage);
380 if (status) {
381 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
382 stage);
383 return -1;
384 } else if (stage != POST_STAGE_ARMFW_RDY) {
385 set_current_state(TASK_INTERRUPTIBLE);
386 schedule_timeout(2 * HZ);
387 timeout += 2;
388 } else {
389 return 0;
390 }
391 } while (timeout < 40);
392
393 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
394 return -1;
395 }
396
397 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
398 {
399 return wrb->payload.embedded_payload;
400 }
401
402 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
403 {
404 return &wrb->payload.sgl[0];
405 }
406
407 /* Don't touch the hdr after it's prepared */
408 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
409 bool embedded, u8 sge_cnt, u32 opcode)
410 {
411 if (embedded)
412 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
413 else
414 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
415 MCC_WRB_SGE_CNT_SHIFT;
416 wrb->payload_length = payload_len;
417 wrb->tag0 = opcode;
418 be_dws_cpu_to_le(wrb, 8);
419 }
420
421 /* Don't touch the hdr after it's prepared */
422 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
423 u8 subsystem, u8 opcode, int cmd_len)
424 {
425 req_hdr->opcode = opcode;
426 req_hdr->subsystem = subsystem;
427 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
428 req_hdr->version = 0;
429 }
430
431 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
432 struct be_dma_mem *mem)
433 {
434 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
435 u64 dma = (u64)mem->dma;
436
437 for (i = 0; i < buf_pages; i++) {
438 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
439 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
440 dma += PAGE_SIZE_4K;
441 }
442 }
443
444 /* Converts interrupt delay in microseconds to multiplier value */
445 static u32 eq_delay_to_mult(u32 usec_delay)
446 {
447 #define MAX_INTR_RATE 651042
448 const u32 round = 10;
449 u32 multiplier;
450
451 if (usec_delay == 0)
452 multiplier = 0;
453 else {
454 u32 interrupt_rate = 1000000 / usec_delay;
455 /* Max delay, corresponding to the lowest interrupt rate */
456 if (interrupt_rate == 0)
457 multiplier = 1023;
458 else {
459 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
460 multiplier /= interrupt_rate;
461 /* Round the multiplier to the closest value.*/
462 multiplier = (multiplier + round/2) / round;
463 multiplier = min(multiplier, (u32)1023);
464 }
465 }
466 return multiplier;
467 }
468
469 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
470 {
471 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
472 struct be_mcc_wrb *wrb
473 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
474 memset(wrb, 0, sizeof(*wrb));
475 return wrb;
476 }
477
478 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
479 {
480 struct be_queue_info *mccq = &adapter->mcc_obj.q;
481 struct be_mcc_wrb *wrb;
482
483 if (atomic_read(&mccq->used) >= mccq->len) {
484 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
485 return NULL;
486 }
487
488 wrb = queue_head_node(mccq);
489 queue_head_inc(mccq);
490 atomic_inc(&mccq->used);
491 memset(wrb, 0, sizeof(*wrb));
492 return wrb;
493 }
494
495 /* Tell fw we're about to start firing cmds by writing a
496 * special pattern across the wrb hdr; uses mbox
497 */
498 int be_cmd_fw_init(struct be_adapter *adapter)
499 {
500 u8 *wrb;
501 int status;
502
503 if (mutex_lock_interruptible(&adapter->mbox_lock))
504 return -1;
505
506 wrb = (u8 *)wrb_from_mbox(adapter);
507 *wrb++ = 0xFF;
508 *wrb++ = 0x12;
509 *wrb++ = 0x34;
510 *wrb++ = 0xFF;
511 *wrb++ = 0xFF;
512 *wrb++ = 0x56;
513 *wrb++ = 0x78;
514 *wrb = 0xFF;
515
516 status = be_mbox_notify_wait(adapter);
517
518 mutex_unlock(&adapter->mbox_lock);
519 return status;
520 }
521
522 /* Tell fw we're done with firing cmds by writing a
523 * special pattern across the wrb hdr; uses mbox
524 */
525 int be_cmd_fw_clean(struct be_adapter *adapter)
526 {
527 u8 *wrb;
528 int status;
529
530 if (adapter->eeh_err)
531 return -EIO;
532
533 if (mutex_lock_interruptible(&adapter->mbox_lock))
534 return -1;
535
536 wrb = (u8 *)wrb_from_mbox(adapter);
537 *wrb++ = 0xFF;
538 *wrb++ = 0xAA;
539 *wrb++ = 0xBB;
540 *wrb++ = 0xFF;
541 *wrb++ = 0xFF;
542 *wrb++ = 0xCC;
543 *wrb++ = 0xDD;
544 *wrb = 0xFF;
545
546 status = be_mbox_notify_wait(adapter);
547
548 mutex_unlock(&adapter->mbox_lock);
549 return status;
550 }
551 int be_cmd_eq_create(struct be_adapter *adapter,
552 struct be_queue_info *eq, int eq_delay)
553 {
554 struct be_mcc_wrb *wrb;
555 struct be_cmd_req_eq_create *req;
556 struct be_dma_mem *q_mem = &eq->dma_mem;
557 int status;
558
559 if (mutex_lock_interruptible(&adapter->mbox_lock))
560 return -1;
561
562 wrb = wrb_from_mbox(adapter);
563 req = embedded_payload(wrb);
564
565 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
566
567 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
568 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
569
570 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
571
572 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
573 /* 4byte eqe*/
574 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
575 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
576 __ilog2_u32(eq->len/256));
577 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
578 eq_delay_to_mult(eq_delay));
579 be_dws_cpu_to_le(req->context, sizeof(req->context));
580
581 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
582
583 status = be_mbox_notify_wait(adapter);
584 if (!status) {
585 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
586 eq->id = le16_to_cpu(resp->eq_id);
587 eq->created = true;
588 }
589
590 mutex_unlock(&adapter->mbox_lock);
591 return status;
592 }
593
594 /* Uses mbox */
595 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
596 u8 type, bool permanent, u32 if_handle)
597 {
598 struct be_mcc_wrb *wrb;
599 struct be_cmd_req_mac_query *req;
600 int status;
601
602 if (mutex_lock_interruptible(&adapter->mbox_lock))
603 return -1;
604
605 wrb = wrb_from_mbox(adapter);
606 req = embedded_payload(wrb);
607
608 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
609 OPCODE_COMMON_NTWK_MAC_QUERY);
610
611 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
612 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
613
614 req->type = type;
615 if (permanent) {
616 req->permanent = 1;
617 } else {
618 req->if_id = cpu_to_le16((u16) if_handle);
619 req->permanent = 0;
620 }
621
622 status = be_mbox_notify_wait(adapter);
623 if (!status) {
624 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
625 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
626 }
627
628 mutex_unlock(&adapter->mbox_lock);
629 return status;
630 }
631
632 /* Uses synchronous MCCQ */
633 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
634 u32 if_id, u32 *pmac_id, u32 domain)
635 {
636 struct be_mcc_wrb *wrb;
637 struct be_cmd_req_pmac_add *req;
638 int status;
639
640 spin_lock_bh(&adapter->mcc_lock);
641
642 wrb = wrb_from_mccq(adapter);
643 if (!wrb) {
644 status = -EBUSY;
645 goto err;
646 }
647 req = embedded_payload(wrb);
648
649 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
650 OPCODE_COMMON_NTWK_PMAC_ADD);
651
652 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
653 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
654
655 req->hdr.domain = domain;
656 req->if_id = cpu_to_le32(if_id);
657 memcpy(req->mac_address, mac_addr, ETH_ALEN);
658
659 status = be_mcc_notify_wait(adapter);
660 if (!status) {
661 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
662 *pmac_id = le32_to_cpu(resp->pmac_id);
663 }
664
665 err:
666 spin_unlock_bh(&adapter->mcc_lock);
667 return status;
668 }
669
670 /* Uses synchronous MCCQ */
671 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
672 {
673 struct be_mcc_wrb *wrb;
674 struct be_cmd_req_pmac_del *req;
675 int status;
676
677 spin_lock_bh(&adapter->mcc_lock);
678
679 wrb = wrb_from_mccq(adapter);
680 if (!wrb) {
681 status = -EBUSY;
682 goto err;
683 }
684 req = embedded_payload(wrb);
685
686 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
687 OPCODE_COMMON_NTWK_PMAC_DEL);
688
689 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
690 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
691
692 req->hdr.domain = dom;
693 req->if_id = cpu_to_le32(if_id);
694 req->pmac_id = cpu_to_le32(pmac_id);
695
696 status = be_mcc_notify_wait(adapter);
697
698 err:
699 spin_unlock_bh(&adapter->mcc_lock);
700 return status;
701 }
702
703 /* Uses Mbox */
704 int be_cmd_cq_create(struct be_adapter *adapter,
705 struct be_queue_info *cq, struct be_queue_info *eq,
706 bool sol_evts, bool no_delay, int coalesce_wm)
707 {
708 struct be_mcc_wrb *wrb;
709 struct be_cmd_req_cq_create *req;
710 struct be_dma_mem *q_mem = &cq->dma_mem;
711 void *ctxt;
712 int status;
713
714 if (mutex_lock_interruptible(&adapter->mbox_lock))
715 return -1;
716
717 wrb = wrb_from_mbox(adapter);
718 req = embedded_payload(wrb);
719 ctxt = &req->context;
720
721 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
722 OPCODE_COMMON_CQ_CREATE);
723
724 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
725 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
726
727 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
728 if (lancer_chip(adapter)) {
729 req->hdr.version = 2;
730 req->page_size = 1; /* 1 for 4K */
731 AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
732 coalesce_wm);
733 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
734 no_delay);
735 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
736 __ilog2_u32(cq->len/256));
737 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
738 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
739 ctxt, 1);
740 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
741 ctxt, eq->id);
742 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
743 } else {
744 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
745 coalesce_wm);
746 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
747 ctxt, no_delay);
748 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
749 __ilog2_u32(cq->len/256));
750 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
751 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
752 ctxt, sol_evts);
753 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
754 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
755 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
756 }
757
758 be_dws_cpu_to_le(ctxt, sizeof(req->context));
759
760 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
761
762 status = be_mbox_notify_wait(adapter);
763 if (!status) {
764 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
765 cq->id = le16_to_cpu(resp->cq_id);
766 cq->created = true;
767 }
768
769 mutex_unlock(&adapter->mbox_lock);
770
771 return status;
772 }
773
774 static u32 be_encoded_q_len(int q_len)
775 {
776 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
777 if (len_encoded == 16)
778 len_encoded = 0;
779 return len_encoded;
780 }
781
782 int be_cmd_mccq_create(struct be_adapter *adapter,
783 struct be_queue_info *mccq,
784 struct be_queue_info *cq)
785 {
786 struct be_mcc_wrb *wrb;
787 struct be_cmd_req_mcc_create *req;
788 struct be_dma_mem *q_mem = &mccq->dma_mem;
789 void *ctxt;
790 int status;
791
792 if (mutex_lock_interruptible(&adapter->mbox_lock))
793 return -1;
794
795 wrb = wrb_from_mbox(adapter);
796 req = embedded_payload(wrb);
797 ctxt = &req->context;
798
799 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
800 OPCODE_COMMON_MCC_CREATE_EXT);
801
802 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
803 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
804
805 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
806 if (lancer_chip(adapter)) {
807 req->hdr.version = 1;
808 req->cq_id = cpu_to_le16(cq->id);
809
810 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
811 be_encoded_q_len(mccq->len));
812 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
813 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
814 ctxt, cq->id);
815 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
816 ctxt, 1);
817
818 } else {
819 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
820 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
821 be_encoded_q_len(mccq->len));
822 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
823 }
824
825 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
826 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
827 be_dws_cpu_to_le(ctxt, sizeof(req->context));
828
829 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
830
831 status = be_mbox_notify_wait(adapter);
832 if (!status) {
833 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
834 mccq->id = le16_to_cpu(resp->id);
835 mccq->created = true;
836 }
837 mutex_unlock(&adapter->mbox_lock);
838
839 return status;
840 }
841
842 int be_cmd_txq_create(struct be_adapter *adapter,
843 struct be_queue_info *txq,
844 struct be_queue_info *cq)
845 {
846 struct be_mcc_wrb *wrb;
847 struct be_cmd_req_eth_tx_create *req;
848 struct be_dma_mem *q_mem = &txq->dma_mem;
849 void *ctxt;
850 int status;
851
852 if (mutex_lock_interruptible(&adapter->mbox_lock))
853 return -1;
854
855 wrb = wrb_from_mbox(adapter);
856 req = embedded_payload(wrb);
857 ctxt = &req->context;
858
859 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
860 OPCODE_ETH_TX_CREATE);
861
862 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
863 sizeof(*req));
864
865 if (lancer_chip(adapter)) {
866 req->hdr.version = 1;
867 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
868 adapter->if_handle);
869 }
870
871 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
872 req->ulp_num = BE_ULP1_NUM;
873 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
874
875 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
876 be_encoded_q_len(txq->len));
877 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
878 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
879
880 be_dws_cpu_to_le(ctxt, sizeof(req->context));
881
882 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
883
884 status = be_mbox_notify_wait(adapter);
885 if (!status) {
886 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
887 txq->id = le16_to_cpu(resp->cid);
888 txq->created = true;
889 }
890
891 mutex_unlock(&adapter->mbox_lock);
892
893 return status;
894 }
895
896 /* Uses mbox */
897 int be_cmd_rxq_create(struct be_adapter *adapter,
898 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
899 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
900 {
901 struct be_mcc_wrb *wrb;
902 struct be_cmd_req_eth_rx_create *req;
903 struct be_dma_mem *q_mem = &rxq->dma_mem;
904 int status;
905
906 if (mutex_lock_interruptible(&adapter->mbox_lock))
907 return -1;
908
909 wrb = wrb_from_mbox(adapter);
910 req = embedded_payload(wrb);
911
912 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
913 OPCODE_ETH_RX_CREATE);
914
915 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
916 sizeof(*req));
917
918 req->cq_id = cpu_to_le16(cq_id);
919 req->frag_size = fls(frag_size) - 1;
920 req->num_pages = 2;
921 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
922 req->interface_id = cpu_to_le32(if_id);
923 req->max_frame_size = cpu_to_le16(max_frame_size);
924 req->rss_queue = cpu_to_le32(rss);
925
926 status = be_mbox_notify_wait(adapter);
927 if (!status) {
928 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
929 rxq->id = le16_to_cpu(resp->id);
930 rxq->created = true;
931 *rss_id = resp->rss_id;
932 }
933
934 mutex_unlock(&adapter->mbox_lock);
935
936 return status;
937 }
938
939 /* Generic destroyer function for all types of queues
940 * Uses Mbox
941 */
942 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
943 int queue_type)
944 {
945 struct be_mcc_wrb *wrb;
946 struct be_cmd_req_q_destroy *req;
947 u8 subsys = 0, opcode = 0;
948 int status;
949
950 if (adapter->eeh_err)
951 return -EIO;
952
953 if (mutex_lock_interruptible(&adapter->mbox_lock))
954 return -1;
955
956 wrb = wrb_from_mbox(adapter);
957 req = embedded_payload(wrb);
958
959 switch (queue_type) {
960 case QTYPE_EQ:
961 subsys = CMD_SUBSYSTEM_COMMON;
962 opcode = OPCODE_COMMON_EQ_DESTROY;
963 break;
964 case QTYPE_CQ:
965 subsys = CMD_SUBSYSTEM_COMMON;
966 opcode = OPCODE_COMMON_CQ_DESTROY;
967 break;
968 case QTYPE_TXQ:
969 subsys = CMD_SUBSYSTEM_ETH;
970 opcode = OPCODE_ETH_TX_DESTROY;
971 break;
972 case QTYPE_RXQ:
973 subsys = CMD_SUBSYSTEM_ETH;
974 opcode = OPCODE_ETH_RX_DESTROY;
975 break;
976 case QTYPE_MCCQ:
977 subsys = CMD_SUBSYSTEM_COMMON;
978 opcode = OPCODE_COMMON_MCC_DESTROY;
979 break;
980 default:
981 BUG();
982 }
983
984 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
985
986 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
987 req->id = cpu_to_le16(q->id);
988
989 status = be_mbox_notify_wait(adapter);
990
991 mutex_unlock(&adapter->mbox_lock);
992
993 return status;
994 }
995
996 /* Create an rx filtering policy configuration on an i/f
997 * Uses mbox
998 */
999 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1000 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1001 u32 domain)
1002 {
1003 struct be_mcc_wrb *wrb;
1004 struct be_cmd_req_if_create *req;
1005 int status;
1006
1007 if (mutex_lock_interruptible(&adapter->mbox_lock))
1008 return -1;
1009
1010 wrb = wrb_from_mbox(adapter);
1011 req = embedded_payload(wrb);
1012
1013 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1014 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1015
1016 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1017 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1018
1019 req->hdr.domain = domain;
1020 req->capability_flags = cpu_to_le32(cap_flags);
1021 req->enable_flags = cpu_to_le32(en_flags);
1022 req->pmac_invalid = pmac_invalid;
1023 if (!pmac_invalid)
1024 memcpy(req->mac_addr, mac, ETH_ALEN);
1025
1026 status = be_mbox_notify_wait(adapter);
1027 if (!status) {
1028 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1029 *if_handle = le32_to_cpu(resp->interface_id);
1030 if (!pmac_invalid)
1031 *pmac_id = le32_to_cpu(resp->pmac_id);
1032 }
1033
1034 mutex_unlock(&adapter->mbox_lock);
1035 return status;
1036 }
1037
1038 /* Uses mbox */
1039 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1040 {
1041 struct be_mcc_wrb *wrb;
1042 struct be_cmd_req_if_destroy *req;
1043 int status;
1044
1045 if (adapter->eeh_err)
1046 return -EIO;
1047
1048 if (mutex_lock_interruptible(&adapter->mbox_lock))
1049 return -1;
1050
1051 wrb = wrb_from_mbox(adapter);
1052 req = embedded_payload(wrb);
1053
1054 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1055 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1056
1057 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1058 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1059
1060 req->hdr.domain = domain;
1061 req->interface_id = cpu_to_le32(interface_id);
1062
1063 status = be_mbox_notify_wait(adapter);
1064
1065 mutex_unlock(&adapter->mbox_lock);
1066
1067 return status;
1068 }
1069
1070 /* Get stats is a non embedded command: the request is not embedded inside
1071 * WRB but is a separate dma memory block
1072 * Uses asynchronous MCC
1073 */
1074 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1075 {
1076 struct be_mcc_wrb *wrb;
1077 struct be_cmd_req_get_stats *req;
1078 struct be_sge *sge;
1079 int status = 0;
1080
1081 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1082 be_cmd_get_die_temperature(adapter);
1083
1084 spin_lock_bh(&adapter->mcc_lock);
1085
1086 wrb = wrb_from_mccq(adapter);
1087 if (!wrb) {
1088 status = -EBUSY;
1089 goto err;
1090 }
1091 req = nonemb_cmd->va;
1092 sge = nonembedded_sgl(wrb);
1093
1094 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1095 OPCODE_ETH_GET_STATISTICS);
1096
1097 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1098 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1099 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1100 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1101 sge->len = cpu_to_le32(nonemb_cmd->size);
1102
1103 be_mcc_notify(adapter);
1104 adapter->stats_cmd_sent = true;
1105
1106 err:
1107 spin_unlock_bh(&adapter->mcc_lock);
1108 return status;
1109 }
1110
1111 /* Uses synchronous mcc */
1112 int be_cmd_link_status_query(struct be_adapter *adapter,
1113 bool *link_up, u8 *mac_speed, u16 *link_speed)
1114 {
1115 struct be_mcc_wrb *wrb;
1116 struct be_cmd_req_link_status *req;
1117 int status;
1118
1119 spin_lock_bh(&adapter->mcc_lock);
1120
1121 wrb = wrb_from_mccq(adapter);
1122 if (!wrb) {
1123 status = -EBUSY;
1124 goto err;
1125 }
1126 req = embedded_payload(wrb);
1127
1128 *link_up = false;
1129
1130 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1131 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1132
1133 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1134 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1135
1136 status = be_mcc_notify_wait(adapter);
1137 if (!status) {
1138 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1139 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1140 *link_up = true;
1141 *link_speed = le16_to_cpu(resp->link_speed);
1142 *mac_speed = resp->mac_speed;
1143 }
1144 }
1145
1146 err:
1147 spin_unlock_bh(&adapter->mcc_lock);
1148 return status;
1149 }
1150
1151 /* Uses synchronous mcc */
1152 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1153 {
1154 struct be_mcc_wrb *wrb;
1155 struct be_cmd_req_get_cntl_addnl_attribs *req;
1156 int status;
1157
1158 spin_lock_bh(&adapter->mcc_lock);
1159
1160 wrb = wrb_from_mccq(adapter);
1161 if (!wrb) {
1162 status = -EBUSY;
1163 goto err;
1164 }
1165 req = embedded_payload(wrb);
1166
1167 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1168 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1169
1170 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1171 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1172
1173 status = be_mcc_notify_wait(adapter);
1174 if (!status) {
1175 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1176 embedded_payload(wrb);
1177 adapter->drv_stats.be_on_die_temperature =
1178 resp->on_die_temperature;
1179 }
1180 /* If IOCTL fails once, do not bother issuing it again */
1181 else
1182 be_get_temp_freq = 0;
1183
1184 err:
1185 spin_unlock_bh(&adapter->mcc_lock);
1186 return status;
1187 }
1188
1189 /* Uses synchronous mcc */
1190 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1191 {
1192 struct be_mcc_wrb *wrb;
1193 struct be_cmd_req_get_fat *req;
1194 int status;
1195
1196 spin_lock_bh(&adapter->mcc_lock);
1197
1198 wrb = wrb_from_mccq(adapter);
1199 if (!wrb) {
1200 status = -EBUSY;
1201 goto err;
1202 }
1203 req = embedded_payload(wrb);
1204
1205 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1206 OPCODE_COMMON_MANAGE_FAT);
1207
1208 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1209 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1210 req->fat_operation = cpu_to_le32(QUERY_FAT);
1211 status = be_mcc_notify_wait(adapter);
1212 if (!status) {
1213 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1214 if (log_size && resp->log_size)
1215 *log_size = le32_to_cpu(resp->log_size -
1216 sizeof(u32));
1217 }
1218 err:
1219 spin_unlock_bh(&adapter->mcc_lock);
1220 return status;
1221 }
1222
1223 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1224 {
1225 struct be_dma_mem get_fat_cmd;
1226 struct be_mcc_wrb *wrb;
1227 struct be_cmd_req_get_fat *req;
1228 struct be_sge *sge;
1229 u32 offset = 0, total_size, buf_size, log_offset = sizeof(u32);
1230 int status;
1231
1232 if (buf_len == 0)
1233 return;
1234
1235 total_size = buf_len;
1236
1237 spin_lock_bh(&adapter->mcc_lock);
1238
1239 wrb = wrb_from_mccq(adapter);
1240 if (!wrb) {
1241 status = -EBUSY;
1242 goto err;
1243 }
1244 while (total_size) {
1245 buf_size = min(total_size, (u32)60*1024);
1246 total_size -= buf_size;
1247
1248 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + buf_size;
1249 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1250 get_fat_cmd.size,
1251 &get_fat_cmd.dma);
1252 if (!get_fat_cmd.va) {
1253 status = -ENOMEM;
1254 dev_err(&adapter->pdev->dev,
1255 "Memory allocation failure while retrieving FAT data\n");
1256 goto err;
1257 }
1258 req = get_fat_cmd.va;
1259 sge = nonembedded_sgl(wrb);
1260
1261 be_wrb_hdr_prepare(wrb, get_fat_cmd.size, false, 1,
1262 OPCODE_COMMON_MANAGE_FAT);
1263
1264 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1265 OPCODE_COMMON_MANAGE_FAT, get_fat_cmd.size);
1266
1267 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.size));
1268 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1269 sge->len = cpu_to_le32(get_fat_cmd.size);
1270
1271 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1272 req->read_log_offset = cpu_to_le32(log_offset);
1273 req->read_log_length = cpu_to_le32(buf_size);
1274 req->data_buffer_size = cpu_to_le32(buf_size);
1275
1276 status = be_mcc_notify_wait(adapter);
1277 if (!status) {
1278 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1279 memcpy(buf + offset,
1280 resp->data_buffer,
1281 resp->read_log_length);
1282 }
1283 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1284 get_fat_cmd.va,
1285 get_fat_cmd.dma);
1286 if (status)
1287 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1288
1289 offset += buf_size;
1290 log_offset += buf_size;
1291 }
1292 err:
1293 spin_unlock_bh(&adapter->mcc_lock);
1294 }
1295
1296 /* Uses Mbox */
1297 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1298 {
1299 struct be_mcc_wrb *wrb;
1300 struct be_cmd_req_get_fw_version *req;
1301 int status;
1302
1303 if (mutex_lock_interruptible(&adapter->mbox_lock))
1304 return -1;
1305
1306 wrb = wrb_from_mbox(adapter);
1307 req = embedded_payload(wrb);
1308
1309 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1310 OPCODE_COMMON_GET_FW_VERSION);
1311
1312 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1313 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1314
1315 status = be_mbox_notify_wait(adapter);
1316 if (!status) {
1317 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1318 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1319 }
1320
1321 mutex_unlock(&adapter->mbox_lock);
1322 return status;
1323 }
1324
1325 /* set the EQ delay interval of an EQ to specified value
1326 * Uses async mcc
1327 */
1328 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1329 {
1330 struct be_mcc_wrb *wrb;
1331 struct be_cmd_req_modify_eq_delay *req;
1332 int status = 0;
1333
1334 spin_lock_bh(&adapter->mcc_lock);
1335
1336 wrb = wrb_from_mccq(adapter);
1337 if (!wrb) {
1338 status = -EBUSY;
1339 goto err;
1340 }
1341 req = embedded_payload(wrb);
1342
1343 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1344 OPCODE_COMMON_MODIFY_EQ_DELAY);
1345
1346 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1347 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1348
1349 req->num_eq = cpu_to_le32(1);
1350 req->delay[0].eq_id = cpu_to_le32(eq_id);
1351 req->delay[0].phase = 0;
1352 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1353
1354 be_mcc_notify(adapter);
1355
1356 err:
1357 spin_unlock_bh(&adapter->mcc_lock);
1358 return status;
1359 }
1360
1361 /* Uses sycnhronous mcc */
1362 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1363 u32 num, bool untagged, bool promiscuous)
1364 {
1365 struct be_mcc_wrb *wrb;
1366 struct be_cmd_req_vlan_config *req;
1367 int status;
1368
1369 spin_lock_bh(&adapter->mcc_lock);
1370
1371 wrb = wrb_from_mccq(adapter);
1372 if (!wrb) {
1373 status = -EBUSY;
1374 goto err;
1375 }
1376 req = embedded_payload(wrb);
1377
1378 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1379 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1380
1381 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1382 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1383
1384 req->interface_id = if_id;
1385 req->promiscuous = promiscuous;
1386 req->untagged = untagged;
1387 req->num_vlan = num;
1388 if (!promiscuous) {
1389 memcpy(req->normal_vlan, vtag_array,
1390 req->num_vlan * sizeof(vtag_array[0]));
1391 }
1392
1393 status = be_mcc_notify_wait(adapter);
1394
1395 err:
1396 spin_unlock_bh(&adapter->mcc_lock);
1397 return status;
1398 }
1399
1400 /* Uses MCC for this command as it may be called in BH context
1401 * Uses synchronous mcc
1402 */
1403 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1404 {
1405 struct be_mcc_wrb *wrb;
1406 struct be_cmd_req_promiscuous_config *req;
1407 int status;
1408
1409 spin_lock_bh(&adapter->mcc_lock);
1410
1411 wrb = wrb_from_mccq(adapter);
1412 if (!wrb) {
1413 status = -EBUSY;
1414 goto err;
1415 }
1416 req = embedded_payload(wrb);
1417
1418 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1419
1420 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1421 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1422
1423 /* In FW versions X.102.149/X.101.487 and later,
1424 * the port setting associated only with the
1425 * issuing pci function will take effect
1426 */
1427 if (port_num)
1428 req->port1_promiscuous = en;
1429 else
1430 req->port0_promiscuous = en;
1431
1432 status = be_mcc_notify_wait(adapter);
1433
1434 err:
1435 spin_unlock_bh(&adapter->mcc_lock);
1436 return status;
1437 }
1438
1439 /*
1440 * Uses MCC for this command as it may be called in BH context
1441 * (mc == NULL) => multicast promiscuous
1442 */
1443 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1444 struct net_device *netdev, struct be_dma_mem *mem)
1445 {
1446 struct be_mcc_wrb *wrb;
1447 struct be_cmd_req_mcast_mac_config *req = mem->va;
1448 struct be_sge *sge;
1449 int status;
1450
1451 spin_lock_bh(&adapter->mcc_lock);
1452
1453 wrb = wrb_from_mccq(adapter);
1454 if (!wrb) {
1455 status = -EBUSY;
1456 goto err;
1457 }
1458 sge = nonembedded_sgl(wrb);
1459 memset(req, 0, sizeof(*req));
1460
1461 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1462 OPCODE_COMMON_NTWK_MULTICAST_SET);
1463 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1464 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1465 sge->len = cpu_to_le32(mem->size);
1466
1467 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1468 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1469
1470 req->interface_id = if_id;
1471 if (netdev) {
1472 int i;
1473 struct netdev_hw_addr *ha;
1474
1475 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1476
1477 i = 0;
1478 netdev_for_each_mc_addr(ha, netdev)
1479 memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1480 } else {
1481 req->promiscuous = 1;
1482 }
1483
1484 status = be_mcc_notify_wait(adapter);
1485
1486 err:
1487 spin_unlock_bh(&adapter->mcc_lock);
1488 return status;
1489 }
1490
1491 /* Uses synchrounous mcc */
1492 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1493 {
1494 struct be_mcc_wrb *wrb;
1495 struct be_cmd_req_set_flow_control *req;
1496 int status;
1497
1498 spin_lock_bh(&adapter->mcc_lock);
1499
1500 wrb = wrb_from_mccq(adapter);
1501 if (!wrb) {
1502 status = -EBUSY;
1503 goto err;
1504 }
1505 req = embedded_payload(wrb);
1506
1507 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1508 OPCODE_COMMON_SET_FLOW_CONTROL);
1509
1510 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1511 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1512
1513 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1514 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1515
1516 status = be_mcc_notify_wait(adapter);
1517
1518 err:
1519 spin_unlock_bh(&adapter->mcc_lock);
1520 return status;
1521 }
1522
1523 /* Uses sycn mcc */
1524 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1525 {
1526 struct be_mcc_wrb *wrb;
1527 struct be_cmd_req_get_flow_control *req;
1528 int status;
1529
1530 spin_lock_bh(&adapter->mcc_lock);
1531
1532 wrb = wrb_from_mccq(adapter);
1533 if (!wrb) {
1534 status = -EBUSY;
1535 goto err;
1536 }
1537 req = embedded_payload(wrb);
1538
1539 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1540 OPCODE_COMMON_GET_FLOW_CONTROL);
1541
1542 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1543 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1544
1545 status = be_mcc_notify_wait(adapter);
1546 if (!status) {
1547 struct be_cmd_resp_get_flow_control *resp =
1548 embedded_payload(wrb);
1549 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1550 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1551 }
1552
1553 err:
1554 spin_unlock_bh(&adapter->mcc_lock);
1555 return status;
1556 }
1557
1558 /* Uses mbox */
1559 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1560 u32 *mode, u32 *caps)
1561 {
1562 struct be_mcc_wrb *wrb;
1563 struct be_cmd_req_query_fw_cfg *req;
1564 int status;
1565
1566 if (mutex_lock_interruptible(&adapter->mbox_lock))
1567 return -1;
1568
1569 wrb = wrb_from_mbox(adapter);
1570 req = embedded_payload(wrb);
1571
1572 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1573 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1574
1575 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1576 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1577
1578 status = be_mbox_notify_wait(adapter);
1579 if (!status) {
1580 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1581 *port_num = le32_to_cpu(resp->phys_port);
1582 *mode = le32_to_cpu(resp->function_mode);
1583 *caps = le32_to_cpu(resp->function_caps);
1584 }
1585
1586 mutex_unlock(&adapter->mbox_lock);
1587 return status;
1588 }
1589
1590 /* Uses mbox */
1591 int be_cmd_reset_function(struct be_adapter *adapter)
1592 {
1593 struct be_mcc_wrb *wrb;
1594 struct be_cmd_req_hdr *req;
1595 int status;
1596
1597 if (mutex_lock_interruptible(&adapter->mbox_lock))
1598 return -1;
1599
1600 wrb = wrb_from_mbox(adapter);
1601 req = embedded_payload(wrb);
1602
1603 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1604 OPCODE_COMMON_FUNCTION_RESET);
1605
1606 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1607 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1608
1609 status = be_mbox_notify_wait(adapter);
1610
1611 mutex_unlock(&adapter->mbox_lock);
1612 return status;
1613 }
1614
1615 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1616 {
1617 struct be_mcc_wrb *wrb;
1618 struct be_cmd_req_rss_config *req;
1619 u32 myhash[10];
1620 int status;
1621
1622 if (mutex_lock_interruptible(&adapter->mbox_lock))
1623 return -1;
1624
1625 wrb = wrb_from_mbox(adapter);
1626 req = embedded_payload(wrb);
1627
1628 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1629 OPCODE_ETH_RSS_CONFIG);
1630
1631 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1632 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1633
1634 req->if_id = cpu_to_le32(adapter->if_handle);
1635 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1636 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1637 memcpy(req->cpu_table, rsstable, table_size);
1638 memcpy(req->hash, myhash, sizeof(myhash));
1639 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1640
1641 status = be_mbox_notify_wait(adapter);
1642
1643 mutex_unlock(&adapter->mbox_lock);
1644 return status;
1645 }
1646
1647 /* Uses sync mcc */
1648 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1649 u8 bcn, u8 sts, u8 state)
1650 {
1651 struct be_mcc_wrb *wrb;
1652 struct be_cmd_req_enable_disable_beacon *req;
1653 int status;
1654
1655 spin_lock_bh(&adapter->mcc_lock);
1656
1657 wrb = wrb_from_mccq(adapter);
1658 if (!wrb) {
1659 status = -EBUSY;
1660 goto err;
1661 }
1662 req = embedded_payload(wrb);
1663
1664 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1665 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1666
1667 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1668 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1669
1670 req->port_num = port_num;
1671 req->beacon_state = state;
1672 req->beacon_duration = bcn;
1673 req->status_duration = sts;
1674
1675 status = be_mcc_notify_wait(adapter);
1676
1677 err:
1678 spin_unlock_bh(&adapter->mcc_lock);
1679 return status;
1680 }
1681
1682 /* Uses sync mcc */
1683 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1684 {
1685 struct be_mcc_wrb *wrb;
1686 struct be_cmd_req_get_beacon_state *req;
1687 int status;
1688
1689 spin_lock_bh(&adapter->mcc_lock);
1690
1691 wrb = wrb_from_mccq(adapter);
1692 if (!wrb) {
1693 status = -EBUSY;
1694 goto err;
1695 }
1696 req = embedded_payload(wrb);
1697
1698 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1699 OPCODE_COMMON_GET_BEACON_STATE);
1700
1701 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1702 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1703
1704 req->port_num = port_num;
1705
1706 status = be_mcc_notify_wait(adapter);
1707 if (!status) {
1708 struct be_cmd_resp_get_beacon_state *resp =
1709 embedded_payload(wrb);
1710 *state = resp->beacon_state;
1711 }
1712
1713 err:
1714 spin_unlock_bh(&adapter->mcc_lock);
1715 return status;
1716 }
1717
1718 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1719 u32 flash_type, u32 flash_opcode, u32 buf_size)
1720 {
1721 struct be_mcc_wrb *wrb;
1722 struct be_cmd_write_flashrom *req;
1723 struct be_sge *sge;
1724 int status;
1725
1726 spin_lock_bh(&adapter->mcc_lock);
1727 adapter->flash_status = 0;
1728
1729 wrb = wrb_from_mccq(adapter);
1730 if (!wrb) {
1731 status = -EBUSY;
1732 goto err_unlock;
1733 }
1734 req = cmd->va;
1735 sge = nonembedded_sgl(wrb);
1736
1737 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1738 OPCODE_COMMON_WRITE_FLASHROM);
1739 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1740
1741 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1742 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1743 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1744 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1745 sge->len = cpu_to_le32(cmd->size);
1746
1747 req->params.op_type = cpu_to_le32(flash_type);
1748 req->params.op_code = cpu_to_le32(flash_opcode);
1749 req->params.data_buf_size = cpu_to_le32(buf_size);
1750
1751 be_mcc_notify(adapter);
1752 spin_unlock_bh(&adapter->mcc_lock);
1753
1754 if (!wait_for_completion_timeout(&adapter->flash_compl,
1755 msecs_to_jiffies(12000)))
1756 status = -1;
1757 else
1758 status = adapter->flash_status;
1759
1760 return status;
1761
1762 err_unlock:
1763 spin_unlock_bh(&adapter->mcc_lock);
1764 return status;
1765 }
1766
1767 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1768 int offset)
1769 {
1770 struct be_mcc_wrb *wrb;
1771 struct be_cmd_write_flashrom *req;
1772 int status;
1773
1774 spin_lock_bh(&adapter->mcc_lock);
1775
1776 wrb = wrb_from_mccq(adapter);
1777 if (!wrb) {
1778 status = -EBUSY;
1779 goto err;
1780 }
1781 req = embedded_payload(wrb);
1782
1783 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1784 OPCODE_COMMON_READ_FLASHROM);
1785
1786 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1787 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1788
1789 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1790 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1791 req->params.offset = cpu_to_le32(offset);
1792 req->params.data_buf_size = cpu_to_le32(0x4);
1793
1794 status = be_mcc_notify_wait(adapter);
1795 if (!status)
1796 memcpy(flashed_crc, req->params.data_buf, 4);
1797
1798 err:
1799 spin_unlock_bh(&adapter->mcc_lock);
1800 return status;
1801 }
1802
1803 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1804 struct be_dma_mem *nonemb_cmd)
1805 {
1806 struct be_mcc_wrb *wrb;
1807 struct be_cmd_req_acpi_wol_magic_config *req;
1808 struct be_sge *sge;
1809 int status;
1810
1811 spin_lock_bh(&adapter->mcc_lock);
1812
1813 wrb = wrb_from_mccq(adapter);
1814 if (!wrb) {
1815 status = -EBUSY;
1816 goto err;
1817 }
1818 req = nonemb_cmd->va;
1819 sge = nonembedded_sgl(wrb);
1820
1821 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1822 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1823
1824 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1825 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1826 memcpy(req->magic_mac, mac, ETH_ALEN);
1827
1828 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1829 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1830 sge->len = cpu_to_le32(nonemb_cmd->size);
1831
1832 status = be_mcc_notify_wait(adapter);
1833
1834 err:
1835 spin_unlock_bh(&adapter->mcc_lock);
1836 return status;
1837 }
1838
1839 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1840 u8 loopback_type, u8 enable)
1841 {
1842 struct be_mcc_wrb *wrb;
1843 struct be_cmd_req_set_lmode *req;
1844 int status;
1845
1846 spin_lock_bh(&adapter->mcc_lock);
1847
1848 wrb = wrb_from_mccq(adapter);
1849 if (!wrb) {
1850 status = -EBUSY;
1851 goto err;
1852 }
1853
1854 req = embedded_payload(wrb);
1855
1856 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1857 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1858
1859 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1860 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1861 sizeof(*req));
1862
1863 req->src_port = port_num;
1864 req->dest_port = port_num;
1865 req->loopback_type = loopback_type;
1866 req->loopback_state = enable;
1867
1868 status = be_mcc_notify_wait(adapter);
1869 err:
1870 spin_unlock_bh(&adapter->mcc_lock);
1871 return status;
1872 }
1873
1874 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1875 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1876 {
1877 struct be_mcc_wrb *wrb;
1878 struct be_cmd_req_loopback_test *req;
1879 int status;
1880
1881 spin_lock_bh(&adapter->mcc_lock);
1882
1883 wrb = wrb_from_mccq(adapter);
1884 if (!wrb) {
1885 status = -EBUSY;
1886 goto err;
1887 }
1888
1889 req = embedded_payload(wrb);
1890
1891 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1892 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1893
1894 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1895 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1896 req->hdr.timeout = cpu_to_le32(4);
1897
1898 req->pattern = cpu_to_le64(pattern);
1899 req->src_port = cpu_to_le32(port_num);
1900 req->dest_port = cpu_to_le32(port_num);
1901 req->pkt_size = cpu_to_le32(pkt_size);
1902 req->num_pkts = cpu_to_le32(num_pkts);
1903 req->loopback_type = cpu_to_le32(loopback_type);
1904
1905 status = be_mcc_notify_wait(adapter);
1906 if (!status) {
1907 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1908 status = le32_to_cpu(resp->status);
1909 }
1910
1911 err:
1912 spin_unlock_bh(&adapter->mcc_lock);
1913 return status;
1914 }
1915
1916 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1917 u32 byte_cnt, struct be_dma_mem *cmd)
1918 {
1919 struct be_mcc_wrb *wrb;
1920 struct be_cmd_req_ddrdma_test *req;
1921 struct be_sge *sge;
1922 int status;
1923 int i, j = 0;
1924
1925 spin_lock_bh(&adapter->mcc_lock);
1926
1927 wrb = wrb_from_mccq(adapter);
1928 if (!wrb) {
1929 status = -EBUSY;
1930 goto err;
1931 }
1932 req = cmd->va;
1933 sge = nonembedded_sgl(wrb);
1934 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1935 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1936 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1937 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1938
1939 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1940 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1941 sge->len = cpu_to_le32(cmd->size);
1942
1943 req->pattern = cpu_to_le64(pattern);
1944 req->byte_count = cpu_to_le32(byte_cnt);
1945 for (i = 0; i < byte_cnt; i++) {
1946 req->snd_buff[i] = (u8)(pattern >> (j*8));
1947 j++;
1948 if (j > 7)
1949 j = 0;
1950 }
1951
1952 status = be_mcc_notify_wait(adapter);
1953
1954 if (!status) {
1955 struct be_cmd_resp_ddrdma_test *resp;
1956 resp = cmd->va;
1957 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1958 resp->snd_err) {
1959 status = -1;
1960 }
1961 }
1962
1963 err:
1964 spin_unlock_bh(&adapter->mcc_lock);
1965 return status;
1966 }
1967
1968 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1969 struct be_dma_mem *nonemb_cmd)
1970 {
1971 struct be_mcc_wrb *wrb;
1972 struct be_cmd_req_seeprom_read *req;
1973 struct be_sge *sge;
1974 int status;
1975
1976 spin_lock_bh(&adapter->mcc_lock);
1977
1978 wrb = wrb_from_mccq(adapter);
1979 if (!wrb) {
1980 status = -EBUSY;
1981 goto err;
1982 }
1983 req = nonemb_cmd->va;
1984 sge = nonembedded_sgl(wrb);
1985
1986 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1987 OPCODE_COMMON_SEEPROM_READ);
1988
1989 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1990 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1991
1992 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1993 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1994 sge->len = cpu_to_le32(nonemb_cmd->size);
1995
1996 status = be_mcc_notify_wait(adapter);
1997
1998 err:
1999 spin_unlock_bh(&adapter->mcc_lock);
2000 return status;
2001 }
2002
2003 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2004 {
2005 struct be_mcc_wrb *wrb;
2006 struct be_cmd_req_get_phy_info *req;
2007 struct be_sge *sge;
2008 int status;
2009
2010 spin_lock_bh(&adapter->mcc_lock);
2011
2012 wrb = wrb_from_mccq(adapter);
2013 if (!wrb) {
2014 status = -EBUSY;
2015 goto err;
2016 }
2017
2018 req = cmd->va;
2019 sge = nonembedded_sgl(wrb);
2020
2021 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2022 OPCODE_COMMON_GET_PHY_DETAILS);
2023
2024 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2025 OPCODE_COMMON_GET_PHY_DETAILS,
2026 sizeof(*req));
2027
2028 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2029 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2030 sge->len = cpu_to_le32(cmd->size);
2031
2032 status = be_mcc_notify_wait(adapter);
2033 err:
2034 spin_unlock_bh(&adapter->mcc_lock);
2035 return status;
2036 }
2037
2038 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2039 {
2040 struct be_mcc_wrb *wrb;
2041 struct be_cmd_req_set_qos *req;
2042 int status;
2043
2044 spin_lock_bh(&adapter->mcc_lock);
2045
2046 wrb = wrb_from_mccq(adapter);
2047 if (!wrb) {
2048 status = -EBUSY;
2049 goto err;
2050 }
2051
2052 req = embedded_payload(wrb);
2053
2054 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2055 OPCODE_COMMON_SET_QOS);
2056
2057 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2058 OPCODE_COMMON_SET_QOS, sizeof(*req));
2059
2060 req->hdr.domain = domain;
2061 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2062 req->max_bps_nic = cpu_to_le32(bps);
2063
2064 status = be_mcc_notify_wait(adapter);
2065
2066 err:
2067 spin_unlock_bh(&adapter->mcc_lock);
2068 return status;
2069 }
2070
2071 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2072 {
2073 struct be_mcc_wrb *wrb;
2074 struct be_cmd_req_cntl_attribs *req;
2075 struct be_cmd_resp_cntl_attribs *resp;
2076 struct be_sge *sge;
2077 int status;
2078 int payload_len = max(sizeof(*req), sizeof(*resp));
2079 struct mgmt_controller_attrib *attribs;
2080 struct be_dma_mem attribs_cmd;
2081
2082 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2083 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2084 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2085 &attribs_cmd.dma);
2086 if (!attribs_cmd.va) {
2087 dev_err(&adapter->pdev->dev,
2088 "Memory allocation failure\n");
2089 return -ENOMEM;
2090 }
2091
2092 if (mutex_lock_interruptible(&adapter->mbox_lock))
2093 return -1;
2094
2095 wrb = wrb_from_mbox(adapter);
2096 if (!wrb) {
2097 status = -EBUSY;
2098 goto err;
2099 }
2100 req = attribs_cmd.va;
2101 sge = nonembedded_sgl(wrb);
2102
2103 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2104 OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2105 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2106 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2107 sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2108 sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2109 sge->len = cpu_to_le32(attribs_cmd.size);
2110
2111 status = be_mbox_notify_wait(adapter);
2112 if (!status) {
2113 attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
2114 sizeof(struct be_cmd_resp_hdr));
2115 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2116 }
2117
2118 err:
2119 mutex_unlock(&adapter->mbox_lock);
2120 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2121 attribs_cmd.dma);
2122 return status;
2123 }
2124
2125 /* Uses mbox */
2126 int be_cmd_check_native_mode(struct be_adapter *adapter)
2127 {
2128 struct be_mcc_wrb *wrb;
2129 struct be_cmd_req_set_func_cap *req;
2130 int status;
2131
2132 if (mutex_lock_interruptible(&adapter->mbox_lock))
2133 return -1;
2134
2135 wrb = wrb_from_mbox(adapter);
2136 if (!wrb) {
2137 status = -EBUSY;
2138 goto err;
2139 }
2140
2141 req = embedded_payload(wrb);
2142
2143 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2144 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2145
2146 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2147 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2148
2149 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2150 CAPABILITY_BE3_NATIVE_ERX_API);
2151 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2152
2153 status = be_mbox_notify_wait(adapter);
2154 if (!status) {
2155 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2156 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2157 CAPABILITY_BE3_NATIVE_ERX_API;
2158 }
2159 err:
2160 mutex_unlock(&adapter->mbox_lock);
2161 return status;
2162 }
Linux kernel - Deliverables
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