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be2net: variable name changes
[deliverable/linux.git] / drivers / net / benet / be_cmds.c
1 /*
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 static void be_mcc_notify(struct be_adapter *adapter)
22 {
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
24 u32 val = 0;
25
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28
29 wmb();
30 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
31 }
32
33 /* To check if valid bit is set, check the entire word as we don't know
34 * the endianness of the data (old entry is host endian while a new entry is
35 * little endian) */
36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
37 {
38 if (compl->flags != 0) {
39 compl->flags = le32_to_cpu(compl->flags);
40 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
41 return true;
42 } else {
43 return false;
44 }
45 }
46
47 /* Need to reset the entire word that houses the valid bit */
48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
49 {
50 compl->flags = 0;
51 }
52
53 static int be_mcc_compl_process(struct be_adapter *adapter,
54 struct be_mcc_compl *compl)
55 {
56 u16 compl_status, extd_status;
57
58 /* Just swap the status to host endian; mcc tag is opaquely copied
59 * from mcc_wrb */
60 be_dws_le_to_cpu(compl, 4);
61
62 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
63 CQE_STATUS_COMPL_MASK;
64
65 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
66 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
67 adapter->flash_status = compl_status;
68 complete(&adapter->flash_compl);
69 }
70
71 if (compl_status == MCC_STATUS_SUCCESS) {
72 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
73 struct be_cmd_resp_get_stats *resp =
74 adapter->stats.cmd.va;
75 be_dws_le_to_cpu(&resp->hw_stats,
76 sizeof(resp->hw_stats));
77 netdev_stats_update(adapter);
78 }
79 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
80 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
81 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
82 CQE_STATUS_EXTD_MASK;
83 dev_warn(&adapter->pdev->dev,
84 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
85 compl->tag0, compl_status, extd_status);
86 }
87 return compl_status;
88 }
89
90 /* Link state evt is a string of bytes; no need for endian swapping */
91 static void be_async_link_state_process(struct be_adapter *adapter,
92 struct be_async_event_link_state *evt)
93 {
94 be_link_status_update(adapter,
95 evt->port_link_status == ASYNC_EVENT_LINK_UP);
96 }
97
98 static inline bool is_link_state_evt(u32 trailer)
99 {
100 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
101 ASYNC_TRAILER_EVENT_CODE_MASK) ==
102 ASYNC_EVENT_CODE_LINK_STATE);
103 }
104
105 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
106 {
107 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
108 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
109
110 if (be_mcc_compl_is_new(compl)) {
111 queue_tail_inc(mcc_cq);
112 return compl;
113 }
114 return NULL;
115 }
116
117 void be_async_mcc_enable(struct be_adapter *adapter)
118 {
119 spin_lock_bh(&adapter->mcc_cq_lock);
120
121 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
122 adapter->mcc_obj.rearm_cq = true;
123
124 spin_unlock_bh(&adapter->mcc_cq_lock);
125 }
126
127 void be_async_mcc_disable(struct be_adapter *adapter)
128 {
129 adapter->mcc_obj.rearm_cq = false;
130 }
131
132 int be_process_mcc(struct be_adapter *adapter, int *status)
133 {
134 struct be_mcc_compl *compl;
135 int num = 0;
136 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
137
138 spin_lock_bh(&adapter->mcc_cq_lock);
139 while ((compl = be_mcc_compl_get(adapter))) {
140 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
141 /* Interpret flags as an async trailer */
142 BUG_ON(!is_link_state_evt(compl->flags));
143
144 /* Interpret compl as a async link evt */
145 be_async_link_state_process(adapter,
146 (struct be_async_event_link_state *) compl);
147 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
148 *status = be_mcc_compl_process(adapter, compl);
149 atomic_dec(&mcc_obj->q.used);
150 }
151 be_mcc_compl_use(compl);
152 num++;
153 }
154
155 spin_unlock_bh(&adapter->mcc_cq_lock);
156 return num;
157 }
158
159 /* Wait till no more pending mcc requests are present */
160 static int be_mcc_wait_compl(struct be_adapter *adapter)
161 {
162 #define mcc_timeout 120000 /* 12s timeout */
163 int i, num, status = 0;
164 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
165
166 for (i = 0; i < mcc_timeout; i++) {
167 num = be_process_mcc(adapter, &status);
168 if (num)
169 be_cq_notify(adapter, mcc_obj->cq.id,
170 mcc_obj->rearm_cq, num);
171
172 if (atomic_read(&mcc_obj->q.used) == 0)
173 break;
174 udelay(100);
175 }
176 if (i == mcc_timeout) {
177 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
178 return -1;
179 }
180 return status;
181 }
182
183 /* Notify MCC requests and wait for completion */
184 static int be_mcc_notify_wait(struct be_adapter *adapter)
185 {
186 be_mcc_notify(adapter);
187 return be_mcc_wait_compl(adapter);
188 }
189
190 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
191 {
192 int msecs = 0;
193 u32 ready;
194
195 do {
196 ready = ioread32(db);
197 if (ready == 0xffffffff) {
198 dev_err(&adapter->pdev->dev,
199 "pci slot disconnected\n");
200 return -1;
201 }
202
203 ready &= MPU_MAILBOX_DB_RDY_MASK;
204 if (ready)
205 break;
206
207 if (msecs > 4000) {
208 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
209 return -1;
210 }
211
212 set_current_state(TASK_INTERRUPTIBLE);
213 schedule_timeout(msecs_to_jiffies(1));
214 msecs++;
215 } while (true);
216
217 return 0;
218 }
219
220 /*
221 * Insert the mailbox address into the doorbell in two steps
222 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
223 */
224 static int be_mbox_notify_wait(struct be_adapter *adapter)
225 {
226 int status;
227 u32 val = 0;
228 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
229 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
230 struct be_mcc_mailbox *mbox = mbox_mem->va;
231 struct be_mcc_compl *compl = &mbox->compl;
232
233 /* wait for ready to be set */
234 status = be_mbox_db_ready_wait(adapter, db);
235 if (status != 0)
236 return status;
237
238 val |= MPU_MAILBOX_DB_HI_MASK;
239 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
240 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
241 iowrite32(val, db);
242
243 /* wait for ready to be set */
244 status = be_mbox_db_ready_wait(adapter, db);
245 if (status != 0)
246 return status;
247
248 val = 0;
249 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
250 val |= (u32)(mbox_mem->dma >> 4) << 2;
251 iowrite32(val, db);
252
253 status = be_mbox_db_ready_wait(adapter, db);
254 if (status != 0)
255 return status;
256
257 /* A cq entry has been made now */
258 if (be_mcc_compl_is_new(compl)) {
259 status = be_mcc_compl_process(adapter, &mbox->compl);
260 be_mcc_compl_use(compl);
261 if (status)
262 return status;
263 } else {
264 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
265 return -1;
266 }
267 return 0;
268 }
269
270 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
271 {
272 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
273
274 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
275 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
276 return -1;
277 else
278 return 0;
279 }
280
281 int be_cmd_POST(struct be_adapter *adapter)
282 {
283 u16 stage;
284 int status, timeout = 0;
285
286 do {
287 status = be_POST_stage_get(adapter, &stage);
288 if (status) {
289 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
290 stage);
291 return -1;
292 } else if (stage != POST_STAGE_ARMFW_RDY) {
293 set_current_state(TASK_INTERRUPTIBLE);
294 schedule_timeout(2 * HZ);
295 timeout += 2;
296 } else {
297 return 0;
298 }
299 } while (timeout < 40);
300
301 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
302 return -1;
303 }
304
305 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
306 {
307 return wrb->payload.embedded_payload;
308 }
309
310 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
311 {
312 return &wrb->payload.sgl[0];
313 }
314
315 /* Don't touch the hdr after it's prepared */
316 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
317 bool embedded, u8 sge_cnt, u32 opcode)
318 {
319 if (embedded)
320 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
321 else
322 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
323 MCC_WRB_SGE_CNT_SHIFT;
324 wrb->payload_length = payload_len;
325 wrb->tag0 = opcode;
326 be_dws_cpu_to_le(wrb, 8);
327 }
328
329 /* Don't touch the hdr after it's prepared */
330 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
331 u8 subsystem, u8 opcode, int cmd_len)
332 {
333 req_hdr->opcode = opcode;
334 req_hdr->subsystem = subsystem;
335 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
336 req_hdr->version = 0;
337 }
338
339 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
340 struct be_dma_mem *mem)
341 {
342 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
343 u64 dma = (u64)mem->dma;
344
345 for (i = 0; i < buf_pages; i++) {
346 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
347 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
348 dma += PAGE_SIZE_4K;
349 }
350 }
351
352 /* Converts interrupt delay in microseconds to multiplier value */
353 static u32 eq_delay_to_mult(u32 usec_delay)
354 {
355 #define MAX_INTR_RATE 651042
356 const u32 round = 10;
357 u32 multiplier;
358
359 if (usec_delay == 0)
360 multiplier = 0;
361 else {
362 u32 interrupt_rate = 1000000 / usec_delay;
363 /* Max delay, corresponding to the lowest interrupt rate */
364 if (interrupt_rate == 0)
365 multiplier = 1023;
366 else {
367 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
368 multiplier /= interrupt_rate;
369 /* Round the multiplier to the closest value.*/
370 multiplier = (multiplier + round/2) / round;
371 multiplier = min(multiplier, (u32)1023);
372 }
373 }
374 return multiplier;
375 }
376
377 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
378 {
379 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
380 struct be_mcc_wrb *wrb
381 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
382 memset(wrb, 0, sizeof(*wrb));
383 return wrb;
384 }
385
386 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
387 {
388 struct be_queue_info *mccq = &adapter->mcc_obj.q;
389 struct be_mcc_wrb *wrb;
390
391 if (atomic_read(&mccq->used) >= mccq->len) {
392 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
393 return NULL;
394 }
395
396 wrb = queue_head_node(mccq);
397 queue_head_inc(mccq);
398 atomic_inc(&mccq->used);
399 memset(wrb, 0, sizeof(*wrb));
400 return wrb;
401 }
402
403 /* Tell fw we're about to start firing cmds by writing a
404 * special pattern across the wrb hdr; uses mbox
405 */
406 int be_cmd_fw_init(struct be_adapter *adapter)
407 {
408 u8 *wrb;
409 int status;
410
411 spin_lock(&adapter->mbox_lock);
412
413 wrb = (u8 *)wrb_from_mbox(adapter);
414 *wrb++ = 0xFF;
415 *wrb++ = 0x12;
416 *wrb++ = 0x34;
417 *wrb++ = 0xFF;
418 *wrb++ = 0xFF;
419 *wrb++ = 0x56;
420 *wrb++ = 0x78;
421 *wrb = 0xFF;
422
423 status = be_mbox_notify_wait(adapter);
424
425 spin_unlock(&adapter->mbox_lock);
426 return status;
427 }
428
429 /* Tell fw we're done with firing cmds by writing a
430 * special pattern across the wrb hdr; uses mbox
431 */
432 int be_cmd_fw_clean(struct be_adapter *adapter)
433 {
434 u8 *wrb;
435 int status;
436
437 if (adapter->eeh_err)
438 return -EIO;
439
440 spin_lock(&adapter->mbox_lock);
441
442 wrb = (u8 *)wrb_from_mbox(adapter);
443 *wrb++ = 0xFF;
444 *wrb++ = 0xAA;
445 *wrb++ = 0xBB;
446 *wrb++ = 0xFF;
447 *wrb++ = 0xFF;
448 *wrb++ = 0xCC;
449 *wrb++ = 0xDD;
450 *wrb = 0xFF;
451
452 status = be_mbox_notify_wait(adapter);
453
454 spin_unlock(&adapter->mbox_lock);
455 return status;
456 }
457 int be_cmd_eq_create(struct be_adapter *adapter,
458 struct be_queue_info *eq, int eq_delay)
459 {
460 struct be_mcc_wrb *wrb;
461 struct be_cmd_req_eq_create *req;
462 struct be_dma_mem *q_mem = &eq->dma_mem;
463 int status;
464
465 spin_lock(&adapter->mbox_lock);
466
467 wrb = wrb_from_mbox(adapter);
468 req = embedded_payload(wrb);
469
470 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
471
472 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
473 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
474
475 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
476
477 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
478 /* 4byte eqe*/
479 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
480 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
481 __ilog2_u32(eq->len/256));
482 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
483 eq_delay_to_mult(eq_delay));
484 be_dws_cpu_to_le(req->context, sizeof(req->context));
485
486 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
487
488 status = be_mbox_notify_wait(adapter);
489 if (!status) {
490 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
491 eq->id = le16_to_cpu(resp->eq_id);
492 eq->created = true;
493 }
494
495 spin_unlock(&adapter->mbox_lock);
496 return status;
497 }
498
499 /* Uses mbox */
500 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
501 u8 type, bool permanent, u32 if_handle)
502 {
503 struct be_mcc_wrb *wrb;
504 struct be_cmd_req_mac_query *req;
505 int status;
506
507 spin_lock(&adapter->mbox_lock);
508
509 wrb = wrb_from_mbox(adapter);
510 req = embedded_payload(wrb);
511
512 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
513 OPCODE_COMMON_NTWK_MAC_QUERY);
514
515 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
516 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
517
518 req->type = type;
519 if (permanent) {
520 req->permanent = 1;
521 } else {
522 req->if_id = cpu_to_le16((u16) if_handle);
523 req->permanent = 0;
524 }
525
526 status = be_mbox_notify_wait(adapter);
527 if (!status) {
528 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
529 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
530 }
531
532 spin_unlock(&adapter->mbox_lock);
533 return status;
534 }
535
536 /* Uses synchronous MCCQ */
537 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
538 u32 if_id, u32 *pmac_id)
539 {
540 struct be_mcc_wrb *wrb;
541 struct be_cmd_req_pmac_add *req;
542 int status;
543
544 spin_lock_bh(&adapter->mcc_lock);
545
546 wrb = wrb_from_mccq(adapter);
547 if (!wrb) {
548 status = -EBUSY;
549 goto err;
550 }
551 req = embedded_payload(wrb);
552
553 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
554 OPCODE_COMMON_NTWK_PMAC_ADD);
555
556 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
557 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
558
559 req->if_id = cpu_to_le32(if_id);
560 memcpy(req->mac_address, mac_addr, ETH_ALEN);
561
562 status = be_mcc_notify_wait(adapter);
563 if (!status) {
564 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
565 *pmac_id = le32_to_cpu(resp->pmac_id);
566 }
567
568 err:
569 spin_unlock_bh(&adapter->mcc_lock);
570 return status;
571 }
572
573 /* Uses synchronous MCCQ */
574 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
575 {
576 struct be_mcc_wrb *wrb;
577 struct be_cmd_req_pmac_del *req;
578 int status;
579
580 spin_lock_bh(&adapter->mcc_lock);
581
582 wrb = wrb_from_mccq(adapter);
583 if (!wrb) {
584 status = -EBUSY;
585 goto err;
586 }
587 req = embedded_payload(wrb);
588
589 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
590 OPCODE_COMMON_NTWK_PMAC_DEL);
591
592 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
593 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
594
595 req->if_id = cpu_to_le32(if_id);
596 req->pmac_id = cpu_to_le32(pmac_id);
597
598 status = be_mcc_notify_wait(adapter);
599
600 err:
601 spin_unlock_bh(&adapter->mcc_lock);
602 return status;
603 }
604
605 /* Uses Mbox */
606 int be_cmd_cq_create(struct be_adapter *adapter,
607 struct be_queue_info *cq, struct be_queue_info *eq,
608 bool sol_evts, bool no_delay, int coalesce_wm)
609 {
610 struct be_mcc_wrb *wrb;
611 struct be_cmd_req_cq_create *req;
612 struct be_dma_mem *q_mem = &cq->dma_mem;
613 void *ctxt;
614 int status;
615
616 spin_lock(&adapter->mbox_lock);
617
618 wrb = wrb_from_mbox(adapter);
619 req = embedded_payload(wrb);
620 ctxt = &req->context;
621
622 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
623 OPCODE_COMMON_CQ_CREATE);
624
625 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
626 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
627
628 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
629
630 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
631 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
632 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
633 __ilog2_u32(cq->len/256));
634 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
635 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
636 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
637 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
638 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
639 be_dws_cpu_to_le(ctxt, sizeof(req->context));
640
641 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
642
643 status = be_mbox_notify_wait(adapter);
644 if (!status) {
645 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
646 cq->id = le16_to_cpu(resp->cq_id);
647 cq->created = true;
648 }
649
650 spin_unlock(&adapter->mbox_lock);
651
652 return status;
653 }
654
655 static u32 be_encoded_q_len(int q_len)
656 {
657 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
658 if (len_encoded == 16)
659 len_encoded = 0;
660 return len_encoded;
661 }
662
663 int be_cmd_mccq_create(struct be_adapter *adapter,
664 struct be_queue_info *mccq,
665 struct be_queue_info *cq)
666 {
667 struct be_mcc_wrb *wrb;
668 struct be_cmd_req_mcc_create *req;
669 struct be_dma_mem *q_mem = &mccq->dma_mem;
670 void *ctxt;
671 int status;
672
673 spin_lock(&adapter->mbox_lock);
674
675 wrb = wrb_from_mbox(adapter);
676 req = embedded_payload(wrb);
677 ctxt = &req->context;
678
679 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
680 OPCODE_COMMON_MCC_CREATE);
681
682 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
683 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
684
685 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
686
687 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
688 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
689 be_encoded_q_len(mccq->len));
690 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
691
692 be_dws_cpu_to_le(ctxt, sizeof(req->context));
693
694 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
695
696 status = be_mbox_notify_wait(adapter);
697 if (!status) {
698 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
699 mccq->id = le16_to_cpu(resp->id);
700 mccq->created = true;
701 }
702 spin_unlock(&adapter->mbox_lock);
703
704 return status;
705 }
706
707 int be_cmd_txq_create(struct be_adapter *adapter,
708 struct be_queue_info *txq,
709 struct be_queue_info *cq)
710 {
711 struct be_mcc_wrb *wrb;
712 struct be_cmd_req_eth_tx_create *req;
713 struct be_dma_mem *q_mem = &txq->dma_mem;
714 void *ctxt;
715 int status;
716
717 spin_lock(&adapter->mbox_lock);
718
719 wrb = wrb_from_mbox(adapter);
720 req = embedded_payload(wrb);
721 ctxt = &req->context;
722
723 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
724 OPCODE_ETH_TX_CREATE);
725
726 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
727 sizeof(*req));
728
729 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
730 req->ulp_num = BE_ULP1_NUM;
731 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
732
733 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
734 be_encoded_q_len(txq->len));
735 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
736 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
737
738 be_dws_cpu_to_le(ctxt, sizeof(req->context));
739
740 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
741
742 status = be_mbox_notify_wait(adapter);
743 if (!status) {
744 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
745 txq->id = le16_to_cpu(resp->cid);
746 txq->created = true;
747 }
748
749 spin_unlock(&adapter->mbox_lock);
750
751 return status;
752 }
753
754 /* Uses mbox */
755 int be_cmd_rxq_create(struct be_adapter *adapter,
756 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
757 u16 max_frame_size, u32 if_id, u32 rss)
758 {
759 struct be_mcc_wrb *wrb;
760 struct be_cmd_req_eth_rx_create *req;
761 struct be_dma_mem *q_mem = &rxq->dma_mem;
762 int status;
763
764 spin_lock(&adapter->mbox_lock);
765
766 wrb = wrb_from_mbox(adapter);
767 req = embedded_payload(wrb);
768
769 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
770 OPCODE_ETH_RX_CREATE);
771
772 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
773 sizeof(*req));
774
775 req->cq_id = cpu_to_le16(cq_id);
776 req->frag_size = fls(frag_size) - 1;
777 req->num_pages = 2;
778 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
779 req->interface_id = cpu_to_le32(if_id);
780 req->max_frame_size = cpu_to_le16(max_frame_size);
781 req->rss_queue = cpu_to_le32(rss);
782
783 status = be_mbox_notify_wait(adapter);
784 if (!status) {
785 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
786 rxq->id = le16_to_cpu(resp->id);
787 rxq->created = true;
788 }
789
790 spin_unlock(&adapter->mbox_lock);
791
792 return status;
793 }
794
795 /* Generic destroyer function for all types of queues
796 * Uses Mbox
797 */
798 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
799 int queue_type)
800 {
801 struct be_mcc_wrb *wrb;
802 struct be_cmd_req_q_destroy *req;
803 u8 subsys = 0, opcode = 0;
804 int status;
805
806 if (adapter->eeh_err)
807 return -EIO;
808
809 spin_lock(&adapter->mbox_lock);
810
811 wrb = wrb_from_mbox(adapter);
812 req = embedded_payload(wrb);
813
814 switch (queue_type) {
815 case QTYPE_EQ:
816 subsys = CMD_SUBSYSTEM_COMMON;
817 opcode = OPCODE_COMMON_EQ_DESTROY;
818 break;
819 case QTYPE_CQ:
820 subsys = CMD_SUBSYSTEM_COMMON;
821 opcode = OPCODE_COMMON_CQ_DESTROY;
822 break;
823 case QTYPE_TXQ:
824 subsys = CMD_SUBSYSTEM_ETH;
825 opcode = OPCODE_ETH_TX_DESTROY;
826 break;
827 case QTYPE_RXQ:
828 subsys = CMD_SUBSYSTEM_ETH;
829 opcode = OPCODE_ETH_RX_DESTROY;
830 break;
831 case QTYPE_MCCQ:
832 subsys = CMD_SUBSYSTEM_COMMON;
833 opcode = OPCODE_COMMON_MCC_DESTROY;
834 break;
835 default:
836 BUG();
837 }
838
839 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
840
841 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
842 req->id = cpu_to_le16(q->id);
843
844 status = be_mbox_notify_wait(adapter);
845
846 spin_unlock(&adapter->mbox_lock);
847
848 return status;
849 }
850
851 /* Create an rx filtering policy configuration on an i/f
852 * Uses mbox
853 */
854 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
855 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
856 u32 domain)
857 {
858 struct be_mcc_wrb *wrb;
859 struct be_cmd_req_if_create *req;
860 int status;
861
862 spin_lock(&adapter->mbox_lock);
863
864 wrb = wrb_from_mbox(adapter);
865 req = embedded_payload(wrb);
866
867 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
868 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
869
870 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
872
873 req->hdr.domain = domain;
874 req->capability_flags = cpu_to_le32(cap_flags);
875 req->enable_flags = cpu_to_le32(en_flags);
876 req->pmac_invalid = pmac_invalid;
877 if (!pmac_invalid)
878 memcpy(req->mac_addr, mac, ETH_ALEN);
879
880 status = be_mbox_notify_wait(adapter);
881 if (!status) {
882 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
883 *if_handle = le32_to_cpu(resp->interface_id);
884 if (!pmac_invalid)
885 *pmac_id = le32_to_cpu(resp->pmac_id);
886 }
887
888 spin_unlock(&adapter->mbox_lock);
889 return status;
890 }
891
892 /* Uses mbox */
893 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
894 {
895 struct be_mcc_wrb *wrb;
896 struct be_cmd_req_if_destroy *req;
897 int status;
898
899 if (adapter->eeh_err)
900 return -EIO;
901
902 spin_lock(&adapter->mbox_lock);
903
904 wrb = wrb_from_mbox(adapter);
905 req = embedded_payload(wrb);
906
907 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
908 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
909
910 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
911 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
912
913 req->interface_id = cpu_to_le32(interface_id);
914
915 status = be_mbox_notify_wait(adapter);
916
917 spin_unlock(&adapter->mbox_lock);
918
919 return status;
920 }
921
922 /* Get stats is a non embedded command: the request is not embedded inside
923 * WRB but is a separate dma memory block
924 * Uses asynchronous MCC
925 */
926 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
927 {
928 struct be_mcc_wrb *wrb;
929 struct be_cmd_req_get_stats *req;
930 struct be_sge *sge;
931 int status = 0;
932
933 spin_lock_bh(&adapter->mcc_lock);
934
935 wrb = wrb_from_mccq(adapter);
936 if (!wrb) {
937 status = -EBUSY;
938 goto err;
939 }
940 req = nonemb_cmd->va;
941 sge = nonembedded_sgl(wrb);
942
943 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
944 OPCODE_ETH_GET_STATISTICS);
945
946 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
947 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
948 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
949 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
950 sge->len = cpu_to_le32(nonemb_cmd->size);
951
952 be_mcc_notify(adapter);
953
954 err:
955 spin_unlock_bh(&adapter->mcc_lock);
956 return status;
957 }
958
959 /* Uses synchronous mcc */
960 int be_cmd_link_status_query(struct be_adapter *adapter,
961 bool *link_up, u8 *mac_speed, u16 *link_speed)
962 {
963 struct be_mcc_wrb *wrb;
964 struct be_cmd_req_link_status *req;
965 int status;
966
967 spin_lock_bh(&adapter->mcc_lock);
968
969 wrb = wrb_from_mccq(adapter);
970 if (!wrb) {
971 status = -EBUSY;
972 goto err;
973 }
974 req = embedded_payload(wrb);
975
976 *link_up = false;
977
978 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
979 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
980
981 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
982 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
983
984 status = be_mcc_notify_wait(adapter);
985 if (!status) {
986 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
987 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
988 *link_up = true;
989 *link_speed = le16_to_cpu(resp->link_speed);
990 *mac_speed = resp->mac_speed;
991 }
992 }
993
994 err:
995 spin_unlock_bh(&adapter->mcc_lock);
996 return status;
997 }
998
999 /* Uses Mbox */
1000 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1001 {
1002 struct be_mcc_wrb *wrb;
1003 struct be_cmd_req_get_fw_version *req;
1004 int status;
1005
1006 spin_lock(&adapter->mbox_lock);
1007
1008 wrb = wrb_from_mbox(adapter);
1009 req = embedded_payload(wrb);
1010
1011 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1012 OPCODE_COMMON_GET_FW_VERSION);
1013
1014 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1015 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1016
1017 status = be_mbox_notify_wait(adapter);
1018 if (!status) {
1019 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1020 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1021 }
1022
1023 spin_unlock(&adapter->mbox_lock);
1024 return status;
1025 }
1026
1027 /* set the EQ delay interval of an EQ to specified value
1028 * Uses async mcc
1029 */
1030 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1031 {
1032 struct be_mcc_wrb *wrb;
1033 struct be_cmd_req_modify_eq_delay *req;
1034 int status = 0;
1035
1036 spin_lock_bh(&adapter->mcc_lock);
1037
1038 wrb = wrb_from_mccq(adapter);
1039 if (!wrb) {
1040 status = -EBUSY;
1041 goto err;
1042 }
1043 req = embedded_payload(wrb);
1044
1045 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1046 OPCODE_COMMON_MODIFY_EQ_DELAY);
1047
1048 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1049 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1050
1051 req->num_eq = cpu_to_le32(1);
1052 req->delay[0].eq_id = cpu_to_le32(eq_id);
1053 req->delay[0].phase = 0;
1054 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1055
1056 be_mcc_notify(adapter);
1057
1058 err:
1059 spin_unlock_bh(&adapter->mcc_lock);
1060 return status;
1061 }
1062
1063 /* Uses sycnhronous mcc */
1064 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1065 u32 num, bool untagged, bool promiscuous)
1066 {
1067 struct be_mcc_wrb *wrb;
1068 struct be_cmd_req_vlan_config *req;
1069 int status;
1070
1071 spin_lock_bh(&adapter->mcc_lock);
1072
1073 wrb = wrb_from_mccq(adapter);
1074 if (!wrb) {
1075 status = -EBUSY;
1076 goto err;
1077 }
1078 req = embedded_payload(wrb);
1079
1080 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1081 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1082
1083 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1084 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1085
1086 req->interface_id = if_id;
1087 req->promiscuous = promiscuous;
1088 req->untagged = untagged;
1089 req->num_vlan = num;
1090 if (!promiscuous) {
1091 memcpy(req->normal_vlan, vtag_array,
1092 req->num_vlan * sizeof(vtag_array[0]));
1093 }
1094
1095 status = be_mcc_notify_wait(adapter);
1096
1097 err:
1098 spin_unlock_bh(&adapter->mcc_lock);
1099 return status;
1100 }
1101
1102 /* Uses MCC for this command as it may be called in BH context
1103 * Uses synchronous mcc
1104 */
1105 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1106 {
1107 struct be_mcc_wrb *wrb;
1108 struct be_cmd_req_promiscuous_config *req;
1109 int status;
1110
1111 spin_lock_bh(&adapter->mcc_lock);
1112
1113 wrb = wrb_from_mccq(adapter);
1114 if (!wrb) {
1115 status = -EBUSY;
1116 goto err;
1117 }
1118 req = embedded_payload(wrb);
1119
1120 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1121
1122 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1123 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1124
1125 /* In FW versions X.102.149/X.101.487 and later,
1126 * the port setting associated only with the
1127 * issuing pci function will take effect
1128 */
1129 if (port_num)
1130 req->port1_promiscuous = en;
1131 else
1132 req->port0_promiscuous = en;
1133
1134 status = be_mcc_notify_wait(adapter);
1135
1136 err:
1137 spin_unlock_bh(&adapter->mcc_lock);
1138 return status;
1139 }
1140
1141 /*
1142 * Uses MCC for this command as it may be called in BH context
1143 * (mc == NULL) => multicast promiscous
1144 */
1145 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1146 struct net_device *netdev, struct be_dma_mem *mem)
1147 {
1148 struct be_mcc_wrb *wrb;
1149 struct be_cmd_req_mcast_mac_config *req = mem->va;
1150 struct be_sge *sge;
1151 int status;
1152
1153 spin_lock_bh(&adapter->mcc_lock);
1154
1155 wrb = wrb_from_mccq(adapter);
1156 if (!wrb) {
1157 status = -EBUSY;
1158 goto err;
1159 }
1160 sge = nonembedded_sgl(wrb);
1161 memset(req, 0, sizeof(*req));
1162
1163 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1164 OPCODE_COMMON_NTWK_MULTICAST_SET);
1165 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1166 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1167 sge->len = cpu_to_le32(mem->size);
1168
1169 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1170 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1171
1172 req->interface_id = if_id;
1173 if (netdev) {
1174 int i;
1175 struct netdev_hw_addr *ha;
1176
1177 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1178
1179 i = 0;
1180 netdev_for_each_mc_addr(ha, netdev)
1181 memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1182 } else {
1183 req->promiscuous = 1;
1184 }
1185
1186 status = be_mcc_notify_wait(adapter);
1187
1188 err:
1189 spin_unlock_bh(&adapter->mcc_lock);
1190 return status;
1191 }
1192
1193 /* Uses synchrounous mcc */
1194 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1195 {
1196 struct be_mcc_wrb *wrb;
1197 struct be_cmd_req_set_flow_control *req;
1198 int status;
1199
1200 spin_lock_bh(&adapter->mcc_lock);
1201
1202 wrb = wrb_from_mccq(adapter);
1203 if (!wrb) {
1204 status = -EBUSY;
1205 goto err;
1206 }
1207 req = embedded_payload(wrb);
1208
1209 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1210 OPCODE_COMMON_SET_FLOW_CONTROL);
1211
1212 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1213 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1214
1215 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1216 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1217
1218 status = be_mcc_notify_wait(adapter);
1219
1220 err:
1221 spin_unlock_bh(&adapter->mcc_lock);
1222 return status;
1223 }
1224
1225 /* Uses sycn mcc */
1226 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1227 {
1228 struct be_mcc_wrb *wrb;
1229 struct be_cmd_req_get_flow_control *req;
1230 int status;
1231
1232 spin_lock_bh(&adapter->mcc_lock);
1233
1234 wrb = wrb_from_mccq(adapter);
1235 if (!wrb) {
1236 status = -EBUSY;
1237 goto err;
1238 }
1239 req = embedded_payload(wrb);
1240
1241 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1242 OPCODE_COMMON_GET_FLOW_CONTROL);
1243
1244 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1245 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1246
1247 status = be_mcc_notify_wait(adapter);
1248 if (!status) {
1249 struct be_cmd_resp_get_flow_control *resp =
1250 embedded_payload(wrb);
1251 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1252 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1253 }
1254
1255 err:
1256 spin_unlock_bh(&adapter->mcc_lock);
1257 return status;
1258 }
1259
1260 /* Uses mbox */
1261 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *mode)
1262 {
1263 struct be_mcc_wrb *wrb;
1264 struct be_cmd_req_query_fw_cfg *req;
1265 int status;
1266
1267 spin_lock(&adapter->mbox_lock);
1268
1269 wrb = wrb_from_mbox(adapter);
1270 req = embedded_payload(wrb);
1271
1272 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1273 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1274
1275 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1276 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1277
1278 status = be_mbox_notify_wait(adapter);
1279 if (!status) {
1280 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1281 *port_num = le32_to_cpu(resp->phys_port);
1282 *mode = le32_to_cpu(resp->function_mode);
1283 }
1284
1285 spin_unlock(&adapter->mbox_lock);
1286 return status;
1287 }
1288
1289 /* Uses mbox */
1290 int be_cmd_reset_function(struct be_adapter *adapter)
1291 {
1292 struct be_mcc_wrb *wrb;
1293 struct be_cmd_req_hdr *req;
1294 int status;
1295
1296 spin_lock(&adapter->mbox_lock);
1297
1298 wrb = wrb_from_mbox(adapter);
1299 req = embedded_payload(wrb);
1300
1301 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1302 OPCODE_COMMON_FUNCTION_RESET);
1303
1304 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1305 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1306
1307 status = be_mbox_notify_wait(adapter);
1308
1309 spin_unlock(&adapter->mbox_lock);
1310 return status;
1311 }
1312
1313 /* Uses sync mcc */
1314 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1315 u8 bcn, u8 sts, u8 state)
1316 {
1317 struct be_mcc_wrb *wrb;
1318 struct be_cmd_req_enable_disable_beacon *req;
1319 int status;
1320
1321 spin_lock_bh(&adapter->mcc_lock);
1322
1323 wrb = wrb_from_mccq(adapter);
1324 if (!wrb) {
1325 status = -EBUSY;
1326 goto err;
1327 }
1328 req = embedded_payload(wrb);
1329
1330 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1331 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1332
1333 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1334 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1335
1336 req->port_num = port_num;
1337 req->beacon_state = state;
1338 req->beacon_duration = bcn;
1339 req->status_duration = sts;
1340
1341 status = be_mcc_notify_wait(adapter);
1342
1343 err:
1344 spin_unlock_bh(&adapter->mcc_lock);
1345 return status;
1346 }
1347
1348 /* Uses sync mcc */
1349 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1350 {
1351 struct be_mcc_wrb *wrb;
1352 struct be_cmd_req_get_beacon_state *req;
1353 int status;
1354
1355 spin_lock_bh(&adapter->mcc_lock);
1356
1357 wrb = wrb_from_mccq(adapter);
1358 if (!wrb) {
1359 status = -EBUSY;
1360 goto err;
1361 }
1362 req = embedded_payload(wrb);
1363
1364 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1365 OPCODE_COMMON_GET_BEACON_STATE);
1366
1367 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1368 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1369
1370 req->port_num = port_num;
1371
1372 status = be_mcc_notify_wait(adapter);
1373 if (!status) {
1374 struct be_cmd_resp_get_beacon_state *resp =
1375 embedded_payload(wrb);
1376 *state = resp->beacon_state;
1377 }
1378
1379 err:
1380 spin_unlock_bh(&adapter->mcc_lock);
1381 return status;
1382 }
1383
1384 /* Uses sync mcc */
1385 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1386 u8 *connector)
1387 {
1388 struct be_mcc_wrb *wrb;
1389 struct be_cmd_req_port_type *req;
1390 int status;
1391
1392 spin_lock_bh(&adapter->mcc_lock);
1393
1394 wrb = wrb_from_mccq(adapter);
1395 if (!wrb) {
1396 status = -EBUSY;
1397 goto err;
1398 }
1399 req = embedded_payload(wrb);
1400
1401 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1402 OPCODE_COMMON_READ_TRANSRECV_DATA);
1403
1404 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1405 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1406
1407 req->port = cpu_to_le32(port);
1408 req->page_num = cpu_to_le32(TR_PAGE_A0);
1409 status = be_mcc_notify_wait(adapter);
1410 if (!status) {
1411 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1412 *connector = resp->data.connector;
1413 }
1414
1415 err:
1416 spin_unlock_bh(&adapter->mcc_lock);
1417 return status;
1418 }
1419
1420 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1421 u32 flash_type, u32 flash_opcode, u32 buf_size)
1422 {
1423 struct be_mcc_wrb *wrb;
1424 struct be_cmd_write_flashrom *req;
1425 struct be_sge *sge;
1426 int status;
1427
1428 spin_lock_bh(&adapter->mcc_lock);
1429 adapter->flash_status = 0;
1430
1431 wrb = wrb_from_mccq(adapter);
1432 if (!wrb) {
1433 status = -EBUSY;
1434 goto err_unlock;
1435 }
1436 req = cmd->va;
1437 sge = nonembedded_sgl(wrb);
1438
1439 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1440 OPCODE_COMMON_WRITE_FLASHROM);
1441 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1442
1443 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1444 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1445 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1446 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1447 sge->len = cpu_to_le32(cmd->size);
1448
1449 req->params.op_type = cpu_to_le32(flash_type);
1450 req->params.op_code = cpu_to_le32(flash_opcode);
1451 req->params.data_buf_size = cpu_to_le32(buf_size);
1452
1453 be_mcc_notify(adapter);
1454 spin_unlock_bh(&adapter->mcc_lock);
1455
1456 if (!wait_for_completion_timeout(&adapter->flash_compl,
1457 msecs_to_jiffies(12000)))
1458 status = -1;
1459 else
1460 status = adapter->flash_status;
1461
1462 return status;
1463
1464 err_unlock:
1465 spin_unlock_bh(&adapter->mcc_lock);
1466 return status;
1467 }
1468
1469 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1470 int offset)
1471 {
1472 struct be_mcc_wrb *wrb;
1473 struct be_cmd_write_flashrom *req;
1474 int status;
1475
1476 spin_lock_bh(&adapter->mcc_lock);
1477
1478 wrb = wrb_from_mccq(adapter);
1479 if (!wrb) {
1480 status = -EBUSY;
1481 goto err;
1482 }
1483 req = embedded_payload(wrb);
1484
1485 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1486 OPCODE_COMMON_READ_FLASHROM);
1487
1488 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1490
1491 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1492 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1493 req->params.offset = cpu_to_le32(offset);
1494 req->params.data_buf_size = cpu_to_le32(0x4);
1495
1496 status = be_mcc_notify_wait(adapter);
1497 if (!status)
1498 memcpy(flashed_crc, req->params.data_buf, 4);
1499
1500 err:
1501 spin_unlock_bh(&adapter->mcc_lock);
1502 return status;
1503 }
1504
1505 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1506 struct be_dma_mem *nonemb_cmd)
1507 {
1508 struct be_mcc_wrb *wrb;
1509 struct be_cmd_req_acpi_wol_magic_config *req;
1510 struct be_sge *sge;
1511 int status;
1512
1513 spin_lock_bh(&adapter->mcc_lock);
1514
1515 wrb = wrb_from_mccq(adapter);
1516 if (!wrb) {
1517 status = -EBUSY;
1518 goto err;
1519 }
1520 req = nonemb_cmd->va;
1521 sge = nonembedded_sgl(wrb);
1522
1523 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1524 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1525
1526 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1527 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1528 memcpy(req->magic_mac, mac, ETH_ALEN);
1529
1530 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1531 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1532 sge->len = cpu_to_le32(nonemb_cmd->size);
1533
1534 status = be_mcc_notify_wait(adapter);
1535
1536 err:
1537 spin_unlock_bh(&adapter->mcc_lock);
1538 return status;
1539 }
1540
1541 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1542 u8 loopback_type, u8 enable)
1543 {
1544 struct be_mcc_wrb *wrb;
1545 struct be_cmd_req_set_lmode *req;
1546 int status;
1547
1548 spin_lock_bh(&adapter->mcc_lock);
1549
1550 wrb = wrb_from_mccq(adapter);
1551 if (!wrb) {
1552 status = -EBUSY;
1553 goto err;
1554 }
1555
1556 req = embedded_payload(wrb);
1557
1558 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1559 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1560
1561 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1562 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1563 sizeof(*req));
1564
1565 req->src_port = port_num;
1566 req->dest_port = port_num;
1567 req->loopback_type = loopback_type;
1568 req->loopback_state = enable;
1569
1570 status = be_mcc_notify_wait(adapter);
1571 err:
1572 spin_unlock_bh(&adapter->mcc_lock);
1573 return status;
1574 }
1575
1576 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1577 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1578 {
1579 struct be_mcc_wrb *wrb;
1580 struct be_cmd_req_loopback_test *req;
1581 int status;
1582
1583 spin_lock_bh(&adapter->mcc_lock);
1584
1585 wrb = wrb_from_mccq(adapter);
1586 if (!wrb) {
1587 status = -EBUSY;
1588 goto err;
1589 }
1590
1591 req = embedded_payload(wrb);
1592
1593 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1594 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1595
1596 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1597 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1598 req->hdr.timeout = cpu_to_le32(4);
1599
1600 req->pattern = cpu_to_le64(pattern);
1601 req->src_port = cpu_to_le32(port_num);
1602 req->dest_port = cpu_to_le32(port_num);
1603 req->pkt_size = cpu_to_le32(pkt_size);
1604 req->num_pkts = cpu_to_le32(num_pkts);
1605 req->loopback_type = cpu_to_le32(loopback_type);
1606
1607 status = be_mcc_notify_wait(adapter);
1608 if (!status) {
1609 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1610 status = le32_to_cpu(resp->status);
1611 }
1612
1613 err:
1614 spin_unlock_bh(&adapter->mcc_lock);
1615 return status;
1616 }
1617
1618 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1619 u32 byte_cnt, struct be_dma_mem *cmd)
1620 {
1621 struct be_mcc_wrb *wrb;
1622 struct be_cmd_req_ddrdma_test *req;
1623 struct be_sge *sge;
1624 int status;
1625 int i, j = 0;
1626
1627 spin_lock_bh(&adapter->mcc_lock);
1628
1629 wrb = wrb_from_mccq(adapter);
1630 if (!wrb) {
1631 status = -EBUSY;
1632 goto err;
1633 }
1634 req = cmd->va;
1635 sge = nonembedded_sgl(wrb);
1636 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1637 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1638 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1639 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1640
1641 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1642 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1643 sge->len = cpu_to_le32(cmd->size);
1644
1645 req->pattern = cpu_to_le64(pattern);
1646 req->byte_count = cpu_to_le32(byte_cnt);
1647 for (i = 0; i < byte_cnt; i++) {
1648 req->snd_buff[i] = (u8)(pattern >> (j*8));
1649 j++;
1650 if (j > 7)
1651 j = 0;
1652 }
1653
1654 status = be_mcc_notify_wait(adapter);
1655
1656 if (!status) {
1657 struct be_cmd_resp_ddrdma_test *resp;
1658 resp = cmd->va;
1659 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1660 resp->snd_err) {
1661 status = -1;
1662 }
1663 }
1664
1665 err:
1666 spin_unlock_bh(&adapter->mcc_lock);
1667 return status;
1668 }
1669
1670 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1671 struct be_dma_mem *nonemb_cmd)
1672 {
1673 struct be_mcc_wrb *wrb;
1674 struct be_cmd_req_seeprom_read *req;
1675 struct be_sge *sge;
1676 int status;
1677
1678 spin_lock_bh(&adapter->mcc_lock);
1679
1680 wrb = wrb_from_mccq(adapter);
1681 req = nonemb_cmd->va;
1682 sge = nonembedded_sgl(wrb);
1683
1684 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1685 OPCODE_COMMON_SEEPROM_READ);
1686
1687 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1688 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1689
1690 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1691 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1692 sge->len = cpu_to_le32(nonemb_cmd->size);
1693
1694 status = be_mcc_notify_wait(adapter);
1695
1696 spin_unlock_bh(&adapter->mcc_lock);
1697 return status;
1698 }
1699
1700 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1701 {
1702 struct be_mcc_wrb *wrb;
1703 struct be_cmd_req_get_phy_info *req;
1704 struct be_sge *sge;
1705 int status;
1706
1707 spin_lock_bh(&adapter->mcc_lock);
1708
1709 wrb = wrb_from_mccq(adapter);
1710 if (!wrb) {
1711 status = -EBUSY;
1712 goto err;
1713 }
1714
1715 req = cmd->va;
1716 sge = nonembedded_sgl(wrb);
1717
1718 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1719 OPCODE_COMMON_GET_PHY_DETAILS);
1720
1721 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1722 OPCODE_COMMON_GET_PHY_DETAILS,
1723 sizeof(*req));
1724
1725 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1726 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1727 sge->len = cpu_to_le32(cmd->size);
1728
1729 status = be_mcc_notify_wait(adapter);
1730 err:
1731 spin_unlock_bh(&adapter->mcc_lock);
1732 return status;
1733 }
1734
1735 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1736 {
1737 struct be_mcc_wrb *wrb;
1738 struct be_cmd_req_set_qos *req;
1739 int status;
1740
1741 spin_lock_bh(&adapter->mcc_lock);
1742
1743 wrb = wrb_from_mccq(adapter);
1744 if (!wrb) {
1745 status = -EBUSY;
1746 goto err;
1747 }
1748
1749 req = embedded_payload(wrb);
1750
1751 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1752 OPCODE_COMMON_SET_QOS);
1753
1754 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1755 OPCODE_COMMON_SET_QOS, sizeof(*req));
1756
1757 req->hdr.domain = domain;
1758 req->valid_bits = BE_QOS_BITS_NIC;
1759 req->max_bps_nic = bps;
1760
1761 status = be_mcc_notify_wait(adapter);
1762
1763 err:
1764 spin_unlock_bh(&adapter->mcc_lock);
1765 return status;
1766 }
Linux kernel - Deliverables
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