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be2net: add code to dump registers for debug
[deliverable/linux.git] / drivers / net / benet / be_cmds.c
1 /*
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 static void be_mcc_notify(struct be_adapter *adapter)
22 {
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
24 u32 val = 0;
25
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28
29 wmb();
30 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
31 }
32
33 /* To check if valid bit is set, check the entire word as we don't know
34 * the endianness of the data (old entry is host endian while a new entry is
35 * little endian) */
36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
37 {
38 if (compl->flags != 0) {
39 compl->flags = le32_to_cpu(compl->flags);
40 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
41 return true;
42 } else {
43 return false;
44 }
45 }
46
47 /* Need to reset the entire word that houses the valid bit */
48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
49 {
50 compl->flags = 0;
51 }
52
53 static int be_mcc_compl_process(struct be_adapter *adapter,
54 struct be_mcc_compl *compl)
55 {
56 u16 compl_status, extd_status;
57
58 /* Just swap the status to host endian; mcc tag is opaquely copied
59 * from mcc_wrb */
60 be_dws_le_to_cpu(compl, 4);
61
62 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
63 CQE_STATUS_COMPL_MASK;
64
65 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
66 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
67 adapter->flash_status = compl_status;
68 complete(&adapter->flash_compl);
69 }
70
71 if (compl_status == MCC_STATUS_SUCCESS) {
72 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
73 struct be_cmd_resp_get_stats *resp =
74 adapter->stats.cmd.va;
75 be_dws_le_to_cpu(&resp->hw_stats,
76 sizeof(resp->hw_stats));
77 netdev_stats_update(adapter);
78 }
79 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
80 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
81 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
82 CQE_STATUS_EXTD_MASK;
83 dev_warn(&adapter->pdev->dev,
84 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
85 compl->tag0, compl_status, extd_status);
86 }
87 return compl_status;
88 }
89
90 /* Link state evt is a string of bytes; no need for endian swapping */
91 static void be_async_link_state_process(struct be_adapter *adapter,
92 struct be_async_event_link_state *evt)
93 {
94 be_link_status_update(adapter,
95 evt->port_link_status == ASYNC_EVENT_LINK_UP);
96 }
97
98 static inline bool is_link_state_evt(u32 trailer)
99 {
100 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
101 ASYNC_TRAILER_EVENT_CODE_MASK) ==
102 ASYNC_EVENT_CODE_LINK_STATE);
103 }
104
105 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
106 {
107 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
108 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
109
110 if (be_mcc_compl_is_new(compl)) {
111 queue_tail_inc(mcc_cq);
112 return compl;
113 }
114 return NULL;
115 }
116
117 void be_async_mcc_enable(struct be_adapter *adapter)
118 {
119 spin_lock_bh(&adapter->mcc_cq_lock);
120
121 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
122 adapter->mcc_obj.rearm_cq = true;
123
124 spin_unlock_bh(&adapter->mcc_cq_lock);
125 }
126
127 void be_async_mcc_disable(struct be_adapter *adapter)
128 {
129 adapter->mcc_obj.rearm_cq = false;
130 }
131
132 int be_process_mcc(struct be_adapter *adapter, int *status)
133 {
134 struct be_mcc_compl *compl;
135 int num = 0;
136 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
137
138 spin_lock_bh(&adapter->mcc_cq_lock);
139 while ((compl = be_mcc_compl_get(adapter))) {
140 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
141 /* Interpret flags as an async trailer */
142 BUG_ON(!is_link_state_evt(compl->flags));
143
144 /* Interpret compl as a async link evt */
145 be_async_link_state_process(adapter,
146 (struct be_async_event_link_state *) compl);
147 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
148 *status = be_mcc_compl_process(adapter, compl);
149 atomic_dec(&mcc_obj->q.used);
150 }
151 be_mcc_compl_use(compl);
152 num++;
153 }
154
155 spin_unlock_bh(&adapter->mcc_cq_lock);
156 return num;
157 }
158
159 /* Wait till no more pending mcc requests are present */
160 static int be_mcc_wait_compl(struct be_adapter *adapter)
161 {
162 #define mcc_timeout 120000 /* 12s timeout */
163 int i, num, status = 0;
164 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
165
166 for (i = 0; i < mcc_timeout; i++) {
167 num = be_process_mcc(adapter, &status);
168 if (num)
169 be_cq_notify(adapter, mcc_obj->cq.id,
170 mcc_obj->rearm_cq, num);
171
172 if (atomic_read(&mcc_obj->q.used) == 0)
173 break;
174 udelay(100);
175 }
176 if (i == mcc_timeout) {
177 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
178 return -1;
179 }
180 return status;
181 }
182
183 /* Notify MCC requests and wait for completion */
184 static int be_mcc_notify_wait(struct be_adapter *adapter)
185 {
186 be_mcc_notify(adapter);
187 return be_mcc_wait_compl(adapter);
188 }
189
190 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
191 {
192 int msecs = 0;
193 u32 ready;
194
195 do {
196 ready = ioread32(db);
197 if (ready == 0xffffffff) {
198 dev_err(&adapter->pdev->dev,
199 "pci slot disconnected\n");
200 return -1;
201 }
202
203 ready &= MPU_MAILBOX_DB_RDY_MASK;
204 if (ready)
205 break;
206
207 if (msecs > 4000) {
208 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
209 be_dump_ue(adapter);
210 return -1;
211 }
212
213 set_current_state(TASK_INTERRUPTIBLE);
214 schedule_timeout(msecs_to_jiffies(1));
215 msecs++;
216 } while (true);
217
218 return 0;
219 }
220
221 /*
222 * Insert the mailbox address into the doorbell in two steps
223 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
224 */
225 static int be_mbox_notify_wait(struct be_adapter *adapter)
226 {
227 int status;
228 u32 val = 0;
229 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
230 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
231 struct be_mcc_mailbox *mbox = mbox_mem->va;
232 struct be_mcc_compl *compl = &mbox->compl;
233
234 /* wait for ready to be set */
235 status = be_mbox_db_ready_wait(adapter, db);
236 if (status != 0)
237 return status;
238
239 val |= MPU_MAILBOX_DB_HI_MASK;
240 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
241 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
242 iowrite32(val, db);
243
244 /* wait for ready to be set */
245 status = be_mbox_db_ready_wait(adapter, db);
246 if (status != 0)
247 return status;
248
249 val = 0;
250 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
251 val |= (u32)(mbox_mem->dma >> 4) << 2;
252 iowrite32(val, db);
253
254 status = be_mbox_db_ready_wait(adapter, db);
255 if (status != 0)
256 return status;
257
258 /* A cq entry has been made now */
259 if (be_mcc_compl_is_new(compl)) {
260 status = be_mcc_compl_process(adapter, &mbox->compl);
261 be_mcc_compl_use(compl);
262 if (status)
263 return status;
264 } else {
265 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
266 return -1;
267 }
268 return 0;
269 }
270
271 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
272 {
273 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
274
275 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
276 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
277 return -1;
278 else
279 return 0;
280 }
281
282 int be_cmd_POST(struct be_adapter *adapter)
283 {
284 u16 stage;
285 int status, timeout = 0;
286
287 do {
288 status = be_POST_stage_get(adapter, &stage);
289 if (status) {
290 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
291 stage);
292 return -1;
293 } else if (stage != POST_STAGE_ARMFW_RDY) {
294 set_current_state(TASK_INTERRUPTIBLE);
295 schedule_timeout(2 * HZ);
296 timeout += 2;
297 } else {
298 return 0;
299 }
300 } while (timeout < 40);
301
302 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
303 return -1;
304 }
305
306 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
307 {
308 return wrb->payload.embedded_payload;
309 }
310
311 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
312 {
313 return &wrb->payload.sgl[0];
314 }
315
316 /* Don't touch the hdr after it's prepared */
317 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
318 bool embedded, u8 sge_cnt, u32 opcode)
319 {
320 if (embedded)
321 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
322 else
323 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
324 MCC_WRB_SGE_CNT_SHIFT;
325 wrb->payload_length = payload_len;
326 wrb->tag0 = opcode;
327 be_dws_cpu_to_le(wrb, 8);
328 }
329
330 /* Don't touch the hdr after it's prepared */
331 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
332 u8 subsystem, u8 opcode, int cmd_len)
333 {
334 req_hdr->opcode = opcode;
335 req_hdr->subsystem = subsystem;
336 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
337 req_hdr->version = 0;
338 }
339
340 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
341 struct be_dma_mem *mem)
342 {
343 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
344 u64 dma = (u64)mem->dma;
345
346 for (i = 0; i < buf_pages; i++) {
347 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
348 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
349 dma += PAGE_SIZE_4K;
350 }
351 }
352
353 /* Converts interrupt delay in microseconds to multiplier value */
354 static u32 eq_delay_to_mult(u32 usec_delay)
355 {
356 #define MAX_INTR_RATE 651042
357 const u32 round = 10;
358 u32 multiplier;
359
360 if (usec_delay == 0)
361 multiplier = 0;
362 else {
363 u32 interrupt_rate = 1000000 / usec_delay;
364 /* Max delay, corresponding to the lowest interrupt rate */
365 if (interrupt_rate == 0)
366 multiplier = 1023;
367 else {
368 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
369 multiplier /= interrupt_rate;
370 /* Round the multiplier to the closest value.*/
371 multiplier = (multiplier + round/2) / round;
372 multiplier = min(multiplier, (u32)1023);
373 }
374 }
375 return multiplier;
376 }
377
378 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
379 {
380 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
381 struct be_mcc_wrb *wrb
382 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
383 memset(wrb, 0, sizeof(*wrb));
384 return wrb;
385 }
386
387 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
388 {
389 struct be_queue_info *mccq = &adapter->mcc_obj.q;
390 struct be_mcc_wrb *wrb;
391
392 if (atomic_read(&mccq->used) >= mccq->len) {
393 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
394 return NULL;
395 }
396
397 wrb = queue_head_node(mccq);
398 queue_head_inc(mccq);
399 atomic_inc(&mccq->used);
400 memset(wrb, 0, sizeof(*wrb));
401 return wrb;
402 }
403
404 /* Tell fw we're about to start firing cmds by writing a
405 * special pattern across the wrb hdr; uses mbox
406 */
407 int be_cmd_fw_init(struct be_adapter *adapter)
408 {
409 u8 *wrb;
410 int status;
411
412 spin_lock(&adapter->mbox_lock);
413
414 wrb = (u8 *)wrb_from_mbox(adapter);
415 *wrb++ = 0xFF;
416 *wrb++ = 0x12;
417 *wrb++ = 0x34;
418 *wrb++ = 0xFF;
419 *wrb++ = 0xFF;
420 *wrb++ = 0x56;
421 *wrb++ = 0x78;
422 *wrb = 0xFF;
423
424 status = be_mbox_notify_wait(adapter);
425
426 spin_unlock(&adapter->mbox_lock);
427 return status;
428 }
429
430 /* Tell fw we're done with firing cmds by writing a
431 * special pattern across the wrb hdr; uses mbox
432 */
433 int be_cmd_fw_clean(struct be_adapter *adapter)
434 {
435 u8 *wrb;
436 int status;
437
438 if (adapter->eeh_err)
439 return -EIO;
440
441 spin_lock(&adapter->mbox_lock);
442
443 wrb = (u8 *)wrb_from_mbox(adapter);
444 *wrb++ = 0xFF;
445 *wrb++ = 0xAA;
446 *wrb++ = 0xBB;
447 *wrb++ = 0xFF;
448 *wrb++ = 0xFF;
449 *wrb++ = 0xCC;
450 *wrb++ = 0xDD;
451 *wrb = 0xFF;
452
453 status = be_mbox_notify_wait(adapter);
454
455 spin_unlock(&adapter->mbox_lock);
456 return status;
457 }
458 int be_cmd_eq_create(struct be_adapter *adapter,
459 struct be_queue_info *eq, int eq_delay)
460 {
461 struct be_mcc_wrb *wrb;
462 struct be_cmd_req_eq_create *req;
463 struct be_dma_mem *q_mem = &eq->dma_mem;
464 int status;
465
466 spin_lock(&adapter->mbox_lock);
467
468 wrb = wrb_from_mbox(adapter);
469 req = embedded_payload(wrb);
470
471 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
472
473 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
474 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
475
476 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
477
478 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
479 /* 4byte eqe*/
480 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
481 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
482 __ilog2_u32(eq->len/256));
483 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
484 eq_delay_to_mult(eq_delay));
485 be_dws_cpu_to_le(req->context, sizeof(req->context));
486
487 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
488
489 status = be_mbox_notify_wait(adapter);
490 if (!status) {
491 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
492 eq->id = le16_to_cpu(resp->eq_id);
493 eq->created = true;
494 }
495
496 spin_unlock(&adapter->mbox_lock);
497 return status;
498 }
499
500 /* Uses mbox */
501 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
502 u8 type, bool permanent, u32 if_handle)
503 {
504 struct be_mcc_wrb *wrb;
505 struct be_cmd_req_mac_query *req;
506 int status;
507
508 spin_lock(&adapter->mbox_lock);
509
510 wrb = wrb_from_mbox(adapter);
511 req = embedded_payload(wrb);
512
513 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
514 OPCODE_COMMON_NTWK_MAC_QUERY);
515
516 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
517 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
518
519 req->type = type;
520 if (permanent) {
521 req->permanent = 1;
522 } else {
523 req->if_id = cpu_to_le16((u16) if_handle);
524 req->permanent = 0;
525 }
526
527 status = be_mbox_notify_wait(adapter);
528 if (!status) {
529 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
530 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
531 }
532
533 spin_unlock(&adapter->mbox_lock);
534 return status;
535 }
536
537 /* Uses synchronous MCCQ */
538 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
539 u32 if_id, u32 *pmac_id)
540 {
541 struct be_mcc_wrb *wrb;
542 struct be_cmd_req_pmac_add *req;
543 int status;
544
545 spin_lock_bh(&adapter->mcc_lock);
546
547 wrb = wrb_from_mccq(adapter);
548 if (!wrb) {
549 status = -EBUSY;
550 goto err;
551 }
552 req = embedded_payload(wrb);
553
554 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
555 OPCODE_COMMON_NTWK_PMAC_ADD);
556
557 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
558 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
559
560 req->if_id = cpu_to_le32(if_id);
561 memcpy(req->mac_address, mac_addr, ETH_ALEN);
562
563 status = be_mcc_notify_wait(adapter);
564 if (!status) {
565 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
566 *pmac_id = le32_to_cpu(resp->pmac_id);
567 }
568
569 err:
570 spin_unlock_bh(&adapter->mcc_lock);
571 return status;
572 }
573
574 /* Uses synchronous MCCQ */
575 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
576 {
577 struct be_mcc_wrb *wrb;
578 struct be_cmd_req_pmac_del *req;
579 int status;
580
581 spin_lock_bh(&adapter->mcc_lock);
582
583 wrb = wrb_from_mccq(adapter);
584 if (!wrb) {
585 status = -EBUSY;
586 goto err;
587 }
588 req = embedded_payload(wrb);
589
590 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
591 OPCODE_COMMON_NTWK_PMAC_DEL);
592
593 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
594 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
595
596 req->if_id = cpu_to_le32(if_id);
597 req->pmac_id = cpu_to_le32(pmac_id);
598
599 status = be_mcc_notify_wait(adapter);
600
601 err:
602 spin_unlock_bh(&adapter->mcc_lock);
603 return status;
604 }
605
606 /* Uses Mbox */
607 int be_cmd_cq_create(struct be_adapter *adapter,
608 struct be_queue_info *cq, struct be_queue_info *eq,
609 bool sol_evts, bool no_delay, int coalesce_wm)
610 {
611 struct be_mcc_wrb *wrb;
612 struct be_cmd_req_cq_create *req;
613 struct be_dma_mem *q_mem = &cq->dma_mem;
614 void *ctxt;
615 int status;
616
617 spin_lock(&adapter->mbox_lock);
618
619 wrb = wrb_from_mbox(adapter);
620 req = embedded_payload(wrb);
621 ctxt = &req->context;
622
623 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
624 OPCODE_COMMON_CQ_CREATE);
625
626 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
627 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
628
629 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
630
631 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
632 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
633 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
634 __ilog2_u32(cq->len/256));
635 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
636 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
637 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
638 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
639 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
640 be_dws_cpu_to_le(ctxt, sizeof(req->context));
641
642 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
643
644 status = be_mbox_notify_wait(adapter);
645 if (!status) {
646 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
647 cq->id = le16_to_cpu(resp->cq_id);
648 cq->created = true;
649 }
650
651 spin_unlock(&adapter->mbox_lock);
652
653 return status;
654 }
655
656 static u32 be_encoded_q_len(int q_len)
657 {
658 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
659 if (len_encoded == 16)
660 len_encoded = 0;
661 return len_encoded;
662 }
663
664 int be_cmd_mccq_create(struct be_adapter *adapter,
665 struct be_queue_info *mccq,
666 struct be_queue_info *cq)
667 {
668 struct be_mcc_wrb *wrb;
669 struct be_cmd_req_mcc_create *req;
670 struct be_dma_mem *q_mem = &mccq->dma_mem;
671 void *ctxt;
672 int status;
673
674 spin_lock(&adapter->mbox_lock);
675
676 wrb = wrb_from_mbox(adapter);
677 req = embedded_payload(wrb);
678 ctxt = &req->context;
679
680 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
681 OPCODE_COMMON_MCC_CREATE);
682
683 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
684 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
685
686 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
687
688 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
689 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
690 be_encoded_q_len(mccq->len));
691 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
692
693 be_dws_cpu_to_le(ctxt, sizeof(req->context));
694
695 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
696
697 status = be_mbox_notify_wait(adapter);
698 if (!status) {
699 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
700 mccq->id = le16_to_cpu(resp->id);
701 mccq->created = true;
702 }
703 spin_unlock(&adapter->mbox_lock);
704
705 return status;
706 }
707
708 int be_cmd_txq_create(struct be_adapter *adapter,
709 struct be_queue_info *txq,
710 struct be_queue_info *cq)
711 {
712 struct be_mcc_wrb *wrb;
713 struct be_cmd_req_eth_tx_create *req;
714 struct be_dma_mem *q_mem = &txq->dma_mem;
715 void *ctxt;
716 int status;
717
718 spin_lock(&adapter->mbox_lock);
719
720 wrb = wrb_from_mbox(adapter);
721 req = embedded_payload(wrb);
722 ctxt = &req->context;
723
724 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
725 OPCODE_ETH_TX_CREATE);
726
727 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
728 sizeof(*req));
729
730 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
731 req->ulp_num = BE_ULP1_NUM;
732 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
733
734 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
735 be_encoded_q_len(txq->len));
736 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
737 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
738
739 be_dws_cpu_to_le(ctxt, sizeof(req->context));
740
741 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
742
743 status = be_mbox_notify_wait(adapter);
744 if (!status) {
745 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
746 txq->id = le16_to_cpu(resp->cid);
747 txq->created = true;
748 }
749
750 spin_unlock(&adapter->mbox_lock);
751
752 return status;
753 }
754
755 /* Uses mbox */
756 int be_cmd_rxq_create(struct be_adapter *adapter,
757 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
758 u16 max_frame_size, u32 if_id, u32 rss)
759 {
760 struct be_mcc_wrb *wrb;
761 struct be_cmd_req_eth_rx_create *req;
762 struct be_dma_mem *q_mem = &rxq->dma_mem;
763 int status;
764
765 spin_lock(&adapter->mbox_lock);
766
767 wrb = wrb_from_mbox(adapter);
768 req = embedded_payload(wrb);
769
770 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
771 OPCODE_ETH_RX_CREATE);
772
773 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
774 sizeof(*req));
775
776 req->cq_id = cpu_to_le16(cq_id);
777 req->frag_size = fls(frag_size) - 1;
778 req->num_pages = 2;
779 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
780 req->interface_id = cpu_to_le32(if_id);
781 req->max_frame_size = cpu_to_le16(max_frame_size);
782 req->rss_queue = cpu_to_le32(rss);
783
784 status = be_mbox_notify_wait(adapter);
785 if (!status) {
786 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
787 rxq->id = le16_to_cpu(resp->id);
788 rxq->created = true;
789 }
790
791 spin_unlock(&adapter->mbox_lock);
792
793 return status;
794 }
795
796 /* Generic destroyer function for all types of queues
797 * Uses Mbox
798 */
799 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
800 int queue_type)
801 {
802 struct be_mcc_wrb *wrb;
803 struct be_cmd_req_q_destroy *req;
804 u8 subsys = 0, opcode = 0;
805 int status;
806
807 if (adapter->eeh_err)
808 return -EIO;
809
810 spin_lock(&adapter->mbox_lock);
811
812 wrb = wrb_from_mbox(adapter);
813 req = embedded_payload(wrb);
814
815 switch (queue_type) {
816 case QTYPE_EQ:
817 subsys = CMD_SUBSYSTEM_COMMON;
818 opcode = OPCODE_COMMON_EQ_DESTROY;
819 break;
820 case QTYPE_CQ:
821 subsys = CMD_SUBSYSTEM_COMMON;
822 opcode = OPCODE_COMMON_CQ_DESTROY;
823 break;
824 case QTYPE_TXQ:
825 subsys = CMD_SUBSYSTEM_ETH;
826 opcode = OPCODE_ETH_TX_DESTROY;
827 break;
828 case QTYPE_RXQ:
829 subsys = CMD_SUBSYSTEM_ETH;
830 opcode = OPCODE_ETH_RX_DESTROY;
831 break;
832 case QTYPE_MCCQ:
833 subsys = CMD_SUBSYSTEM_COMMON;
834 opcode = OPCODE_COMMON_MCC_DESTROY;
835 break;
836 default:
837 BUG();
838 }
839
840 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
841
842 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
843 req->id = cpu_to_le16(q->id);
844
845 status = be_mbox_notify_wait(adapter);
846
847 spin_unlock(&adapter->mbox_lock);
848
849 return status;
850 }
851
852 /* Create an rx filtering policy configuration on an i/f
853 * Uses mbox
854 */
855 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
856 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
857 u32 domain)
858 {
859 struct be_mcc_wrb *wrb;
860 struct be_cmd_req_if_create *req;
861 int status;
862
863 spin_lock(&adapter->mbox_lock);
864
865 wrb = wrb_from_mbox(adapter);
866 req = embedded_payload(wrb);
867
868 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
869 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
870
871 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
872 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
873
874 req->hdr.domain = domain;
875 req->capability_flags = cpu_to_le32(cap_flags);
876 req->enable_flags = cpu_to_le32(en_flags);
877 req->pmac_invalid = pmac_invalid;
878 if (!pmac_invalid)
879 memcpy(req->mac_addr, mac, ETH_ALEN);
880
881 status = be_mbox_notify_wait(adapter);
882 if (!status) {
883 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
884 *if_handle = le32_to_cpu(resp->interface_id);
885 if (!pmac_invalid)
886 *pmac_id = le32_to_cpu(resp->pmac_id);
887 }
888
889 spin_unlock(&adapter->mbox_lock);
890 return status;
891 }
892
893 /* Uses mbox */
894 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
895 {
896 struct be_mcc_wrb *wrb;
897 struct be_cmd_req_if_destroy *req;
898 int status;
899
900 if (adapter->eeh_err)
901 return -EIO;
902
903 spin_lock(&adapter->mbox_lock);
904
905 wrb = wrb_from_mbox(adapter);
906 req = embedded_payload(wrb);
907
908 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
909 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
910
911 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
912 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
913
914 req->interface_id = cpu_to_le32(interface_id);
915
916 status = be_mbox_notify_wait(adapter);
917
918 spin_unlock(&adapter->mbox_lock);
919
920 return status;
921 }
922
923 /* Get stats is a non embedded command: the request is not embedded inside
924 * WRB but is a separate dma memory block
925 * Uses asynchronous MCC
926 */
927 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
928 {
929 struct be_mcc_wrb *wrb;
930 struct be_cmd_req_get_stats *req;
931 struct be_sge *sge;
932 int status = 0;
933
934 spin_lock_bh(&adapter->mcc_lock);
935
936 wrb = wrb_from_mccq(adapter);
937 if (!wrb) {
938 status = -EBUSY;
939 goto err;
940 }
941 req = nonemb_cmd->va;
942 sge = nonembedded_sgl(wrb);
943
944 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
945 OPCODE_ETH_GET_STATISTICS);
946
947 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
948 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
949 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
950 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
951 sge->len = cpu_to_le32(nonemb_cmd->size);
952
953 be_mcc_notify(adapter);
954
955 err:
956 spin_unlock_bh(&adapter->mcc_lock);
957 return status;
958 }
959
960 /* Uses synchronous mcc */
961 int be_cmd_link_status_query(struct be_adapter *adapter,
962 bool *link_up, u8 *mac_speed, u16 *link_speed)
963 {
964 struct be_mcc_wrb *wrb;
965 struct be_cmd_req_link_status *req;
966 int status;
967
968 spin_lock_bh(&adapter->mcc_lock);
969
970 wrb = wrb_from_mccq(adapter);
971 if (!wrb) {
972 status = -EBUSY;
973 goto err;
974 }
975 req = embedded_payload(wrb);
976
977 *link_up = false;
978
979 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
980 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
981
982 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
983 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
984
985 status = be_mcc_notify_wait(adapter);
986 if (!status) {
987 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
988 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
989 *link_up = true;
990 *link_speed = le16_to_cpu(resp->link_speed);
991 *mac_speed = resp->mac_speed;
992 }
993 }
994
995 err:
996 spin_unlock_bh(&adapter->mcc_lock);
997 return status;
998 }
999
1000 /* Uses Mbox */
1001 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1002 {
1003 struct be_mcc_wrb *wrb;
1004 struct be_cmd_req_get_fw_version *req;
1005 int status;
1006
1007 spin_lock(&adapter->mbox_lock);
1008
1009 wrb = wrb_from_mbox(adapter);
1010 req = embedded_payload(wrb);
1011
1012 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1013 OPCODE_COMMON_GET_FW_VERSION);
1014
1015 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1016 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1017
1018 status = be_mbox_notify_wait(adapter);
1019 if (!status) {
1020 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1021 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1022 }
1023
1024 spin_unlock(&adapter->mbox_lock);
1025 return status;
1026 }
1027
1028 /* set the EQ delay interval of an EQ to specified value
1029 * Uses async mcc
1030 */
1031 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1032 {
1033 struct be_mcc_wrb *wrb;
1034 struct be_cmd_req_modify_eq_delay *req;
1035 int status = 0;
1036
1037 spin_lock_bh(&adapter->mcc_lock);
1038
1039 wrb = wrb_from_mccq(adapter);
1040 if (!wrb) {
1041 status = -EBUSY;
1042 goto err;
1043 }
1044 req = embedded_payload(wrb);
1045
1046 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1047 OPCODE_COMMON_MODIFY_EQ_DELAY);
1048
1049 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1050 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1051
1052 req->num_eq = cpu_to_le32(1);
1053 req->delay[0].eq_id = cpu_to_le32(eq_id);
1054 req->delay[0].phase = 0;
1055 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1056
1057 be_mcc_notify(adapter);
1058
1059 err:
1060 spin_unlock_bh(&adapter->mcc_lock);
1061 return status;
1062 }
1063
1064 /* Uses sycnhronous mcc */
1065 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1066 u32 num, bool untagged, bool promiscuous)
1067 {
1068 struct be_mcc_wrb *wrb;
1069 struct be_cmd_req_vlan_config *req;
1070 int status;
1071
1072 spin_lock_bh(&adapter->mcc_lock);
1073
1074 wrb = wrb_from_mccq(adapter);
1075 if (!wrb) {
1076 status = -EBUSY;
1077 goto err;
1078 }
1079 req = embedded_payload(wrb);
1080
1081 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1082 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1083
1084 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1085 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1086
1087 req->interface_id = if_id;
1088 req->promiscuous = promiscuous;
1089 req->untagged = untagged;
1090 req->num_vlan = num;
1091 if (!promiscuous) {
1092 memcpy(req->normal_vlan, vtag_array,
1093 req->num_vlan * sizeof(vtag_array[0]));
1094 }
1095
1096 status = be_mcc_notify_wait(adapter);
1097
1098 err:
1099 spin_unlock_bh(&adapter->mcc_lock);
1100 return status;
1101 }
1102
1103 /* Uses MCC for this command as it may be called in BH context
1104 * Uses synchronous mcc
1105 */
1106 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1107 {
1108 struct be_mcc_wrb *wrb;
1109 struct be_cmd_req_promiscuous_config *req;
1110 int status;
1111
1112 spin_lock_bh(&adapter->mcc_lock);
1113
1114 wrb = wrb_from_mccq(adapter);
1115 if (!wrb) {
1116 status = -EBUSY;
1117 goto err;
1118 }
1119 req = embedded_payload(wrb);
1120
1121 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1122
1123 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1124 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1125
1126 /* In FW versions X.102.149/X.101.487 and later,
1127 * the port setting associated only with the
1128 * issuing pci function will take effect
1129 */
1130 if (port_num)
1131 req->port1_promiscuous = en;
1132 else
1133 req->port0_promiscuous = en;
1134
1135 status = be_mcc_notify_wait(adapter);
1136
1137 err:
1138 spin_unlock_bh(&adapter->mcc_lock);
1139 return status;
1140 }
1141
1142 /*
1143 * Uses MCC for this command as it may be called in BH context
1144 * (mc == NULL) => multicast promiscous
1145 */
1146 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1147 struct net_device *netdev, struct be_dma_mem *mem)
1148 {
1149 struct be_mcc_wrb *wrb;
1150 struct be_cmd_req_mcast_mac_config *req = mem->va;
1151 struct be_sge *sge;
1152 int status;
1153
1154 spin_lock_bh(&adapter->mcc_lock);
1155
1156 wrb = wrb_from_mccq(adapter);
1157 if (!wrb) {
1158 status = -EBUSY;
1159 goto err;
1160 }
1161 sge = nonembedded_sgl(wrb);
1162 memset(req, 0, sizeof(*req));
1163
1164 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1165 OPCODE_COMMON_NTWK_MULTICAST_SET);
1166 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1167 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1168 sge->len = cpu_to_le32(mem->size);
1169
1170 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1171 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1172
1173 req->interface_id = if_id;
1174 if (netdev) {
1175 int i;
1176 struct netdev_hw_addr *ha;
1177
1178 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1179
1180 i = 0;
1181 netdev_for_each_mc_addr(ha, netdev)
1182 memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1183 } else {
1184 req->promiscuous = 1;
1185 }
1186
1187 status = be_mcc_notify_wait(adapter);
1188
1189 err:
1190 spin_unlock_bh(&adapter->mcc_lock);
1191 return status;
1192 }
1193
1194 /* Uses synchrounous mcc */
1195 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1196 {
1197 struct be_mcc_wrb *wrb;
1198 struct be_cmd_req_set_flow_control *req;
1199 int status;
1200
1201 spin_lock_bh(&adapter->mcc_lock);
1202
1203 wrb = wrb_from_mccq(adapter);
1204 if (!wrb) {
1205 status = -EBUSY;
1206 goto err;
1207 }
1208 req = embedded_payload(wrb);
1209
1210 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1211 OPCODE_COMMON_SET_FLOW_CONTROL);
1212
1213 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1214 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1215
1216 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1217 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1218
1219 status = be_mcc_notify_wait(adapter);
1220
1221 err:
1222 spin_unlock_bh(&adapter->mcc_lock);
1223 return status;
1224 }
1225
1226 /* Uses sycn mcc */
1227 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1228 {
1229 struct be_mcc_wrb *wrb;
1230 struct be_cmd_req_get_flow_control *req;
1231 int status;
1232
1233 spin_lock_bh(&adapter->mcc_lock);
1234
1235 wrb = wrb_from_mccq(adapter);
1236 if (!wrb) {
1237 status = -EBUSY;
1238 goto err;
1239 }
1240 req = embedded_payload(wrb);
1241
1242 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1243 OPCODE_COMMON_GET_FLOW_CONTROL);
1244
1245 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1246 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1247
1248 status = be_mcc_notify_wait(adapter);
1249 if (!status) {
1250 struct be_cmd_resp_get_flow_control *resp =
1251 embedded_payload(wrb);
1252 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1253 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1254 }
1255
1256 err:
1257 spin_unlock_bh(&adapter->mcc_lock);
1258 return status;
1259 }
1260
1261 /* Uses mbox */
1262 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *mode)
1263 {
1264 struct be_mcc_wrb *wrb;
1265 struct be_cmd_req_query_fw_cfg *req;
1266 int status;
1267
1268 spin_lock(&adapter->mbox_lock);
1269
1270 wrb = wrb_from_mbox(adapter);
1271 req = embedded_payload(wrb);
1272
1273 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1274 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1275
1276 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1277 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1278
1279 status = be_mbox_notify_wait(adapter);
1280 if (!status) {
1281 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1282 *port_num = le32_to_cpu(resp->phys_port);
1283 *mode = le32_to_cpu(resp->function_mode);
1284 }
1285
1286 spin_unlock(&adapter->mbox_lock);
1287 return status;
1288 }
1289
1290 /* Uses mbox */
1291 int be_cmd_reset_function(struct be_adapter *adapter)
1292 {
1293 struct be_mcc_wrb *wrb;
1294 struct be_cmd_req_hdr *req;
1295 int status;
1296
1297 spin_lock(&adapter->mbox_lock);
1298
1299 wrb = wrb_from_mbox(adapter);
1300 req = embedded_payload(wrb);
1301
1302 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1303 OPCODE_COMMON_FUNCTION_RESET);
1304
1305 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1306 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1307
1308 status = be_mbox_notify_wait(adapter);
1309
1310 spin_unlock(&adapter->mbox_lock);
1311 return status;
1312 }
1313
1314 /* Uses sync mcc */
1315 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1316 u8 bcn, u8 sts, u8 state)
1317 {
1318 struct be_mcc_wrb *wrb;
1319 struct be_cmd_req_enable_disable_beacon *req;
1320 int status;
1321
1322 spin_lock_bh(&adapter->mcc_lock);
1323
1324 wrb = wrb_from_mccq(adapter);
1325 if (!wrb) {
1326 status = -EBUSY;
1327 goto err;
1328 }
1329 req = embedded_payload(wrb);
1330
1331 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1332 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1333
1334 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1335 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1336
1337 req->port_num = port_num;
1338 req->beacon_state = state;
1339 req->beacon_duration = bcn;
1340 req->status_duration = sts;
1341
1342 status = be_mcc_notify_wait(adapter);
1343
1344 err:
1345 spin_unlock_bh(&adapter->mcc_lock);
1346 return status;
1347 }
1348
1349 /* Uses sync mcc */
1350 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1351 {
1352 struct be_mcc_wrb *wrb;
1353 struct be_cmd_req_get_beacon_state *req;
1354 int status;
1355
1356 spin_lock_bh(&adapter->mcc_lock);
1357
1358 wrb = wrb_from_mccq(adapter);
1359 if (!wrb) {
1360 status = -EBUSY;
1361 goto err;
1362 }
1363 req = embedded_payload(wrb);
1364
1365 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1366 OPCODE_COMMON_GET_BEACON_STATE);
1367
1368 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1369 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1370
1371 req->port_num = port_num;
1372
1373 status = be_mcc_notify_wait(adapter);
1374 if (!status) {
1375 struct be_cmd_resp_get_beacon_state *resp =
1376 embedded_payload(wrb);
1377 *state = resp->beacon_state;
1378 }
1379
1380 err:
1381 spin_unlock_bh(&adapter->mcc_lock);
1382 return status;
1383 }
1384
1385 /* Uses sync mcc */
1386 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1387 u8 *connector)
1388 {
1389 struct be_mcc_wrb *wrb;
1390 struct be_cmd_req_port_type *req;
1391 int status;
1392
1393 spin_lock_bh(&adapter->mcc_lock);
1394
1395 wrb = wrb_from_mccq(adapter);
1396 if (!wrb) {
1397 status = -EBUSY;
1398 goto err;
1399 }
1400 req = embedded_payload(wrb);
1401
1402 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1403 OPCODE_COMMON_READ_TRANSRECV_DATA);
1404
1405 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1406 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1407
1408 req->port = cpu_to_le32(port);
1409 req->page_num = cpu_to_le32(TR_PAGE_A0);
1410 status = be_mcc_notify_wait(adapter);
1411 if (!status) {
1412 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1413 *connector = resp->data.connector;
1414 }
1415
1416 err:
1417 spin_unlock_bh(&adapter->mcc_lock);
1418 return status;
1419 }
1420
1421 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1422 u32 flash_type, u32 flash_opcode, u32 buf_size)
1423 {
1424 struct be_mcc_wrb *wrb;
1425 struct be_cmd_write_flashrom *req;
1426 struct be_sge *sge;
1427 int status;
1428
1429 spin_lock_bh(&adapter->mcc_lock);
1430 adapter->flash_status = 0;
1431
1432 wrb = wrb_from_mccq(adapter);
1433 if (!wrb) {
1434 status = -EBUSY;
1435 goto err_unlock;
1436 }
1437 req = cmd->va;
1438 sge = nonembedded_sgl(wrb);
1439
1440 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1441 OPCODE_COMMON_WRITE_FLASHROM);
1442 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1443
1444 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1445 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1446 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1447 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1448 sge->len = cpu_to_le32(cmd->size);
1449
1450 req->params.op_type = cpu_to_le32(flash_type);
1451 req->params.op_code = cpu_to_le32(flash_opcode);
1452 req->params.data_buf_size = cpu_to_le32(buf_size);
1453
1454 be_mcc_notify(adapter);
1455 spin_unlock_bh(&adapter->mcc_lock);
1456
1457 if (!wait_for_completion_timeout(&adapter->flash_compl,
1458 msecs_to_jiffies(12000)))
1459 status = -1;
1460 else
1461 status = adapter->flash_status;
1462
1463 return status;
1464
1465 err_unlock:
1466 spin_unlock_bh(&adapter->mcc_lock);
1467 return status;
1468 }
1469
1470 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1471 int offset)
1472 {
1473 struct be_mcc_wrb *wrb;
1474 struct be_cmd_write_flashrom *req;
1475 int status;
1476
1477 spin_lock_bh(&adapter->mcc_lock);
1478
1479 wrb = wrb_from_mccq(adapter);
1480 if (!wrb) {
1481 status = -EBUSY;
1482 goto err;
1483 }
1484 req = embedded_payload(wrb);
1485
1486 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1487 OPCODE_COMMON_READ_FLASHROM);
1488
1489 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1490 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1491
1492 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1493 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1494 req->params.offset = cpu_to_le32(offset);
1495 req->params.data_buf_size = cpu_to_le32(0x4);
1496
1497 status = be_mcc_notify_wait(adapter);
1498 if (!status)
1499 memcpy(flashed_crc, req->params.data_buf, 4);
1500
1501 err:
1502 spin_unlock_bh(&adapter->mcc_lock);
1503 return status;
1504 }
1505
1506 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1507 struct be_dma_mem *nonemb_cmd)
1508 {
1509 struct be_mcc_wrb *wrb;
1510 struct be_cmd_req_acpi_wol_magic_config *req;
1511 struct be_sge *sge;
1512 int status;
1513
1514 spin_lock_bh(&adapter->mcc_lock);
1515
1516 wrb = wrb_from_mccq(adapter);
1517 if (!wrb) {
1518 status = -EBUSY;
1519 goto err;
1520 }
1521 req = nonemb_cmd->va;
1522 sge = nonembedded_sgl(wrb);
1523
1524 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1525 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1526
1527 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1528 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1529 memcpy(req->magic_mac, mac, ETH_ALEN);
1530
1531 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1532 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1533 sge->len = cpu_to_le32(nonemb_cmd->size);
1534
1535 status = be_mcc_notify_wait(adapter);
1536
1537 err:
1538 spin_unlock_bh(&adapter->mcc_lock);
1539 return status;
1540 }
1541
1542 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1543 u8 loopback_type, u8 enable)
1544 {
1545 struct be_mcc_wrb *wrb;
1546 struct be_cmd_req_set_lmode *req;
1547 int status;
1548
1549 spin_lock_bh(&adapter->mcc_lock);
1550
1551 wrb = wrb_from_mccq(adapter);
1552 if (!wrb) {
1553 status = -EBUSY;
1554 goto err;
1555 }
1556
1557 req = embedded_payload(wrb);
1558
1559 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1560 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1561
1562 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1563 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1564 sizeof(*req));
1565
1566 req->src_port = port_num;
1567 req->dest_port = port_num;
1568 req->loopback_type = loopback_type;
1569 req->loopback_state = enable;
1570
1571 status = be_mcc_notify_wait(adapter);
1572 err:
1573 spin_unlock_bh(&adapter->mcc_lock);
1574 return status;
1575 }
1576
1577 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1578 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1579 {
1580 struct be_mcc_wrb *wrb;
1581 struct be_cmd_req_loopback_test *req;
1582 int status;
1583
1584 spin_lock_bh(&adapter->mcc_lock);
1585
1586 wrb = wrb_from_mccq(adapter);
1587 if (!wrb) {
1588 status = -EBUSY;
1589 goto err;
1590 }
1591
1592 req = embedded_payload(wrb);
1593
1594 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1595 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1596
1597 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1598 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1599 req->hdr.timeout = cpu_to_le32(4);
1600
1601 req->pattern = cpu_to_le64(pattern);
1602 req->src_port = cpu_to_le32(port_num);
1603 req->dest_port = cpu_to_le32(port_num);
1604 req->pkt_size = cpu_to_le32(pkt_size);
1605 req->num_pkts = cpu_to_le32(num_pkts);
1606 req->loopback_type = cpu_to_le32(loopback_type);
1607
1608 status = be_mcc_notify_wait(adapter);
1609 if (!status) {
1610 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1611 status = le32_to_cpu(resp->status);
1612 }
1613
1614 err:
1615 spin_unlock_bh(&adapter->mcc_lock);
1616 return status;
1617 }
1618
1619 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1620 u32 byte_cnt, struct be_dma_mem *cmd)
1621 {
1622 struct be_mcc_wrb *wrb;
1623 struct be_cmd_req_ddrdma_test *req;
1624 struct be_sge *sge;
1625 int status;
1626 int i, j = 0;
1627
1628 spin_lock_bh(&adapter->mcc_lock);
1629
1630 wrb = wrb_from_mccq(adapter);
1631 if (!wrb) {
1632 status = -EBUSY;
1633 goto err;
1634 }
1635 req = cmd->va;
1636 sge = nonembedded_sgl(wrb);
1637 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1638 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1639 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1640 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1641
1642 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1643 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1644 sge->len = cpu_to_le32(cmd->size);
1645
1646 req->pattern = cpu_to_le64(pattern);
1647 req->byte_count = cpu_to_le32(byte_cnt);
1648 for (i = 0; i < byte_cnt; i++) {
1649 req->snd_buff[i] = (u8)(pattern >> (j*8));
1650 j++;
1651 if (j > 7)
1652 j = 0;
1653 }
1654
1655 status = be_mcc_notify_wait(adapter);
1656
1657 if (!status) {
1658 struct be_cmd_resp_ddrdma_test *resp;
1659 resp = cmd->va;
1660 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1661 resp->snd_err) {
1662 status = -1;
1663 }
1664 }
1665
1666 err:
1667 spin_unlock_bh(&adapter->mcc_lock);
1668 return status;
1669 }
1670
1671 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1672 struct be_dma_mem *nonemb_cmd)
1673 {
1674 struct be_mcc_wrb *wrb;
1675 struct be_cmd_req_seeprom_read *req;
1676 struct be_sge *sge;
1677 int status;
1678
1679 spin_lock_bh(&adapter->mcc_lock);
1680
1681 wrb = wrb_from_mccq(adapter);
1682 req = nonemb_cmd->va;
1683 sge = nonembedded_sgl(wrb);
1684
1685 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1686 OPCODE_COMMON_SEEPROM_READ);
1687
1688 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1689 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1690
1691 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1692 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1693 sge->len = cpu_to_le32(nonemb_cmd->size);
1694
1695 status = be_mcc_notify_wait(adapter);
1696
1697 spin_unlock_bh(&adapter->mcc_lock);
1698 return status;
1699 }
1700
1701 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1702 {
1703 struct be_mcc_wrb *wrb;
1704 struct be_cmd_req_get_phy_info *req;
1705 struct be_sge *sge;
1706 int status;
1707
1708 spin_lock_bh(&adapter->mcc_lock);
1709
1710 wrb = wrb_from_mccq(adapter);
1711 if (!wrb) {
1712 status = -EBUSY;
1713 goto err;
1714 }
1715
1716 req = cmd->va;
1717 sge = nonembedded_sgl(wrb);
1718
1719 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1720 OPCODE_COMMON_GET_PHY_DETAILS);
1721
1722 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1723 OPCODE_COMMON_GET_PHY_DETAILS,
1724 sizeof(*req));
1725
1726 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1727 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1728 sge->len = cpu_to_le32(cmd->size);
1729
1730 status = be_mcc_notify_wait(adapter);
1731 err:
1732 spin_unlock_bh(&adapter->mcc_lock);
1733 return status;
1734 }
1735
1736 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1737 {
1738 struct be_mcc_wrb *wrb;
1739 struct be_cmd_req_set_qos *req;
1740 int status;
1741
1742 spin_lock_bh(&adapter->mcc_lock);
1743
1744 wrb = wrb_from_mccq(adapter);
1745 if (!wrb) {
1746 status = -EBUSY;
1747 goto err;
1748 }
1749
1750 req = embedded_payload(wrb);
1751
1752 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1753 OPCODE_COMMON_SET_QOS);
1754
1755 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1756 OPCODE_COMMON_SET_QOS, sizeof(*req));
1757
1758 req->hdr.domain = domain;
1759 req->valid_bits = BE_QOS_BITS_NIC;
1760 req->max_bps_nic = bps;
1761
1762 status = be_mcc_notify_wait(adapter);
1763
1764 err:
1765 spin_unlock_bh(&adapter->mcc_lock);
1766 return status;
1767 }
Linux kernel - Deliverables
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