drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 static void be_mcc_notify(struct be_adapter *adapter)
  22 {
  23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24         u32 val = 0;
  25
  26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  29 }
  30
  31 /* To check if valid bit is set, check the entire word as we don't know
  32  * the endianness of the data (old entry is host endian while a new entry is
  33  * little endian) */
  34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  35 {
  36         if (compl->flags != 0) {
  37                 compl->flags = le32_to_cpu(compl->flags);
  38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  39                 return true;
  40         } else {
  41                 return false;
  42         }
  43 }
  44
  45 /* Need to reset the entire word that houses the valid bit */
  46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  47 {
  48         compl->flags = 0;
  49 }
  50
  51 static int be_mcc_compl_process(struct be_adapter *adapter,
  52         struct be_mcc_compl *compl)
  53 {
  54         u16 compl_status, extd_status;
  55
  56         /* Just swap the status to host endian; mcc tag is opaquely copied
  57          * from mcc_wrb */
  58         be_dws_le_to_cpu(compl, 4);
  59
  60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  61                                 CQE_STATUS_COMPL_MASK;
  62         if (compl_status == MCC_STATUS_SUCCESS) {
  63                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
  64                         struct be_cmd_resp_get_stats *resp =
  65                                                 adapter->stats.cmd.va;
  66                         be_dws_le_to_cpu(&resp->hw_stats,
  67                                                 sizeof(resp->hw_stats));
  68                         netdev_stats_update(adapter);
  69                 }
  70         } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
  71                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  72                                 CQE_STATUS_EXTD_MASK;
  73                 dev_warn(&adapter->pdev->dev,
  74                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  75                         compl->tag0, compl_status, extd_status);
  76         }
  77         return compl_status;
  78 }
  79
  80 /* Link state evt is a string of bytes; no need for endian swapping */
  81 static void be_async_link_state_process(struct be_adapter *adapter,
  82                 struct be_async_event_link_state *evt)
  83 {
  84         be_link_status_update(adapter,
  85                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
  86 }
  87
  88 static inline bool is_link_state_evt(u32 trailer)
  89 {
  90         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
  91                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
  92                                 ASYNC_EVENT_CODE_LINK_STATE);
  93 }
  94
  95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
  96 {
  97         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
  98         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
  99
 100         if (be_mcc_compl_is_new(compl)) {
 101                 queue_tail_inc(mcc_cq);
 102                 return compl;
 103         }
 104         return NULL;
 105 }
 106
 107 void be_async_mcc_enable(struct be_adapter *adapter)
 108 {
 109         spin_lock_bh(&adapter->mcc_cq_lock);
 110
 111         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 112         adapter->mcc_obj.rearm_cq = true;
 113
 114         spin_unlock_bh(&adapter->mcc_cq_lock);
 115 }
 116
 117 void be_async_mcc_disable(struct be_adapter *adapter)
 118 {
 119         adapter->mcc_obj.rearm_cq = false;
 120 }
 121
 122 int be_process_mcc(struct be_adapter *adapter, int *status)
 123 {
 124         struct be_mcc_compl *compl;
 125         int num = 0;
 126         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 127
 128         spin_lock_bh(&adapter->mcc_cq_lock);
 129         while ((compl = be_mcc_compl_get(adapter))) {
 130                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 131                         /* Interpret flags as an async trailer */
 132                         BUG_ON(!is_link_state_evt(compl->flags));
 133
 134                         /* Interpret compl as a async link evt */
 135                         be_async_link_state_process(adapter,
 136                                 (struct be_async_event_link_state *) compl);
 137                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 138                                 *status = be_mcc_compl_process(adapter, compl);
 139                                 atomic_dec(&mcc_obj->q.used);
 140                 }
 141                 be_mcc_compl_use(compl);
 142                 num++;
 143         }
 144
 145         spin_unlock_bh(&adapter->mcc_cq_lock);
 146         return num;
 147 }
 148
 149 /* Wait till no more pending mcc requests are present */
 150 static int be_mcc_wait_compl(struct be_adapter *adapter)
 151 {
 152 #define mcc_timeout             120000 /* 12s timeout */
 153         int i, num, status = 0;
 154         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 155
 156         for (i = 0; i < mcc_timeout; i++) {
 157                 num = be_process_mcc(adapter, &status);
 158                 if (num)
 159                         be_cq_notify(adapter, mcc_obj->cq.id,
 160                                 mcc_obj->rearm_cq, num);
 161
 162                 if (atomic_read(&mcc_obj->q.used) == 0)
 163                         break;
 164                 udelay(100);
 165         }
 166         if (i == mcc_timeout) {
 167                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 168                 return -1;
 169         }
 170         return status;
 171 }
 172
 173 /* Notify MCC requests and wait for completion */
 174 static int be_mcc_notify_wait(struct be_adapter *adapter)
 175 {
 176         be_mcc_notify(adapter);
 177         return be_mcc_wait_compl(adapter);
 178 }
 179
 180 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 181 {
 182         int cnt = 0, wait = 5;
 183         u32 ready;
 184
 185         do {
 186                 ready = ioread32(db);
 187                 if (ready == 0xffffffff) {
 188                         dev_err(&adapter->pdev->dev,
 189                                 "pci slot disconnected\n");
 190                         return -1;
 191                 }
 192
 193                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 194                 if (ready)
 195                         break;
 196
 197                 if (cnt > 4000000) {
 198                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 199                         return -1;
 200                 }
 201
 202                 if (cnt > 50)
 203                         wait = 200;
 204                 cnt += wait;
 205                 udelay(wait);
 206         } while (true);
 207
 208         return 0;
 209 }
 210
 211 /*
 212  * Insert the mailbox address into the doorbell in two steps
 213  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 214  */
 215 static int be_mbox_notify_wait(struct be_adapter *adapter)
 216 {
 217         int status;
 218         u32 val = 0;
 219         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 220         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 221         struct be_mcc_mailbox *mbox = mbox_mem->va;
 222         struct be_mcc_compl *compl = &mbox->compl;
 223
 224         /* wait for ready to be set */
 225         status = be_mbox_db_ready_wait(adapter, db);
 226         if (status != 0)
 227                 return status;
 228
 229         val |= MPU_MAILBOX_DB_HI_MASK;
 230         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 231         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 232         iowrite32(val, db);
 233
 234         /* wait for ready to be set */
 235         status = be_mbox_db_ready_wait(adapter, db);
 236         if (status != 0)
 237                 return status;
 238
 239         val = 0;
 240         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 241         val |= (u32)(mbox_mem->dma >> 4) << 2;
 242         iowrite32(val, db);
 243
 244         status = be_mbox_db_ready_wait(adapter, db);
 245         if (status != 0)
 246                 return status;
 247
 248         /* A cq entry has been made now */
 249         if (be_mcc_compl_is_new(compl)) {
 250                 status = be_mcc_compl_process(adapter, &mbox->compl);
 251                 be_mcc_compl_use(compl);
 252                 if (status)
 253                         return status;
 254         } else {
 255                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 256                 return -1;
 257         }
 258         return 0;
 259 }
 260
 261 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 262 {
 263         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 264
 265         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 266         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 267                 return -1;
 268         else
 269                 return 0;
 270 }
 271
 272 int be_cmd_POST(struct be_adapter *adapter)
 273 {
 274         u16 stage;
 275         int status, timeout = 0;
 276
 277         do {
 278                 status = be_POST_stage_get(adapter, &stage);
 279                 if (status) {
 280                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
 281                                 stage);
 282                         return -1;
 283                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 284                         set_current_state(TASK_INTERRUPTIBLE);
 285                         schedule_timeout(2 * HZ);
 286                         timeout += 2;
 287                 } else {
 288                         return 0;
 289                 }
 290         } while (timeout < 20);
 291
 292         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
 293         return -1;
 294 }
 295
 296 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 297 {
 298         return wrb->payload.embedded_payload;
 299 }
 300
 301 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 302 {
 303         return &wrb->payload.sgl[0];
 304 }
 305
 306 /* Don't touch the hdr after it's prepared */
 307 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 308                                 bool embedded, u8 sge_cnt, u32 opcode)
 309 {
 310         if (embedded)
 311                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 312         else
 313                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 314                                 MCC_WRB_SGE_CNT_SHIFT;
 315         wrb->payload_length = payload_len;
 316         wrb->tag0 = opcode;
 317         be_dws_cpu_to_le(wrb, 8);
 318 }
 319
 320 /* Don't touch the hdr after it's prepared */
 321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 322                                 u8 subsystem, u8 opcode, int cmd_len)
 323 {
 324         req_hdr->opcode = opcode;
 325         req_hdr->subsystem = subsystem;
 326         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 327         req_hdr->version = 0;
 328 }
 329
 330 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 331                         struct be_dma_mem *mem)
 332 {
 333         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 334         u64 dma = (u64)mem->dma;
 335
 336         for (i = 0; i < buf_pages; i++) {
 337                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 338                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 339                 dma += PAGE_SIZE_4K;
 340         }
 341 }
 342
 343 /* Converts interrupt delay in microseconds to multiplier value */
 344 static u32 eq_delay_to_mult(u32 usec_delay)
 345 {
 346 #define MAX_INTR_RATE                   651042
 347         const u32 round = 10;
 348         u32 multiplier;
 349
 350         if (usec_delay == 0)
 351                 multiplier = 0;
 352         else {
 353                 u32 interrupt_rate = 1000000 / usec_delay;
 354                 /* Max delay, corresponding to the lowest interrupt rate */
 355                 if (interrupt_rate == 0)
 356                         multiplier = 1023;
 357                 else {
 358                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 359                         multiplier /= interrupt_rate;
 360                         /* Round the multiplier to the closest value.*/
 361                         multiplier = (multiplier + round/2) / round;
 362                         multiplier = min(multiplier, (u32)1023);
 363                 }
 364         }
 365         return multiplier;
 366 }
 367
 368 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 369 {
 370         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 371         struct be_mcc_wrb *wrb
 372                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 373         memset(wrb, 0, sizeof(*wrb));
 374         return wrb;
 375 }
 376
 377 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 378 {
 379         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 380         struct be_mcc_wrb *wrb;
 381
 382         if (atomic_read(&mccq->used) >= mccq->len) {
 383                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 384                 return NULL;
 385         }
 386
 387         wrb = queue_head_node(mccq);
 388         queue_head_inc(mccq);
 389         atomic_inc(&mccq->used);
 390         memset(wrb, 0, sizeof(*wrb));
 391         return wrb;
 392 }
 393
 394 /* Tell fw we're about to start firing cmds by writing a
 395  * special pattern across the wrb hdr; uses mbox
 396  */
 397 int be_cmd_fw_init(struct be_adapter *adapter)
 398 {
 399         u8 *wrb;
 400         int status;
 401
 402         spin_lock(&adapter->mbox_lock);
 403
 404         wrb = (u8 *)wrb_from_mbox(adapter);
 405         *wrb++ = 0xFF;
 406         *wrb++ = 0x12;
 407         *wrb++ = 0x34;
 408         *wrb++ = 0xFF;
 409         *wrb++ = 0xFF;
 410         *wrb++ = 0x56;
 411         *wrb++ = 0x78;
 412         *wrb = 0xFF;
 413
 414         status = be_mbox_notify_wait(adapter);
 415
 416         spin_unlock(&adapter->mbox_lock);
 417         return status;
 418 }
 419
 420 /* Tell fw we're done with firing cmds by writing a
 421  * special pattern across the wrb hdr; uses mbox
 422  */
 423 int be_cmd_fw_clean(struct be_adapter *adapter)
 424 {
 425         u8 *wrb;
 426         int status;
 427
 428         if (adapter->eeh_err)
 429                 return -EIO;
 430
 431         spin_lock(&adapter->mbox_lock);
 432
 433         wrb = (u8 *)wrb_from_mbox(adapter);
 434         *wrb++ = 0xFF;
 435         *wrb++ = 0xAA;
 436         *wrb++ = 0xBB;
 437         *wrb++ = 0xFF;
 438         *wrb++ = 0xFF;
 439         *wrb++ = 0xCC;
 440         *wrb++ = 0xDD;
 441         *wrb = 0xFF;
 442
 443         status = be_mbox_notify_wait(adapter);
 444
 445         spin_unlock(&adapter->mbox_lock);
 446         return status;
 447 }
 448 int be_cmd_eq_create(struct be_adapter *adapter,
 449                 struct be_queue_info *eq, int eq_delay)
 450 {
 451         struct be_mcc_wrb *wrb;
 452         struct be_cmd_req_eq_create *req;
 453         struct be_dma_mem *q_mem = &eq->dma_mem;
 454         int status;
 455
 456         spin_lock(&adapter->mbox_lock);
 457
 458         wrb = wrb_from_mbox(adapter);
 459         req = embedded_payload(wrb);
 460
 461         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 462
 463         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 464                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 465
 466         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 467
 468         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 469         /* 4byte eqe*/
 470         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 471         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 472                         __ilog2_u32(eq->len/256));
 473         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 474                         eq_delay_to_mult(eq_delay));
 475         be_dws_cpu_to_le(req->context, sizeof(req->context));
 476
 477         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 478
 479         status = be_mbox_notify_wait(adapter);
 480         if (!status) {
 481                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 482                 eq->id = le16_to_cpu(resp->eq_id);
 483                 eq->created = true;
 484         }
 485
 486         spin_unlock(&adapter->mbox_lock);
 487         return status;
 488 }
 489
 490 /* Uses mbox */
 491 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 492                         u8 type, bool permanent, u32 if_handle)
 493 {
 494         struct be_mcc_wrb *wrb;
 495         struct be_cmd_req_mac_query *req;
 496         int status;
 497
 498         spin_lock(&adapter->mbox_lock);
 499
 500         wrb = wrb_from_mbox(adapter);
 501         req = embedded_payload(wrb);
 502
 503         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 504                         OPCODE_COMMON_NTWK_MAC_QUERY);
 505
 506         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 507                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 508
 509         req->type = type;
 510         if (permanent) {
 511                 req->permanent = 1;
 512         } else {
 513                 req->if_id = cpu_to_le16((u16) if_handle);
 514                 req->permanent = 0;
 515         }
 516
 517         status = be_mbox_notify_wait(adapter);
 518         if (!status) {
 519                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 520                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 521         }
 522
 523         spin_unlock(&adapter->mbox_lock);
 524         return status;
 525 }
 526
 527 /* Uses synchronous MCCQ */
 528 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 529                 u32 if_id, u32 *pmac_id)
 530 {
 531         struct be_mcc_wrb *wrb;
 532         struct be_cmd_req_pmac_add *req;
 533         int status;
 534
 535         spin_lock_bh(&adapter->mcc_lock);
 536
 537         wrb = wrb_from_mccq(adapter);
 538         if (!wrb) {
 539                 status = -EBUSY;
 540                 goto err;
 541         }
 542         req = embedded_payload(wrb);
 543
 544         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 545                         OPCODE_COMMON_NTWK_PMAC_ADD);
 546
 547         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 548                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 549
 550         req->if_id = cpu_to_le32(if_id);
 551         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 552
 553         status = be_mcc_notify_wait(adapter);
 554         if (!status) {
 555                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 556                 *pmac_id = le32_to_cpu(resp->pmac_id);
 557         }
 558
 559 err:
 560         spin_unlock_bh(&adapter->mcc_lock);
 561         return status;
 562 }
 563
 564 /* Uses synchronous MCCQ */
 565 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
 566 {
 567         struct be_mcc_wrb *wrb;
 568         struct be_cmd_req_pmac_del *req;
 569         int status;
 570
 571         spin_lock_bh(&adapter->mcc_lock);
 572
 573         wrb = wrb_from_mccq(adapter);
 574         if (!wrb) {
 575                 status = -EBUSY;
 576                 goto err;
 577         }
 578         req = embedded_payload(wrb);
 579
 580         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 581                         OPCODE_COMMON_NTWK_PMAC_DEL);
 582
 583         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 584                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 585
 586         req->if_id = cpu_to_le32(if_id);
 587         req->pmac_id = cpu_to_le32(pmac_id);
 588
 589         status = be_mcc_notify_wait(adapter);
 590
 591 err:
 592         spin_unlock_bh(&adapter->mcc_lock);
 593         return status;
 594 }
 595
 596 /* Uses Mbox */
 597 int be_cmd_cq_create(struct be_adapter *adapter,
 598                 struct be_queue_info *cq, struct be_queue_info *eq,
 599                 bool sol_evts, bool no_delay, int coalesce_wm)
 600 {
 601         struct be_mcc_wrb *wrb;
 602         struct be_cmd_req_cq_create *req;
 603         struct be_dma_mem *q_mem = &cq->dma_mem;
 604         void *ctxt;
 605         int status;
 606
 607         spin_lock(&adapter->mbox_lock);
 608
 609         wrb = wrb_from_mbox(adapter);
 610         req = embedded_payload(wrb);
 611         ctxt = &req->context;
 612
 613         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 614                         OPCODE_COMMON_CQ_CREATE);
 615
 616         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 617                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 618
 619         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 620
 621         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
 622         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
 623         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
 624                         __ilog2_u32(cq->len/256));
 625         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
 626         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
 627         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
 628         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
 629         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
 630         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 631
 632         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 633
 634         status = be_mbox_notify_wait(adapter);
 635         if (!status) {
 636                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 637                 cq->id = le16_to_cpu(resp->cq_id);
 638                 cq->created = true;
 639         }
 640
 641         spin_unlock(&adapter->mbox_lock);
 642
 643         return status;
 644 }
 645
 646 static u32 be_encoded_q_len(int q_len)
 647 {
 648         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 649         if (len_encoded == 16)
 650                 len_encoded = 0;
 651         return len_encoded;
 652 }
 653
 654 int be_cmd_mccq_create(struct be_adapter *adapter,
 655                         struct be_queue_info *mccq,
 656                         struct be_queue_info *cq)
 657 {
 658         struct be_mcc_wrb *wrb;
 659         struct be_cmd_req_mcc_create *req;
 660         struct be_dma_mem *q_mem = &mccq->dma_mem;
 661         void *ctxt;
 662         int status;
 663
 664         spin_lock(&adapter->mbox_lock);
 665
 666         wrb = wrb_from_mbox(adapter);
 667         req = embedded_payload(wrb);
 668         ctxt = &req->context;
 669
 670         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 671                         OPCODE_COMMON_MCC_CREATE);
 672
 673         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 674                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 675
 676         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 677
 678         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
 679         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
 680                 be_encoded_q_len(mccq->len));
 681         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
 682
 683         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 684
 685         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 686
 687         status = be_mbox_notify_wait(adapter);
 688         if (!status) {
 689                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 690                 mccq->id = le16_to_cpu(resp->id);
 691                 mccq->created = true;
 692         }
 693         spin_unlock(&adapter->mbox_lock);
 694
 695         return status;
 696 }
 697
 698 int be_cmd_txq_create(struct be_adapter *adapter,
 699                         struct be_queue_info *txq,
 700                         struct be_queue_info *cq)
 701 {
 702         struct be_mcc_wrb *wrb;
 703         struct be_cmd_req_eth_tx_create *req;
 704         struct be_dma_mem *q_mem = &txq->dma_mem;
 705         void *ctxt;
 706         int status;
 707
 708         spin_lock(&adapter->mbox_lock);
 709
 710         wrb = wrb_from_mbox(adapter);
 711         req = embedded_payload(wrb);
 712         ctxt = &req->context;
 713
 714         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 715                         OPCODE_ETH_TX_CREATE);
 716
 717         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 718                 sizeof(*req));
 719
 720         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 721         req->ulp_num = BE_ULP1_NUM;
 722         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 723
 724         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 725                 be_encoded_q_len(txq->len));
 726         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 727         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 728
 729         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 730
 731         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 732
 733         status = be_mbox_notify_wait(adapter);
 734         if (!status) {
 735                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 736                 txq->id = le16_to_cpu(resp->cid);
 737                 txq->created = true;
 738         }
 739
 740         spin_unlock(&adapter->mbox_lock);
 741
 742         return status;
 743 }
 744
 745 /* Uses mbox */
 746 int be_cmd_rxq_create(struct be_adapter *adapter,
 747                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 748                 u16 max_frame_size, u32 if_id, u32 rss)
 749 {
 750         struct be_mcc_wrb *wrb;
 751         struct be_cmd_req_eth_rx_create *req;
 752         struct be_dma_mem *q_mem = &rxq->dma_mem;
 753         int status;
 754
 755         spin_lock(&adapter->mbox_lock);
 756
 757         wrb = wrb_from_mbox(adapter);
 758         req = embedded_payload(wrb);
 759
 760         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 761                         OPCODE_ETH_RX_CREATE);
 762
 763         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 764                 sizeof(*req));
 765
 766         req->cq_id = cpu_to_le16(cq_id);
 767         req->frag_size = fls(frag_size) - 1;
 768         req->num_pages = 2;
 769         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 770         req->interface_id = cpu_to_le32(if_id);
 771         req->max_frame_size = cpu_to_le16(max_frame_size);
 772         req->rss_queue = cpu_to_le32(rss);
 773
 774         status = be_mbox_notify_wait(adapter);
 775         if (!status) {
 776                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 777                 rxq->id = le16_to_cpu(resp->id);
 778                 rxq->created = true;
 779         }
 780
 781         spin_unlock(&adapter->mbox_lock);
 782
 783         return status;
 784 }
 785
 786 /* Generic destroyer function for all types of queues
 787  * Uses Mbox
 788  */
 789 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 790                 int queue_type)
 791 {
 792         struct be_mcc_wrb *wrb;
 793         struct be_cmd_req_q_destroy *req;
 794         u8 subsys = 0, opcode = 0;
 795         int status;
 796
 797         if (adapter->eeh_err)
 798                 return -EIO;
 799
 800         spin_lock(&adapter->mbox_lock);
 801
 802         wrb = wrb_from_mbox(adapter);
 803         req = embedded_payload(wrb);
 804
 805         switch (queue_type) {
 806         case QTYPE_EQ:
 807                 subsys = CMD_SUBSYSTEM_COMMON;
 808                 opcode = OPCODE_COMMON_EQ_DESTROY;
 809                 break;
 810         case QTYPE_CQ:
 811                 subsys = CMD_SUBSYSTEM_COMMON;
 812                 opcode = OPCODE_COMMON_CQ_DESTROY;
 813                 break;
 814         case QTYPE_TXQ:
 815                 subsys = CMD_SUBSYSTEM_ETH;
 816                 opcode = OPCODE_ETH_TX_DESTROY;
 817                 break;
 818         case QTYPE_RXQ:
 819                 subsys = CMD_SUBSYSTEM_ETH;
 820                 opcode = OPCODE_ETH_RX_DESTROY;
 821                 break;
 822         case QTYPE_MCCQ:
 823                 subsys = CMD_SUBSYSTEM_COMMON;
 824                 opcode = OPCODE_COMMON_MCC_DESTROY;
 825                 break;
 826         default:
 827                 BUG();
 828         }
 829
 830         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
 831
 832         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 833         req->id = cpu_to_le16(q->id);
 834
 835         status = be_mbox_notify_wait(adapter);
 836
 837         spin_unlock(&adapter->mbox_lock);
 838
 839         return status;
 840 }
 841
 842 /* Create an rx filtering policy configuration on an i/f
 843  * Uses mbox
 844  */
 845 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
 846                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
 847 {
 848         struct be_mcc_wrb *wrb;
 849         struct be_cmd_req_if_create *req;
 850         int status;
 851
 852         spin_lock(&adapter->mbox_lock);
 853
 854         wrb = wrb_from_mbox(adapter);
 855         req = embedded_payload(wrb);
 856
 857         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 858                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
 859
 860         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 861                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
 862
 863         req->capability_flags = cpu_to_le32(cap_flags);
 864         req->enable_flags = cpu_to_le32(en_flags);
 865         req->pmac_invalid = pmac_invalid;
 866         if (!pmac_invalid)
 867                 memcpy(req->mac_addr, mac, ETH_ALEN);
 868
 869         status = be_mbox_notify_wait(adapter);
 870         if (!status) {
 871                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
 872                 *if_handle = le32_to_cpu(resp->interface_id);
 873                 if (!pmac_invalid)
 874                         *pmac_id = le32_to_cpu(resp->pmac_id);
 875         }
 876
 877         spin_unlock(&adapter->mbox_lock);
 878         return status;
 879 }
 880
 881 /* Uses mbox */
 882 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 883 {
 884         struct be_mcc_wrb *wrb;
 885         struct be_cmd_req_if_destroy *req;
 886         int status;
 887
 888         if (adapter->eeh_err)
 889                 return -EIO;
 890
 891         spin_lock(&adapter->mbox_lock);
 892
 893         wrb = wrb_from_mbox(adapter);
 894         req = embedded_payload(wrb);
 895
 896         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 897                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
 898
 899         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 900                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
 901
 902         req->interface_id = cpu_to_le32(interface_id);
 903
 904         status = be_mbox_notify_wait(adapter);
 905
 906         spin_unlock(&adapter->mbox_lock);
 907
 908         return status;
 909 }
 910
 911 /* Get stats is a non embedded command: the request is not embedded inside
 912  * WRB but is a separate dma memory block
 913  * Uses asynchronous MCC
 914  */
 915 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
 916 {
 917         struct be_mcc_wrb *wrb;
 918         struct be_cmd_req_get_stats *req;
 919         struct be_sge *sge;
 920         int status = 0;
 921
 922         spin_lock_bh(&adapter->mcc_lock);
 923
 924         wrb = wrb_from_mccq(adapter);
 925         if (!wrb) {
 926                 status = -EBUSY;
 927                 goto err;
 928         }
 929         req = nonemb_cmd->va;
 930         sge = nonembedded_sgl(wrb);
 931
 932         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
 933                         OPCODE_ETH_GET_STATISTICS);
 934
 935         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 936                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
 937         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
 938         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
 939         sge->len = cpu_to_le32(nonemb_cmd->size);
 940
 941         be_mcc_notify(adapter);
 942
 943 err:
 944         spin_unlock_bh(&adapter->mcc_lock);
 945         return status;
 946 }
 947
 948 /* Uses synchronous mcc */
 949 int be_cmd_link_status_query(struct be_adapter *adapter,
 950                         bool *link_up, u8 *mac_speed, u16 *link_speed)
 951 {
 952         struct be_mcc_wrb *wrb;
 953         struct be_cmd_req_link_status *req;
 954         int status;
 955
 956         spin_lock_bh(&adapter->mcc_lock);
 957
 958         wrb = wrb_from_mccq(adapter);
 959         if (!wrb) {
 960                 status = -EBUSY;
 961                 goto err;
 962         }
 963         req = embedded_payload(wrb);
 964
 965         *link_up = false;
 966
 967         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 968                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
 969
 970         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 971                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
 972
 973         status = be_mcc_notify_wait(adapter);
 974         if (!status) {
 975                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
 976                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
 977                         *link_up = true;
 978                         *link_speed = le16_to_cpu(resp->link_speed);
 979                         *mac_speed = resp->mac_speed;
 980                 }
 981         }
 982
 983 err:
 984         spin_unlock_bh(&adapter->mcc_lock);
 985         return status;
 986 }
 987
 988 /* Uses Mbox */
 989 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
 990 {
 991         struct be_mcc_wrb *wrb;
 992         struct be_cmd_req_get_fw_version *req;
 993         int status;
 994
 995         spin_lock(&adapter->mbox_lock);
 996
 997         wrb = wrb_from_mbox(adapter);
 998         req = embedded_payload(wrb);
 999
1000         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1001                         OPCODE_COMMON_GET_FW_VERSION);
1002
1003         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1004                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1005
1006         status = be_mbox_notify_wait(adapter);
1007         if (!status) {
1008                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1009                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1010         }
1011
1012         spin_unlock(&adapter->mbox_lock);
1013         return status;
1014 }
1015
1016 /* set the EQ delay interval of an EQ to specified value
1017  * Uses async mcc
1018  */
1019 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1020 {
1021         struct be_mcc_wrb *wrb;
1022         struct be_cmd_req_modify_eq_delay *req;
1023         int status = 0;
1024
1025         spin_lock_bh(&adapter->mcc_lock);
1026
1027         wrb = wrb_from_mccq(adapter);
1028         if (!wrb) {
1029                 status = -EBUSY;
1030                 goto err;
1031         }
1032         req = embedded_payload(wrb);
1033
1034         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1035                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1036
1037         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1038                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1039
1040         req->num_eq = cpu_to_le32(1);
1041         req->delay[0].eq_id = cpu_to_le32(eq_id);
1042         req->delay[0].phase = 0;
1043         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1044
1045         be_mcc_notify(adapter);
1046
1047 err:
1048         spin_unlock_bh(&adapter->mcc_lock);
1049         return status;
1050 }
1051
1052 /* Uses sycnhronous mcc */
1053 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1054                         u32 num, bool untagged, bool promiscuous)
1055 {
1056         struct be_mcc_wrb *wrb;
1057         struct be_cmd_req_vlan_config *req;
1058         int status;
1059
1060         spin_lock_bh(&adapter->mcc_lock);
1061
1062         wrb = wrb_from_mccq(adapter);
1063         if (!wrb) {
1064                 status = -EBUSY;
1065                 goto err;
1066         }
1067         req = embedded_payload(wrb);
1068
1069         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1070                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1071
1072         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1073                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1074
1075         req->interface_id = if_id;
1076         req->promiscuous = promiscuous;
1077         req->untagged = untagged;
1078         req->num_vlan = num;
1079         if (!promiscuous) {
1080                 memcpy(req->normal_vlan, vtag_array,
1081                         req->num_vlan * sizeof(vtag_array[0]));
1082         }
1083
1084         status = be_mcc_notify_wait(adapter);
1085
1086 err:
1087         spin_unlock_bh(&adapter->mcc_lock);
1088         return status;
1089 }
1090
1091 /* Uses MCC for this command as it may be called in BH context
1092  * Uses synchronous mcc
1093  */
1094 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1095 {
1096         struct be_mcc_wrb *wrb;
1097         struct be_cmd_req_promiscuous_config *req;
1098         int status;
1099
1100         spin_lock_bh(&adapter->mcc_lock);
1101
1102         wrb = wrb_from_mccq(adapter);
1103         if (!wrb) {
1104                 status = -EBUSY;
1105                 goto err;
1106         }
1107         req = embedded_payload(wrb);
1108
1109         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1110
1111         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1112                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1113
1114         if (port_num)
1115                 req->port1_promiscuous = en;
1116         else
1117                 req->port0_promiscuous = en;
1118
1119         status = be_mcc_notify_wait(adapter);
1120
1121 err:
1122         spin_unlock_bh(&adapter->mcc_lock);
1123         return status;
1124 }
1125
1126 /*
1127  * Uses MCC for this command as it may be called in BH context
1128  * (mc == NULL) => multicast promiscous
1129  */
1130 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1131                 struct net_device *netdev, struct be_dma_mem *mem)
1132 {
1133         struct be_mcc_wrb *wrb;
1134         struct be_cmd_req_mcast_mac_config *req = mem->va;
1135         struct be_sge *sge;
1136         int status;
1137
1138         spin_lock_bh(&adapter->mcc_lock);
1139
1140         wrb = wrb_from_mccq(adapter);
1141         if (!wrb) {
1142                 status = -EBUSY;
1143                 goto err;
1144         }
1145         sge = nonembedded_sgl(wrb);
1146         memset(req, 0, sizeof(*req));
1147
1148         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1149                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1150         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1151         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1152         sge->len = cpu_to_le32(mem->size);
1153
1154         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1155                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1156
1157         req->interface_id = if_id;
1158         if (netdev) {
1159                 int i;
1160                 struct dev_mc_list *mc;
1161
1162                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1163
1164                 i = 0;
1165                 netdev_for_each_mc_addr(mc, netdev)
1166                         memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1167         } else {
1168                 req->promiscuous = 1;
1169         }
1170
1171         status = be_mcc_notify_wait(adapter);
1172
1173 err:
1174         spin_unlock_bh(&adapter->mcc_lock);
1175         return status;
1176 }
1177
1178 /* Uses synchrounous mcc */
1179 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1180 {
1181         struct be_mcc_wrb *wrb;
1182         struct be_cmd_req_set_flow_control *req;
1183         int status;
1184
1185         spin_lock_bh(&adapter->mcc_lock);
1186
1187         wrb = wrb_from_mccq(adapter);
1188         if (!wrb) {
1189                 status = -EBUSY;
1190                 goto err;
1191         }
1192         req = embedded_payload(wrb);
1193
1194         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1195                         OPCODE_COMMON_SET_FLOW_CONTROL);
1196
1197         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1198                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1199
1200         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1201         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1202
1203         status = be_mcc_notify_wait(adapter);
1204
1205 err:
1206         spin_unlock_bh(&adapter->mcc_lock);
1207         return status;
1208 }
1209
1210 /* Uses sycn mcc */
1211 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1212 {
1213         struct be_mcc_wrb *wrb;
1214         struct be_cmd_req_get_flow_control *req;
1215         int status;
1216
1217         spin_lock_bh(&adapter->mcc_lock);
1218
1219         wrb = wrb_from_mccq(adapter);
1220         if (!wrb) {
1221                 status = -EBUSY;
1222                 goto err;
1223         }
1224         req = embedded_payload(wrb);
1225
1226         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1227                         OPCODE_COMMON_GET_FLOW_CONTROL);
1228
1229         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1230                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1231
1232         status = be_mcc_notify_wait(adapter);
1233         if (!status) {
1234                 struct be_cmd_resp_get_flow_control *resp =
1235                                                 embedded_payload(wrb);
1236                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1237                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1238         }
1239
1240 err:
1241         spin_unlock_bh(&adapter->mcc_lock);
1242         return status;
1243 }
1244
1245 /* Uses mbox */
1246 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1247 {
1248         struct be_mcc_wrb *wrb;
1249         struct be_cmd_req_query_fw_cfg *req;
1250         int status;
1251
1252         spin_lock(&adapter->mbox_lock);
1253
1254         wrb = wrb_from_mbox(adapter);
1255         req = embedded_payload(wrb);
1256
1257         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1258                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1259
1260         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1261                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1262
1263         status = be_mbox_notify_wait(adapter);
1264         if (!status) {
1265                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1266                 *port_num = le32_to_cpu(resp->phys_port);
1267                 *cap = le32_to_cpu(resp->function_cap);
1268         }
1269
1270         spin_unlock(&adapter->mbox_lock);
1271         return status;
1272 }
1273
1274 /* Uses mbox */
1275 int be_cmd_reset_function(struct be_adapter *adapter)
1276 {
1277         struct be_mcc_wrb *wrb;
1278         struct be_cmd_req_hdr *req;
1279         int status;
1280
1281         spin_lock(&adapter->mbox_lock);
1282
1283         wrb = wrb_from_mbox(adapter);
1284         req = embedded_payload(wrb);
1285
1286         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1287                         OPCODE_COMMON_FUNCTION_RESET);
1288
1289         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1290                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1291
1292         status = be_mbox_notify_wait(adapter);
1293
1294         spin_unlock(&adapter->mbox_lock);
1295         return status;
1296 }
1297
1298 /* Uses sync mcc */
1299 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1300                         u8 bcn, u8 sts, u8 state)
1301 {
1302         struct be_mcc_wrb *wrb;
1303         struct be_cmd_req_enable_disable_beacon *req;
1304         int status;
1305
1306         spin_lock_bh(&adapter->mcc_lock);
1307
1308         wrb = wrb_from_mccq(adapter);
1309         if (!wrb) {
1310                 status = -EBUSY;
1311                 goto err;
1312         }
1313         req = embedded_payload(wrb);
1314
1315         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1316                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1317
1318         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1319                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1320
1321         req->port_num = port_num;
1322         req->beacon_state = state;
1323         req->beacon_duration = bcn;
1324         req->status_duration = sts;
1325
1326         status = be_mcc_notify_wait(adapter);
1327
1328 err:
1329         spin_unlock_bh(&adapter->mcc_lock);
1330         return status;
1331 }
1332
1333 /* Uses sync mcc */
1334 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1335 {
1336         struct be_mcc_wrb *wrb;
1337         struct be_cmd_req_get_beacon_state *req;
1338         int status;
1339
1340         spin_lock_bh(&adapter->mcc_lock);
1341
1342         wrb = wrb_from_mccq(adapter);
1343         if (!wrb) {
1344                 status = -EBUSY;
1345                 goto err;
1346         }
1347         req = embedded_payload(wrb);
1348
1349         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1350                         OPCODE_COMMON_GET_BEACON_STATE);
1351
1352         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1353                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1354
1355         req->port_num = port_num;
1356
1357         status = be_mcc_notify_wait(adapter);
1358         if (!status) {
1359                 struct be_cmd_resp_get_beacon_state *resp =
1360                                                 embedded_payload(wrb);
1361                 *state = resp->beacon_state;
1362         }
1363
1364 err:
1365         spin_unlock_bh(&adapter->mcc_lock);
1366         return status;
1367 }
1368
1369 /* Uses sync mcc */
1370 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1371                                 u8 *connector)
1372 {
1373         struct be_mcc_wrb *wrb;
1374         struct be_cmd_req_port_type *req;
1375         int status;
1376
1377         spin_lock_bh(&adapter->mcc_lock);
1378
1379         wrb = wrb_from_mccq(adapter);
1380         if (!wrb) {
1381                 status = -EBUSY;
1382                 goto err;
1383         }
1384         req = embedded_payload(wrb);
1385
1386         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1387                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1388
1389         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1390                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1391
1392         req->port = cpu_to_le32(port);
1393         req->page_num = cpu_to_le32(TR_PAGE_A0);
1394         status = be_mcc_notify_wait(adapter);
1395         if (!status) {
1396                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1397                         *connector = resp->data.connector;
1398         }
1399
1400 err:
1401         spin_unlock_bh(&adapter->mcc_lock);
1402         return status;
1403 }
1404
1405 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1406                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1407 {
1408         struct be_mcc_wrb *wrb;
1409         struct be_cmd_write_flashrom *req;
1410         struct be_sge *sge;
1411         int status;
1412
1413         spin_lock_bh(&adapter->mcc_lock);
1414
1415         wrb = wrb_from_mccq(adapter);
1416         if (!wrb) {
1417                 status = -EBUSY;
1418                 goto err;
1419         }
1420         req = cmd->va;
1421         sge = nonembedded_sgl(wrb);
1422
1423         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1424                         OPCODE_COMMON_WRITE_FLASHROM);
1425
1426         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1427                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1428         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1429         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1430         sge->len = cpu_to_le32(cmd->size);
1431
1432         req->params.op_type = cpu_to_le32(flash_type);
1433         req->params.op_code = cpu_to_le32(flash_opcode);
1434         req->params.data_buf_size = cpu_to_le32(buf_size);
1435
1436         status = be_mcc_notify_wait(adapter);
1437
1438 err:
1439         spin_unlock_bh(&adapter->mcc_lock);
1440         return status;
1441 }
1442
1443 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1444                          int offset)
1445 {
1446         struct be_mcc_wrb *wrb;
1447         struct be_cmd_write_flashrom *req;
1448         int status;
1449
1450         spin_lock_bh(&adapter->mcc_lock);
1451
1452         wrb = wrb_from_mccq(adapter);
1453         if (!wrb) {
1454                 status = -EBUSY;
1455                 goto err;
1456         }
1457         req = embedded_payload(wrb);
1458
1459         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1460                         OPCODE_COMMON_READ_FLASHROM);
1461
1462         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1463                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1464
1465         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1466         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1467         req->params.offset = cpu_to_le32(offset);
1468         req->params.data_buf_size = cpu_to_le32(0x4);
1469
1470         status = be_mcc_notify_wait(adapter);
1471         if (!status)
1472                 memcpy(flashed_crc, req->params.data_buf, 4);
1473
1474 err:
1475         spin_unlock_bh(&adapter->mcc_lock);
1476         return status;
1477 }
1478
1479 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1480                                 struct be_dma_mem *nonemb_cmd)
1481 {
1482         struct be_mcc_wrb *wrb;
1483         struct be_cmd_req_acpi_wol_magic_config *req;
1484         struct be_sge *sge;
1485         int status;
1486
1487         spin_lock_bh(&adapter->mcc_lock);
1488
1489         wrb = wrb_from_mccq(adapter);
1490         if (!wrb) {
1491                 status = -EBUSY;
1492                 goto err;
1493         }
1494         req = nonemb_cmd->va;
1495         sge = nonembedded_sgl(wrb);
1496
1497         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1498                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1499
1500         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1501                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1502         memcpy(req->magic_mac, mac, ETH_ALEN);
1503
1504         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1505         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1506         sge->len = cpu_to_le32(nonemb_cmd->size);
1507
1508         status = be_mcc_notify_wait(adapter);
1509
1510 err:
1511         spin_unlock_bh(&adapter->mcc_lock);
1512         return status;
1513 }
1514
1515 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1516                         u8 loopback_type, u8 enable)
1517 {
1518         struct be_mcc_wrb *wrb;
1519         struct be_cmd_req_set_lmode *req;
1520         int status;
1521
1522         spin_lock_bh(&adapter->mcc_lock);
1523
1524         wrb = wrb_from_mccq(adapter);
1525         if (!wrb) {
1526                 status = -EBUSY;
1527                 goto err;
1528         }
1529
1530         req = embedded_payload(wrb);
1531
1532         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1533                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1534
1535         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1536                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1537                         sizeof(*req));
1538
1539         req->src_port = port_num;
1540         req->dest_port = port_num;
1541         req->loopback_type = loopback_type;
1542         req->loopback_state = enable;
1543
1544         status = be_mcc_notify_wait(adapter);
1545 err:
1546         spin_unlock_bh(&adapter->mcc_lock);
1547         return status;
1548 }
1549
1550 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1551                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1552 {
1553         struct be_mcc_wrb *wrb;
1554         struct be_cmd_req_loopback_test *req;
1555         int status;
1556
1557         spin_lock_bh(&adapter->mcc_lock);
1558
1559         wrb = wrb_from_mccq(adapter);
1560         if (!wrb) {
1561                 status = -EBUSY;
1562                 goto err;
1563         }
1564
1565         req = embedded_payload(wrb);
1566
1567         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1568                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1569
1570         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1571                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1572         req->hdr.timeout = 4;
1573
1574         req->pattern = cpu_to_le64(pattern);
1575         req->src_port = cpu_to_le32(port_num);
1576         req->dest_port = cpu_to_le32(port_num);
1577         req->pkt_size = cpu_to_le32(pkt_size);
1578         req->num_pkts = cpu_to_le32(num_pkts);
1579         req->loopback_type = cpu_to_le32(loopback_type);
1580
1581         status = be_mcc_notify_wait(adapter);
1582         if (!status) {
1583                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1584                 status = le32_to_cpu(resp->status);
1585         }
1586
1587 err:
1588         spin_unlock_bh(&adapter->mcc_lock);
1589         return status;
1590 }
1591
1592 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1593                                 u32 byte_cnt, struct be_dma_mem *cmd)
1594 {
1595         struct be_mcc_wrb *wrb;
1596         struct be_cmd_req_ddrdma_test *req;
1597         struct be_sge *sge;
1598         int status;
1599         int i, j = 0;
1600
1601         spin_lock_bh(&adapter->mcc_lock);
1602
1603         wrb = wrb_from_mccq(adapter);
1604         if (!wrb) {
1605                 status = -EBUSY;
1606                 goto err;
1607         }
1608         req = cmd->va;
1609         sge = nonembedded_sgl(wrb);
1610         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1611                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1612         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1613                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1614
1615         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1616         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1617         sge->len = cpu_to_le32(cmd->size);
1618
1619         req->pattern = cpu_to_le64(pattern);
1620         req->byte_count = cpu_to_le32(byte_cnt);
1621         for (i = 0; i < byte_cnt; i++) {
1622                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1623                 j++;
1624                 if (j > 7)
1625                         j = 0;
1626         }
1627
1628         status = be_mcc_notify_wait(adapter);
1629
1630         if (!status) {
1631                 struct be_cmd_resp_ddrdma_test *resp;
1632                 resp = cmd->va;
1633                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1634                                 resp->snd_err) {
1635                         status = -1;
1636                 }
1637         }
1638
1639 err:
1640         spin_unlock_bh(&adapter->mcc_lock);
1641         return status;
1642 }
1643
1644 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1645                                 struct be_dma_mem *nonemb_cmd)
1646 {
1647         struct be_mcc_wrb *wrb;
1648         struct be_cmd_req_seeprom_read *req;
1649         struct be_sge *sge;
1650         int status;
1651
1652         spin_lock_bh(&adapter->mcc_lock);
1653
1654         wrb = wrb_from_mccq(adapter);
1655         req = nonemb_cmd->va;
1656         sge = nonembedded_sgl(wrb);
1657
1658         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1659                         OPCODE_COMMON_SEEPROM_READ);
1660
1661         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1663
1664         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1665         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1666         sge->len = cpu_to_le32(nonemb_cmd->size);
1667
1668         status = be_mcc_notify_wait(adapter);
1669
1670         spin_unlock_bh(&adapter->mcc_lock);
1671         return status;
1672 }