2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter
*adapter
)
23 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
26 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
27 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
28 iowrite32(val
, adapter
->db
+ DB_MCCQ_OFFSET
);
31 /* To check if valid bit is set, check the entire word as we don't know
32 * the endianness of the data (old entry is host endian while a new entry is
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
36 if (compl->flags
!= 0) {
37 compl->flags
= le32_to_cpu(compl->flags
);
38 BUG_ON((compl->flags
& CQE_FLAGS_VALID_MASK
) == 0);
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
51 static int be_mcc_compl_process(struct be_adapter
*adapter
,
52 struct be_mcc_compl
*compl)
54 u16 compl_status
, extd_status
;
56 /* Just swap the status to host endian; mcc tag is opaquely copied
58 be_dws_le_to_cpu(compl, 4);
60 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
61 CQE_STATUS_COMPL_MASK
;
62 if (compl_status
== MCC_STATUS_SUCCESS
) {
63 if (compl->tag0
== OPCODE_ETH_GET_STATISTICS
) {
64 struct be_cmd_resp_get_stats
*resp
=
65 adapter
->stats
.cmd
.va
;
66 be_dws_le_to_cpu(&resp
->hw_stats
,
67 sizeof(resp
->hw_stats
));
68 netdev_stats_update(adapter
);
70 } else if (compl_status
!= MCC_STATUS_NOT_SUPPORTED
) {
71 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
73 dev_warn(&adapter
->pdev
->dev
,
74 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75 compl->tag0
, compl_status
, extd_status
);
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter
*adapter
,
82 struct be_async_event_link_state
*evt
)
84 be_link_status_update(adapter
,
85 evt
->port_link_status
== ASYNC_EVENT_LINK_UP
);
88 static inline bool is_link_state_evt(u32 trailer
)
90 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
91 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
92 ASYNC_EVENT_CODE_LINK_STATE
);
95 static struct be_mcc_compl
*be_mcc_compl_get(struct be_adapter
*adapter
)
97 struct be_queue_info
*mcc_cq
= &adapter
->mcc_obj
.cq
;
98 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
100 if (be_mcc_compl_is_new(compl)) {
101 queue_tail_inc(mcc_cq
);
107 void be_async_mcc_enable(struct be_adapter
*adapter
)
109 spin_lock_bh(&adapter
->mcc_cq_lock
);
111 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, true, 0);
112 adapter
->mcc_obj
.rearm_cq
= true;
114 spin_unlock_bh(&adapter
->mcc_cq_lock
);
117 void be_async_mcc_disable(struct be_adapter
*adapter
)
119 adapter
->mcc_obj
.rearm_cq
= false;
122 int be_process_mcc(struct be_adapter
*adapter
, int *status
)
124 struct be_mcc_compl
*compl;
126 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
128 spin_lock_bh(&adapter
->mcc_cq_lock
);
129 while ((compl = be_mcc_compl_get(adapter
))) {
130 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
131 /* Interpret flags as an async trailer */
132 BUG_ON(!is_link_state_evt(compl->flags
));
134 /* Interpret compl as a async link evt */
135 be_async_link_state_process(adapter
,
136 (struct be_async_event_link_state
*) compl);
137 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
138 *status
= be_mcc_compl_process(adapter
, compl);
139 atomic_dec(&mcc_obj
->q
.used
);
141 be_mcc_compl_use(compl);
145 spin_unlock_bh(&adapter
->mcc_cq_lock
);
149 /* Wait till no more pending mcc requests are present */
150 static int be_mcc_wait_compl(struct be_adapter
*adapter
)
152 #define mcc_timeout 120000 /* 12s timeout */
153 int i
, num
, status
= 0;
154 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
156 for (i
= 0; i
< mcc_timeout
; i
++) {
157 num
= be_process_mcc(adapter
, &status
);
159 be_cq_notify(adapter
, mcc_obj
->cq
.id
,
160 mcc_obj
->rearm_cq
, num
);
162 if (atomic_read(&mcc_obj
->q
.used
) == 0)
166 if (i
== mcc_timeout
) {
167 dev_err(&adapter
->pdev
->dev
, "mccq poll timed out\n");
173 /* Notify MCC requests and wait for completion */
174 static int be_mcc_notify_wait(struct be_adapter
*adapter
)
176 be_mcc_notify(adapter
);
177 return be_mcc_wait_compl(adapter
);
180 static int be_mbox_db_ready_wait(struct be_adapter
*adapter
, void __iomem
*db
)
182 int cnt
= 0, wait
= 5;
186 ready
= ioread32(db
);
187 if (ready
== 0xffffffff) {
188 dev_err(&adapter
->pdev
->dev
,
189 "pci slot disconnected\n");
193 ready
&= MPU_MAILBOX_DB_RDY_MASK
;
198 dev_err(&adapter
->pdev
->dev
, "mbox poll timed out\n");
212 * Insert the mailbox address into the doorbell in two steps
213 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
215 static int be_mbox_notify_wait(struct be_adapter
*adapter
)
219 void __iomem
*db
= adapter
->db
+ MPU_MAILBOX_DB_OFFSET
;
220 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
221 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
222 struct be_mcc_compl
*compl = &mbox
->compl;
224 /* wait for ready to be set */
225 status
= be_mbox_db_ready_wait(adapter
, db
);
229 val
|= MPU_MAILBOX_DB_HI_MASK
;
230 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
234 /* wait for ready to be set */
235 status
= be_mbox_db_ready_wait(adapter
, db
);
240 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
244 status
= be_mbox_db_ready_wait(adapter
, db
);
248 /* A cq entry has been made now */
249 if (be_mcc_compl_is_new(compl)) {
250 status
= be_mcc_compl_process(adapter
, &mbox
->compl);
251 be_mcc_compl_use(compl);
255 dev_err(&adapter
->pdev
->dev
, "invalid mailbox completion\n");
261 static int be_POST_stage_get(struct be_adapter
*adapter
, u16
*stage
)
263 u32 sem
= ioread32(adapter
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
265 *stage
= sem
& EP_SEMAPHORE_POST_STAGE_MASK
;
266 if ((sem
>> EP_SEMAPHORE_POST_ERR_SHIFT
) & EP_SEMAPHORE_POST_ERR_MASK
)
272 int be_cmd_POST(struct be_adapter
*adapter
)
275 int status
, timeout
= 0;
278 status
= be_POST_stage_get(adapter
, &stage
);
280 dev_err(&adapter
->pdev
->dev
, "POST error; stage=0x%x\n",
283 } else if (stage
!= POST_STAGE_ARMFW_RDY
) {
284 set_current_state(TASK_INTERRUPTIBLE
);
285 schedule_timeout(2 * HZ
);
290 } while (timeout
< 20);
292 dev_err(&adapter
->pdev
->dev
, "POST timeout; stage=0x%x\n", stage
);
296 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
298 return wrb
->payload
.embedded_payload
;
301 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
303 return &wrb
->payload
.sgl
[0];
306 /* Don't touch the hdr after it's prepared */
307 static void be_wrb_hdr_prepare(struct be_mcc_wrb
*wrb
, int payload_len
,
308 bool embedded
, u8 sge_cnt
, u32 opcode
)
311 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
313 wrb
->embedded
|= (sge_cnt
& MCC_WRB_SGE_CNT_MASK
) <<
314 MCC_WRB_SGE_CNT_SHIFT
;
315 wrb
->payload_length
= payload_len
;
317 be_dws_cpu_to_le(wrb
, 8);
320 /* Don't touch the hdr after it's prepared */
321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
322 u8 subsystem
, u8 opcode
, int cmd_len
)
324 req_hdr
->opcode
= opcode
;
325 req_hdr
->subsystem
= subsystem
;
326 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
327 req_hdr
->version
= 0;
330 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
331 struct be_dma_mem
*mem
)
333 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
334 u64 dma
= (u64
)mem
->dma
;
336 for (i
= 0; i
< buf_pages
; i
++) {
337 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
338 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
343 /* Converts interrupt delay in microseconds to multiplier value */
344 static u32
eq_delay_to_mult(u32 usec_delay
)
346 #define MAX_INTR_RATE 651042
347 const u32 round
= 10;
353 u32 interrupt_rate
= 1000000 / usec_delay
;
354 /* Max delay, corresponding to the lowest interrupt rate */
355 if (interrupt_rate
== 0)
358 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
359 multiplier
/= interrupt_rate
;
360 /* Round the multiplier to the closest value.*/
361 multiplier
= (multiplier
+ round
/2) / round
;
362 multiplier
= min(multiplier
, (u32
)1023);
368 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_adapter
*adapter
)
370 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
371 struct be_mcc_wrb
*wrb
372 = &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
373 memset(wrb
, 0, sizeof(*wrb
));
377 static struct be_mcc_wrb
*wrb_from_mccq(struct be_adapter
*adapter
)
379 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
380 struct be_mcc_wrb
*wrb
;
382 if (atomic_read(&mccq
->used
) >= mccq
->len
) {
383 dev_err(&adapter
->pdev
->dev
, "Out of MCCQ wrbs\n");
387 wrb
= queue_head_node(mccq
);
388 queue_head_inc(mccq
);
389 atomic_inc(&mccq
->used
);
390 memset(wrb
, 0, sizeof(*wrb
));
394 /* Tell fw we're about to start firing cmds by writing a
395 * special pattern across the wrb hdr; uses mbox
397 int be_cmd_fw_init(struct be_adapter
*adapter
)
402 spin_lock(&adapter
->mbox_lock
);
404 wrb
= (u8
*)wrb_from_mbox(adapter
);
414 status
= be_mbox_notify_wait(adapter
);
416 spin_unlock(&adapter
->mbox_lock
);
420 /* Tell fw we're done with firing cmds by writing a
421 * special pattern across the wrb hdr; uses mbox
423 int be_cmd_fw_clean(struct be_adapter
*adapter
)
428 if (adapter
->eeh_err
)
431 spin_lock(&adapter
->mbox_lock
);
433 wrb
= (u8
*)wrb_from_mbox(adapter
);
443 status
= be_mbox_notify_wait(adapter
);
445 spin_unlock(&adapter
->mbox_lock
);
448 int be_cmd_eq_create(struct be_adapter
*adapter
,
449 struct be_queue_info
*eq
, int eq_delay
)
451 struct be_mcc_wrb
*wrb
;
452 struct be_cmd_req_eq_create
*req
;
453 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
456 spin_lock(&adapter
->mbox_lock
);
458 wrb
= wrb_from_mbox(adapter
);
459 req
= embedded_payload(wrb
);
461 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0, OPCODE_COMMON_EQ_CREATE
);
463 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
464 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
));
466 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
468 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
470 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
471 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
472 __ilog2_u32(eq
->len
/256));
473 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
474 eq_delay_to_mult(eq_delay
));
475 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
477 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
479 status
= be_mbox_notify_wait(adapter
);
481 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
482 eq
->id
= le16_to_cpu(resp
->eq_id
);
486 spin_unlock(&adapter
->mbox_lock
);
491 int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
492 u8 type
, bool permanent
, u32 if_handle
)
494 struct be_mcc_wrb
*wrb
;
495 struct be_cmd_req_mac_query
*req
;
498 spin_lock(&adapter
->mbox_lock
);
500 wrb
= wrb_from_mbox(adapter
);
501 req
= embedded_payload(wrb
);
503 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
504 OPCODE_COMMON_NTWK_MAC_QUERY
);
506 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
507 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
));
513 req
->if_id
= cpu_to_le16((u16
) if_handle
);
517 status
= be_mbox_notify_wait(adapter
);
519 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
520 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
523 spin_unlock(&adapter
->mbox_lock
);
527 /* Uses synchronous MCCQ */
528 int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
529 u32 if_id
, u32
*pmac_id
)
531 struct be_mcc_wrb
*wrb
;
532 struct be_cmd_req_pmac_add
*req
;
535 spin_lock_bh(&adapter
->mcc_lock
);
537 wrb
= wrb_from_mccq(adapter
);
542 req
= embedded_payload(wrb
);
544 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
545 OPCODE_COMMON_NTWK_PMAC_ADD
);
547 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
548 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
));
550 req
->if_id
= cpu_to_le32(if_id
);
551 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
553 status
= be_mcc_notify_wait(adapter
);
555 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
556 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
560 spin_unlock_bh(&adapter
->mcc_lock
);
564 /* Uses synchronous MCCQ */
565 int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
, u32 pmac_id
)
567 struct be_mcc_wrb
*wrb
;
568 struct be_cmd_req_pmac_del
*req
;
571 spin_lock_bh(&adapter
->mcc_lock
);
573 wrb
= wrb_from_mccq(adapter
);
578 req
= embedded_payload(wrb
);
580 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
581 OPCODE_COMMON_NTWK_PMAC_DEL
);
583 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
584 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
));
586 req
->if_id
= cpu_to_le32(if_id
);
587 req
->pmac_id
= cpu_to_le32(pmac_id
);
589 status
= be_mcc_notify_wait(adapter
);
592 spin_unlock_bh(&adapter
->mcc_lock
);
597 int be_cmd_cq_create(struct be_adapter
*adapter
,
598 struct be_queue_info
*cq
, struct be_queue_info
*eq
,
599 bool sol_evts
, bool no_delay
, int coalesce_wm
)
601 struct be_mcc_wrb
*wrb
;
602 struct be_cmd_req_cq_create
*req
;
603 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
607 spin_lock(&adapter
->mbox_lock
);
609 wrb
= wrb_from_mbox(adapter
);
610 req
= embedded_payload(wrb
);
611 ctxt
= &req
->context
;
613 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
614 OPCODE_COMMON_CQ_CREATE
);
616 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
617 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
));
619 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
621 AMAP_SET_BITS(struct amap_cq_context
, coalescwm
, ctxt
, coalesce_wm
);
622 AMAP_SET_BITS(struct amap_cq_context
, nodelay
, ctxt
, no_delay
);
623 AMAP_SET_BITS(struct amap_cq_context
, count
, ctxt
,
624 __ilog2_u32(cq
->len
/256));
625 AMAP_SET_BITS(struct amap_cq_context
, valid
, ctxt
, 1);
626 AMAP_SET_BITS(struct amap_cq_context
, solevent
, ctxt
, sol_evts
);
627 AMAP_SET_BITS(struct amap_cq_context
, eventable
, ctxt
, 1);
628 AMAP_SET_BITS(struct amap_cq_context
, eqid
, ctxt
, eq
->id
);
629 AMAP_SET_BITS(struct amap_cq_context
, armed
, ctxt
, 1);
630 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
632 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
634 status
= be_mbox_notify_wait(adapter
);
636 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
637 cq
->id
= le16_to_cpu(resp
->cq_id
);
641 spin_unlock(&adapter
->mbox_lock
);
646 static u32
be_encoded_q_len(int q_len
)
648 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
649 if (len_encoded
== 16)
654 int be_cmd_mccq_create(struct be_adapter
*adapter
,
655 struct be_queue_info
*mccq
,
656 struct be_queue_info
*cq
)
658 struct be_mcc_wrb
*wrb
;
659 struct be_cmd_req_mcc_create
*req
;
660 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
664 spin_lock(&adapter
->mbox_lock
);
666 wrb
= wrb_from_mbox(adapter
);
667 req
= embedded_payload(wrb
);
668 ctxt
= &req
->context
;
670 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
671 OPCODE_COMMON_MCC_CREATE
);
673 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
674 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
));
676 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
678 AMAP_SET_BITS(struct amap_mcc_context
, valid
, ctxt
, 1);
679 AMAP_SET_BITS(struct amap_mcc_context
, ring_size
, ctxt
,
680 be_encoded_q_len(mccq
->len
));
681 AMAP_SET_BITS(struct amap_mcc_context
, cq_id
, ctxt
, cq
->id
);
683 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
685 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
687 status
= be_mbox_notify_wait(adapter
);
689 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
690 mccq
->id
= le16_to_cpu(resp
->id
);
691 mccq
->created
= true;
693 spin_unlock(&adapter
->mbox_lock
);
698 int be_cmd_txq_create(struct be_adapter
*adapter
,
699 struct be_queue_info
*txq
,
700 struct be_queue_info
*cq
)
702 struct be_mcc_wrb
*wrb
;
703 struct be_cmd_req_eth_tx_create
*req
;
704 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
708 spin_lock(&adapter
->mbox_lock
);
710 wrb
= wrb_from_mbox(adapter
);
711 req
= embedded_payload(wrb
);
712 ctxt
= &req
->context
;
714 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
715 OPCODE_ETH_TX_CREATE
);
717 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_TX_CREATE
,
720 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
721 req
->ulp_num
= BE_ULP1_NUM
;
722 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
724 AMAP_SET_BITS(struct amap_tx_context
, tx_ring_size
, ctxt
,
725 be_encoded_q_len(txq
->len
));
726 AMAP_SET_BITS(struct amap_tx_context
, ctx_valid
, ctxt
, 1);
727 AMAP_SET_BITS(struct amap_tx_context
, cq_id_send
, ctxt
, cq
->id
);
729 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
731 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
733 status
= be_mbox_notify_wait(adapter
);
735 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(wrb
);
736 txq
->id
= le16_to_cpu(resp
->cid
);
740 spin_unlock(&adapter
->mbox_lock
);
746 int be_cmd_rxq_create(struct be_adapter
*adapter
,
747 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
748 u16 max_frame_size
, u32 if_id
, u32 rss
)
750 struct be_mcc_wrb
*wrb
;
751 struct be_cmd_req_eth_rx_create
*req
;
752 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
755 spin_lock(&adapter
->mbox_lock
);
757 wrb
= wrb_from_mbox(adapter
);
758 req
= embedded_payload(wrb
);
760 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
761 OPCODE_ETH_RX_CREATE
);
763 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_RX_CREATE
,
766 req
->cq_id
= cpu_to_le16(cq_id
);
767 req
->frag_size
= fls(frag_size
) - 1;
769 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
770 req
->interface_id
= cpu_to_le32(if_id
);
771 req
->max_frame_size
= cpu_to_le16(max_frame_size
);
772 req
->rss_queue
= cpu_to_le32(rss
);
774 status
= be_mbox_notify_wait(adapter
);
776 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
777 rxq
->id
= le16_to_cpu(resp
->id
);
781 spin_unlock(&adapter
->mbox_lock
);
786 /* Generic destroyer function for all types of queues
789 int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
792 struct be_mcc_wrb
*wrb
;
793 struct be_cmd_req_q_destroy
*req
;
794 u8 subsys
= 0, opcode
= 0;
797 if (adapter
->eeh_err
)
800 spin_lock(&adapter
->mbox_lock
);
802 wrb
= wrb_from_mbox(adapter
);
803 req
= embedded_payload(wrb
);
805 switch (queue_type
) {
807 subsys
= CMD_SUBSYSTEM_COMMON
;
808 opcode
= OPCODE_COMMON_EQ_DESTROY
;
811 subsys
= CMD_SUBSYSTEM_COMMON
;
812 opcode
= OPCODE_COMMON_CQ_DESTROY
;
815 subsys
= CMD_SUBSYSTEM_ETH
;
816 opcode
= OPCODE_ETH_TX_DESTROY
;
819 subsys
= CMD_SUBSYSTEM_ETH
;
820 opcode
= OPCODE_ETH_RX_DESTROY
;
823 subsys
= CMD_SUBSYSTEM_COMMON
;
824 opcode
= OPCODE_COMMON_MCC_DESTROY
;
830 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0, opcode
);
832 be_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
));
833 req
->id
= cpu_to_le16(q
->id
);
835 status
= be_mbox_notify_wait(adapter
);
837 spin_unlock(&adapter
->mbox_lock
);
842 /* Create an rx filtering policy configuration on an i/f
845 int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
, u32 en_flags
,
846 u8
*mac
, bool pmac_invalid
, u32
*if_handle
, u32
*pmac_id
)
848 struct be_mcc_wrb
*wrb
;
849 struct be_cmd_req_if_create
*req
;
852 spin_lock(&adapter
->mbox_lock
);
854 wrb
= wrb_from_mbox(adapter
);
855 req
= embedded_payload(wrb
);
857 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
858 OPCODE_COMMON_NTWK_INTERFACE_CREATE
);
860 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
861 OPCODE_COMMON_NTWK_INTERFACE_CREATE
, sizeof(*req
));
863 req
->capability_flags
= cpu_to_le32(cap_flags
);
864 req
->enable_flags
= cpu_to_le32(en_flags
);
865 req
->pmac_invalid
= pmac_invalid
;
867 memcpy(req
->mac_addr
, mac
, ETH_ALEN
);
869 status
= be_mbox_notify_wait(adapter
);
871 struct be_cmd_resp_if_create
*resp
= embedded_payload(wrb
);
872 *if_handle
= le32_to_cpu(resp
->interface_id
);
874 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
877 spin_unlock(&adapter
->mbox_lock
);
882 int be_cmd_if_destroy(struct be_adapter
*adapter
, u32 interface_id
)
884 struct be_mcc_wrb
*wrb
;
885 struct be_cmd_req_if_destroy
*req
;
888 if (adapter
->eeh_err
)
891 spin_lock(&adapter
->mbox_lock
);
893 wrb
= wrb_from_mbox(adapter
);
894 req
= embedded_payload(wrb
);
896 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
897 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
);
899 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
900 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
, sizeof(*req
));
902 req
->interface_id
= cpu_to_le32(interface_id
);
904 status
= be_mbox_notify_wait(adapter
);
906 spin_unlock(&adapter
->mbox_lock
);
911 /* Get stats is a non embedded command: the request is not embedded inside
912 * WRB but is a separate dma memory block
913 * Uses asynchronous MCC
915 int be_cmd_get_stats(struct be_adapter
*adapter
, struct be_dma_mem
*nonemb_cmd
)
917 struct be_mcc_wrb
*wrb
;
918 struct be_cmd_req_get_stats
*req
;
922 spin_lock_bh(&adapter
->mcc_lock
);
924 wrb
= wrb_from_mccq(adapter
);
929 req
= nonemb_cmd
->va
;
930 sge
= nonembedded_sgl(wrb
);
932 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1,
933 OPCODE_ETH_GET_STATISTICS
);
935 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
936 OPCODE_ETH_GET_STATISTICS
, sizeof(*req
));
937 sge
->pa_hi
= cpu_to_le32(upper_32_bits(nonemb_cmd
->dma
));
938 sge
->pa_lo
= cpu_to_le32(nonemb_cmd
->dma
& 0xFFFFFFFF);
939 sge
->len
= cpu_to_le32(nonemb_cmd
->size
);
941 be_mcc_notify(adapter
);
944 spin_unlock_bh(&adapter
->mcc_lock
);
948 /* Uses synchronous mcc */
949 int be_cmd_link_status_query(struct be_adapter
*adapter
,
950 bool *link_up
, u8
*mac_speed
, u16
*link_speed
)
952 struct be_mcc_wrb
*wrb
;
953 struct be_cmd_req_link_status
*req
;
956 spin_lock_bh(&adapter
->mcc_lock
);
958 wrb
= wrb_from_mccq(adapter
);
963 req
= embedded_payload(wrb
);
967 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
968 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
);
970 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
971 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
, sizeof(*req
));
973 status
= be_mcc_notify_wait(adapter
);
975 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
976 if (resp
->mac_speed
!= PHY_LINK_SPEED_ZERO
) {
978 *link_speed
= le16_to_cpu(resp
->link_speed
);
979 *mac_speed
= resp
->mac_speed
;
984 spin_unlock_bh(&adapter
->mcc_lock
);
989 int be_cmd_get_fw_ver(struct be_adapter
*adapter
, char *fw_ver
)
991 struct be_mcc_wrb
*wrb
;
992 struct be_cmd_req_get_fw_version
*req
;
995 spin_lock(&adapter
->mbox_lock
);
997 wrb
= wrb_from_mbox(adapter
);
998 req
= embedded_payload(wrb
);
1000 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1001 OPCODE_COMMON_GET_FW_VERSION
);
1003 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1004 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
));
1006 status
= be_mbox_notify_wait(adapter
);
1008 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
1009 strncpy(fw_ver
, resp
->firmware_version_string
, FW_VER_LEN
);
1012 spin_unlock(&adapter
->mbox_lock
);
1016 /* set the EQ delay interval of an EQ to specified value
1019 int be_cmd_modify_eqd(struct be_adapter
*adapter
, u32 eq_id
, u32 eqd
)
1021 struct be_mcc_wrb
*wrb
;
1022 struct be_cmd_req_modify_eq_delay
*req
;
1025 spin_lock_bh(&adapter
->mcc_lock
);
1027 wrb
= wrb_from_mccq(adapter
);
1032 req
= embedded_payload(wrb
);
1034 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1035 OPCODE_COMMON_MODIFY_EQ_DELAY
);
1037 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1038 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
));
1040 req
->num_eq
= cpu_to_le32(1);
1041 req
->delay
[0].eq_id
= cpu_to_le32(eq_id
);
1042 req
->delay
[0].phase
= 0;
1043 req
->delay
[0].delay_multiplier
= cpu_to_le32(eqd
);
1045 be_mcc_notify(adapter
);
1048 spin_unlock_bh(&adapter
->mcc_lock
);
1052 /* Uses sycnhronous mcc */
1053 int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
, u16
*vtag_array
,
1054 u32 num
, bool untagged
, bool promiscuous
)
1056 struct be_mcc_wrb
*wrb
;
1057 struct be_cmd_req_vlan_config
*req
;
1060 spin_lock_bh(&adapter
->mcc_lock
);
1062 wrb
= wrb_from_mccq(adapter
);
1067 req
= embedded_payload(wrb
);
1069 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1070 OPCODE_COMMON_NTWK_VLAN_CONFIG
);
1072 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1073 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
));
1075 req
->interface_id
= if_id
;
1076 req
->promiscuous
= promiscuous
;
1077 req
->untagged
= untagged
;
1078 req
->num_vlan
= num
;
1080 memcpy(req
->normal_vlan
, vtag_array
,
1081 req
->num_vlan
* sizeof(vtag_array
[0]));
1084 status
= be_mcc_notify_wait(adapter
);
1087 spin_unlock_bh(&adapter
->mcc_lock
);
1091 /* Uses MCC for this command as it may be called in BH context
1092 * Uses synchronous mcc
1094 int be_cmd_promiscuous_config(struct be_adapter
*adapter
, u8 port_num
, bool en
)
1096 struct be_mcc_wrb
*wrb
;
1097 struct be_cmd_req_promiscuous_config
*req
;
1100 spin_lock_bh(&adapter
->mcc_lock
);
1102 wrb
= wrb_from_mccq(adapter
);
1107 req
= embedded_payload(wrb
);
1109 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0, OPCODE_ETH_PROMISCUOUS
);
1111 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1112 OPCODE_ETH_PROMISCUOUS
, sizeof(*req
));
1115 req
->port1_promiscuous
= en
;
1117 req
->port0_promiscuous
= en
;
1119 status
= be_mcc_notify_wait(adapter
);
1122 spin_unlock_bh(&adapter
->mcc_lock
);
1127 * Uses MCC for this command as it may be called in BH context
1128 * (mc == NULL) => multicast promiscous
1130 int be_cmd_multicast_set(struct be_adapter
*adapter
, u32 if_id
,
1131 struct net_device
*netdev
, struct be_dma_mem
*mem
)
1133 struct be_mcc_wrb
*wrb
;
1134 struct be_cmd_req_mcast_mac_config
*req
= mem
->va
;
1138 spin_lock_bh(&adapter
->mcc_lock
);
1140 wrb
= wrb_from_mccq(adapter
);
1145 sge
= nonembedded_sgl(wrb
);
1146 memset(req
, 0, sizeof(*req
));
1148 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1,
1149 OPCODE_COMMON_NTWK_MULTICAST_SET
);
1150 sge
->pa_hi
= cpu_to_le32(upper_32_bits(mem
->dma
));
1151 sge
->pa_lo
= cpu_to_le32(mem
->dma
& 0xFFFFFFFF);
1152 sge
->len
= cpu_to_le32(mem
->size
);
1154 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1155 OPCODE_COMMON_NTWK_MULTICAST_SET
, sizeof(*req
));
1157 req
->interface_id
= if_id
;
1160 struct dev_mc_list
*mc
;
1162 req
->num_mac
= cpu_to_le16(netdev_mc_count(netdev
));
1165 netdev_for_each_mc_addr(mc
, netdev
)
1166 memcpy(req
->mac
[i
].byte
, mc
->dmi_addr
, ETH_ALEN
);
1168 req
->promiscuous
= 1;
1171 status
= be_mcc_notify_wait(adapter
);
1174 spin_unlock_bh(&adapter
->mcc_lock
);
1178 /* Uses synchrounous mcc */
1179 int be_cmd_set_flow_control(struct be_adapter
*adapter
, u32 tx_fc
, u32 rx_fc
)
1181 struct be_mcc_wrb
*wrb
;
1182 struct be_cmd_req_set_flow_control
*req
;
1185 spin_lock_bh(&adapter
->mcc_lock
);
1187 wrb
= wrb_from_mccq(adapter
);
1192 req
= embedded_payload(wrb
);
1194 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1195 OPCODE_COMMON_SET_FLOW_CONTROL
);
1197 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1198 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
));
1200 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
1201 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
1203 status
= be_mcc_notify_wait(adapter
);
1206 spin_unlock_bh(&adapter
->mcc_lock
);
1211 int be_cmd_get_flow_control(struct be_adapter
*adapter
, u32
*tx_fc
, u32
*rx_fc
)
1213 struct be_mcc_wrb
*wrb
;
1214 struct be_cmd_req_get_flow_control
*req
;
1217 spin_lock_bh(&adapter
->mcc_lock
);
1219 wrb
= wrb_from_mccq(adapter
);
1224 req
= embedded_payload(wrb
);
1226 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1227 OPCODE_COMMON_GET_FLOW_CONTROL
);
1229 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1230 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
));
1232 status
= be_mcc_notify_wait(adapter
);
1234 struct be_cmd_resp_get_flow_control
*resp
=
1235 embedded_payload(wrb
);
1236 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
1237 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
1241 spin_unlock_bh(&adapter
->mcc_lock
);
1246 int be_cmd_query_fw_cfg(struct be_adapter
*adapter
, u32
*port_num
, u32
*cap
)
1248 struct be_mcc_wrb
*wrb
;
1249 struct be_cmd_req_query_fw_cfg
*req
;
1252 spin_lock(&adapter
->mbox_lock
);
1254 wrb
= wrb_from_mbox(adapter
);
1255 req
= embedded_payload(wrb
);
1257 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1258 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
);
1260 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1261 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
, sizeof(*req
));
1263 status
= be_mbox_notify_wait(adapter
);
1265 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
1266 *port_num
= le32_to_cpu(resp
->phys_port
);
1267 *cap
= le32_to_cpu(resp
->function_cap
);
1270 spin_unlock(&adapter
->mbox_lock
);
1275 int be_cmd_reset_function(struct be_adapter
*adapter
)
1277 struct be_mcc_wrb
*wrb
;
1278 struct be_cmd_req_hdr
*req
;
1281 spin_lock(&adapter
->mbox_lock
);
1283 wrb
= wrb_from_mbox(adapter
);
1284 req
= embedded_payload(wrb
);
1286 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1287 OPCODE_COMMON_FUNCTION_RESET
);
1289 be_cmd_hdr_prepare(req
, CMD_SUBSYSTEM_COMMON
,
1290 OPCODE_COMMON_FUNCTION_RESET
, sizeof(*req
));
1292 status
= be_mbox_notify_wait(adapter
);
1294 spin_unlock(&adapter
->mbox_lock
);
1299 int be_cmd_set_beacon_state(struct be_adapter
*adapter
, u8 port_num
,
1300 u8 bcn
, u8 sts
, u8 state
)
1302 struct be_mcc_wrb
*wrb
;
1303 struct be_cmd_req_enable_disable_beacon
*req
;
1306 spin_lock_bh(&adapter
->mcc_lock
);
1308 wrb
= wrb_from_mccq(adapter
);
1313 req
= embedded_payload(wrb
);
1315 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1316 OPCODE_COMMON_ENABLE_DISABLE_BEACON
);
1318 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1319 OPCODE_COMMON_ENABLE_DISABLE_BEACON
, sizeof(*req
));
1321 req
->port_num
= port_num
;
1322 req
->beacon_state
= state
;
1323 req
->beacon_duration
= bcn
;
1324 req
->status_duration
= sts
;
1326 status
= be_mcc_notify_wait(adapter
);
1329 spin_unlock_bh(&adapter
->mcc_lock
);
1334 int be_cmd_get_beacon_state(struct be_adapter
*adapter
, u8 port_num
, u32
*state
)
1336 struct be_mcc_wrb
*wrb
;
1337 struct be_cmd_req_get_beacon_state
*req
;
1340 spin_lock_bh(&adapter
->mcc_lock
);
1342 wrb
= wrb_from_mccq(adapter
);
1347 req
= embedded_payload(wrb
);
1349 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1350 OPCODE_COMMON_GET_BEACON_STATE
);
1352 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1353 OPCODE_COMMON_GET_BEACON_STATE
, sizeof(*req
));
1355 req
->port_num
= port_num
;
1357 status
= be_mcc_notify_wait(adapter
);
1359 struct be_cmd_resp_get_beacon_state
*resp
=
1360 embedded_payload(wrb
);
1361 *state
= resp
->beacon_state
;
1365 spin_unlock_bh(&adapter
->mcc_lock
);
1370 int be_cmd_read_port_type(struct be_adapter
*adapter
, u32 port
,
1373 struct be_mcc_wrb
*wrb
;
1374 struct be_cmd_req_port_type
*req
;
1377 spin_lock_bh(&adapter
->mcc_lock
);
1379 wrb
= wrb_from_mccq(adapter
);
1384 req
= embedded_payload(wrb
);
1386 be_wrb_hdr_prepare(wrb
, sizeof(struct be_cmd_resp_port_type
), true, 0,
1387 OPCODE_COMMON_READ_TRANSRECV_DATA
);
1389 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1390 OPCODE_COMMON_READ_TRANSRECV_DATA
, sizeof(*req
));
1392 req
->port
= cpu_to_le32(port
);
1393 req
->page_num
= cpu_to_le32(TR_PAGE_A0
);
1394 status
= be_mcc_notify_wait(adapter
);
1396 struct be_cmd_resp_port_type
*resp
= embedded_payload(wrb
);
1397 *connector
= resp
->data
.connector
;
1401 spin_unlock_bh(&adapter
->mcc_lock
);
1405 int be_cmd_write_flashrom(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
1406 u32 flash_type
, u32 flash_opcode
, u32 buf_size
)
1408 struct be_mcc_wrb
*wrb
;
1409 struct be_cmd_write_flashrom
*req
;
1413 spin_lock_bh(&adapter
->mcc_lock
);
1415 wrb
= wrb_from_mccq(adapter
);
1421 sge
= nonembedded_sgl(wrb
);
1423 be_wrb_hdr_prepare(wrb
, cmd
->size
, false, 1,
1424 OPCODE_COMMON_WRITE_FLASHROM
);
1426 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1427 OPCODE_COMMON_WRITE_FLASHROM
, cmd
->size
);
1428 sge
->pa_hi
= cpu_to_le32(upper_32_bits(cmd
->dma
));
1429 sge
->pa_lo
= cpu_to_le32(cmd
->dma
& 0xFFFFFFFF);
1430 sge
->len
= cpu_to_le32(cmd
->size
);
1432 req
->params
.op_type
= cpu_to_le32(flash_type
);
1433 req
->params
.op_code
= cpu_to_le32(flash_opcode
);
1434 req
->params
.data_buf_size
= cpu_to_le32(buf_size
);
1436 status
= be_mcc_notify_wait(adapter
);
1439 spin_unlock_bh(&adapter
->mcc_lock
);
1443 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
1446 struct be_mcc_wrb
*wrb
;
1447 struct be_cmd_write_flashrom
*req
;
1450 spin_lock_bh(&adapter
->mcc_lock
);
1452 wrb
= wrb_from_mccq(adapter
);
1457 req
= embedded_payload(wrb
);
1459 be_wrb_hdr_prepare(wrb
, sizeof(*req
)+4, true, 0,
1460 OPCODE_COMMON_READ_FLASHROM
);
1462 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1463 OPCODE_COMMON_READ_FLASHROM
, sizeof(*req
)+4);
1465 req
->params
.op_type
= cpu_to_le32(IMG_TYPE_REDBOOT
);
1466 req
->params
.op_code
= cpu_to_le32(FLASHROM_OPER_REPORT
);
1467 req
->params
.offset
= cpu_to_le32(offset
);
1468 req
->params
.data_buf_size
= cpu_to_le32(0x4);
1470 status
= be_mcc_notify_wait(adapter
);
1472 memcpy(flashed_crc
, req
->params
.data_buf
, 4);
1475 spin_unlock_bh(&adapter
->mcc_lock
);
1479 extern int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
1480 struct be_dma_mem
*nonemb_cmd
)
1482 struct be_mcc_wrb
*wrb
;
1483 struct be_cmd_req_acpi_wol_magic_config
*req
;
1487 spin_lock_bh(&adapter
->mcc_lock
);
1489 wrb
= wrb_from_mccq(adapter
);
1494 req
= nonemb_cmd
->va
;
1495 sge
= nonembedded_sgl(wrb
);
1497 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1,
1498 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
);
1500 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1501 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
, sizeof(*req
));
1502 memcpy(req
->magic_mac
, mac
, ETH_ALEN
);
1504 sge
->pa_hi
= cpu_to_le32(upper_32_bits(nonemb_cmd
->dma
));
1505 sge
->pa_lo
= cpu_to_le32(nonemb_cmd
->dma
& 0xFFFFFFFF);
1506 sge
->len
= cpu_to_le32(nonemb_cmd
->size
);
1508 status
= be_mcc_notify_wait(adapter
);
1511 spin_unlock_bh(&adapter
->mcc_lock
);
1515 int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
1516 u8 loopback_type
, u8 enable
)
1518 struct be_mcc_wrb
*wrb
;
1519 struct be_cmd_req_set_lmode
*req
;
1522 spin_lock_bh(&adapter
->mcc_lock
);
1524 wrb
= wrb_from_mccq(adapter
);
1530 req
= embedded_payload(wrb
);
1532 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1533 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
);
1535 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
1536 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
,
1539 req
->src_port
= port_num
;
1540 req
->dest_port
= port_num
;
1541 req
->loopback_type
= loopback_type
;
1542 req
->loopback_state
= enable
;
1544 status
= be_mcc_notify_wait(adapter
);
1546 spin_unlock_bh(&adapter
->mcc_lock
);
1550 int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
1551 u32 loopback_type
, u32 pkt_size
, u32 num_pkts
, u64 pattern
)
1553 struct be_mcc_wrb
*wrb
;
1554 struct be_cmd_req_loopback_test
*req
;
1557 spin_lock_bh(&adapter
->mcc_lock
);
1559 wrb
= wrb_from_mccq(adapter
);
1565 req
= embedded_payload(wrb
);
1567 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0,
1568 OPCODE_LOWLEVEL_LOOPBACK_TEST
);
1570 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
1571 OPCODE_LOWLEVEL_LOOPBACK_TEST
, sizeof(*req
));
1572 req
->hdr
.timeout
= 4;
1574 req
->pattern
= cpu_to_le64(pattern
);
1575 req
->src_port
= cpu_to_le32(port_num
);
1576 req
->dest_port
= cpu_to_le32(port_num
);
1577 req
->pkt_size
= cpu_to_le32(pkt_size
);
1578 req
->num_pkts
= cpu_to_le32(num_pkts
);
1579 req
->loopback_type
= cpu_to_le32(loopback_type
);
1581 status
= be_mcc_notify_wait(adapter
);
1583 struct be_cmd_resp_loopback_test
*resp
= embedded_payload(wrb
);
1584 status
= le32_to_cpu(resp
->status
);
1588 spin_unlock_bh(&adapter
->mcc_lock
);
1592 int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
1593 u32 byte_cnt
, struct be_dma_mem
*cmd
)
1595 struct be_mcc_wrb
*wrb
;
1596 struct be_cmd_req_ddrdma_test
*req
;
1601 spin_lock_bh(&adapter
->mcc_lock
);
1603 wrb
= wrb_from_mccq(adapter
);
1609 sge
= nonembedded_sgl(wrb
);
1610 be_wrb_hdr_prepare(wrb
, cmd
->size
, false, 1,
1611 OPCODE_LOWLEVEL_HOST_DDR_DMA
);
1612 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
1613 OPCODE_LOWLEVEL_HOST_DDR_DMA
, cmd
->size
);
1615 sge
->pa_hi
= cpu_to_le32(upper_32_bits(cmd
->dma
));
1616 sge
->pa_lo
= cpu_to_le32(cmd
->dma
& 0xFFFFFFFF);
1617 sge
->len
= cpu_to_le32(cmd
->size
);
1619 req
->pattern
= cpu_to_le64(pattern
);
1620 req
->byte_count
= cpu_to_le32(byte_cnt
);
1621 for (i
= 0; i
< byte_cnt
; i
++) {
1622 req
->snd_buff
[i
] = (u8
)(pattern
>> (j
*8));
1628 status
= be_mcc_notify_wait(adapter
);
1631 struct be_cmd_resp_ddrdma_test
*resp
;
1633 if ((memcmp(resp
->rcv_buff
, req
->snd_buff
, byte_cnt
) != 0) ||
1640 spin_unlock_bh(&adapter
->mcc_lock
);
1644 extern int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
1645 struct be_dma_mem
*nonemb_cmd
)
1647 struct be_mcc_wrb
*wrb
;
1648 struct be_cmd_req_seeprom_read
*req
;
1652 spin_lock_bh(&adapter
->mcc_lock
);
1654 wrb
= wrb_from_mccq(adapter
);
1655 req
= nonemb_cmd
->va
;
1656 sge
= nonembedded_sgl(wrb
);
1658 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1,
1659 OPCODE_COMMON_SEEPROM_READ
);
1661 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1662 OPCODE_COMMON_SEEPROM_READ
, sizeof(*req
));
1664 sge
->pa_hi
= cpu_to_le32(upper_32_bits(nonemb_cmd
->dma
));
1665 sge
->pa_lo
= cpu_to_le32(nonemb_cmd
->dma
& 0xFFFFFFFF);
1666 sge
->len
= cpu_to_le32(nonemb_cmd
->size
);
1668 status
= be_mcc_notify_wait(adapter
);
1670 spin_unlock_bh(&adapter
->mcc_lock
);