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af4bbff5feba2427b089076a3e503843daeff3e1
[deliverable/linux.git] / drivers / net / benet / be_cmds.h
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 /*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26 struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30 };
31
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45 };
46
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52 /* Completion Status */
53 enum {
54 MCC_STATUS_SUCCESS = 0x0,
55 /* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57 /* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59 /* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61 /* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63 /* The command is completing with a DMA error */
64 MCC_STATUS_DMA_FAILED = 0x5,
65 MCC_STATUS_NOT_SUPPORTED = 66
66 };
67
68 #define CQE_STATUS_COMPL_MASK 0xFFFF
69 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70 #define CQE_STATUS_EXTD_MASK 0xFFFF
71 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
72
73 struct be_mcc_compl {
74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78 };
79
80 /* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
87 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
88 #define ASYNC_EVENT_CODE_GRP_5 0x5
89 #define ASYNC_EVENT_QOS_SPEED 0x1
90 #define ASYNC_EVENT_COS_PRIORITY 0x2
91 #define ASYNC_EVENT_PVID_STATE 0x3
92 struct be_async_event_trailer {
93 u32 code;
94 };
95
96 enum {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
99 };
100
101 /* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104 struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112 } __packed;
113
114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117 struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123 } __packed;
124
125 /* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128 struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136 } __packed;
137
138 /* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141 struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148 } __packed;
149
150 struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
152 struct be_mcc_compl compl;
153 };
154
155 #define CMD_SUBSYSTEM_COMMON 0x1
156 #define CMD_SUBSYSTEM_ETH 0x3
157 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
158
159 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
160 #define OPCODE_COMMON_NTWK_MAC_SET 2
161 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
164 #define OPCODE_COMMON_READ_FLASHROM 6
165 #define OPCODE_COMMON_WRITE_FLASHROM 7
166 #define OPCODE_COMMON_CQ_CREATE 12
167 #define OPCODE_COMMON_EQ_CREATE 13
168 #define OPCODE_COMMON_MCC_CREATE 21
169 #define OPCODE_COMMON_SET_QOS 28
170 #define OPCODE_COMMON_MCC_CREATE_EXT 90
171 #define OPCODE_COMMON_SEEPROM_READ 30
172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
173 #define OPCODE_COMMON_NTWK_RX_FILTER 34
174 #define OPCODE_COMMON_GET_FW_VERSION 35
175 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
176 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
177 #define OPCODE_COMMON_SET_FRAME_SIZE 39
178 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
179 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
182 #define OPCODE_COMMON_MCC_DESTROY 53
183 #define OPCODE_COMMON_CQ_DESTROY 54
184 #define OPCODE_COMMON_EQ_DESTROY 55
185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
186 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
187 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
188 #define OPCODE_COMMON_FUNCTION_RESET 61
189 #define OPCODE_COMMON_MANAGE_FAT 68
190 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
191 #define OPCODE_COMMON_GET_BEACON_STATE 70
192 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
193 #define OPCODE_COMMON_GET_PHY_DETAILS 102
194 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
195 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
196
197 #define OPCODE_ETH_RSS_CONFIG 1
198 #define OPCODE_ETH_ACPI_CONFIG 2
199 #define OPCODE_ETH_PROMISCUOUS 3
200 #define OPCODE_ETH_GET_STATISTICS 4
201 #define OPCODE_ETH_TX_CREATE 7
202 #define OPCODE_ETH_RX_CREATE 8
203 #define OPCODE_ETH_TX_DESTROY 9
204 #define OPCODE_ETH_RX_DESTROY 10
205 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
206
207 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
208 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
209 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
210
211 struct be_cmd_req_hdr {
212 u8 opcode; /* dword 0 */
213 u8 subsystem; /* dword 0 */
214 u8 port_number; /* dword 0 */
215 u8 domain; /* dword 0 */
216 u32 timeout; /* dword 1 */
217 u32 request_length; /* dword 2 */
218 u8 version; /* dword 3 */
219 u8 rsvd[3]; /* dword 3 */
220 };
221
222 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
223 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
224 struct be_cmd_resp_hdr {
225 u32 info; /* dword 0 */
226 u32 status; /* dword 1 */
227 u32 response_length; /* dword 2 */
228 u32 actual_resp_len; /* dword 3 */
229 };
230
231 struct phys_addr {
232 u32 lo;
233 u32 hi;
234 };
235
236 /**************************
237 * BE Command definitions *
238 **************************/
239
240 /* Pseudo amap definition in which each bit of the actual structure is defined
241 * as a byte: used to calculate offset/shift/mask of each field */
242 struct amap_eq_context {
243 u8 cidx[13]; /* dword 0*/
244 u8 rsvd0[3]; /* dword 0*/
245 u8 epidx[13]; /* dword 0*/
246 u8 valid; /* dword 0*/
247 u8 rsvd1; /* dword 0*/
248 u8 size; /* dword 0*/
249 u8 pidx[13]; /* dword 1*/
250 u8 rsvd2[3]; /* dword 1*/
251 u8 pd[10]; /* dword 1*/
252 u8 count[3]; /* dword 1*/
253 u8 solevent; /* dword 1*/
254 u8 stalled; /* dword 1*/
255 u8 armed; /* dword 1*/
256 u8 rsvd3[4]; /* dword 2*/
257 u8 func[8]; /* dword 2*/
258 u8 rsvd4; /* dword 2*/
259 u8 delaymult[10]; /* dword 2*/
260 u8 rsvd5[2]; /* dword 2*/
261 u8 phase[2]; /* dword 2*/
262 u8 nodelay; /* dword 2*/
263 u8 rsvd6[4]; /* dword 2*/
264 u8 rsvd7[32]; /* dword 3*/
265 } __packed;
266
267 struct be_cmd_req_eq_create {
268 struct be_cmd_req_hdr hdr;
269 u16 num_pages; /* sword */
270 u16 rsvd0; /* sword */
271 u8 context[sizeof(struct amap_eq_context) / 8];
272 struct phys_addr pages[8];
273 } __packed;
274
275 struct be_cmd_resp_eq_create {
276 struct be_cmd_resp_hdr resp_hdr;
277 u16 eq_id; /* sword */
278 u16 rsvd0; /* sword */
279 } __packed;
280
281 /******************** Mac query ***************************/
282 enum {
283 MAC_ADDRESS_TYPE_STORAGE = 0x0,
284 MAC_ADDRESS_TYPE_NETWORK = 0x1,
285 MAC_ADDRESS_TYPE_PD = 0x2,
286 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
287 };
288
289 struct mac_addr {
290 u16 size_of_struct;
291 u8 addr[ETH_ALEN];
292 } __packed;
293
294 struct be_cmd_req_mac_query {
295 struct be_cmd_req_hdr hdr;
296 u8 type;
297 u8 permanent;
298 u16 if_id;
299 } __packed;
300
301 struct be_cmd_resp_mac_query {
302 struct be_cmd_resp_hdr hdr;
303 struct mac_addr mac;
304 };
305
306 /******************** PMac Add ***************************/
307 struct be_cmd_req_pmac_add {
308 struct be_cmd_req_hdr hdr;
309 u32 if_id;
310 u8 mac_address[ETH_ALEN];
311 u8 rsvd0[2];
312 } __packed;
313
314 struct be_cmd_resp_pmac_add {
315 struct be_cmd_resp_hdr hdr;
316 u32 pmac_id;
317 };
318
319 /******************** PMac Del ***************************/
320 struct be_cmd_req_pmac_del {
321 struct be_cmd_req_hdr hdr;
322 u32 if_id;
323 u32 pmac_id;
324 };
325
326 /******************** Create CQ ***************************/
327 /* Pseudo amap definition in which each bit of the actual structure is defined
328 * as a byte: used to calculate offset/shift/mask of each field */
329 struct amap_cq_context_be {
330 u8 cidx[11]; /* dword 0*/
331 u8 rsvd0; /* dword 0*/
332 u8 coalescwm[2]; /* dword 0*/
333 u8 nodelay; /* dword 0*/
334 u8 epidx[11]; /* dword 0*/
335 u8 rsvd1; /* dword 0*/
336 u8 count[2]; /* dword 0*/
337 u8 valid; /* dword 0*/
338 u8 solevent; /* dword 0*/
339 u8 eventable; /* dword 0*/
340 u8 pidx[11]; /* dword 1*/
341 u8 rsvd2; /* dword 1*/
342 u8 pd[10]; /* dword 1*/
343 u8 eqid[8]; /* dword 1*/
344 u8 stalled; /* dword 1*/
345 u8 armed; /* dword 1*/
346 u8 rsvd3[4]; /* dword 2*/
347 u8 func[8]; /* dword 2*/
348 u8 rsvd4[20]; /* dword 2*/
349 u8 rsvd5[32]; /* dword 3*/
350 } __packed;
351
352 struct amap_cq_context_lancer {
353 u8 rsvd0[12]; /* dword 0*/
354 u8 coalescwm[2]; /* dword 0*/
355 u8 nodelay; /* dword 0*/
356 u8 rsvd1[12]; /* dword 0*/
357 u8 count[2]; /* dword 0*/
358 u8 valid; /* dword 0*/
359 u8 rsvd2; /* dword 0*/
360 u8 eventable; /* dword 0*/
361 u8 eqid[16]; /* dword 1*/
362 u8 rsvd3[15]; /* dword 1*/
363 u8 armed; /* dword 1*/
364 u8 rsvd4[32]; /* dword 2*/
365 u8 rsvd5[32]; /* dword 3*/
366 } __packed;
367
368 struct be_cmd_req_cq_create {
369 struct be_cmd_req_hdr hdr;
370 u16 num_pages;
371 u8 page_size;
372 u8 rsvd0;
373 u8 context[sizeof(struct amap_cq_context_be) / 8];
374 struct phys_addr pages[8];
375 } __packed;
376
377
378 struct be_cmd_resp_cq_create {
379 struct be_cmd_resp_hdr hdr;
380 u16 cq_id;
381 u16 rsvd0;
382 } __packed;
383
384 struct be_cmd_req_get_fat {
385 struct be_cmd_req_hdr hdr;
386 u32 fat_operation;
387 u32 read_log_offset;
388 u32 read_log_length;
389 u32 data_buffer_size;
390 u32 data_buffer[1];
391 } __packed;
392
393 struct be_cmd_resp_get_fat {
394 struct be_cmd_resp_hdr hdr;
395 u32 log_size;
396 u32 read_log_length;
397 u32 rsvd[2];
398 u32 data_buffer[1];
399 } __packed;
400
401
402 /******************** Create MCCQ ***************************/
403 /* Pseudo amap definition in which each bit of the actual structure is defined
404 * as a byte: used to calculate offset/shift/mask of each field */
405 struct amap_mcc_context_be {
406 u8 con_index[14];
407 u8 rsvd0[2];
408 u8 ring_size[4];
409 u8 fetch_wrb;
410 u8 fetch_r2t;
411 u8 cq_id[10];
412 u8 prod_index[14];
413 u8 fid[8];
414 u8 pdid[9];
415 u8 valid;
416 u8 rsvd1[32];
417 u8 rsvd2[32];
418 } __packed;
419
420 struct amap_mcc_context_lancer {
421 u8 async_cq_id[16];
422 u8 ring_size[4];
423 u8 rsvd0[12];
424 u8 rsvd1[31];
425 u8 valid;
426 u8 async_cq_valid[1];
427 u8 rsvd2[31];
428 u8 rsvd3[32];
429 } __packed;
430
431 struct be_cmd_req_mcc_create {
432 struct be_cmd_req_hdr hdr;
433 u16 num_pages;
434 u16 cq_id;
435 u32 async_event_bitmap[1];
436 u8 context[sizeof(struct amap_mcc_context_be) / 8];
437 struct phys_addr pages[8];
438 } __packed;
439
440 struct be_cmd_resp_mcc_create {
441 struct be_cmd_resp_hdr hdr;
442 u16 id;
443 u16 rsvd0;
444 } __packed;
445
446 /******************** Create TxQ ***************************/
447 #define BE_ETH_TX_RING_TYPE_STANDARD 2
448 #define BE_ULP1_NUM 1
449
450 /* Pseudo amap definition in which each bit of the actual structure is defined
451 * as a byte: used to calculate offset/shift/mask of each field */
452 struct amap_tx_context {
453 u8 if_id[16]; /* dword 0 */
454 u8 tx_ring_size[4]; /* dword 0 */
455 u8 rsvd1[26]; /* dword 0 */
456 u8 pci_func_id[8]; /* dword 1 */
457 u8 rsvd2[9]; /* dword 1 */
458 u8 ctx_valid; /* dword 1 */
459 u8 cq_id_send[16]; /* dword 2 */
460 u8 rsvd3[16]; /* dword 2 */
461 u8 rsvd4[32]; /* dword 3 */
462 u8 rsvd5[32]; /* dword 4 */
463 u8 rsvd6[32]; /* dword 5 */
464 u8 rsvd7[32]; /* dword 6 */
465 u8 rsvd8[32]; /* dword 7 */
466 u8 rsvd9[32]; /* dword 8 */
467 u8 rsvd10[32]; /* dword 9 */
468 u8 rsvd11[32]; /* dword 10 */
469 u8 rsvd12[32]; /* dword 11 */
470 u8 rsvd13[32]; /* dword 12 */
471 u8 rsvd14[32]; /* dword 13 */
472 u8 rsvd15[32]; /* dword 14 */
473 u8 rsvd16[32]; /* dword 15 */
474 } __packed;
475
476 struct be_cmd_req_eth_tx_create {
477 struct be_cmd_req_hdr hdr;
478 u8 num_pages;
479 u8 ulp_num;
480 u8 type;
481 u8 bound_port;
482 u8 context[sizeof(struct amap_tx_context) / 8];
483 struct phys_addr pages[8];
484 } __packed;
485
486 struct be_cmd_resp_eth_tx_create {
487 struct be_cmd_resp_hdr hdr;
488 u16 cid;
489 u16 rsvd0;
490 } __packed;
491
492 /******************** Create RxQ ***************************/
493 struct be_cmd_req_eth_rx_create {
494 struct be_cmd_req_hdr hdr;
495 u16 cq_id;
496 u8 frag_size;
497 u8 num_pages;
498 struct phys_addr pages[2];
499 u32 interface_id;
500 u16 max_frame_size;
501 u16 rsvd0;
502 u32 rss_queue;
503 } __packed;
504
505 struct be_cmd_resp_eth_rx_create {
506 struct be_cmd_resp_hdr hdr;
507 u16 id;
508 u8 rss_id;
509 u8 rsvd0;
510 } __packed;
511
512 /******************** Q Destroy ***************************/
513 /* Type of Queue to be destroyed */
514 enum {
515 QTYPE_EQ = 1,
516 QTYPE_CQ,
517 QTYPE_TXQ,
518 QTYPE_RXQ,
519 QTYPE_MCCQ
520 };
521
522 struct be_cmd_req_q_destroy {
523 struct be_cmd_req_hdr hdr;
524 u16 id;
525 u16 bypass_flush; /* valid only for rx q destroy */
526 } __packed;
527
528 /************ I/f Create (it's actually I/f Config Create)**********/
529
530 /* Capability flags for the i/f */
531 enum be_if_flags {
532 BE_IF_FLAGS_RSS = 0x4,
533 BE_IF_FLAGS_PROMISCUOUS = 0x8,
534 BE_IF_FLAGS_BROADCAST = 0x10,
535 BE_IF_FLAGS_UNTAGGED = 0x20,
536 BE_IF_FLAGS_ULP = 0x40,
537 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
538 BE_IF_FLAGS_VLAN = 0x100,
539 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
540 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
541 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
542 BE_IF_FLAGS_MULTICAST = 0x1000
543 };
544
545 /* An RX interface is an object with one or more MAC addresses and
546 * filtering capabilities. */
547 struct be_cmd_req_if_create {
548 struct be_cmd_req_hdr hdr;
549 u32 version; /* ignore currently */
550 u32 capability_flags;
551 u32 enable_flags;
552 u8 mac_addr[ETH_ALEN];
553 u8 rsvd0;
554 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
555 u32 vlan_tag; /* not used currently */
556 } __packed;
557
558 struct be_cmd_resp_if_create {
559 struct be_cmd_resp_hdr hdr;
560 u32 interface_id;
561 u32 pmac_id;
562 };
563
564 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
565 struct be_cmd_req_if_destroy {
566 struct be_cmd_req_hdr hdr;
567 u32 interface_id;
568 };
569
570 /*************** HW Stats Get **********************************/
571 struct be_port_rxf_stats {
572 u32 rx_bytes_lsd; /* dword 0*/
573 u32 rx_bytes_msd; /* dword 1*/
574 u32 rx_total_frames; /* dword 2*/
575 u32 rx_unicast_frames; /* dword 3*/
576 u32 rx_multicast_frames; /* dword 4*/
577 u32 rx_broadcast_frames; /* dword 5*/
578 u32 rx_crc_errors; /* dword 6*/
579 u32 rx_alignment_symbol_errors; /* dword 7*/
580 u32 rx_pause_frames; /* dword 8*/
581 u32 rx_control_frames; /* dword 9*/
582 u32 rx_in_range_errors; /* dword 10*/
583 u32 rx_out_range_errors; /* dword 11*/
584 u32 rx_frame_too_long; /* dword 12*/
585 u32 rx_address_match_errors; /* dword 13*/
586 u32 rx_vlan_mismatch; /* dword 14*/
587 u32 rx_dropped_too_small; /* dword 15*/
588 u32 rx_dropped_too_short; /* dword 16*/
589 u32 rx_dropped_header_too_small; /* dword 17*/
590 u32 rx_dropped_tcp_length; /* dword 18*/
591 u32 rx_dropped_runt; /* dword 19*/
592 u32 rx_64_byte_packets; /* dword 20*/
593 u32 rx_65_127_byte_packets; /* dword 21*/
594 u32 rx_128_256_byte_packets; /* dword 22*/
595 u32 rx_256_511_byte_packets; /* dword 23*/
596 u32 rx_512_1023_byte_packets; /* dword 24*/
597 u32 rx_1024_1518_byte_packets; /* dword 25*/
598 u32 rx_1519_2047_byte_packets; /* dword 26*/
599 u32 rx_2048_4095_byte_packets; /* dword 27*/
600 u32 rx_4096_8191_byte_packets; /* dword 28*/
601 u32 rx_8192_9216_byte_packets; /* dword 29*/
602 u32 rx_ip_checksum_errs; /* dword 30*/
603 u32 rx_tcp_checksum_errs; /* dword 31*/
604 u32 rx_udp_checksum_errs; /* dword 32*/
605 u32 rx_non_rss_packets; /* dword 33*/
606 u32 rx_ipv4_packets; /* dword 34*/
607 u32 rx_ipv6_packets; /* dword 35*/
608 u32 rx_ipv4_bytes_lsd; /* dword 36*/
609 u32 rx_ipv4_bytes_msd; /* dword 37*/
610 u32 rx_ipv6_bytes_lsd; /* dword 38*/
611 u32 rx_ipv6_bytes_msd; /* dword 39*/
612 u32 rx_chute1_packets; /* dword 40*/
613 u32 rx_chute2_packets; /* dword 41*/
614 u32 rx_chute3_packets; /* dword 42*/
615 u32 rx_management_packets; /* dword 43*/
616 u32 rx_switched_unicast_packets; /* dword 44*/
617 u32 rx_switched_multicast_packets; /* dword 45*/
618 u32 rx_switched_broadcast_packets; /* dword 46*/
619 u32 tx_bytes_lsd; /* dword 47*/
620 u32 tx_bytes_msd; /* dword 48*/
621 u32 tx_unicastframes; /* dword 49*/
622 u32 tx_multicastframes; /* dword 50*/
623 u32 tx_broadcastframes; /* dword 51*/
624 u32 tx_pauseframes; /* dword 52*/
625 u32 tx_controlframes; /* dword 53*/
626 u32 tx_64_byte_packets; /* dword 54*/
627 u32 tx_65_127_byte_packets; /* dword 55*/
628 u32 tx_128_256_byte_packets; /* dword 56*/
629 u32 tx_256_511_byte_packets; /* dword 57*/
630 u32 tx_512_1023_byte_packets; /* dword 58*/
631 u32 tx_1024_1518_byte_packets; /* dword 59*/
632 u32 tx_1519_2047_byte_packets; /* dword 60*/
633 u32 tx_2048_4095_byte_packets; /* dword 61*/
634 u32 tx_4096_8191_byte_packets; /* dword 62*/
635 u32 tx_8192_9216_byte_packets; /* dword 63*/
636 u32 rx_fifo_overflow; /* dword 64*/
637 u32 rx_input_fifo_overflow; /* dword 65*/
638 };
639
640 struct be_rxf_stats {
641 struct be_port_rxf_stats port[2];
642 u32 rx_drops_no_pbuf; /* dword 132*/
643 u32 rx_drops_no_txpb; /* dword 133*/
644 u32 rx_drops_no_erx_descr; /* dword 134*/
645 u32 rx_drops_no_tpre_descr; /* dword 135*/
646 u32 management_rx_port_packets; /* dword 136*/
647 u32 management_rx_port_bytes; /* dword 137*/
648 u32 management_rx_port_pause_frames; /* dword 138*/
649 u32 management_rx_port_errors; /* dword 139*/
650 u32 management_tx_port_packets; /* dword 140*/
651 u32 management_tx_port_bytes; /* dword 141*/
652 u32 management_tx_port_pause; /* dword 142*/
653 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
654 u32 rx_drops_too_many_frags; /* dword 144*/
655 u32 rx_drops_invalid_ring; /* dword 145*/
656 u32 forwarded_packets; /* dword 146*/
657 u32 rx_drops_mtu; /* dword 147*/
658 u32 rsvd0[7];
659 u32 port0_jabber_events;
660 u32 port1_jabber_events;
661 u32 rsvd1[6];
662 };
663
664 struct be_erx_stats {
665 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
666 u32 debug_wdma_sent_hold; /* dword 44*/
667 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
668 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
669 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
670 };
671
672 struct be_pmem_stats {
673 u32 eth_red_drops;
674 u32 rsvd[4];
675 };
676
677 struct be_hw_stats {
678 struct be_rxf_stats rxf;
679 u32 rsvd[48];
680 struct be_erx_stats erx;
681 struct be_pmem_stats pmem;
682 };
683
684 struct be_cmd_req_get_stats {
685 struct be_cmd_req_hdr hdr;
686 u8 rsvd[sizeof(struct be_hw_stats)];
687 };
688
689 struct be_cmd_resp_get_stats {
690 struct be_cmd_resp_hdr hdr;
691 struct be_hw_stats hw_stats;
692 };
693
694 struct be_cmd_req_get_cntl_addnl_attribs {
695 struct be_cmd_req_hdr hdr;
696 u8 rsvd[8];
697 };
698
699 struct be_cmd_resp_get_cntl_addnl_attribs {
700 struct be_cmd_resp_hdr hdr;
701 u16 ipl_file_number;
702 u8 ipl_file_version;
703 u8 rsvd0;
704 u8 on_die_temperature; /* in degrees centigrade*/
705 u8 rsvd1[3];
706 };
707
708 struct be_cmd_req_vlan_config {
709 struct be_cmd_req_hdr hdr;
710 u8 interface_id;
711 u8 promiscuous;
712 u8 untagged;
713 u8 num_vlan;
714 u16 normal_vlan[64];
715 } __packed;
716
717 struct be_cmd_req_promiscuous_config {
718 struct be_cmd_req_hdr hdr;
719 u8 port0_promiscuous;
720 u8 port1_promiscuous;
721 u16 rsvd0;
722 } __packed;
723
724 /******************** Multicast MAC Config *******************/
725 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
726 struct macaddr {
727 u8 byte[ETH_ALEN];
728 };
729
730 struct be_cmd_req_mcast_mac_config {
731 struct be_cmd_req_hdr hdr;
732 u16 num_mac;
733 u8 promiscuous;
734 u8 interface_id;
735 struct macaddr mac[BE_MAX_MC];
736 } __packed;
737
738 static inline struct be_hw_stats *
739 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
740 {
741 return &cmd->hw_stats;
742 }
743
744 /******************** Link Status Query *******************/
745 struct be_cmd_req_link_status {
746 struct be_cmd_req_hdr hdr;
747 u32 rsvd;
748 };
749
750 enum {
751 PHY_LINK_DUPLEX_NONE = 0x0,
752 PHY_LINK_DUPLEX_HALF = 0x1,
753 PHY_LINK_DUPLEX_FULL = 0x2
754 };
755
756 enum {
757 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
758 PHY_LINK_SPEED_10MBPS = 0x1,
759 PHY_LINK_SPEED_100MBPS = 0x2,
760 PHY_LINK_SPEED_1GBPS = 0x3,
761 PHY_LINK_SPEED_10GBPS = 0x4
762 };
763
764 struct be_cmd_resp_link_status {
765 struct be_cmd_resp_hdr hdr;
766 u8 physical_port;
767 u8 mac_duplex;
768 u8 mac_speed;
769 u8 mac_fault;
770 u8 mgmt_mac_duplex;
771 u8 mgmt_mac_speed;
772 u16 link_speed;
773 u32 rsvd0;
774 } __packed;
775
776 /******************** Port Identification ***************************/
777 /* Identifies the type of port attached to NIC */
778 struct be_cmd_req_port_type {
779 struct be_cmd_req_hdr hdr;
780 u32 page_num;
781 u32 port;
782 };
783
784 enum {
785 TR_PAGE_A0 = 0xa0,
786 TR_PAGE_A2 = 0xa2
787 };
788
789 struct be_cmd_resp_port_type {
790 struct be_cmd_resp_hdr hdr;
791 u32 page_num;
792 u32 port;
793 struct data {
794 u8 identifier;
795 u8 identifier_ext;
796 u8 connector;
797 u8 transceiver[8];
798 u8 rsvd0[3];
799 u8 length_km;
800 u8 length_hm;
801 u8 length_om1;
802 u8 length_om2;
803 u8 length_cu;
804 u8 length_cu_m;
805 u8 vendor_name[16];
806 u8 rsvd;
807 u8 vendor_oui[3];
808 u8 vendor_pn[16];
809 u8 vendor_rev[4];
810 } data;
811 };
812
813 /******************** Get FW Version *******************/
814 struct be_cmd_req_get_fw_version {
815 struct be_cmd_req_hdr hdr;
816 u8 rsvd0[FW_VER_LEN];
817 u8 rsvd1[FW_VER_LEN];
818 } __packed;
819
820 struct be_cmd_resp_get_fw_version {
821 struct be_cmd_resp_hdr hdr;
822 u8 firmware_version_string[FW_VER_LEN];
823 u8 fw_on_flash_version_string[FW_VER_LEN];
824 } __packed;
825
826 /******************** Set Flow Contrl *******************/
827 struct be_cmd_req_set_flow_control {
828 struct be_cmd_req_hdr hdr;
829 u16 tx_flow_control;
830 u16 rx_flow_control;
831 } __packed;
832
833 /******************** Get Flow Contrl *******************/
834 struct be_cmd_req_get_flow_control {
835 struct be_cmd_req_hdr hdr;
836 u32 rsvd;
837 };
838
839 struct be_cmd_resp_get_flow_control {
840 struct be_cmd_resp_hdr hdr;
841 u16 tx_flow_control;
842 u16 rx_flow_control;
843 } __packed;
844
845 /******************** Modify EQ Delay *******************/
846 struct be_cmd_req_modify_eq_delay {
847 struct be_cmd_req_hdr hdr;
848 u32 num_eq;
849 struct {
850 u32 eq_id;
851 u32 phase;
852 u32 delay_multiplier;
853 } delay[8];
854 } __packed;
855
856 struct be_cmd_resp_modify_eq_delay {
857 struct be_cmd_resp_hdr hdr;
858 u32 rsvd0;
859 } __packed;
860
861 /******************** Get FW Config *******************/
862 #define BE_FUNCTION_CAPS_RSS 0x2
863 struct be_cmd_req_query_fw_cfg {
864 struct be_cmd_req_hdr hdr;
865 u32 rsvd[31];
866 };
867
868 struct be_cmd_resp_query_fw_cfg {
869 struct be_cmd_resp_hdr hdr;
870 u32 be_config_number;
871 u32 asic_revision;
872 u32 phys_port;
873 u32 function_mode;
874 u32 rsvd[26];
875 u32 function_caps;
876 };
877
878 /******************** RSS Config *******************/
879 /* RSS types */
880 #define RSS_ENABLE_NONE 0x0
881 #define RSS_ENABLE_IPV4 0x1
882 #define RSS_ENABLE_TCP_IPV4 0x2
883 #define RSS_ENABLE_IPV6 0x4
884 #define RSS_ENABLE_TCP_IPV6 0x8
885
886 struct be_cmd_req_rss_config {
887 struct be_cmd_req_hdr hdr;
888 u32 if_id;
889 u16 enable_rss;
890 u16 cpu_table_size_log2;
891 u32 hash[10];
892 u8 cpu_table[128];
893 u8 flush;
894 u8 rsvd0[3];
895 };
896
897 /******************** Port Beacon ***************************/
898
899 #define BEACON_STATE_ENABLED 0x1
900 #define BEACON_STATE_DISABLED 0x0
901
902 struct be_cmd_req_enable_disable_beacon {
903 struct be_cmd_req_hdr hdr;
904 u8 port_num;
905 u8 beacon_state;
906 u8 beacon_duration;
907 u8 status_duration;
908 } __packed;
909
910 struct be_cmd_resp_enable_disable_beacon {
911 struct be_cmd_resp_hdr resp_hdr;
912 u32 rsvd0;
913 } __packed;
914
915 struct be_cmd_req_get_beacon_state {
916 struct be_cmd_req_hdr hdr;
917 u8 port_num;
918 u8 rsvd0;
919 u16 rsvd1;
920 } __packed;
921
922 struct be_cmd_resp_get_beacon_state {
923 struct be_cmd_resp_hdr resp_hdr;
924 u8 beacon_state;
925 u8 rsvd0[3];
926 } __packed;
927
928 /****************** Firmware Flash ******************/
929 struct flashrom_params {
930 u32 op_code;
931 u32 op_type;
932 u32 data_buf_size;
933 u32 offset;
934 u8 data_buf[4];
935 };
936
937 struct be_cmd_write_flashrom {
938 struct be_cmd_req_hdr hdr;
939 struct flashrom_params params;
940 };
941
942 /************************ WOL *******************************/
943 struct be_cmd_req_acpi_wol_magic_config{
944 struct be_cmd_req_hdr hdr;
945 u32 rsvd0[145];
946 u8 magic_mac[6];
947 u8 rsvd2[2];
948 } __packed;
949
950 /********************** LoopBack test *********************/
951 struct be_cmd_req_loopback_test {
952 struct be_cmd_req_hdr hdr;
953 u32 loopback_type;
954 u32 num_pkts;
955 u64 pattern;
956 u32 src_port;
957 u32 dest_port;
958 u32 pkt_size;
959 };
960
961 struct be_cmd_resp_loopback_test {
962 struct be_cmd_resp_hdr resp_hdr;
963 u32 status;
964 u32 num_txfer;
965 u32 num_rx;
966 u32 miscomp_off;
967 u32 ticks_compl;
968 };
969
970 struct be_cmd_req_set_lmode {
971 struct be_cmd_req_hdr hdr;
972 u8 src_port;
973 u8 dest_port;
974 u8 loopback_type;
975 u8 loopback_state;
976 };
977
978 struct be_cmd_resp_set_lmode {
979 struct be_cmd_resp_hdr resp_hdr;
980 u8 rsvd0[4];
981 };
982
983 /********************** DDR DMA test *********************/
984 struct be_cmd_req_ddrdma_test {
985 struct be_cmd_req_hdr hdr;
986 u64 pattern;
987 u32 byte_count;
988 u32 rsvd0;
989 u8 snd_buff[4096];
990 u8 rsvd1[4096];
991 };
992
993 struct be_cmd_resp_ddrdma_test {
994 struct be_cmd_resp_hdr hdr;
995 u64 pattern;
996 u32 byte_cnt;
997 u32 snd_err;
998 u8 rsvd0[4096];
999 u8 rcv_buff[4096];
1000 };
1001
1002 /*********************** SEEPROM Read ***********************/
1003
1004 #define BE_READ_SEEPROM_LEN 1024
1005 struct be_cmd_req_seeprom_read {
1006 struct be_cmd_req_hdr hdr;
1007 u8 rsvd0[BE_READ_SEEPROM_LEN];
1008 };
1009
1010 struct be_cmd_resp_seeprom_read {
1011 struct be_cmd_req_hdr hdr;
1012 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1013 };
1014
1015 enum {
1016 PHY_TYPE_CX4_10GB = 0,
1017 PHY_TYPE_XFP_10GB,
1018 PHY_TYPE_SFP_1GB,
1019 PHY_TYPE_SFP_PLUS_10GB,
1020 PHY_TYPE_KR_10GB,
1021 PHY_TYPE_KX4_10GB,
1022 PHY_TYPE_BASET_10GB,
1023 PHY_TYPE_BASET_1GB,
1024 PHY_TYPE_DISABLED = 255
1025 };
1026
1027 struct be_cmd_req_get_phy_info {
1028 struct be_cmd_req_hdr hdr;
1029 u8 rsvd0[24];
1030 };
1031 struct be_cmd_resp_get_phy_info {
1032 struct be_cmd_req_hdr hdr;
1033 u16 phy_type;
1034 u16 interface_type;
1035 u32 misc_params;
1036 u32 future_use[4];
1037 };
1038
1039 /*********************** Set QOS ***********************/
1040
1041 #define BE_QOS_BITS_NIC 1
1042
1043 struct be_cmd_req_set_qos {
1044 struct be_cmd_req_hdr hdr;
1045 u32 valid_bits;
1046 u32 max_bps_nic;
1047 u32 rsvd[7];
1048 };
1049
1050 struct be_cmd_resp_set_qos {
1051 struct be_cmd_resp_hdr hdr;
1052 u32 rsvd;
1053 };
1054
1055 /*********************** Controller Attributes ***********************/
1056 struct be_cmd_req_cntl_attribs {
1057 struct be_cmd_req_hdr hdr;
1058 };
1059
1060 struct be_cmd_resp_cntl_attribs {
1061 struct be_cmd_resp_hdr hdr;
1062 struct mgmt_controller_attrib attribs;
1063 };
1064
1065 /*********************** Set driver function ***********************/
1066 #define CAPABILITY_SW_TIMESTAMPS 2
1067 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1068
1069 struct be_cmd_req_set_func_cap {
1070 struct be_cmd_req_hdr hdr;
1071 u32 valid_cap_flags;
1072 u32 cap_flags;
1073 u8 rsvd[212];
1074 };
1075
1076 struct be_cmd_resp_set_func_cap {
1077 struct be_cmd_resp_hdr hdr;
1078 u32 valid_cap_flags;
1079 u32 cap_flags;
1080 u8 rsvd[212];
1081 };
1082
1083 extern int be_pci_fnum_get(struct be_adapter *adapter);
1084 extern int be_cmd_POST(struct be_adapter *adapter);
1085 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1086 u8 type, bool permanent, u32 if_handle);
1087 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1088 u32 if_id, u32 *pmac_id, u32 domain);
1089 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1090 u32 pmac_id, u32 domain);
1091 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1092 u32 en_flags, u8 *mac, bool pmac_invalid,
1093 u32 *if_handle, u32 *pmac_id, u32 domain);
1094 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1095 u32 domain);
1096 extern int be_cmd_eq_create(struct be_adapter *adapter,
1097 struct be_queue_info *eq, int eq_delay);
1098 extern int be_cmd_cq_create(struct be_adapter *adapter,
1099 struct be_queue_info *cq, struct be_queue_info *eq,
1100 bool sol_evts, bool no_delay,
1101 int num_cqe_dma_coalesce);
1102 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1103 struct be_queue_info *mccq,
1104 struct be_queue_info *cq);
1105 extern int be_cmd_txq_create(struct be_adapter *adapter,
1106 struct be_queue_info *txq,
1107 struct be_queue_info *cq);
1108 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1109 struct be_queue_info *rxq, u16 cq_id,
1110 u16 frag_size, u16 max_frame_size, u32 if_id,
1111 u32 rss, u8 *rss_id);
1112 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1113 int type);
1114 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1115 bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom);
1116 extern int be_cmd_reset(struct be_adapter *adapter);
1117 extern int be_cmd_get_stats(struct be_adapter *adapter,
1118 struct be_dma_mem *nonemb_cmd);
1119 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1120
1121 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1122 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1123 u16 *vtag_array, u32 num, bool untagged,
1124 bool promiscuous);
1125 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
1126 u8 port_num, bool en);
1127 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1128 struct net_device *netdev, struct be_dma_mem *mem);
1129 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1130 u32 tx_fc, u32 rx_fc);
1131 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1132 u32 *tx_fc, u32 *rx_fc);
1133 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1134 u32 *port_num, u32 *function_mode, u32 *function_caps);
1135 extern int be_cmd_reset_function(struct be_adapter *adapter);
1136 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1137 u16 table_size);
1138 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1139 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1140 u8 port_num, u8 beacon, u8 status, u8 state);
1141 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1142 u8 port_num, u32 *state);
1143 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1144 struct be_dma_mem *cmd, u32 flash_oper,
1145 u32 flash_opcode, u32 buf_size);
1146 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1147 int offset);
1148 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1149 struct be_dma_mem *nonemb_cmd);
1150 extern int be_cmd_fw_init(struct be_adapter *adapter);
1151 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1152 extern void be_async_mcc_enable(struct be_adapter *adapter);
1153 extern void be_async_mcc_disable(struct be_adapter *adapter);
1154 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1155 u32 loopback_type, u32 pkt_size,
1156 u32 num_pkts, u64 pattern);
1157 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1158 u32 byte_cnt, struct be_dma_mem *cmd);
1159 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1160 struct be_dma_mem *nonemb_cmd);
1161 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1162 u8 loopback_type, u8 enable);
1163 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1164 struct be_dma_mem *cmd);
1165 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1166 extern void be_detect_dump_ue(struct be_adapter *adapter);
1167 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1168 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1169 extern int be_cmd_check_native_mode(struct be_adapter *adapter);
1170 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1171 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1172
Linux kernel - Deliverables
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